TW202146913A - Pulse-width modulation detection circuit and method for power saving and anti-noise - Google Patents

Abstract

A pulse-width modulation (PWM) detection circuit for power saving and anti-noise includes a first circuit, a second circuit and an output circuit. The second circuit is coupled between the first circuit and output circuit. When the first circuit receives a PWM signal, the first circuit generates a current sampling result according to a time when PWM signal is at high-level through asynchronous sampling, and compares the current sampling result with at least one previous sampling result to generate a comparing result related to whether the time when the PWM signal is at high-level changes. The second circuit is controlled by the first circuit to selectively calculate a current duty cycle according to the current sampling result or use a previous duty cycle according to the comparing result. The output circuit generates an output current according to the current duty cycle or previous duty cycle provided by the second circuit.

Description

Pulse width modulation detection circuit and method for power saving and anti-noise

The present invention is related to pulse width modulation (Pulse-width modulation, PWM) technology, and more particularly, to a PWM detection circuit and method for power saving and anti-noise.

In the prior art, a common power saving method is to calculate the length difference between two consecutive duty cycles of the PWM signal through an input hysteresis unit and set a threshold value. When the length difference between the two working cycles is greater than the threshold value, it is determined that the two working cycles are different. Therefore, the subsequent normal operation procedure is continued until the output current is generated; when the length difference between the two working cycles is less than the threshold value, the Then it is determined that the two duty cycles are the same, therefore, the subsequent operation program will stop and directly use the previous duty cycle value to achieve the power saving effect.

However, when the duty cycle value of the input PWM signal is larger, the jitter generated by the PWM signal is also larger, and the noise caused by it is also more serious and difficult to filter effectively.

In view of this, the present invention provides a PWM detection circuit and method for power saving and anti-noise, so as to effectively solve the above-mentioned problems encountered in the prior art.

A specific embodiment of the present invention is a pulse width modulation detection circuit. In this embodiment, the PWM detection circuit can achieve both power saving and anti-noise effects. The pulse width modulation detection circuit includes a first circuit, a second circuit and an output circuit. The second circuit is coupled between the first circuit and the output circuit. When the first circuit receives the input PWM signal, the first circuit generates a current sampling result by asynchronous sampling to the time when the PWM signal is at a high level, and compares the current sampling result with at least one previous sampling result to produce comparison results. The comparison result is related to whether the time when the PWM signal is at a high level changes. The second circuit is controlled by the first circuit to selectively use the current sampling result to calculate the current duty cycle value or use the previous duty cycle value according to the comparison result. The output circuit generates an output current according to the current duty cycle value or the previous duty cycle value provided by the second circuit.

In one embodiment, the first circuit includes a sampling unit for asynchronously sampling the time when the PWM signal is at a high level to generate the current sampling result.

In one embodiment, the first circuit includes a comparison unit for comparing the current sampling result with at least one previous sampling result to generate a comparison result.

In one embodiment, the first circuit includes a switching unit coupled to the second circuit for generating a control signal to the second circuit according to the comparison result to control the operation of the second circuit.

In one embodiment, the first circuit further includes an anti-noise unit, coupled to the comparison unit, for setting an adjustment threshold value according to the frequency, and after adjusting the adjustment threshold value with the previous duty cycle value, the adjustment threshold value is provided to the comparison unit, so as to judge. Whether the time when the PWM signal is at a high level has changed.

In one embodiment, the first circuit includes an anti-noise unit. The de-noising unit is used for recording a plurality of previous duty cycle values. If the amplitude between the two previous duty cycle values of the plurality of previous duty cycle values is smaller than an adjustment threshold value, the first circuit determines that the time when the PWM signal is at a high level has changed.

In one embodiment, the first circuit includes an anti-noise unit. The de-noising unit is used for recording a plurality of previous duty cycle values and encoding a duty cycle variation profile (Profile) according to the average difference of two previous duty cycle values among the plurality of previous duty cycle values. If the number of transitions of the duty cycle variation profile is 1 and the duty cycle variation profile conforms to a specific profile, the first circuit determines that the time when the PWM signal is at a high level has changed.

In one embodiment, when the comparison result is that the time during which the PWM signal is at a high level has not changed, the second circuit retains the previous duty cycle value.

In one embodiment, when the comparison result is that the time when the PWM signal is at a high level has changed, the second circuit calculates the current duty cycle value according to the current sampling result.

In one embodiment, the second circuit includes a determination unit and an operation unit. The determination unit is coupled between the first circuit and the operation unit, and is controlled by the first circuit to determine whether the calculation needs to be performed. The operation unit is coupled between the determination unit and the output circuit, and is used for selectively calculating the current duty cycle value or using the previous duty cycle value according to the current sampling result according to the determination result of the determination unit.

In one embodiment, the output circuit includes an output hysteresis unit and a digital-to-analog conversion unit. The output hysteresis unit is coupled between the second circuit and the digital-to-analog converting unit, and is used for generating an output hysteresis signal according to the current duty cycle value or the previous duty cycle value provided by the second circuit. The digital-to-analog conversion unit is coupled to the output hysteresis unit for generating an output current according to the output hysteresis signal.

Another specific embodiment according to the present invention is a pulse width modulation detection method. In this embodiment, the pulse width modulation detection method is applied to the pulse width modulation detection circuit and can take into account the effects of power saving and anti-noise at the same time. The pulse width modulation detection circuit includes a first circuit, a second circuit and an output circuit. The second circuit is coupled between the first circuit and the output circuit. The PWM detection method includes the following steps:

Step (a): when the first circuit receives the input PWM signal, the first circuit generates the current sampling result by asynchronous sampling to the time when the PWM signal is at a high level;

Step (b): the first circuit compares the current sampling result with at least one previous sampling result to generate a comparison result, wherein the comparison result is related to whether the time when the PWM signal is at a high level changes;

Step (c): the second circuit is controlled by the first circuit to selectively use the current sampling result to calculate the current duty cycle value or use the previous duty cycle value according to the comparison result; and

Step (d): the output circuit generates an output current according to the current duty cycle value or the previous duty cycle value provided by the second circuit.

Compared with the prior art, the PWM detection circuit and method according to the present invention can take into account the effects of power saving and anti-noise at the same time, when comparing the current sampling result of the PWM signal with at least one previous sampling result As a result, when it is determined that the time when the PWM signal is at a high level does not change, the subsequent normal operation procedure is stopped and the previous duty cycle value is directly used, so as to achieve the effect of power saving, even if the duty cycle value of the input PWM signal is not changed. When the jitter becomes larger and more severe, the PWM detection circuit and method according to the present invention can still effectively eliminate the noise caused by the jitter of the PWM signal.

The advantages and spirit of the present invention can be further understood from the following detailed description of the invention and the accompanying drawings.

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Elements/components using the same or similar numbers in the drawings and the embodiments are intended to represent the same or similar parts.

A specific embodiment of the present invention is a pulse width modulation detection circuit. In this embodiment, the PWM detection circuit can achieve both power saving and anti-noise effects. Please refer to FIG. 1 . FIG. 1 is a functional block diagram of the PWM detection circuit of this embodiment.

As shown in FIG. 1 , the PWM detection circuit 1 includes a first circuit 10 , a second circuit 12 and an output circuit 14 . The second circuit 12 is coupled between the first circuit 10 and the output circuit 14 .

When the first circuit 10 receives the input pulse width modulation signal PWM, the first circuit 10 samples the input pulse width modulation signal PWM in an asynchronous sampling manner to obtain the pulse width modulation signal. When the variable signal is at a high-level, a current sampling result CSR is generated accordingly.

Next, the first circuit 10 also compares the current sampling result CSR with at least one previous sampling result PSR to generate a comparison result CR to the second circuit 12 . In addition, the first circuit 10 also generates a control signal SS to the second circuit 12 according to the comparison result CR. The comparison result CR is related to whether the time when the pulse width modulation signal PWM is at a high level changes.

The second circuit 12 is controlled by the control signal SS of the first circuit 10 to selectively use the current sampling result CSR to calculate a current duty cycle value CDV or use a previous duty cycle value PDV according to the comparison result CR, and output the current duty cycle value CDV or previous duty cycle value PDV to output circuit 14 . The output circuit 14 then generates the output current IOUT according to the current duty cycle value CDV or the previous duty cycle value PDV provided by the second circuit 12 .

Next, the internal circuit structures of the first circuit 10 , the second circuit 12 and the output circuit 14 will be described in detail respectively.

As shown in FIG. 1 , in this embodiment, the first circuit 10 may include a sampling unit 100 , a de-noising unit 102 , a comparing unit 104 and a switching unit 106 . The sampling unit 100 is coupled to the denoising unit 102 and the comparing unit 104 . The de-noising unit 102 is coupled to the sampling unit 100 and the comparing unit 104 . The comparison unit 104 is coupled to the sampling unit 100 , the switching unit 106 and the second circuit 12 . The switching unit 106 is coupled to the comparing unit 104 and the second circuit 12 .

The sampling unit 100 is used for asynchronously sampling the input pulse width modulation signal PWM, so as to obtain the time when the pulse width modulation signal PWM is at a high level by sampling, and generate the current sampling result CSR accordingly. The comparing unit 104 is used for comparing the current sampling result CSR with at least one previous sampling result PSR, and generating a comparison result CR to the second circuit 12 accordingly. The switching unit 106 is used for generating a control signal SS to the second circuit 12 according to the comparison result CR to control the operation of the second circuit 12 .

It should be noted that the denoising unit 102 in this embodiment is used to set an adjustment threshold value MF according to the frequency, and adjust the adjustment threshold value MF with the previous duty cycle value PDV, and then provide the adjustment threshold value MF to the comparison unit 104, so as to be used in the comparison unit. 104 When comparing the current sampling result CSR with at least one previous sampling result PSR, it can be determined whether the time when the pulse width modulation signal PWM is at a high level changes.

For example, as shown in FIG. 1 , the de-noise unit 102 may include a setter 1020 , a regulator 1022 and a multiplexer 1024 . The setter 1020 is coupled between the sampling unit 100 and the multiplexer 1024 . The regulator 1022 is coupled between the sampling unit 100 and the multiplexer 1024 . The multiplexer 1024 is respectively coupled to the setter 1020 , the adjuster 1022 and the comparison unit 104 . The setter 1020 is used for setting an adjustment threshold value MF according to the frequency. The adjuster 1022 is used to adjust the adjustment threshold value MF through the previous duty cycle value PDV. The multiplexer 1024 is used for providing the adjusted adjustment threshold value MF to the comparison unit 104 .

As shown in FIG. 1 , in this embodiment, the second circuit 12 may include a determination unit 120 and an operation unit 122 . The determination unit 120 is coupled between the first circuit 10 and the operation unit 122 , and is controlled by the control signal SS of the first circuit 10 to determine whether the subsequent calculation procedure still needs to be performed. The operation unit 122 is coupled between the determination unit 120 and the output circuit 14 for selectively calculating the current duty cycle value CDV or directly using the previous duty cycle value PDV according to the determination result of the determination unit 120 according to the current sampling result CSR.

It should be noted that, when the comparison result CR obtained by comparing the current sampling result CSR and at least one previous sampling result PSR by the comparing unit 104 is that the time when the pulse width modulation signal PWM is at the high level has not changed, the determining unit 120 is controlled by the first sampling result. The control signal SS of a circuit 10 determines that the subsequent calculation process does not need to be performed, so the operation unit 122 does not perform operation and directly uses the previous duty cycle value PDV. When the comparison result CR obtained by comparing the current sampling result CSR with at least one previous sampling result PSR by the comparing unit 104 is that the time when the pulse width modulation signal PWM is at a high level has changed, the determining unit 120 is controlled by the first circuit 10 The signal SS determines that the subsequent calculation process still needs to be performed, so the operation unit 122 still performs normal operation and calculates the current duty cycle value CDV according to the current sampling result CSR.

As shown in FIG. 1 , in this embodiment, the output circuit 14 includes an output hysteresis unit 140 and a digital-to-analog conversion unit 142 . The output hysteresis unit 140 is coupled between the second circuit 12 and the digital-to-analog conversion unit 142 for generating an output hysteresis signal HY according to the current duty cycle value CDV or the previous duty cycle value PDV provided by the second circuit 12 . The digital-to-analog conversion unit 142 is coupled to the output hysteresis unit 140, and is used for performing digital-to-analog conversion on the output hysteresis signal HY to generate the output current IOUT.

In another embodiment, please refer to FIG. 2, the de-noising unit 102' can also be used to record a plurality of previous duty cycle values (eg PDV1-PDVN, N is a positive integer greater than 1, but not limited to this) and provided to the comparison unit 104 . The de-noising unit 102 ′ can also encode a work cycle according to the average difference of two previous work cycle values (such as PDV1 and PDV2 , but not limited to) among the plurality of previous work cycle values (such as PDV1 to PDVN). The periodic variation profile (Profile) DP is provided to the comparison unit 104 .

For example, as shown in Figure 2, the de-noise unit 102' may include a recorder 1020', an encoder 1022', and a multiplexer 1024'. The recorder 1020' is coupled between the sampling unit 100 and the multiplexer 1024'. The encoder 1022' is coupled between the sampling unit 100 and the multiplexer 1024'. The multiplexer 1024' is coupled to the recorder 1020', the encoder 1022' and the comparison unit 104, respectively. The recorder 1020' is used to record a plurality of previous duty cycle values (for example, PDV1˜PDVN, where N is a positive integer greater than 1, but not limited thereto). The encoder 1022' is used for encoding a duty cycle variation profile DP according to the average difference of two previous duty cycle values (eg, PDV1 and PDV2) among the plurality of previous duty cycle values (eg, PDV1-PDVN). The multiplexer 1024' is used to provide a plurality of previous duty cycle values (eg PDV1˜PDVN) or the duty cycle variation profile DP to the comparison unit 104.

If the amplitude between the two previous duty cycle values (for example, PDV1 and PDV2 ) among the plurality of previous duty cycle values (for example, PDV1 to PDVN) is smaller than an adjustment threshold value MF, the comparison unit 104 compares the current sampling result CSR with the At least one previous sampling result PSR determines the time change when the pulse width modulation signal PWM is at a high level. If the number of transitions of the duty cycle variation profile DP is 1 and the duty cycle variation profile DP conforms to a specific profile, the comparison unit 104 determines that the pulse width modulation signal PWM is at High level time changes.

Table 1 PDV1 PDV2 PDV3 average Duty Cycle Variation Profile DP critical result 103 103 103 103 111 No transition The time that the pulse width modulation signal PWM is at a high level does not change 103 103 100 102 110 1 transition and conforms to a specific profile The time change of the pulse width modulation signal PWM at high level 103 100 100 101 100 jumps 1 time but does not conform to a specific contour The time that the pulse width modulation signal PWM is at a high level does not change 100 100 100 100 000 No transition The time that the pulse width modulation signal PWM is at a high level does not change 100 100 103 101 001 Jump 1 time and conform to a specific contour The time change of the pulse width modulation signal PWM at high level 100 103 103 102 011 Jump 1 time but does not match the specific contour The time that the pulse width modulation signal PWM is at a high level does not change 103 103 103 103 111 No transition The time that the pulse width modulation signal PWM is at a high level does not change

For example, as shown in Table 1, if three previous duty cycle values PDV1 to PDV3 are recorded as an example, assuming that the specific contour is {110, 001}, the comparison unit 104 compares the current sampling result CSR with at least one previous sampling When the result is PSR, only when the duty cycle change profile DP jumps once and conforms to the specific profile {110, 001} will it be judged that the time of the PWM signal PWM is at a high level, otherwise it will be judged as PWM The time that the signal PWM is at a high level is unchanged.

Another specific embodiment according to the present invention is a pulse width modulation detection method. In this embodiment, the pulse width modulation detection method is applied to the pulse width modulation detection circuit and can take into account the effects of power saving and anti-noise at the same time. The pulse width modulation detection circuit includes a first circuit, a second circuit and an output circuit. The second circuit is coupled between the first circuit and the output circuit.

Please refer to FIG. 3 . FIG. 3 is a flowchart of the PWM detection method in this embodiment. As shown in Figure 3, the PWM detection method includes the following steps:

Step S10: when the first circuit receives the PWM signal, the first circuit generates the current sampling result by asynchronous sampling to the time when the PWM signal is at a high level;

Step S12: the first circuit compares the current sampling result with at least one previous sampling result to generate a comparison result, wherein the comparison result is related to whether the time when the PWM signal is at a high level changes;

Step S14 : the second circuit is controlled by the first circuit to selectively calculate the current duty cycle value or use the previous duty cycle value with the current sampling result according to the comparison result; and

Step S16: The output circuit generates an output current according to the current duty cycle value or the previous duty cycle value provided by the second circuit.

In an embodiment, the second circuit in step S14 is controlled by the first circuit means: the first circuit generates a control signal to the second circuit according to the comparison result to control the operation of the second circuit, but not limit.

In another embodiment, the PWM detection method may further include the following steps:

An adjustment threshold value is set according to the frequency, and the adjustment threshold value is adjusted according to the previous duty cycle value, so as to determine whether the time when the PWM signal is at a high level changes.

In another embodiment, the PWM detection method may further include the following steps:

Multiple previous duty cycle values are recorded.

In practical applications, if the amplitude between the two previous duty cycle values in the plurality of previous duty cycle values is less than an adjustment threshold value, the comparison result in step S12 will determine the time when the PWM signal is at a high level There are changes.

In another embodiment, the PWM detection method may further include the following steps:

A plurality of previous duty cycle values are recorded and encoded as a duty cycle variation profile according to the average difference of two previous duty cycle values among the plurality of previous duty cycle values.

In practical applications, if the number of transitions of the duty cycle variation profile is 1 and the duty cycle variation profile conforms to a specific profile, the comparison result in step S12 will determine that the time when the PWM signal is at a high level has changed.

It should be noted that, when the comparison result in step S12 is that the time during which the PWM signal is at a high level does not change, the second circuit in step S14 uses the previous duty cycle value. When the comparison result in step S12 is that the time when the PWM signal is at a high level changes, the second circuit in step S14 calculates the current duty cycle value according to the current sampling result.

In practical applications, step S14 may include the following two sub-steps, but not limited thereto:

Controlled by the first circuit to determine whether subsequent operation procedures need to be performed; and

According to the above judgment result, the current duty cycle value is selectively calculated according to the current sampling result or the previous duty cycle value is used.

In practical applications, step S16 may include the following two sub-steps, but not limited to this:

generating an output hysteresis signal according to the current duty cycle value or the previous duty cycle value provided by the second circuit; and

The output current is generated according to the output hysteresis signal.

Compared with the prior art, the PWM detection circuit and method according to the present invention can take into account the effects of power saving and anti-noise at the same time, when comparing the current sampling result of the PWM signal with at least one previous sampling result As a result, when it is determined that the time when the PWM signal is at a high level does not change, the subsequent normal operation procedure is stopped and the previous duty cycle value is directly used, so as to achieve the effect of power saving, even if the duty cycle value of the input PWM signal is not changed. When the jitter becomes larger and more severe, the PWM detection circuit and method according to the present invention can still effectively eliminate the noise caused by the jitter of the PWM signal.

S10~S16: Steps 1: PWM detection circuit 10: The first circuit 12: Second circuit 14: Output circuit PWM: Pulse Width Modulation Signal CSR: Current Sampling Results PSR: previous sampling result CR: Compare Results SS: control signal CDV: Current duty cycle value PDV: previous duty cycle value IOUT: output current 100: Sampling unit 102: De-noise unit 104: Comparison Unit 106: Switch unit MF: Adjust the threshold value 1020: Setter 1022: Adjuster 1024: Multiplexer 120: Judgment unit 122: Operation unit 140: Output hysteresis unit 142: Digital to analog conversion unit HY: output hysteresis signal 102': De-noise unit PDV1~PDVN: previous duty cycle value DP: duty cycle variation profile 1020’: Recorder 1022': encoder 1024': Multiplexer

The accompanying drawings of the present invention are described as follows: FIG. 1 is a functional block diagram of a PWM detection circuit according to a preferred embodiment of the present invention. FIG. 2 is a functional block diagram of a PWM detection circuit according to another preferred embodiment of the present invention. FIG. 3 is a flowchart illustrating a PWM detection method according to another preferred embodiment of the present invention.

S10~S16: Steps

Claims (20)

A pulse width modulation detection circuit, comprising: a first circuit, when the first circuit receives a PWM signal, the first circuit generates a current sampling result by asynchronously sampling the time when the PWM signal is at a high level, and compares the The current sampling result and at least one previous sampling result are used to generate a comparison result, wherein the comparison result is related to whether the time when the PWM signal is at a high level changes; a second circuit coupled to the first circuit, the second circuit is controlled by the first circuit to selectively calculate a current duty cycle value or use a previous duty cycle value with the current sampling result according to the comparison result; as well as An output circuit is coupled to the second circuit for generating an output current according to the current duty cycle value or the previous duty cycle value provided by the second circuit. The pulse width modulation detection circuit as described in claim 1, wherein the first circuit comprises: A sampling unit is used for asynchronously sampling the time when the PWM signal is at a high level to generate the current sampling result. The pulse width modulation detection circuit as described in claim 1, wherein the first circuit comprises: a comparison unit for comparing the current sampling result with the at least one previous sampling result to generate the comparison result. The pulse width modulation detection circuit as described in claim 1, wherein the first circuit comprises: A switching unit is coupled to the second circuit for generating a control signal to the second circuit according to the comparison result to control the operation of the second circuit. The pulse width modulation detection circuit as described in claim 3, wherein the first circuit comprises: an anti-noise unit for setting an adjustment threshold value according to the frequency, and after adjusting the adjustment threshold value with the previous duty cycle value and providing it to the comparison unit to determine whether the time when the PWM signal is at a high level has changed . The pulse width modulation detection circuit as described in claim 1, wherein the first circuit comprises: a de-noising unit for recording a plurality of previous duty cycle values, and if the amplitude between two previous duty cycle values in the plurality of previous duty cycle values is less than an adjustment threshold, the first circuit determines that the pulse width modulation The time when the variable signal is at a high level changes. The pulse width modulation detection circuit as described in claim 1, wherein the first circuit comprises: a de-noising unit that records a plurality of previous duty cycle values and encodes a duty cycle change profile (Profile) according to the average difference of two previous duty cycle values among the plurality of previous duty cycle values, if the duty cycle change profile The number of transitions is 1 and the duty cycle variation profile conforms to a specific profile, then the first circuit determines that the time when the PWM signal is at a high level has changed. The PWM detection circuit of claim 1, wherein when the comparison result is that the time during which the PWM signal is at a high level has not changed, the second circuit continues to use the previous duty cycle value. The PWM detection circuit as described in claim 1, wherein when the comparison result is that the time when the PWM signal is at a high level has changed, the second circuit calculates the current sampling result according to the current sampling result. Current duty cycle value. The pulse width modulation detection circuit as described in claim 1, wherein the second circuit comprises: a judging unit, coupled to the first circuit, for being controlled by the first circuit and judging whether the subsequent operation procedure needs to be performed; and an arithmetic unit coupled between the judging unit and the output circuit for selectively calculating the current duty cycle value according to the current sampling result or continuing to use the previous duty cycle value according to the judging result of the judging unit. The pulse width modulation detection circuit as described in claim 1, wherein the output circuit comprises: an output hysteresis unit, coupled to the second circuit, for generating an output hysteresis signal according to the current duty cycle value or the previous duty cycle value provided by the second circuit; and A digital-to-analog conversion unit is coupled to the output hysteresis unit for generating the output current according to the output hysteresis signal. A pulse width modulation detection method is applied to a pulse width modulation detection circuit, the pulse width modulation detection circuit comprises a first circuit, a second circuit and an output circuit, the second circuit is coupled to Between the first circuit and the output circuit, the PWM detection method includes the following steps: (a) when the first circuit receives a PWM signal, the first circuit generates a current sampling result by asynchronously sampling to the time when the PWM signal is at a high level; (b) the first circuit compares the current sampling result with at least one previous sampling result to generate a comparison result, wherein the comparison result is related to whether the time when the PWM signal is at a high level changes; (c) the second circuit is controlled by the first circuit to selectively use the current sampling result to calculate a current duty cycle value or use a previous duty cycle value according to the comparison result; and (d) The output circuit generates an output current according to the current duty cycle value or the previous duty cycle value provided by the second circuit. The pulse width modulation detection method as described in item 12 of the patent application scope further includes: The first circuit generates a control signal to the second circuit according to the comparison result to control the operation of the second circuit. The pulse width modulation detection method as described in item 12 of the patent application scope further includes: An adjustment threshold value is set according to the frequency, and the adjustment threshold value is adjusted according to the previous duty cycle value, so as to determine whether the time during which the PWM signal is at a high level changes. The pulse width modulation detection method as described in item 12 of the patent application scope further includes: A plurality of previous duty cycle values are recorded, and if the amplitude between two previous duty cycle values in the plurality of previous duty cycle values is less than an adjustment threshold, it is determined that the time when the PWM signal is at a high level has changed. The pulse width modulation detection method as described in item 12 of the patent application scope further includes: Record a plurality of previous duty cycle values and encode it as a duty cycle variation profile according to the average difference between the previous duty cycle values of the plurality of previous duty cycle values, if the number of transitions of the duty cycle profile is 1 and the work If the periodic variation profile conforms to a specific profile, it is determined that the time when the PWM signal is at a high level has changed. The PWM detection method as described in claim 12, wherein when the comparison result is that the time when the PWM signal is at a high level has not changed, the second circuit in step (c) is This previous duty cycle value is inherited. The PWM detection method described in claim 12, wherein when the comparison result is that the time when the PWM signal is at a high level has changed, the second circuit in step (c) is The current duty cycle value is calculated according to the current sampling result. The pulse width modulation detection method as described in item 12 of the claimed scope, wherein step (c) comprises: (c1) is controlled by the first circuit to determine whether subsequent operation procedures need to be performed; and (c2) According to the judgment result of step (c1), selectively calculate the current duty cycle value or use the previous duty cycle value according to the current sampling result. The pulse width modulation detection method as described in item 12 of the claimed scope, wherein step (d) comprises: (d1) generating an output hysteresis signal according to the current duty cycle value or the previous duty cycle value provided by the second circuit; and (d2) generating the output current according to the output hysteresis signal.

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