TW202139398A - Semiconductor structure and package structure - Google Patents

Abstract

A semiconductor structure includes a base layer, semiconductor dies on the base layer, and an inter-die connection layer electrically connecting two adjacent semiconductor dies. Each of the semiconductor dies includes an active area and a seal ring area including a seal ring surrounding the active area. The inter-die connection layer extends over adjacent portions of the seal rings in the seal ring areas of the two adjacent semiconductor dies.

Description

Semiconductor structure and package structure

The field of semiconductor technology of the present invention particularly relates to a semiconductor packaging structure and a packaging structure.

Semiconductor packaging can not only provide protection for the semiconductor die from environmental pollutants, but also provide an electrical connection between the semiconductor die packaged in it and another device (such as a printed circuit board (PCB)). connect. For example, one or more semiconductor dies may be encapsulated in an encapsulating material and electrically connected to the substrate of the semiconductor package. Then, a bonding process can be used to electrically connect the semiconductor package to the printed circuit board. For example, the semiconductor package may have a bump structure on the bottom surface of the substrate, and the bump structure is mounted on a printed circuit board and electrically coupled to the printed circuit board. Different package types of semiconductor packages have been developed to improve the electrical performance of the die in the package.

Although the existing packaging structures are sufficient for their intended purpose, they are not completely satisfactory in all respects. For example, signal loss and/or power loss may occur between the die of the package structure. Therefore, there are still problems to be overcome regarding semiconductor structures and package structures having crystal grains obtained from semiconductor structures.

In view of this, the present invention provides a semiconductor packaging structure and a packaging structure to solve the above-mentioned problems.

According to a first aspect of the present invention, a semiconductor structure is disclosed, including: Basal layer Semiconductor die, on the base layer, each semiconductor die includes an active area and a seal ring area, the seal ring area includes a seal ring surrounding the active area; and The inter-grain connection layer electrically connects two adjacent semiconductor dies, and the inter-grain connection layer extends on the adjacent part of the seal ring in the sealing ring region of the two adjacent semiconductor dies .

According to a second aspect of the present invention, a package structure is disclosed, including: A substrate having a first surface and a second surface opposite to the first surface, wherein the substrate includes a redistribution layer; A polycrystalline grain component disposed above the first surface of the substrate and electrically coupled to the redistribution layer of the substrate, wherein the polycrystalline grain component includes: a base layer; a plurality of semiconductor dies on the base layer And are spaced apart from each other; and an inter-grain connection layer that electrically connects two adjacent semiconductor dies; wherein the inter-grain connection layer extends on the seal ring in the seal ring region of the two adjacent semiconductor dies .

The semiconductor structure of the present invention includes: a base layer; semiconductor crystal grains, on the base layer, each semiconductor crystal grain includes an active area and a sealing ring area, and the sealing ring area includes a sealing ring surrounding the active area; And an inter-grain connection layer, which electrically connects two adjacent semiconductor dies, and the inter-grain connection layer is on the adjacent part of the seal ring in the sealing ring region of the two adjacent semiconductor dies extend. Therefore, after the wafer sawing process is performed in the present invention, a package structure can be formed by arranging a multi-die component including two or more semiconductor die electrically connected to each other. The semiconductor dies of the multi-grain component provide fast and reliable signal transmission through the inter-grain connection layer between the semiconductor dies. This is because the electrical communication between adjacent semiconductor dies through the inter-grain connection layer can pass through the shortest path to fulfill. Therefore, since the signal loss (and/or power loss) between the semiconductor dies of the embodiment can be significantly reduced, it is similar to the package structure including the multi-die component having a plurality of semiconductor dies in the embodiment, and Compared with a package structure in which a conventional wafer has a plurality of dies alone, it has better electrical performance.

The following description is the best conceptual mode for implementing the present invention. This description is made to illustrate the general principle of the present invention, and should not be considered as limiting. The scope of the present invention is determined by the attached patent scope.

Hereinafter, the inventive concept will be fully described with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are shown. The advantages and features of the inventive concept and the method of realizing them will become apparent from the following exemplary embodiments, which will be described in more detail with reference to the accompanying drawings. However, it should be noted that the inventive concept is not limited to the following exemplary embodiments, and may be implemented in various forms. Therefore, the exemplary embodiments are provided only for disclosing the inventive concept, and for letting those with ordinary knowledge in the technical field know the category of the inventive concept. Moreover, the drawings shown are only schematic and are non-limiting. In the drawings, the size of some elements may be exaggerated and not drawn to scale for illustrative purposes. In the practice of the present invention, the size and the relative size do not correspond to the actual size.

The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular terms "a," "an," and "the" are also intended to include the plural, unless the context clearly dictates otherwise. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "contacting" to another element, it can directly connect or contact the other element, or intervening elements may be present.

Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. In contrast, the term "directly" means that there are no intervening elements. It should be understood that when used herein, the term "comprises" and/or "comprises" specifies the presence of the stated features, integers, steps, operations, elements and/or components, but does not exclude the presence or addition One or more other features, integers, steps, operations, elements, components, and/or combinations thereof.

In addition, for the convenience of description, the text such as "below", "below", "below", "above", and "below", "below", "below", "below", "below", "below Spatially relative terms such as "上" are used to describe the relationship between an element or feature and it. Another element or feature as shown in the figure. In addition to the orientations described in the figures, the spatially relative terms are also intended to cover different orientations of the device in use or operation. It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teaching of the present invention, the first element in some embodiments may be referred to as the second element in other embodiments. The exemplary embodiments of aspects of the inventive concept explained and illustrated herein include their complementary equivalents. Throughout the specification, the same or similar reference signs or reference signs indicate the same or similar elements.

Some embodiments of the invention are described. It should be noted that additional operations may be provided before, during, and/or after the stages described in these embodiments. For different embodiments, some of the described stages can be replaced or eliminated. Additional features can be added to the semiconductor device structure. For different embodiments, some of the features described below can be replaced or eliminated. Although some embodiments are discussed with operations performed in a specific sequence, these operations may be performed in another logical sequence.

1A and 1B are top views of an intermediate stage of a method for forming a semiconductor structure according to some embodiments of the present invention. The semiconductor structure may be a wafer including a plurality of semiconductor dies on the base layer 10. 1A and 1B depict a portion of the semiconductor die 11 on the base layer 10 to illustrate some embodiments. In some embodiments, each semiconductor die 11 includes an active area A _A and a sealing ring R _S surrounding the active area A _A. The active area A _A includes active components, such as an integrated circuit and one or more transistors. The sealing ring R _S protects the active components in the active area A _A from harmful contaminants such as moisture, moisture, particulates and/or ionic impurity.

As shown in FIGS. 1A and 1B, the semiconductor dies 11 on the base layer 10 may be arranged in a matrix pattern. In some embodiments, the semiconductor dies on the base layer are separated from each other through the spacer pattern SP. The spacing pattern SP includes a plurality of first spaces SP1 extending in the first direction D1 (for example, the X direction) and second spaces SP2 extending in the second direction D2 (for example, the Y direction). The second direction D2 is different from the first direction D1. For example, the second direction D2 (for example, the Y direction) is perpendicular to the first direction D1 (for example, the X direction). The first spaces SP1 are spaced apart from each other in the second direction D2, and the second spaces SP2 are spaced apart from each other in the first direction D1.

According to an embodiment of the present invention, several die components are formed after a wafer sawing process. Most of each die component includes two or more semiconductor dies 11, so these die components can be referred to as polycrystalline components. Each poly-die part may include a sealing frame F _S on the outside of the semiconductor die 11, wherein the sealing frame F _S surrounds the semiconductor die 11 to define a die area. In some embodiments, the sealing frame F _S also provide an effective environmental barrier that protects the semiconductor die 11 from moisture, moisture, particles or ionic impurities. As shown in FIG. 1B, as an example, four crystal grain regions 12 each including four semiconductor crystal grains 11 and two crystal grain regions 13 each including two semiconductor crystal grains 11 are shown. Furthermore, the semiconductor dies 11 in the die region 12/13 are electrically connected to each other _{through one or more inter-grain connection layers L IC.}

In this example, as shown in FIG. 1B, the first sealing frame F _S1 on the base layer 10 surrounds the first group (for example, four) of semiconductor die 11 to define the first die region 12-1 and the second die region 12-1. sealing frame 10 on the base layer F _S2 about the second set (e.g., four) of semiconductor dies 11 to define a second die region 12-2. The third sealing frame F _S3 on the base layer 10 surrounds the third group (for example, four) of semiconductor die 11 to define the third die region 12-3, and the fourth sealing frame F _S4 on the base layer 10 surrounds the fourth Groups (for example, four) of semiconductor dies 11 to define the fourth crystal grain region 12-4, and the fifth sealing frame FS5 on the base layer 10 surrounds the fifth group (for example, two) of semiconductor dies 11 to define the fifth crystal grain. The grain area 13-1, and the sixth sealing frame F _S6 on the base layer 10 surrounds the sixth group (for example, two) of semiconductor dies 11 to define the sixth grain area 13-2. The first crystal grain area 12-1, the second crystal grain area 12-2, the third crystal grain area 12-3, and the fourth crystal grain area 12-4 may be simply referred to as the crystal grain area 12, and the fifth crystal grain area 13 -1 and the sixth crystal grain region 13-2 may be simply referred to as the crystal grain region 13. Similarly, the first sealing frame F _S1 , the second sealing frame F _S2 , the third sealing frame F _S3 , the fourth sealing frame F _S4 , the fifth sealing frame F _S5 and the sixth sealing frame F _S6 may be simply referred to as the sealing frame F _S.

During the wafer sawing process, the scribe line LS passes through the space between the die regions 12/13 (defined by the sealing frame F _S ). In some embodiments, as shown in FIG. 1B, the scribe line LS between the die regions 12/13 includes a first scribe line LS1 extending in the first direction D1 (for example, the X direction) and a second direction D2. The second scribe line LS2 extending upward (for example, in the Y direction). As shown in FIG. 1B, the first scribing line LS1 passes through one of the first spaces SP1, and the second scribing line LS2 passes through one of the second spaces SP2. Specifically, according to some embodiments, each first scribing line LS1 overlaps with a part of a first space SP1, and each second scribing line LS2 overlaps with a part of a second space SP2.

In addition, as shown in FIG. 1B, the first scribe line LS1 is located between the fifth crystal grain region 13-1 and the sixth crystal grain region 13-2 (for example, passes through the space between them), and is located in the first crystal grain. The region 12-1 and the third crystal grain region 12-3 are also located between the second crystal grain region 12-2 and the fourth crystal grain region 12-4. The second scribe line LS2 is located between the first crystal grain region 12-1 and the second crystal grain region 12-2 (for example, passing through the space between them), and is also located between the third crystal grain region 12-3 and the fourth crystal grain region 12-3. Between the grain regions 12-4. The other second scribe line LS2 is located between the first crystal grain region 12-1 and the fifth crystal grain region 13-1, and is also located between the third crystal grain region 12-3 and the sixth crystal grain region 13-2 . It should be noted that there is no inter-grain connection layer extending over the neighboring die region to connect the semiconductor die of the neighboring die region. For example, there is no inter-grain connection layer extending on the first crystal grain region 12-1 and the second crystal grain region 12-2 to connect the semiconductor crystals of the first crystal grain region 12-1 and the second crystal grain region 12-2. grain. Therefore, according to the embodiment of the present invention, the inter-die connection layer is not cut during the wafer sawing process.

Figure 2 is a top view of a semiconductor structure according to some embodiments of the present invention. In some embodiments, the formation of several (plural) of a wafer of semiconductor die 11, and forming several sealing frame F _S on the base layer 10 to define a die region (e.g., region including crystal grains in the underlayer 10 12, 13, and 14). In FIG. 2, most of the die regions include two or more semiconductor die 11. For example, the wafer in FIG. 2 includes nine die regions 12, four die regions 13 and four die regions 14. Each die region 12 includes four semiconductor die 11, each die region 13 includes two semiconductor die 11, and each die region 14 includes one semiconductor die 11. It should be noted that the arrangement of the crystal grain regions and the number of semiconductor crystal grains provide an exemplary illustrative example in each of the crystal grain regions shown in FIG. 2, and the present invention is not limited thereto.

In addition, as shown in FIG. 2, in some embodiments, a first scribing line LS1 (such as the X direction) extending in the first direction D1 and a second scribing line LS2 (such as the Y direction) extending in the second direction D2 pass through Pass the space between two adjacent grain regions 12, 13, and 14. If the semiconductor crystal grain 11 in each of the crystal grain regions 12 and 13 manufactured on the base layer 10 has the same function, the crystal grain regions 12 and 13 may be referred to as a polycrystalline grain component region. However, the semiconductor die 11 on the base layer 10 may have the same function or different functions.

In addition, although FIG. 2 depicts the semiconductor die 11 in one of the die regions 12 or 13 as being separated from each other, two adjacent semiconductor die 11 in one of the die regions 12 or 13 are electrically connected to each other , Can be realized _{through, for example, one of the inter-grain connection layers L IC} in FIG. 1B or another of the plurality of inter-grain connection layers L IC. According to some embodiments of the present invention, after the wafer sawing process is performed, a package structure may be formed by arranging a multi-die component including two or more (for example, four) semiconductor die 11 electrically connected to each other . The semiconductor die 11 of the polycrystalline component provides fast and reliable signal transmission through the inter-grain connection layer between the semiconductor die 11, because the electrical communication between adjacent semiconductor die 11 (for example, through the die Interconnection layer) can be achieved through the shortest path. Therefore, since the signal loss (and/or power loss) between the semiconductor dies 11 (electrically connected to each other via the inter-die connection layer L _IC ) of the embodiment can be significantly reduced, it is similar to that in the embodiment that has plural The packaging structure of a multi-die component of a semiconductor die 11 has better electrical performance than a packaging structure having a plurality of dies separately from a conventional wafer. As shown in FIG. 2, the semiconductor structure in this embodiment includes: a first sealing frame on the base layer and surrounding a first group of semiconductor die (for example, including two or four or one semiconductor die), wherein the The first sealing frame defines a first die region; and a second sealing frame on the base layer and surrounding a second group of semiconductor die (for example, including two or four or one semiconductor die), wherein the second sealing The frame defines a second crystal grain area, wherein the second crystal grain area is adjacent to the first crystal grain area, and a scribe line is located between the first crystal grain area and the second crystal grain area. Wherein, there is no inter-grain connection layer extending above the first crystal grain region and the second crystal grain region. Wherein, the number of semiconductor crystal grains (for example, including two semiconductor crystal grains) in the first crystal grain region and the number of semiconductor crystal grains (for example, including two or four or one semiconductor crystal grains) in the second crystal grain region are Grains) the same or different. The semiconductor structure further includes: a third sealing frame on the base layer and surrounding the third group of semiconductor die, wherein the third sealing frame defines a third die region, and the semiconductor die in the third die region is The number is different from the number of semiconductor crystal grains in the second crystal grain region. Wherein, the third crystal grain area is adjacent to the first crystal grain area or the second crystal grain area, and another scribe line is located between the third crystal grain area and the first crystal grain area or the second crystal grain area. Between regions.

For the sake of example, the details of the inter-grain connection layer for connecting adjacent semiconductor dies in a single die region are provided below.

FIG. 3 is a top view of a die region of a semiconductor structure according to some embodiments of the present invention. 4 is a cross-sectional view taken along the cross-sectional line 4-4 of the semiconductor structure in FIG. 3. FIG. 5 is a cross-sectional view taken along the cross-sectional line 5-5 of the semiconductor structure in FIG. 3. According to some embodiments of the present invention, the top view of two adjacent semiconductor die in the die region in FIG. 3.

Features/components in FIGS. 3, 4, 5, and 6 that are similar or identical to those in FIGS. 1A, 1B, and 2 are denoted by similar or identical reference numerals, and these similar or identical features /Parts will not be repeated here. In addition, it should be noted that according to some embodiments of the present invention, the structures in FIG. 3, FIG. 4, FIG. 5, and FIG. 6 are provided for illustrating electrical connections between adjacent semiconductor dies in one die region. An applicable design. The present invention is not limited to this.

As shown in FIG. 3, in some embodiments, the die region 12 is on the base layer 10, and the die region 12 includes four semiconductor dies 11-1, 11-2, 11-3, and 11-4. The base layer 10 has a top surface 101 and a bottom surface 102 opposite to the top surface 101, wherein semiconductor die (for example, semiconductor die 11-1 and 11-2) are disposed on the top surface 101 of the base layer 10. The semiconductor die 11-1 includes an active area A _A1 and a sealing ring R _S1 surrounding the active area A _A1 . The semiconductor die 11-2 includes an active area A _A2 and a sealing ring R _S2 surrounding the active area A _A2 . The semiconductor die 11-3 includes an active area A _A3 and a sealing ring R _S3 surrounding the active area A _A3 . The semiconductor die 11-4 includes an active area A _A4 and a sealing ring R _S4 surrounding the active area A _A4 . _{The sealing frame F S} on the base layer 10 surrounds the semiconductor die 11-1, 11-2, 11-3 and 11-4 to define the die region 12. It should be noted in the present invention that the base layer 10 is made of wafers, and the wafers may include single crystal silicon, polycrystalline silicon or compound wafers (such as gallium arsenide, gallium nitride, etc.), which can all be used for production electronics. Crystal wafers), and silicon wafers. Therefore, the base layer 10 includes the material of the wafer, such as silicon, and the base layer 10 also includes transistors, as well as source/drain contacts, gate contacts, etc., and the base layer 10 does not include wiring or winding, etc. (such as copper Layers, etc.). Therefore, the base layer 10 is completely different from the substrate or printed circuit board, including the materials used (the substrate or printed circuit board, including resin, copper layer, etc.), the process used, and the structure (the substrate or printed circuit board, etc.) The wiring layers such as copper alternate with resins, etc., and the base layer 10 is formed on a single piece of silicon wafer through photolithography, etching and other steps).

In addition, the semiconductor dies 11-1, 11-2, 11-3, and 11-4 may be arranged in a 2×2 matrix and spaced apart from each other. For example, the semiconductor die 11-1 is spaced apart from the semiconductor die 11-3 through the first space SP1, and is spaced from the semiconductor die 11-2 through the second space SP2. Similarly, the semiconductor die 11-4 is spaced apart from the semiconductor die 11-2 through the first space SP1, and is spaced from the semiconductor die 11-3 through the second space SP2. Furthermore, the semiconductor dies are electrically connected to each other through the inter-die connection layer L _IC. For example, the semiconductor die 11-1 is _{electrically connected to the semiconductor die 11-2 through the inter-die connection layer L IC1} , and the semiconductor die 11-2 is electrically connected to the semiconductor die 11-4 through the inter-die connection layer L _IC2. . Similarly, the semiconductor die 11-1 is electrically connected to the semiconductor die 11-3 through the inter-grain connection layer L _IC3 , and the semiconductor die 11-3 is electrically connected to the semiconductor die 11- through the inter-grain connection layer L _IC4. 4.

4 is a cross-sectional view taken along the cross-sectional line 4-4 of the semiconductor structure in FIG. 3, where the cross-sectional line 4-4 passes through a position between the _{inter-crystalline connection layers L IC1.} Therefore, according to some embodiments of the present invention, FIG. 4 only depicts the structure of the sealing ring of two adjacent semiconductor dies 11-1 and 11-2, without any inter-die connection layer L _IC1 .

As shown in FIG. 4, in some embodiments, the semiconductor die 11-1 includes a seal ring area A _R1 and an active area A _A1 , and the semiconductor die 11-2 includes a seal ring area A _R2 and an active area A _A2. . The active areas A _A1 and A _A2 may include active elements such as transistors and integrated circuits. Each of the seal ring areas A _R1 and A _R2 may include a plurality of interconnection stacks stacked vertically to provide mechanical protection and moisture protection for the _{active areas A A1} and A _A2.

In this example, three interconnect stacks on the base layer 10 (for example, on the top surface 101 of the base layer 10) form a sealing ring of the semiconductor die. As shown in FIG. 4, the sealing ring R _{S1 of the} semiconductor die 11-1 includes a first interconnect stack 211 above the base layer 10 and surrounding the active area A _A1 , on the first interconnect stack 211 and surrounding the active area A A1. a _A1 region second interconnect stack 212, and a second interconnect stack 212 and stack 213 around the third active region a _A1 of interconnection. The first interconnect stack 211 includes a plurality of first conductive lines 211L and first conductive vias 211V connected to the first conductive lines 211L. The second interconnection stack 212 includes a plurality of second conductive lines 212L and second conductive vias 212V, wherein the second conductive vias 212V connect two adjacent second conductive lines 212L and connect the lowermost second conductive line 212L and the uppermost second conductive line 212L.的第一线211L。 The first wire 211L. The third interconnection stack 213 includes at least one third conductive line 213L and several third conductive vias 213V, wherein the third conductive via 213V connects the third conductive line 213L and the uppermost second conductive line 212L.

In some embodiments, the first wire 211L of the first interconnection stack 211, the second wire 212L of the second interconnection stack 212, and the third wire 213L of the third interconnection stack 213 are respectively formed of a first metal layer (for example, , M1), the second metal layer (for example, M2), and the third metal layer (for example, M3). For example, the first wire 211L and the second wire 212L are made of copper (Cu), and the third wire 213L is made of aluminum (Al). The outermost third wire 213L is made of aluminum (Al), which has better oxidation resistance and can protect the internal copper layer and other structures. In addition, in some embodiments, wherein each of the first conductive lines 211L has a first thickness t1, each of the second conductive lines 212L has a second thickness t2, and each of the third conductive lines 213L has a third thickness t3. The thickness t2 is greater than the first thickness t1, and the third thickness t3 is greater than the second thickness t2, but is not limited thereto. In this embodiment, starting from the base layer 10, the metal layers or wires that go up can be thicker and thicker to facilitate manufacturing. At the same time, metal layers or wires with a smaller thickness in the lower layer can be used to transmit signals, etc., while the thickness of the upper layer is larger. The metal layer or wire can be used to connect to power or ground. Therefore, in this embodiment, the metal layers or wires with different functions are arranged separately to improve work efficiency and prevent crosstalk.

In addition, in this example, as shown in FIG. 4, the active area A _{A1 of the} semiconductor die 11-1 includes a first conductive stack 311 above the base layer 10, and a second conductive stack on the first conductive stack 311. 312 and the third conductive stack 313 on the second conductive stack 312 are used to form an integrated circuit of the semiconductor die 11-1. In some embodiments, the first conductive stack 311 includes a plurality of wires 311L and a plurality of conductive vias 311V, the second conductive stack 312 includes two wires 312L and a plurality of conductive vias 312V, and the third conductive stack 313 includes one A wire 313L and a plurality of conductive vias 313V. The third conductive stack 313 is electrically connected to the second conductive stack 312, and the second conductive stack 312 is electrically connected to the first conductive stack 311. The first conductive stack 311 may be electrically connected to one or more active elements (for example, transistors) in the base layer 10. In some embodiments, the wires 311L of the first conductive stack 311, the wires 312L of the second conductive stack 312, and the wires 313L of the third conductive stack 313 are respectively composed of a first metal layer (for example, M1) and a second metal layer. A layer (such as M2) and a third metal layer (such as M3) are formed.

Similarly, in some embodiments, as shown in FIG. 4, the semiconductor die 11-2 R _S2 comprises a sealing ring above the base layer 10 surrounding the active region and a first interconnect stack 221 A _A2, the first The second interconnection stack 222 above the interconnection stack 221 and surrounding the active area A _A2 , and the third interconnection stack 223 above the second interconnection stack 222 and surrounding the active area A _A2. The first interconnection stack 221 includes a plurality of first conductive lines 221L and first conductive vias 221V connected to the first conductive lines 221L. The second interconnection stack 222 includes a plurality of second conductive lines 222L and second conductive vias 222V, wherein the second conductive via 222V connects two adjacent second conductive lines 222L and connects the lowermost second conductive line 222L and the uppermost second conductive line 222L. The first wire 221L. The third interconnection stack 223 includes at least one third wire 223L and a plurality of third conductive vias 223V, wherein the third conductive via 223V connects the third wire 223L and the uppermost second wire 222L. In some embodiments, the first wire 221L of the first interconnection stack 221, the second wire 222L of the second interconnection stack 222, and the third wire 223L of the third interconnection stack 223 are respectively composed of a first metal layer (for example, M1), a second metal layer (for example, M2), and a third metal layer (for example, M3) are formed.

In addition, in this example, as shown in FIG. 4, the active area AA2 of the semiconductor die 11-2 includes a first conductive stack 321 located above the base layer 10, and a second conductive stack 322 located on the first conductive stack 321. And the third conductive stack 323 on the second conductive stack 322 is used to form an integrated circuit of the semiconductor die 11-2. In some embodiments, the first conductive stack 321 includes a plurality of wires 321L and a few conductive vias 321V, the second conductive stack 322 includes two wires 322L and a few conductive vias 322V, and the third conductive stack 323 includes one Wire 323L and several conductive vias 323V. The third conductive stack 323 is electrically connected to the second conductive stack 322, and the second conductive stack 322 is electrically connected to the first conductive stack 321. The first conductive stack 321 may be electrically connected to one or a plurality of active elements (for example, a transistor, not shown) in the base layer 10. In some embodiments, the wires 321L of the first conductive stack 321, the wires 322L of the second conductive stack 322, and the wires 323L of the third conductive stack 323 are respectively composed of a first metal layer (for example, M1) and a second metal layer. A layer (for example, M2) and a third metal layer (for example, M3) are formed.

In some embodiments, as shown in FIG. 4, the semiconductor die 11-1 further includes a dummy area A _{D1 between the seal ring area A R1} and the active area A1. The dummy area A _D1 may include several (plural) wires 311D, 312D, 313D, and wires 311D, 311D, 313D, which are similar to the stack of conductive stacks (eg 311-313) in the active area A _A1. 312D and 313D can be formed on the same layer as the wires 311L, 312L, and 313L, for example, in the same manufacturing process. Moreover, the semiconductor die further includes a dummy region 11-2 A _D2 between the seal ring region and the active region A _R2 to A _A2. The dummy area A _D2 may include several (plural) wires 321D, 322D, and 323D similar to the stack of conductive stacks (eg 321-323) in the active area A _{A2 (eg, 321L-323L).} 322D and 323D can be formed on the same layer as the wires 321L, 322L, and 323L, for example, in the same manufacturing process. The dummy areas A _D1 and A _{D2 are} used as buffers, _{and the wires in the dummy areas A D1} and A _D2 will enhance the conductive stack of the wafer after the sawing process is performed along the scribe line between the die areas (for example, 311- 313) the mechanical strength of the wire (such as 311L-313L). The metal layers or wires in the dummy areas A _D1 and A _D2 may not be connected to other metal layers or wires, for example, floating, and adding metal layers and wires to the above two areas can also protect the active area A _A1 In the conductive stack, and increase the overall mechanical strength of the semiconductor structure.

5 is a cross-sectional view taken along the cross-sectional line 5-5 of the semiconductor structure in FIG. 3, wherein the cross-sectional line 5-5 passes through a position corresponding to the _{inter-crystalline connection layer L IC1.} Therefore, according to some embodiments of the present invention, FIG. 5 shows that a plurality of inter-die connection layers L _{IC1 pass through the seal ring area A R1 of the} semiconductor die 11-1 and the seal ring area A of the semiconductor die 11-2. _R2 . FIG 6 shows a top view of a semiconductor die 11-1 and 11-2, wherein the grain layer L _IC1 is connected through a concave portion 21R of the seal ring and the seal ring R _S1 R _S2 concave portion 22R. 6, the seal ring R _S1 of the concave portion 21R disposed side by side in a second direction D2 (e.g., Y direction). The concave portion 21R and the sealing ring opposite the sealing R _S1 R _S2 ring portion 22R of the recess in the second direction D2 (e.g., Y direction) and separated from each other. It should be noted that in FIGS. 5, 6 and 4, similar or identical reference numerals are used to denote similar or identical features/components, and the details of similar or identical features/components (such as their structure and materials) This will not be repeated. In this embodiment, the inter-die connection layers 421, 422, and 433 are electrically insulated _{from the sealing ring (for example, the sealing ring R S1} and the sealing ring R _{S2 ).} In the prior art, the position of the recesses 21R and 31R is the structure of the seal ring (for example, the structure of the seal ring formed by layered metal layers), because it is not necessary here (the position of the recesses 21R and 31R) in the prior art Leave a place to provide the connection between the dies (in the prior art, the dies are cut into individual pieces, and the individual dies are connected through the substrate or the redistribution layer structure after the split). In the embodiment of the present invention, there is no seal ring structure in the prior art, or the seal ring structure in the prior art is removed, thereby forming (or assuming forming) recesses 21R and 31R, which are used in this embodiment The inter-grain connection layers 421, 422, and 433 pass through and are formed in the recesses 21R and 31R to electrically connect adjacent dies. In addition, the inter-die connection layers 421, 422, and 433 in the embodiment of the present invention are different from the leads or wires in the prior art. The leads or wires in the prior art are drawn from the pads of one die to another. On the pad of a die, and the lead or wire is formed by using the lead or wire to connect outside the metal layer of the die; the inter-grain connection layer in the present invention can be formed together with the metal layer in the die, The structure is obviously different, there is no need to leave a pad for the connection between the dies, and the manufacturing process is simpler and more convenient, and at the same time, it avoids the shortcomings of the prior art that the wire bonding electrical connection is unstable and easy to damage.

As shown in FIGS. 5 and 6, the adjacent portions of the sealing rings RS1 and RS2 of the two adjacent semiconductor dies 11-1 and 11-2 have recesses 21R and 22R, and the inter-grain connection layer L _IC1 passes through Concavities 21R and 22R. Each of the recesses 21R and 22R may correspond to one or two of the interconnected stack of seal rings. In some embodiments, the second interconnect stack 212 of the _{seal ring R S1} has a first recess 211R, and the third interconnect stack 213 of the _{seal ring R S1 has a second recess 212R.} The second recess 212R communicates with the first recess 211R. The first recess 211R and the second recess 212R form a recess 21R of the _{seal ring R S1.} Similarly, the second seal ring R _S2 interconnect stack 222 having a first recessed portion 221R, and the sealing ring RS2 third interconnect stack 223 has a second recessed portion 222R. The second recess 222R communicates with the first recess 221R. The first recess and the second recess portion 221R 222R seal ring R _S2 is formed a recess 22R. Wherein the first recess 221R may have one or more inter-grain connecting layers passing through, the second recess 222R may have one or more inter-grain connecting layers passing through, and the recess 31R may have one or more crystal grains. The inter-connection layer passes through, and the above can be set freely according to design requirements.

In this example, three inter-die connection layers 421, 422, and 423 (referred to as inter-die connection layers L _IC1 ) are constructed to electrically connect two adjacent semiconductor die. 5, the grain layers 421 and 422 connected to the first recess portion 211R through the sealing ring and the seal ring of R _S1 R _S2 of the first recess portion 221R. In some embodiments, the inter-die connection layers 421 and 422, the second wire 212L of the second interconnection stack 212, and the second wire 222L of the second interconnection stack 222 are made of the same material (for example, the second metal Layer (for example, M2)). Furthermore, as shown in FIGS. 4 and 5, the inter-die connection layers 421 and 422 are at the same level (same layer) as the second wires 212L and 222L. The inter-die connection layers 421 and 422 can connect the active elements of the semiconductor dies 11-1 and 11-2, and the inter-die connection layer 423 can also connect the active elements of the semiconductor dies 11-1 and 11-2. In addition, although the inter-grain connection layers 421, 422, and 423 may be disconnected in the figure, this is because the figure is a cross-sectional view. In fact, each of the inter-grain connection layers 421, 422, and 423 is It is interconnected, not disconnected.

In addition, as shown in FIG. 5, the inter-die connection layer 423 penetrates _{the second recess 212R of the seal ring R S1 and} the second recess 222R of the seal ring R _S2 . In some embodiments, the inter-die connection layer 423, the third wire 213L of the third interconnection stack 213, and the third wire 223L of the third interconnection stack 223 are made of the same material (for example, a third metal layer (eg, M3) made of materials). Moreover, as shown in FIGS. 4 and 5, the inter-die connection layer 423 is at the same level (the same layer) as the third wires 213L and 223L. The inter-die connection layer 423 can connect other active elements of the semiconductor die 11-1 and 11-2.

The first wires (for example, 211L and 221L) and the third wires (for example, 213L and 223L) may be made of different materials. The second wires (for example, 212L and 222L) and the third wires (for example, 213L and 223L) may be made of different materials. For example, the first wires (eg, 211L and 221L) and the second wires (eg, 212L and 222L) are made of copper (Cu), and the third wires (eg, 213L and 223L) are made of aluminum (Al). In addition, in some embodiments, each of the first conductive lines 211L and 221L has a first thickness t1, each of the second conductive lines 212L and 222L has a second thickness t2, and each of the third conductive lines 213L and 223L has a third thickness t3. , Wherein the second thickness t2 is greater than the first thickness t1, and the third thickness t3 is greater than the second thickness t2. In some embodiments, each of the inter-die connection layers 421, 422, and 433 has a thickness (for example, t2) greater than the thickness (for example, t1) of each of the first conductive lines 211L and 221L. Moreover, in some embodiments, the inter-grain connection layer 423 (such as the connection layer between the dies formed by the third metal layer (M3)) has a third thickness t3, which is greater than the first wire 211L And the thickness of any one of 221L (for example, t1). In addition, in some embodiments, the third thickness t3 of the inter-grain connection layer 423 is greater than the second thickness t2 of each of the inter-grain connection layers 421 and 422.

In addition, in some embodiments, as shown in FIGS. 4 and 5, each semiconductor die further includes a dummy area surrounding the active area and located between the seal ring area and the active area. For example, as described above, the dummy area _{AD1 is} formed between the seal ring area _AR1 and the active area AA1 of the semiconductor die 11-1, and the dummy area _{AD2 is} formed between the seal ring area _AR2 and the semiconductor die 11-2. The active area between _{A and A2.} In some embodiments, as shown in FIGS. 5 and 6, further through the connection layer L _IC1 concave portion 32R in the dummy region A _D1 concave portion 31R and the dummy region AD2 of the grain. As shown in FIG. 6, _{the recesses 31R in the dummy area A D1} are arranged in the second direction D2 (for example, the Y direction) and are separated from each other. Arranged and separated from each other with the concave portion 31R of the dummy region A _D1 A _D2 dummy region opposing a recess 32R in the second direction D2 (e.g., Y direction).

It should be noted that the number of _{inter-grain connection layers L IC1} can be changed and determined according to the design requirements of the semiconductor structure to be formed in the application. Some variations of the embodiment are provided below for illustration.

Figure 7A is a cross-sectional view of a semiconductor structure according to some embodiments of the present invention. Referring to FIGS. 4 and 7A, two inter-die connecting layers are formed as conductive bridges between adjacent semiconductor die. It should be noted that in FIGS. 7A and 4-5, similar or identical reference numerals are used to denote similar or identical features/components, and the details of similar or identical features/components (such as their structure and materials) are described herein. Do not repeat it again.

The difference between the semiconductor structure of FIG. 7A and the semiconductor structure of FIG. 5 lies in the number of _{inter-grain connection layers L IC1 for electrically connecting semiconductor dies 11-1 and 11-2.}

In FIG. 7A, two inter-grain connecting layers L _IC1 (including one inter-grain connecting layer 423 and one inter-grain connecting layer 422) are configured to electrically connect two adjacent semiconductor dies. 7A, in some embodiments, the grain layer 211R 422 is connected through the sealing ring of the first recess portion R _S1 'of the first recess and the sealing ring in R _S2 221R'. Further, in this example, the grain layer 422 is further connected through a recess 32R in the dummy region A _D1 concave portion 31R and the dummy region AD2, shown in Figure 7A. In some embodiments, the inter-die connection layer 422, the second wire 212L of the second interconnect stack 212, and the second wire 222L of the second interconnect stack 222 are made of the same material (for example, the second metal layer (for example, M2) ) Material) made. Moreover, the inter-die connection layer 422 is flush with one of the second wires 212L or 222L. For example, the inter-die connection layer 422 is flush with the uppermost layer of the second wires 212L and 222L, as shown in FIG. 7A.

In addition, as shown in FIG. 7A, the inter-die connection layer 423 penetrates _{the second recess 212R of the seal ring R S1 and} the second recess 222R of the seal ring R _S2 . In addition, in this example, the inter-grain connection layer 423 further penetrates the recess 31R in the dummy area AD1 and the recess 32R in the dummy area AD2, as shown in FIG. 7A. In some embodiments, the inter-die connection layer 423, the third wire 213L of the third interconnection stack 213, and the third wire 223L of the third interconnection stack 223 are made of the same material (for example, a third metal layer (eg, M3)) made of materials). Moreover, the inter-die connection layer 423 is flush with the third wires 213L and 223L, as shown in FIG. 4 and FIG. 7A. The inter-die connection layer 422 can connect the active elements of the semiconductor dies 11-1 and 11-2, and the inter-die connection layer 423 can connect other active elements of the semiconductor dies 11-1 and 11-2.

In addition, the recess 21R of the seal ring R _S1 and the recess 22R of the _{seal ring R S2} in FIG. 5 are deeper than the recess 21R' _{of the seal ring R S1} and the recess 22R' of the _{seal ring R S2 in FIG.} Multi-layer inter-grain connection layer. For example, the first recesses 211R and 221R in FIG. 5 (the two inter-grain connection layers 421 and 422R pass through) are larger than the first recesses 211R' and 221R' (one inter-grain connection layer 422 passes through) in FIG. 7A. Deeper.

Figure 7B is a cross-sectional view of a semiconductor structure according to some embodiments of the present invention. Referring to FIGS. 4 and 7B, one inter-die connection layer is formed as a conductive bridge between adjacent semiconductor die, and the sealing ring is formed by two interconnection stacks. It should be noted that in FIGS. 7B and FIGS. 4-5, similar or identical reference numerals are used to denote similar or identical features/components, and the details of similar or identical features/components (such as their structure and materials) are described herein. Do not repeat it again.

The difference between the semiconductor structure of FIG. 7B and the semiconductor structure of FIG. 5 includes: the number of interconnect stacks of the seal ring and the number of inter-grain connection layers L _{IC1 for electrically connecting semiconductor dies 11-1 and 11-2} .

In FIG. 7B, two interconnected stacks on the base layer 10 form a sealing ring of the semiconductor die. For example, the sealing ring R _{S1 of the} semiconductor die 11-1 includes a first interconnect stack 211 above the base layer 10 and a second interconnect stack 212 on the first interconnect stack 211, wherein the first interconnect stack 211 And the second interconnect stack 212 surround the active area AA1. The first interconnect stack 211 includes a plurality of first conductive lines 211L and first conductive vias 211V connected to the first conductive lines 211L. The second interconnection stack 212 includes a plurality of second conductive lines 212L and second conductive vias 212V, wherein the second conductive vias 212V connect two adjacent second conductive lines 212L and connect the lowermost second conductive line 212L and the uppermost second conductive line 212L.的第一线211L。 The first wire 211L. In some embodiments, the first conductive line 211L of the first interconnection stack 211 is formed of a first metal layer (for example, M1), and the second conductive line 212L of the second interconnection stack 212 is formed of a second metal layer (for example, M2). )form.

In addition, as shown in FIG. 7B, the active area AA1 of the semiconductor die 11-1 includes a first conductive stack 311 located above the base layer 10 and a second conductive stack 312 located on the first conductive stack 311, for forming a semiconductor Integrated circuit of die 11-1. In some embodiments, the first conductive stack 311 includes several conductive lines 311L and several conductive vias 311V. The second conductive stack 312 includes two conductive lines 312L and several conductive vias 312V. The second conductive stack 312 is electrically connected to the first conductive stack 311. The first conductive stack 311 may be electrically connected to one or a plurality of active elements (for example, transistors) in the base layer 10. In some embodiments, the conductive stack 311L of the first conductive stack is formed of a first metal layer (eg, M1), and the conductive stack 312L of the second conductive stack 312 is formed of a second metal layer (eg, M2). form.

Similarly, in some embodiments, as shown in FIG. 7B, the sealing ring RS2 of the semiconductor die 11-2 includes a first interconnect stack 221 located above the base layer 10 and a second interconnect stack 221 located on the first interconnect stack 221 The interconnection stack 222, wherein the first interconnection stack 221 and the second interconnection stack 222 surround the active area AA2. The first interconnection stack 221 includes a plurality of first conductive lines 221L and first conductive vias 221V connected to the first conductive lines 221L. The second interconnection stack 222 includes a plurality of second conductive lines 222L and second conductive vias 222V, wherein the second conductive via 222V connects two adjacent second conductive lines 222L and connects the lowermost second conductive line 222L and the uppermost second conductive line 222L. The first wire 221L. In some embodiments, the first wire 221L of the first interconnect stack 221 is formed of a first metal layer (for example, M1), and the second wire 222L of the second interconnect stack 222 is formed of a second metal layer (for example, M2). )form.

In addition, in this example, as shown in FIG. 7B, the active area AA2 of the semiconductor die 11-2 includes a first conductive stack 321 located above the base layer 10 and a second conductive stack 322 located on the first conductive stack 321 , Used to form an integrated circuit of semiconductor die 11-2. In some embodiments, the first conductive stack 321 includes several conductive lines 321L and several conductive vias 321V. The second conductive stack 322 includes two conductive lines 322L and several conductive vias 322V. The second conductive stack 322 is electrically connected to the first conductive stack 321. The first conductive stack 321 may be electrically connected to one or a plurality of active elements (for example, a transistor, not shown) in the base layer 10. In some embodiments, the first conductive stack 321 in the first conductive stack 321 of the first conductive stack 321 of the wire 321L is formed of a first metal layer (for example, M1), and the wire of the second conductive stack 322 322L is formed of a second metal layer (for example, M2).

In FIG. 7B, the inter-die connection layer 422 is configured to electrically connect two adjacent semiconductor die. For example, the power element of the semiconductor die 11-1 is electrically connected to the power element of the semiconductor die 11-2 through the inter-die connection layer 422. As shown in FIG. 7B, in some embodiments, the inter-die connecting layer 422 passes through the recess 21R" of the seal ring RS1 and the recess 22R" of the seal ring RS2. In addition, in this example, the inter-grain connection layer 422 further penetrates the recess 31R in the dummy area AD1 and the recess 32R in the dummy area AD2, as shown in FIG. 7B. In some embodiments, the inter-die connection layer 422, the second wire 212L of the second interconnect stack 212, and the second wire 222L of the second interconnect stack 222 are made of the same material (for example, the second metal layer (for example, M2) Material). Moreover, the inter-die connection layer 422 is flush with one of the second wires 212L or 222L (on the same layer, or on the same level). For example, the inter-die connection layer 422 is flush with the uppermost layer of the second wires 212L and 222L, as shown in FIG. 7B.

Although in some embodiments, the above-mentioned inter-die connection layer is formed in the recess of the sealing ring of the semiconductor die, the present invention is not limited thereto. In some other embodiments, an inter-grain connection layer may be formed above the sealing ring of two adjacent semiconductor dies in the die region without making any part of the sealing ring recessed.

FIG. 8 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present invention. It should be noted that in FIG. 8 and FIG. 4, FIG. 5, FIG. 7A and FIG. 7B, similar or identical reference numerals are used to denote similar or identical features/components, and similar or identical features/components (for example, their structures) And materials) details are not repeated here.

As shown in FIG. 8, each sealing ring includes several interconnected stacks above the base layer 10. For example, the sealing ring R _{S1 of the} semiconductor die 11-1 includes a first interconnection stack 211 above the base layer 10 and surrounding the active region A _{A1, and} a first interconnection stack 211 on the first interconnection stack 211 and surrounding the active region A _A1 The second interconnection stack 212, and the third interconnection stack 213 on the second interconnection stack 212 and surrounding the active area A _A1. 11-2 semiconductor die comprises a seal ring R _S2 and stacked over the base layer 10 around the first interconnection 221 A _A2 of the active region, a first interconnect stack on the active region 221 and surrounds the second A _A2 The interconnection stack 222, and the third interconnection stack 221 located on the second interconnection stack 222 and surrounding the active area A _A2.

In some embodiments, as shown in FIG. 8, an inter-die connection layer 501 is formed over those interconnect stacks (for example, 211/212/213 and 221/222/223). Similarly, grain extends over an adjacent portion of the connection layer 501 and the sealing ring the sealing ring RS1 A _R2 region of the sealing ring RS2 in the semiconductor die seal ring region A _R1 11-1 and 11-2 in. The inter-die connection layer 501 can connect the active elements of the semiconductor die 11-1 and 11-2 through the conductive via 501V, thereby serving as a bridge between the semiconductor die 11-1 and 11-2.

In addition, in some embodiments, as shown in FIG. 8, the inter-die connection layer 501 and the interconnect stack (for example, 211-213 and 221-223 of the sealing rings R _S1 and R _S2 ) are made of the same material. However, the present invention is not limited to this. The material of the inter-die connection layer 501 may be the same as or different from the material of the uppermost wires (for example, the third wires 213L and 223L) of the _{sealing rings R S1} and R _S2.

FIG. 9A is a top view of a multi-grain component 120 according to some embodiments of the present invention. After the wafer sawing process is performed along the scribe lines between the die regions on the wafer (as shown in Figure 2), several multi-grain parts can be obtained. Each poly-die component may include two or more semiconductor die. In this example, as shown in FIG. 9A, a multi-grain part 120 including four semiconductor dies 11-1, 11-2, 11-3, and 11-4 is exemplified. It should be noted that in FIG. 9A, FIG. 1B and FIG. 3, similar or identical reference numerals are used to indicate similar or identical features/components. The semiconductor dies 11-1, 11-2, 11-3, and 11-4 (such as structures and materials) and related components (such as the sealing frame F _S , the first space SP1, the second space SP2, and the crystal grains) described above The details of the intergranular connection layers L _IC1 -L _IC4 will not be repeated.

FIG. 9B is a cross-sectional view of a package structure 120P including the multi-die component 120 in FIG. 9A according to some embodiments of the present invention. Due to the cross-sectional view, FIG. 9B only shows the semiconductor dies 11-1 and 11-2 of the multi-grain component 120 in the package structure 120P. In addition, it should be noted that depending on the design requirements of the application, two or more multi-grain components may be arranged on the substrate of the package structure. In order to simplify the figure, a multi-die component 120 is disposed on the substrate 100 of the package structure 120P.

In some embodiments, the package structure 120P includes a substrate 100 and a multi-die component 120 bonded to the substrate 100. In this example, as shown in FIG. 9B, the substrate 100 has a first surface 100a and a second surface 100b opposite to the first surface 100a. The substrate 100 includes a redistribution pattern 100L having a redistribution layer (RDL) and other elements (for example, conductive vias and conductive pads). The layout of the redistribution pattern 100L is determined according to the substrate design of the present application. In some embodiments, the multi-die part 120 is arranged on the first surface 100 a of the substrate 100, and the multi-die part 120 is electrically coupled to the redistribution layer of the redistribution pattern 100L in the substrate 100.

In some embodiments, the substrate 100 further includes an inter-metal dielectric (IMD) layer 100M, and the redistribution pattern 100L is embedded in the inter-metal dielectric layer 100M. In some embodiments, the intermetal dielectric layer may be formed of organic materials including polymer base materials, including non-organic materials such as silicon nitride (SiNx), silicon oxide (SiOx), graphene, and the like. For example, the intermetal dielectric layer is made of a polymer base material. It should be noted that the number and configuration of intermetal dielectric layers, conductive pads, conductive vias, and redistribution layers shown in FIG. 9B are only exemplary and do not limit the present invention.

In some embodiments, the multi-die component 120 is on the base layer 10 and includes a plurality of semiconductor die, such as semiconductor die 11-1, 11-2, 11-3, and 11-4 of FIG. 9A. Also, semiconductor dies 11-1, 11-2, 11-3, and 11-4 are disposed on the top surface 101 of the base layer 10 (under the base layer 10 as viewed in FIG. 9B), and are spaced apart from each other. In some embodiments, as shown in FIG. 9B, the package structure 120P further includes a plurality of conductive structures 113, wherein the polycrystalline component 120 is bonded to the substrate 100 through the conductive structure 113. As shown in FIG. 9B, the top surface 101 of the base layer 10 of the multi-grain part 120 faces the first surface 100 a of the substrate 100. The conductive structure 113 is disposed above the first surface 100a of the substrate 100 and below the first semiconductor dies 11-1 and 11-2.

In addition, an inter-die connection layer L _IC is formed to electrically connect two adjacent semiconductor die. For example, as shown in FIGS. 9A and 9B, the inter-grain connection layer L _IC1 electrically connects the semiconductor dies 11-1 and 11-2 as conductive bridges between the semiconductor dies 11-1 and 11-2. Likewise, the inter-die connection layer L _IC extends on the seal rings (such as the seal rings R _S 1 and R _S2 ) of two adjacent semiconductor dies, as described in the above description. Likewise, the inter-die connection layer L _IC passes through the space between two adjacent semiconductor die of the poly die component 120. For example, as shown in FIG. 9B, the inter-die connection layer L _IC1 passes through the second space SP2 between the first semiconductor die 11-1 and the second semiconductor die 11-2. In addition, in some embodiments, as shown in FIG. 9B, when the multi-die component 120 is bonded to the substrate 100, the inter-die connection layer L _IC is located between the top surface 101 and the first surface of the base layer 10. The details such as the structure and material of the inter-grain connection layer LIC have been described above, and will not be repeated here.

In some embodiments, as shown in FIG. 9B, the package structure 120P further includes a molding material 110 that surrounds the semiconductor dies 11-1, 11-2, 11-3, and 11 of the multi-die component 120 -4 and fill the space. The molding material 110 abuts the sidewalls of the semiconductor dies 11-1, 11-2, 11-3, and 11-4. That is, the semiconductor crystal grains 11-1, 11-2, 11-3, and 11-4 are separated from each other through the molding material 110. In addition, the molding material 110 encapsulates the inter-die connection layer L _IC extending between the semiconductors, and the inter-die connection layer L _IC passes through the molding material 110. For example, as shown in FIG. 9B, the semiconductor dies 11-1 and 11-2 are separated from each other through the molding material 110. The inter-grain connection layer L _IC1 between the semiconductor dies 11-1 and 11-2 passes through the molding material 110.

In some embodiments, the molding material 110 includes a non-conductive material, such as epoxy, resin, moldable polymer, or another suitable molding material. In some embodiments, the molding material 110 is applied when it is substantially liquid, and then cured through a chemical reaction. In some other embodiments, the molding material 110 is an ultraviolet (UV) or thermally cured polymer applied as a gel or a malleable solid, and then cured through an ultraviolet or thermal curing process. The molding material 110 may be cured with a mold (not shown).

In some embodiments, the surface of the semiconductor die 11-1 and 11-2 facing away from the first surface 100a of the substrate 100 is exposed by the molding material 110, so that the heat sink (not shown) can be directly attached to the semiconductor die. On the surface of grains 11-1 and 11-2. Therefore, the heat dissipation efficiency of the semiconductor package structure 120P can be improved, especially for a large semiconductor package structure, such as 50 mm×50 mm, which is preferable for high-power applications.

In some embodiments, as shown in FIG. 9B, the package structure 120P further includes a polymer material 115 disposed under the molding material 110, the semiconductor dies 11-1 and 11-2 and between the conductive structure 113. The structure 120P may further include an underfill layer (not shown) interposed between the first surface 100 a of the substrate 100 and the polymer material 115. In some embodiments, the semiconductor die 11-1 and 11-2 and the molding material 110 are surrounded by an underfill layer. The polymer material 115 and/or the underfill layer are provided to compensate for the different coefficients of thermal expansion (CTE) between the substrate 100, the conductive structure 113, and the semiconductor dies 11-1 and 11-2.

The package structure 120P of FIG. 9B may be mounted on a board (not shown). In some embodiments, the package structure 120P may be a system-in-package (SIP) structure. Also, the board may include a printed circuit board (PCB) and may be formed of polypropylene (PP). The package structure 120P can be mounted on the board through a bonding process. For example, the package structure 120P further includes a bump structure (not shown) on the second surface 100 b of the substrate 100. The bump structure may be a conductive ball structure (for example, a ball grid array (BGA)), a conductive pillar structure, or a conductive paste structure, which is mounted on a board (for example, PCB) and electrically coupled to the board through a bonding process.

According to some of the above-mentioned embodiments, the semiconductor structure and the package structure having the multi-grain components obtained from the semiconductor structure achieve a plurality of advantages. After performing the wafer sawing process, a plurality of multi-die parts can be obtained. In some embodiments, each multi-grain component includes several semiconductor dies. The semiconductor dies of the multi-grain component may have the same function. In addition, in some embodiments, two adjacent semiconductor dies of the multi-grain component _{are electrically connected to each other through one or more inter-grain connection layers L IC} (as shown in FIG. 1B, FIG. 3, FIG. 5, and FIG. 6, Figure 7A, Figure 7B and Figure 8). According to some embodiments of the present invention, a package structure can be formed by bonding one or more multi-die components to a substrate. Through the inter-die connection layer L _IC , electrical communication between adjacent semiconductor die can be achieved through the shortest path. Therefore, the semiconductor die of the multi-die component can provide fast and reliable signal transmission through the inter-die connection layer. The inter-die connection layer L _IC1 may extend on the seal ring area of the adjacent semiconductor die of the polycrystalline part. In some embodiments, the seal ring of the adjacent semiconductor die has a recess, and one or more inter-die connection layers pass through the recess of the seal ring. In some other embodiments, one or more inter-die connection layers extending over the seal ring area are formed above the interconnect stack of the seal ring. In a conventional package structure (or semiconductor package), the dies are individually bonded on the substrate, and can be electrically connected to each other through the redistribution layer in the substrate. Also, each die obtained from a conventional wafer may include a single semiconductor die. According to some embodiments, each multi-die component obtained from a wafer may include two or more semiconductor dies, and the package structure uses on-die wiring (for example, an inter-die connection layer L _IC ) to integrate the multiple Die semiconductor die. Mold parts. Compared with a package structure including a plurality of dies from a conventional wafer (each die is a single semiconductor die), a package structure including a multi-die component having a plurality of semiconductor dies of a plurality of embodiments is due to the signal It has better electrical performance due to loss and/or power. It is possible to significantly reduce the loss between the semiconductor dies in the multi-grain components (the multi-crystalline components are electrically connected to each other _{through the inter-grain connection layer L IC).}

It should be noted that the details of the structure of the embodiment are provided for example, and the details of the description of the embodiment are not intended to limit the present invention. It should be noted that not all embodiments of the present invention are shown. Modifications and variations can be made to meet the requirements of practical applications without departing from the spirit of the present invention. Therefore, there may be other embodiments of the present invention that are not specifically shown. In addition, the drawings are simplified to clearly show the embodiments. The size and ratio in the figure may not be proportional to the actual product. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Although the embodiments of the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made to the present invention without departing from the spirit of the invention and the scope defined by the scope of the patent application. The described embodiments are only used for illustrative purposes in all aspects and are not used to limit the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention.

10: Base layer 11, 11-1, 11-2, 11-3, 11-4: Semiconductor die 12, 13, 12-1, 12-2, 12-3, 12-4, 13-1, 13 -2: Die area L _IC , L _IC1 , L _IC2 , L _IC3 , L _IC4 : Inter-grain connection layer SP: Space pattern SP1: First space SP2: Second space F _S , F _S1 , F _S2 , F _S3 , F _S4 , F _S5 , F _S6 : Sealing frame A _A1 , A _A2 , A _A3 , A _A4 : Active area R _S1 , R _S2 , R _S3 , R _S4 : Sealing ring 4-4, 5-5: Section line LS1: first scribe line LS2: second scribe line A _D1 , A _D2 : dummy area A _R1 , A _R2 : seal ring area 211, 221, 311, 321: first interconnection stack 212, 222, 312, 322: second interconnection stack 213, 223, 313, 323: third interconnection Connect stack 211V, 221V: first conductive via 211L, 221L: first wire 212V, 222V: second conductive via 212L, 222L: second wire 213V, 223V: third conductive via 213L, 223L: third wire t1: first thickness t2: second thickness t3: third thickness 311V, 312V, 313V, 321V, 322V, 323V, 501V: conductive vias 311L, 312L, 313L, 321L, 322L, 323L, 311D, 312D, 313D, 321D, 322D, 323D: wire 211R, 211R', 221R: first recess 212R, 212R', 222R: second recess 21R, 21R';21R'', 22R, 22R', 22R'', 31R, 32R: recess 421, 422, 423, 501: Inter-die connection layer 120: Multi-die component 120P: Package structure 102: Bottom surface 101: Top surface 115: Polymer material 100: Substrate 100a: First surface 100b: Second surface 100M: Intermetallic dielectric layer 100L : Redistribution pattern

The present invention can be understood more comprehensively by reading the following detailed description and embodiments. This embodiment is given with reference to the accompanying drawings, in which: 1A and 1B are top views of an intermediate stage of a method for forming a semiconductor structure according to some embodiments of the present invention. Figure 2 is a top view of a semiconductor structure according to some embodiments of the present invention. FIG. 3 is a top view of a die region of a semiconductor structure according to some embodiments of the present invention. 4 is a cross-sectional view taken along the cross-sectional line 4-4 of the semiconductor structure in FIG. 3. FIG. 5 is a cross-sectional view taken along the cross-sectional line 5-5 of the semiconductor structure in FIG. 3. FIG. 6 is a top view of two adjacent semiconductor dies in the die region in FIG. 3 according to some embodiments of the present invention. Figure 7A is a cross-sectional view of a semiconductor structure according to some embodiments of the present invention. Figure 7B is a cross-sectional view of a semiconductor structure according to some embodiments of the present invention. FIG. 8 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present invention. Figure 9A is a top view of a multi-grain component according to some embodiments of the invention. 9B is a cross-sectional view of a package structure including the multi-die component in FIG. 9A according to some embodiments of the present invention.

10: basal layer

11-1, 11-2, 11-3, 11-4: semiconductor die

12: Grain area

L _IC , L _IC1 , L _IC2 , L _IC3 , L _IC4 : inter-grain connection layer

SP: Space pattern

SP1: the first space

SP2: second space

F _S : sealed frame

A _A1 , A _A2 , A _A3 , A _A4 : active area

R _S1 , R _S2 , R _S3 , R _S4 : sealing ring

4-4, 5-5: Section line

Claims (26)

A semiconductor structure including: Basal layer Semiconductor die, on the base layer, each semiconductor die includes an active area and a seal ring area, the seal ring area includes a seal ring surrounding the active area; and The inter-grain connection layer electrically connects two adjacent semiconductor dies, and the inter-grain connection layer extends on the adjacent part of the seal ring in the sealing ring region of the two adjacent semiconductor dies . The semiconductor structure of claim 1, wherein adjacent portions of the sealing ring of the two adjacent semiconductor dies have a recess, and the inter-die connection layer passes through the recess. The semiconductor structure of claim 1, wherein the inter-die connection layer and a conductive layer of the sealing ring are at the same level. The semiconductor structure of claim 1, wherein the sealing ring of each semiconductor die includes: A first interconnect stack above the base layer and surrounding the active area, wherein the first interconnect stack includes a first wire; and A second interconnect stack is above the first interconnect stack and surrounds the active area, wherein the second interconnect stack includes a second wire. The semiconductor structure of claim 4, wherein the second interconnect stack has a first recess, and the inter-die connection layer passes through the first recess. The semiconductor structure of claim 5, wherein the inter-die connection layer is flush with one of the second wires. The semiconductor structure of claim 5, wherein the second wire and the inter-die connection layer are made of the same material. The semiconductor structure of claim 4, wherein the thickness of the inter-die connection layer is greater than the thickness of one of the first wires. The semiconductor structure of claim 4, wherein the sealing ring of each semiconductor die further includes: A third interconnection stack on the second interconnection stack and surrounding the active area, wherein the third interconnection stack includes a third wire, The second interconnect stack has a first recess, the third interconnect stack has a second recess, and the second recess communicates with the first recess. The semiconductor structure of claim 9, wherein the inter-die connection layer passes through the first recess and/or the second recess. The semiconductor structure of claim 9, wherein the inter-die connection layer passes through the first recess, and the semiconductor structure further includes another inter-die connection layer, and the other inter-die connection layer passes through the second Recess. The semiconductor structure of claim 11, wherein the inter-die connection layer is flush with one of the second wires, and the other inter-die connection layer is flush with one of the third wires. The semiconductor structure of claim 11, wherein the second wire and the inter-die connection layer are made of the same material, and the third wire and the other inter-die connection layer are made of the same material. The semiconductor structure of claim 11, wherein the inter-die connection layer and the other inter-die connection layer are made of different materials. The semiconductor structure of claim 11, wherein the thickness of the inter-die connection layer is greater than the thickness of one of the first wires, and the thickness of the other inter-die connection layer is greater than the thickness of one of the second wires. The semiconductor structure of claim 11, wherein the thickness of the other inter-die connection layer is greater than the thickness of the inter-die connection layer. Such as the semiconductor structure of claim 1, which also includes: The sealing frame is on the base layer, wherein the sealing frame surrounds the semiconductor die and defines a die area. The semiconductor structure of claim 17, wherein the semiconductor die in the die region are spaced apart from each other. The semiconductor structure of claim 17, wherein the semiconductor dies in the die region have the same function. The semiconductor structure of claim 1, wherein the semiconductor dies on the base layer are separated from each other by a spacing pattern, and the spacing pattern includes: The first space extends in the first direction; and The second space extends in a second direction, wherein the first direction is different from the second direction. For example, the semiconductor structure of claim 20 also includes: A plurality of scribe lines pass through the first space and a part of the second space. The semiconductor structure of claim 1, wherein the sealing ring includes a plurality of interconnection stacks above the base layer, and the inter-die connection layer is formed above the plurality of interconnection stacks. The semiconductor structure of claim 22, wherein the uppermost conductive layer and the inter-crystalline connection layer in the plurality of interconnection stacks are made of the same material. The semiconductor structure of claim 1, wherein the inter-die connection layer is electrically insulated from the sealing ring. The semiconductor structure of claim 1, wherein the base layer includes active devices electrically connected to each semiconductor die. A packaging structure, including: A substrate having a first surface and a second surface opposite to the first surface, wherein the substrate includes a redistribution layer; A polycrystalline grain component disposed above the first surface of the substrate and electrically coupled to the redistribution layer of the substrate, wherein the polycrystalline grain component includes: a base layer; a plurality of semiconductor dies on the base layer And are spaced apart from each other; and an inter-grain connection layer that electrically connects two adjacent semiconductor dies; wherein the inter-grain connection layer extends on the seal ring in the seal ring region of the two adjacent semiconductor dies .

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