TW202123477A - Structure of semiconductor device and method for fabricating the same - Google Patents

Abstract

A structure of semiconductor device includes a substrate, having a first region and a second region. A first inter-layer dielectric (ILD) layer is disposed on the substrate. A first metal layer within the second region is formed in the first inter-layer dielectric layer. A second ILD layer is disposed on the first ILD layer and covers the first metal layer. A second metal layer is in the second ILD layer, having a first part within the first region with an indent from the second ILD layer and a second part having a via structure with a metal route layer on top thereof within the second region in contact with the first metal layer. A bottom of the first part is lower than a bottom of the via structure.

Description

Semiconductor element structure and manufacturing method thereof

The present invention relates to a semiconductor element and its manufacturing method. Semiconductor components include metal-insulator-metal (MIM) capacitor components.

Capacitors are very common components in integrated circuits and are used to store electrical charges. Capacitors are connected to circuit components such as transistors in accordance with semiconductor manufacturing technology in integrated circuits.

There are many different designs of capacitor structure, of which metal-insulator-metal capacitor is one of the structures, which is suitable for connecting with other semiconductor components of integrated circuits under the requirement of reducing the size of components, and finally forming a circuit chip.

In the manufacture of general metal-insulator-metal capacitors, since the metal layer is opaque, it needs to form some concavo-convex structure on the metal layer, which is used as an align mark to align the metal-insulator-metal capacitor. Metal layer. To form the alignment mark on the metal layer, generally, a process is deliberately added to form the alignment mark.

In the research and development of manufacturing technology, how to simplify the formation of the alignment mark of the metal layer requires further consideration and improvement.

The present invention relates to a semiconductor element and its manufacturing method. Semiconductor components include the formation of metal-insulator-metal capacitors. When manufacturing metal-insulator-metal capacitors, the present invention can be compatible with other interconnect manufacturing processes, and simplify the process of forming alignment marks with undulating geometric structures on the metal layer.

In one embodiment, the present invention provides a semiconductor device structure including a substrate with a first area and a second area. The first inner dielectric layer is disposed on the substrate. The first metal layer is formed in the first inner dielectric layer in the second region. The second inner dielectric layer is disposed on the first inner dielectric layer. The second metal layer is in the second inner dielectric layer, including a first portion in the first area, and a recess with respect to the second inner dielectric layer; and the second portion in the second area, It contains a through-window structure in contact with the first metal layer and a metal circuit layer on the through-window structure. The bottom of the first part is lower than the bottom of the window structure.

In one embodiment, for the semiconductor device structure, it further includes a metal-insulator-metal capacitor formed on the second inner dielectric layer, and a plurality of contact plugs respectively contact the metal-insulator-metal capacitor The two electrode plates of the capacitor and the second part of the second metal layer.

In one embodiment, for the semiconductor device structure, the lower electrode layer and the upper electrode layer of the metal-insulator-metal capacitor are flat structures.

In one embodiment, for the semiconductor device structure, the second portion of the second metal layer and the second inner dielectric layer have the same height, and the recess of the first portion of the second metal layer is at the same height The height is lower than the second inner dielectric layer.

In one embodiment, for the semiconductor device structure, the first part of the second metal layer is used as an alignment mark.

In one embodiment, for the semiconductor device structure, the second portion of the second metal layer is a partial structure of the device wafer.

In one embodiment, the present invention also provides a method of manufacturing a semiconductor device, including providing a substrate having a first area and a second area. The first inner dielectric layer is formed on the substrate. The first metal layer is formed in the second region and in the first inner dielectric layer. A second inner dielectric layer is formed on the first inner dielectric layer and covers the first metal layer. The second metal layer is formed in the second inner dielectric layer, including the first part in the first region, and has a recess relative to the second inner dielectric layer. The second part is in the second area and contains a through-window structure in contact with the first metal layer and a metal circuit layer on the through-window structure. The bottom of the first part is lower than the bottom of the window structure.

In one embodiment, for the method of manufacturing a semiconductor device, it includes: forming a metal-insulator-metal capacitor on the second inner dielectric layer; and forming a plurality of contact plugs to respectively contact the metal -Insulator-the two electrode plates of the metal capacitor and the second part of the second metal layer.

In one embodiment, for the method of manufacturing a semiconductor device, the lower electrode layer and the upper electrode layer of the metal-insulator-metal capacitor have a flat structure.

In one embodiment, for the method of manufacturing a semiconductor device, the second portion of the second metal layer and the second inner dielectric layer have the same height, and the first portion of the second metal layer has the same height The recess is lower in height than the second inner dielectric layer.

In one embodiment, for the method of manufacturing a semiconductor device, the first part of the second metal layer is used as an alignment mark.

In one embodiment, for the method of manufacturing a semiconductor device, the second part of the second metal layer is a partial structure of the device wafer.

In one embodiment, the present invention also provides a method of manufacturing a semiconductor device, including providing a substrate with a first area and a second area. The first inner dielectric layer is formed on the substrate. The first metal layer is formed in the first inner dielectric layer and located in the second region. The second inner dielectric layer is formed on the first inner dielectric layer. Defining the first inner layer dielectric layer and the second inner layer dielectric layer to form a structure includes: a first opening pattern in the first area extending to the first inner layer dielectric layer; and a second opening pattern Contains the window opening and stops at the first metal layer. A second metal layer is formed in the first opening pattern and the second opening pattern. The first part of the second metal layer in the first opening pattern has a recess, which is lower than the second part of the second metal layer, and is used as an alignment mark. The second portion of the second metal layer in the second opening pattern is the same height as the second inner dielectric layer.

In one embodiment, for the method of manufacturing a semiconductor device, the first part of the second metal layer is used as an alignment mark.

In one embodiment, for the method of manufacturing a semiconductor device, the second part of the second metal layer is a partial structure of the device wafer.

In the manufacture of metal-insulator-metal capacitors, it is necessary to form alignment marks on the metal layer corresponding to the lower electrode. The present invention can cooperate with the manufacturing process of the internal wiring of other integrated circuits, and at the same time, the alignment mark is formed on the metal layer, and no additional manufacturing process is required to form the alignment mark. The material of the metal layer is, for example, copper, which is a material for general interconnections, but the present invention is not limited to copper, and other applicable metals can be used.

The present invention discusses the manufacturing process of general metal-insulator-metal capacitors in order to understand the problems of existing manufacturing technology and further propose appropriate improvements.

Some examples are given below to illustrate the present invention, but the present invention is not limited to the examples. In addition, there may be appropriate combinations between the cited embodiments.

FIG. 1 is a schematic diagram of the structure of a semiconductor element of a general metal-insulator-metal capacitor considered in the present invention. Referring to FIG. 1, for the traditional manufacturing of semiconductor components that generally include metal-insulator-metal capacitors, they are manufactured in the component area 135 of the substrate 50, but the metal layers 112 and 116 of the capacitor will also extend into the alignment mark area 130 at the same time. , Contains alignment marks to provide the alignment required to define the metal layers 112, 116.

Structurally, in the inner dielectric layer 100 on the substrate 50, the inner dielectric layer 100 located in the element area 135 will also form an interconnect structure, including a via structure and a via structure. Metal layer 104. The subsequent formation of the metal-insulator-metal capacitor electrode metal layer. In the manufacturing process of the matching device region 135 on the inner dielectric layer 100, there are generally thin dielectric layers 106, 108 of oxide or nitride layers. To obtain an alignment mark on the metal layer 112 in the alignment mark area 130, a lithography and etching process is used to form recesses 110 on the dielectric layers 106 and 108. When the metal layer 112 covers the recess 100, the recess is also generated, which serves as an alignment mark. The depression of the metal layer 112 can be used as an alignment mark in the process of defining the metal layer 112, so that the lower electrode layer of the capacitor can be accurately manufactured in the device region 135, which is a part of the definition of the metal layer 112. The recess 110 also continues to exist in the structure layer such as the capacitor dielectric layer 114 to be formed later, to provide an alignment function.

Subsequent dielectric layer 118, low-k dielectric layer 120, contact plug 122, etc. can continue to be manufactured to complete the manufacturing of the capacitor. The invention is not limited to subsequent manufacturing applications.

In the present invention, after exploring the structure and manufacturing process of FIG. 1, it is observed that the alignment mark is additionally formed by using lithography and etching to form the recess 110 to generate the alignment mark. The present invention proposes that the formation of the alignment mark can be completed in conjunction with the manufacturing process of the metal interconnection of the device area 135, and the process of lithography and etching may not be required.

2A to 2C are schematic diagrams of the cross-sectional structure of a process of manufacturing an alignment mark of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2A, an alignment mark area 130 and a device area 135 are planned on the substrate 50. The alignment mark is expected to be formed in the quasi-mark area 130. It is expected that an integrated circuit including a capacitor will be formed in the element area 135.

An inner dielectric layer 150 will be formed on the substrate 50. A metal layer 140 of connecting lines is formed in the inner dielectric layer 150 in the device region 135. The actual semiconductor manufacturing process, including deposition, lithography, and etching processes, is a process that can be generally understood and will not be detailed here. Then another inner layer dielectric layer 157 is formed on the inner layer dielectric layer 150. The inner dielectric layer 157 includes, for example, a nitride layer 152, an oxide layer 154, and a hard mask layer 156, but is not limited thereto. An opening 158A is formed on the inner dielectric layer 157 of the alignment mark area 130. An opening 158B is formed on the inner dielectric layer 157 of the element region 135. The opening 158B is used to subsequently form a via structure, so its width is determined according to the size of the via window. The lower part of the opening 158A and the forming opening 158B is filled with buffered dielectric materials 160 and 162.

Referring to FIG. 2B, a photoresist layer 164 is formed on the inner dielectric layer 157. The opening pattern of the photoresist layer 164 in the element region 135 corresponds to the opening pattern 166B of the circuit layer to be subsequently connected to the via structure. The opening pattern of the photoresist layer 164 in the alignment mark area 135 corresponds to the position where the alignment mark is to be formed later. Using the photoresist layer 164 as a mask, the inner dielectric layer 157 and the dielectric materials 160 and 162 are etched. In the inner dielectric layer 157 of the alignment mark area 130, with the aid of the dielectric materials 160 and 162, the opening pattern 166A formed in the inner dielectric layer 157 will extend to the underlying inner dielectric layer 150. That is, the opening pattern 166A has a larger depth and will extend into the inner dielectric layer 150. An opening pattern 166B is formed in the inner dielectric layer 157 of the device region 135. The dielectric material 162 can buffer the etching, but is also finally removed to create an opening 166C that stops at the metal layer 140. The opening 166C exposes the metal layer 140. The opening pattern 166B and the opening 166C are connected and merged.

It can be seen that the depth of the opening pattern 166B is smaller than the depth of the opening pattern 166A. The opening pattern 166A is a position where an alignment mark is expected to be formed later.

2C, after the opening pattern 166A and the opening patterns 166B, 116C in the alignment mark area 130 and the device area 135 are completed, the photoresist layer 164 is removed. Thereafter, a metal material may be formed on the inner dielectric layer 157, and fill the opening pattern 166A, the opening pattern 166B, and the opening 166C. Since the depth of the opening pattern 166B is smaller than the depth of the opening pattern 166A, the initial metal layer naturally forms a larger depression above the opening pattern 166A. After that, grinding is performed to expose the oxide layer 154 and reach the required thickness of the metal layer of the metal circuit, and then stop. In this way, a metal layer 168B is formed in the inner dielectric layer 157 of the element region 135, and a metal layer 168A is formed in the inner dielectric layer 157 of the alignment mark region 130. The metal layer 168A and the metal layer 168B are formed at the same time, and can be regarded as two parts of a metal layer.

It can be seen here that due to the large depth of the opening pattern 166A, the surface of the polished metal layer 168A relative to the inner dielectric layer 157 will have a depression 170. The metal layer 168B in the inner dielectric layer 157 of the device region 135 may substantially form a flat surface with the inner dielectric layer 157. The metal layer 168B is an interconnection structure belonging to the device. The upper part is a circuit structure, and the lower part is a through-window structure connected to the metal layer 140. In this way, the recess 170 of the metal layer 168A is compatible with the manufacturing in the device region 135. The recess 170 can be used as an alignment mark, and no additional lithography and etching processes are required to form the alignment mark.

FIG. 3 is a schematic cross-sectional structure diagram of a semiconductor device including a metal-insulator-metal capacitor and an alignment mark according to an embodiment of the present invention. Referring to FIG. 3, using the metal layer 168A formed in FIG. 2C, the recess 170 of the metal layer 168A can provide an alignment mark. In the present invention, the metal layer 168A where the recess 170 is formed uses the manufacturing process of the device region 135, and no additional lithography and etching processes are required to form the recess. Subsequently, the lower electrode metal layer 112 of the metal-insulator-metal capacitor will be formed in the device region 135. The metal layer 112 is formed on the inner dielectric layer 157 of the alignment mark area 130 and the recess 170 of the metal layer 168A at the same time. In this way, the metal layer 112 still retains the structure of the recess 170 in the alignment mark area 130, which can be used to provide an alignment mark when the metal layer 112 is subjected to a photolithographic etching process. For example, the recess 170 will continue to exist, providing the function of an alignment mark.

Part of the same device as in FIG. 1, the metal layer 112 and the metal layer 116 in the device area 135 are the two electrode layers of the capacitor, and the capacitor dielectric layer 114 is in between. The whole component structure can be completed later. The present invention is not limited to the subsequently applied components. The present invention proposes to form a geometric structure of alignment marks on the metal layer. Since the metal layer does not transmit light, the formed alignment mark can be aligned when defining the metal layer. The alignment mark can be completed at the same time as the component area is manufactured, effectively simplifying the stroke of the alignment mark.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

50: substrate 100: inner dielectric layer 102: Window structure 104: Metal layer 106, 108: Dielectric layer 110: sunken 112, 116: Metal layer 114: Capacitor dielectric layer 118, 120: Dielectric layer 122: contact plug 130: Alignment mark area 135: component area 140: Metal layer 150, 157: inner dielectric layer 152: Nitrided layer 154: Oxide layer 156: Hard Mask Layer 158A, 158B: opening 160, 162: Dielectric materials 164: photoresist layer 166A, 166B: opening pattern 166C: Window opening 168A, 168B: metal layer 170: sunken

FIG. 1 is a schematic diagram of the structure of a semiconductor element of a general metal-insulator-metal capacitor considered in the present invention. 2A to 2C are schematic diagrams of the cross-sectional structure of a process of manufacturing an alignment mark of a semiconductor device according to an embodiment of the present invention. FIG. 3 is a schematic cross-sectional structure diagram of a semiconductor device including a metal-insulator-metal capacitor and an alignment mark according to an embodiment of the present invention.

50: substrate

130: Alignment mark area

135: component area

140: Metal layer

150, 157: inner dielectric layer

152: Nitrided layer

154: Oxide layer

168A, 168B: metal layer

170: sunken

Claims (15)

A semiconductor element structure, including: A substrate having a first area and a second area; The first inner dielectric layer is provided on the substrate; The first metal layer, in the second region, is formed in the first inner dielectric layer; The second inner dielectric layer is disposed on the first inner dielectric layer; and The second metal layer, in the second inner dielectric layer, includes: The first part is in the first area and has a recess relative to the second inner dielectric layer; and The second part is in the second area and contains a through-window structure in contact with the first metal layer and a metal circuit layer on the through-window structure, wherein the bottom of the first part is lower than the bottom of the through-window structure. The semiconductor device structure described in item 1 of the scope of patent application further includes: A metal-insulator-metal capacitor is formed on the second inner dielectric layer; and A plurality of contact plugs respectively contact the two electrode plates of the metal-insulator-metal capacitor and the second part of the second metal layer. According to the semiconductor device structure described in item 2 of the scope of the patent application, the lower electrode layer and the upper electrode layer of the metal-insulator-metal capacitor are flat structures. According to the semiconductor device structure described in claim 1, wherein the second part of the second metal layer and the second inner dielectric layer are at the same height, and the first part of the second metal layer has the same height The recess is lower in height than the second inner dielectric layer. According to the semiconductor device structure described in claim 1, wherein the first part of the second metal layer is used as an alignment mark. According to the semiconductor device structure described in claim 1, wherein the second part of the second metal layer is a partial structure of the device wafer. A method of manufacturing semiconductor components, including: Provide a substrate having a first area and a second area; Forming a first inner dielectric layer on the substrate; A first metal layer is formed in the second region, and in the first inner dielectric layer; Forming a second inner dielectric layer on the first inner dielectric layer and covering the first metal layer; and Forming a second metal layer in the second inner dielectric layer includes: The first part is in the first area and has a recess relative to the second inner dielectric layer; and The second part is in the second area and contains a through-window structure in contact with the first metal layer and a metal circuit layer on the through-window structure, wherein the bottom of the first part is lower than the bottom of the through-window structure. The method of manufacturing semiconductor components as described in item 7 of the scope of patent application further includes: Forming a metal-insulator-metal capacitor on the second inner dielectric layer; and A plurality of contact plugs are formed to respectively contact the two electrode plates of the metal-insulator-metal capacitor and the second part of the second metal layer. According to the method for manufacturing a semiconductor device described in item 7 of the scope of patent application, the lower electrode layer and the upper electrode layer of the metal-insulator-metal capacitor are flat structures. The method for manufacturing a semiconductor device as described in claim 7, wherein the second part of the second metal layer and the second inner dielectric layer are at the same height, and the first part of the second metal layer The recess is lower in height than the second inner dielectric layer. According to the method of manufacturing a semiconductor device as described in item 7 of the scope of patent application, the first part of the second metal layer is used as an alignment mark. According to the method of manufacturing a semiconductor device as described in claim 7, wherein the second part of the second metal layer is a partial structure of the device wafer. A method of manufacturing semiconductor components, including: Provide a substrate having a first area and a second area; Forming a first inner dielectric layer on the substrate; Forming a first metal layer in the first inner dielectric layer, located in the second region; Forming a second inner dielectric layer on the first inner dielectric layer; Defining the first inner dielectric layer and the second inner dielectric layer to form a structure includes: The first opening pattern extends to the first inner dielectric layer in the first region; and The second opening pattern, including the window opening, stops at the first metal layer; and Forming a second metal layer, in the first opening pattern and the second opening pattern, Wherein the first part of the second metal layer in the first opening pattern has a recess, which is lower than the second part of the second metal layer for use as an alignment mark, and the second part in the second opening pattern The second part of the metal layer is at the same height as the second inner dielectric layer. According to the method of manufacturing a semiconductor device described in item 13 of the scope of patent application, the first part of the second metal layer is used as an alignment mark. The method for manufacturing a semiconductor device as described in the scope of patent application, wherein the second part of the second metal layer is a part of the structure of the device wafer.

Images