TW202106130A - Fine interlayer circuit structure and method for making the same - Google Patents

Abstract

A fine interlayer circuit structure includes a base circuit board, a insulating layer, a second circuit layer and a conductive paste layer. The base circuit board has a first circuit layer located at a topmost layer of the base circuit board. The insulating layer covers the first circuit layer and has multiple openings from which a part of the first circuit layer is exposed. The second circuit layer is formed on the top surface of the insulating layer. The conductive paste layer is filled in the openings in a manner that the first and second circuit layers are electrically connected through the conductive paste layer. Copper plating layer is not formed on the wall of the openings.

Description

Micro-layer circuit structure and its manufacturing method

The invention relates to a circuit board structure, in particular to a structure with fine interlayer circuits and a manufacturing method thereof.

As the circuit design of 3C equipment becomes more refined, the requirements for the fineness of its carrier board circuits are also increasing. In the structure of the existing circuit carrier board involving the electrical connection between the layers, the insulating layer between the two layers of circuits will be drilled, and then electroplating will be carried out to fill a copper plated layer in the via hole, and then the electroplated layer will be brushed and polished. Surface circuit layer, but the existing process has its shortcomings. The process of electroplating and brushing will cause the copper thickness of the surface circuit layer to be uneven, resulting in extremely difficult production of small-pitch surface circuit layers, and the yield rate is too low to be mass-produced. In addition, the electroplating process will also increase the thickness of the copper layer of the surface circuit layer, and once the thickness of the copper layer cannot be reduced, it is difficult to form a fine circuit structure and the circuit density is difficult to increase.

The main purpose of the present invention is to provide a circuit structure and its manufacturing method which is helpful to realize the fineness and yield of the high-level circuit.

In order to achieve the above and other objectives, the present invention provides a fine interlayer circuit structure, which includes a base circuit board, an insulating layer, a second circuit layer, and a conductive paste layer. The base circuit board has a first circuit layer, and a first circuit layer. The circuit layer is located on the top layer of the base circuit board, the insulating layer covers the first circuit layer, and the insulating layer has a plurality of openings, a part of the first circuit layer is exposed from the openings, and the second circuit layer is formed on the top of the insulating layer On the surface, the conductive paste layer is filled in the window, so that the first and second circuit layers are electrically connected through the conductive paste layer; wherein, no copper plating layer is formed on the hole wall of the window.

In order to achieve the above and other objectives, the present invention also provides a method for manufacturing a fine interlayer circuit structure, including:

A base circuit board is provided, the base circuit board has a first circuit layer, and the first circuit layer is located on the topmost layer of the base circuit board;

Laminating an insulating layer of copper foil on the top surface of the first circuit layer;

Forming a plurality of opening areas on the copper foil, and forming a plurality of openings corresponding to the opening areas on the insulating layer, so that a part of the first circuit layer is exposed from the openings; and

The conductive paste is filled in the openings to form a conductive paste layer, so that the first circuit layer and the copper foil are electrically connected through the conductive paste layer; wherein, after the insulating layer forms the opening, the hole walls of the openings There is no copper plating treatment.

The present invention uses conductive paste to replace the copper-plated layer commonly used in the through holes of the previous circuit structure, so that the circuit between the layers can be electrically connected without affecting the thickness of the top circuit layer. In this way, The copper plating and surface brushing process in the existing manufacturing process can be omitted, and the thickness of the top surface circuit layer is thinner, the circuit fineness can be improved, the thickness can be uniform, and the yield rate can be significantly improved, so that mass production is possible.

Please refer to FIG. 1, which is an embodiment of the micro-interlayer circuit structure of the present invention, which has a base circuit board 10, an insulating layer 20, a second circuit layer 30, a conductive paste layer 40, and a Electroplating layer 50.

In this embodiment, the base circuit board 10 has a single-layer board structure, which has a substrate 11 and a first circuit layer 12 on the topmost layer. The first circuit layer 12 is, for example, a copper layer. In other possible embodiments, the base circuit board may also be a multilayer board with multiple circuit layers.

The insulating layer 20 covers the first circuit layer 12, and the insulating layer 20 has a plurality of openings 21. A part of the first circuit layer 12 is exposed from the openings 21, and there is no hole wall of the openings 21. A copper plating layer is formed, that is, the openings 21 are not subjected to electroless plating or electroplating treatment. The insulating layer 20 is, for example, BT resin (Bismaleimide Triazine), FR-4 epoxy resin, polyimide or other common substrate materials, dielectric or solder resist materials for circuit boards, and during the manufacturing process, the insulating layer 20 may have Photoimageable characteristics.

The second circuit layer 30 is formed on the top surface of the insulating layer 20. The second circuit layer 30 is a copper layer, and its thickness is preferably less than 5 μm to form fine circuits.

The conductive paste layer 40 is filled in the openings 21, so that the first and second circuit layers 12, 30 are electrically connected through the conductive paste layer 40, and the conductivity is preferably less than 1.0×10 ^-4 Ω·cm For example, a conductive silver paste or a conductive copper paste is used to form the conductive paste layer 40.

In a possible implementation, the second circuit layer 30 can be used to mount surface mounted devices. At this time, the top surface of the second circuit layer 30 can also be formed with the electroplating layer 50, such as It may be an electroplated nickel/gold layer commonly known as "soft gold", and the electroplated layer 50 is not a copper layer. In other possible implementations as shown in Figure 2, the second circuit layer 30 can also be one of the inner layers of other multilayer circuit boards, and there is no need to mount surface mount components on the second circuit layer 30. At this time, the electroplating layer can be omitted.

Hereinafter, the manufacturing process of the foregoing embodiment will be described through FIGS. 3-7.

As shown in Figure 3, first, a base circuit board 10 is provided. In this embodiment, the base circuit board 10 is exemplarily shown as a single-layer board structure with a base material 11 and a first circuit layer on the topmost layer. 12, such as a copper layer. The first circuit layer 12 can be made by performing conventional patterning processing on the copper layer according to the required circuit design.

As shown in Figure 4, a vacuum laminating machine is used to laminate an insulating layer 20 with a copper foil 30A on the top surface of the first circuit layer 12. The thickness of the copper foil 30A is less than 5µm, and the insulating layer 20 is The photoimageable resin, and the insulating layer 20 has not yet been cured by light during lamination.

As shown in Figure 5, a plurality of window areas 31 are formed on the copper foil 30A. The specific method can be to attach a thin photolithography layer on the copper foil 30A, expose and develop the photolithography layer, and etch the unlithography. The copper covered by the layer is finally removed from the photolithography layer, so that the partial insulating layer 20 is exposed from the window area 31. The insulating layer 20 after the window 21 is formed and necessary post curing can be performed.

As shown in FIG. 6, the insulating layer 20 is etched to remove the exposed part of the window opening area 31, so that a plurality of windows 21 corresponding to the window opening areas 31 are formed in the insulating layer 20. Furthermore, a part of the first circuit layer 12 is exposed from the openings 21.

As shown in Figure 7, a dispenser is used to fill the openings 21 with conductive paste, such as conductive silver paste or conductive copper paste, to form a conductive paste layer 40, so that the first circuit layer 12 and the copper foil 30A are formed Electrical connection; wherein, before the conductive paste is filled, the hole walls of the openings 21 have not been copper-plated, including electroless copper plating and copper electroplating, so that the copper plating will not be caused by the copper plating. The thickness of the foil 30A is increased. In other possible embodiments, after the conductive paste layer 40 is formed, an additional metal layer may be formed on the top surface of the conductive paste layer 40, for example, a copper layer is formed by electroplating, but the copper layer is not in contact with the hole wall of the window 21 contact. In a possible embodiment, the top surface of the conductive paste layer 40 is flush with the top surface of the copper foil 30A.

Finally, the copper foil 30A is patterned into a second circuit layer 30, and a non-copper electroplating layer 50 such as an electroplated nickel/gold layer, etc. is formed on the second circuit layer as necessary to form a structure as shown in FIG. 1. In a possible implementation manner, before the electroplating layer 50 is formed, the second circuit layer 30 and the conductive paste layer 40 may be covered with a solder mask (not shown) where the electroplating layer 50 is not required to be formed.

In the foregoing manufacturing process, the copper foil 30A is patterned after the window 21 is filled with conductive paste. However, in other possible embodiments, the copper foil 30A can also be patterned as the second circuit layer in advance. The opening 21 is filled with conductive paste.

In the foregoing manufacturing process, the formation of the window area 31 and the formation of the window 21 are achieved through two steps. However, in other possible embodiments, a laser engraving machine can also be used to burn through the copper foil 30A and the insulating layer 20 at the same time. The window opening area 31 and the window opening 21 are simultaneously formed in one processing station.

In summary, the present invention uses conductive paste to replace the copper-plated layer commonly used in the through holes of the previous circuit structure, so that the layer-to-layer circuit can be electrically connected without affecting the thickness of the top circuit layer. As a result, the electroplated hole copper and surface brushing process in the existing process can be omitted, and the thickness of the top circuit layer is thinner, the circuit fineness can be improved, the thickness can be uniform, and the yield rate can be significantly improved, thereby enabling mass production Possible.

10: base circuit board 11: Substrate 12: The first circuit layer 20: Insulation layer 21: open window 30: The second circuit layer 30A: Copper foil 31: Window area 40: conductive paste layer 50: electroplating layer

Figure 1 is a schematic cross-sectional view of one embodiment of the micro-layer circuit structure of the present invention.

Figure 2 is a schematic cross-sectional view of another embodiment of the fine interlayer circuit structure of the present invention.

3 to 7 are schematic diagrams of the manufacturing process of one embodiment of the micro-interlayer wiring structure of the present invention.

10: base circuit board

11: Substrate

12: The first circuit layer

20: Insulation layer

21: open window

30: The second circuit layer

40: conductive paste layer

50: electroplating layer

Claims (10)

A fine interlayer wiring structure, including: A base circuit board having a first circuit layer, and the first circuit layer is located on the topmost layer of the base circuit board; An insulating layer covering the first circuit layer, the insulating layer having a plurality of openings, and a part of the first circuit layer is exposed from the openings; A second circuit layer formed on the top surface of the insulating layer; and A conductive paste layer is filled in the openings so that the first and second circuit layers are electrically connected through the conductive paste layer; Among them, no copper plating layer is formed on the hole walls of the openings. The fine interlayer circuit structure according to claim 1, wherein the thickness of the second circuit layer is less than 5 µm. The fine interlayer circuit structure according to claim 1, wherein the conductivity of the conductive paste layer is lower than 1.0×10 ^-4 Ω·cm. The fine interlayer circuit structure according to claim 1, wherein a non-copper electroplating layer is further formed on the top surface of the second circuit layer. A manufacturing method of fine interlayer circuit structure, including: Providing a base circuit board, the base circuit board having a first circuit layer, and the first circuit layer is located on the topmost layer of the base circuit board; On the top surface of the first circuit layer is laminated an insulating layer with a copper foil on the top surface; Forming a plurality of window openings in the copper foil, and forming a plurality of openings corresponding to the opening regions in the insulating layer, so that a part of the first circuit layer is exposed from the openings; and Filling the openings with conductive paste to form a conductive paste layer, so that the first circuit layer and the copper foil are electrically connected through the conductive paste layer; Wherein, after the insulating layer forms the opening, the hole walls of the openings are not copper-plated. According to the manufacturing method of the fine interlayer circuit structure of claim 5, the copper foil has been patterned into a second circuit layer before the conductive paste layer is filled in the openings. According to the manufacturing method of the fine interlayer circuit structure of claim 5, after the conductive paste layer is filled in the openings, the copper foil is patterned into a second circuit layer. The method for manufacturing a fine interlayer circuit structure according to claim 5, wherein the thickness of the copper foil and the second circuit layer is less than 5 μm. The method for manufacturing a fine interlayer circuit structure according to claim 5, wherein the conductivity of the conductive paste layer is lower than 1.0×10 ^-4 Ω·cm. According to claim 5, the method for manufacturing a fine interlayer circuit structure, wherein a non-copper electroplating layer is further formed on the top surface of the second circuit layer.

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