TW202036936A - A Light-emitting Module - Google Patents

Abstract

The present disclosure provides a light-emitting module including a common carrier; a plurality of semiconductor devices formed on the common carrier, and each of the plurality of semiconductor devices including at least three semiconductor dies; a carrier including a connecting surface; a third bonding pad and a fourth bonding pad formed on the connecting surface; and a connecting layer. At least one of the three semiconductor dies includes a stacking structure; a first bonding pad with an outmost surface positioned away from the stacking structure; and a second bonding pad, wherein a shortest distance between the first bonding pad and the second bonding pad is less than 150 microns. The connecting layer includes a first conductive part formed between the first bonding pad and the third bonding pad and including a first conductive material having a first shape; a second conductive part formed between the second bonding pad and the fourth bonding pad and including the first conductive material; and a blocking part covering the first conductive part and including a second conductive material having a second shape with a diameter in a cross-sectional view, wherein the first shape has a height greater than the diameter.

Description

Light-emitting module

The present invention relates to a light-emitting module, and particularly to a light-emitting module structure with a plurality of semiconductor devices.

Semiconductor devices include compound semiconductors composed of group III-V elements, such as gallium phosphide (GaP), gallium arsenide (GaAs), gallium nitride (GaN), and semiconductor devices can be light emitting diodes (LED), power devices Or solar cells. Among them, the structure of the LED includes a p-type semiconductor layer, an n-type semiconductor layer, and an active layer. The active layer is arranged between the p-type semiconductor layer and the n-type semiconductor layer, so that under an external electric field, the n-type semiconductor layer The electrons and holes provided by the p-type semiconductor layer and the p-type semiconductor layer are recombined in the active layer to convert electrical energy into light energy.

In order to improve the electrical performance and heat dissipation efficiency of LEDs, flip-chip LEDs in which the chip is directly bonded to the substrate have emerged. However, as electronic products become thinner, the yield of flip-chip LEDs prepared by conventional methods has decreased. The reliability of mounted LEDs is also affected.

The invention relates to a light emitting module structure, which includes a common carrier board, a plurality of semiconductor devices, a first bonding pad to a fourth bonding pad, a carrier board, and a conductive bonding layer. Wherein, a plurality of semiconductor devices are formed on a common carrier, each semiconductor device includes at least three semiconductor dies, and one of the aforementioned at least three semiconductor dies includes a stacked structure. Wherein, the first bonding pad and the second bonding pad are arranged on an upper surface of the laminated structure, and the first bonding pad has a top surface away from the foregoing upper surface, and the shortest distance between the first bonding pad and the second bonding pad is less than 150 μm. The carrier has a surface, and the third bonding pad and the fourth bonding pad are arranged on the surface. The conductive bonding layer includes a first conductive portion provided between the first bonding pad and the third bonding pad; the first conductive portion includes a first conductive material having a first shape, and the first shape has a height. The conductive bonding layer further includes a second conductive portion provided between the second bonding pad and the fourth bonding pad; the second conductive portion includes the aforementioned first conductive material. The conductive bonding layer further includes a current isolation region, viewed from a cross-sectional view, the current isolation region covers the first conductive portion; and the current isolation region includes a second conductive material having a second shape. Wherein, the second shape has a particle size, and the aforementioned height is greater than the particle size.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, some embodiments are described in detail in conjunction with the accompanying drawings. In the drawings or descriptions, similar or identical structures use the same reference numerals. It should be noted that the components not shown in the figure should be well known to those with ordinary knowledge in the art.

Please refer to FIG. 1, which is a cross-sectional view of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a semiconductor die 1 and a carrier 2. The semiconductor die 1 and the carrier 2 are arranged between There is a conductive bonding layer 3 to electrically connect the semiconductor die 1 to the carrier 2 through the conductive bonding layer 3. The semiconductor die 1 includes a first bonding pad 112 and a second bonding pad 113, the carrier 2 includes a third bonding pad 22 and a fourth bonding pad 23, and the conductive bonding layer 3 has a current conducting region 31 and a The current isolation region 32 and the current conduction region 31 are provided between the first bonding pad 112 and the third bonding pad 22 and between the second bonding pad 113 and the fourth bonding pad 23.

In detail, the semiconductor die 1 is formed after cutting a semiconductor wafer during the manufacturing process. In order to meet the application requirements of thinner electronic products, the area of the semiconductor die 1 in an embodiment of the present invention is controlled, for example, Below 150 mil2, and the shortest distance d between the first bonding pad 112 and the second bonding pad 113 is less than 150 μm, for example, the shortest distance d is 15-100 μm. In addition, the semiconductor die 1 can be a light-emitting die, a power device or a solar cell. The semiconductor die 1 has a stacked structure 11, the stacked structure 11 has a surface 111, and the first bonding pad 112 and the second bonding pad 113 are provided on the surface 111. The first bonding pad 112 has a first bonding surface 112a, the first bonding surface 112a is approximately parallel to the surface 111 of the semiconductor die 1, and the first bonding surface 112a has a first normal direction perpendicular to the first bonding surface 112a a1. Generally speaking, the first bonding surface 112a is a surface with a larger area than other surfaces of the first bonding pad 112, and the outer surface material of the first bonding pad 112 and the second bonding pad 113 can be selected as gold , Silver, copper, tin, nickel or alloys of the above metals. In an embodiment, the semiconductor die 1 is a light-emitting die and its operating current is less than 10 mA. The semiconductor die 1 of the present invention includes a bare die without packaging material, a die with a conformal phosphor layer on the surface of the bare die, or a die-scale-package (chip-scale-package; CSP) Technology-formed die containing packaging material.

Please refer to Figure 1 again, the carrier 2 has a surface 21, the third bonding pad 22 and the fourth bonding pad 23 are protrudingly provided on the surface 21 of the carrier 2, and the third bonding pad 22 has a second The joint surface 22a, the second joint surface 22a is substantially parallel to the surface 21 of the carrier board 2, the second joint surface 22a has a second normal direction a2 perpendicular to the second joint surface 22a, and generally speaking, the second joint surface 22a is a surface with a larger area than the other surfaces of the third bonding pad 22. The outer surface material of the third bonding pad 22 and the fourth bonding pad 23 can be selected from gold, silver, copper, tin, nickel or the above metals The alloy. The third bonding pad 22 and the fourth bonding pad 23 are substantially opposite to the first bonding pad 112 and the second bonding pad 113, respectively. In one embodiment, when the carrier 2 and the semiconductor die 1 are bonded through the conductive bonding layer 3 , The first normal direction a1 of the first bonding pad 112 is substantially parallel to the second normal direction a2 of the third bonding pad 22, so that the first bonding pad 112 and the second bonding pad 113 face the third bonding pad 22, respectively. In the direction of the fourth bonding pad 23 and the conductive bonding layer 3, the semiconductor die 1 and the carrier 2 are combined to allow current to flow through the semiconductor die 1 and the carrier 2. In detail, there is an angle between the first normal direction a1 and the second normal direction a2, and the angle is 160-200 degrees, preferably 180 degrees. In another embodiment, when the carrier 2 and the semiconductor die 1 are combined through the conductive bonding layer 3, the distance between the surface 111 of the laminated structure 11 and the surface 21 of the carrier 2 is preferably less than 60 μm, so that the semiconductor device is formed The height of 100 can be effectively reduced to apply to small or thin devices. The carrier board 2 is used to electrically connect to an external power supply. For example, the carrier board 2 can be a load board or a printed circuit board (PCB). The current flows through the third bonding pad 22 and the fourth bonding pad 23 of the carrier board 2 To the conductive bonding layer 3, it is transferred to the semiconductor die 1 through the first bonding pad 112 and the second bonding pad 113 to drive the semiconductor die 1.

Please refer to FIG. 2, which is a cross-sectional view of the first embodiment of the semiconductor device 100 of the present invention, in which the current conducting region 31 of the conductive bonding layer 3 is provided between the first bonding pad 112 and the third bonding pad 22 , And between the second bonding pad 113 and the fourth bonding pad 23, and the current isolation region 32 is located outside the current conduction region 31 in the conductive bonding layer 3. For example, the current isolation region 32 of this embodiment is located in Between the surface 111 of the laminated structure 11 provided with the first bonding pad 112 and the second bonding pad 113 and the surface 21 of the carrier 2 without the third bonding pad 22 and the fourth bonding pad 23; in other words, the current The isolation region 32 is shared by the first bonding pad 112, the second bonding pad 113, the third bonding pad 22, the fourth bonding pad 23, the surface 111 of the semiconductor die 1, the surface 21 of the carrier 2 and the current conducting region 31 Defined, the current isolation region 32 surrounds and covers the current conduction region 31, for example. In the first embodiment, in the semiconductor device 100, the surface 111 of the semiconductor die 1 and the surface 21 of the carrier 2 are approximately parallel, and the structure is as described above, and in order to be applied in the field of thinning semiconductor devices, the current conducts The thickness of the region 31 is, for example, less than 40 μm, that is, the distance between the first bonding pad 112 and the third bonding pad 22 is, for example, less than 40 μm, or the distance between the second bonding pad 113 and the fourth bonding pad 23 is, for example, less than 40 μm, so as to reduce the semiconductor device 100. The overall thickness. The conductive bonding layer 3 includes a conductive material C1 and a non-conductive material I1. The current conducting region 31 and the current isolation region 32 contain different contents of the conductive material C1. In detail, the content of the conductive material C1 in the current conducting region 31 is greater than The content of the conductive material C1 in the current isolation region 32. For example, in the first embodiment shown in Figure 2, the content of the conductive material C1 in the current conducting region 31 is 7% to 75%, and preferably 15% to 30%, and the current isolation region 32 is The content of the conductive material C1 is 2%-50%, and preferably 3%-10%. It should be noted that the “content of conductive material C1” referred to in this application refers to the cross-sectional microscopic image of the semiconductor device 100 to define the content of conductive material C1 in a specific area. In detail, in a cross-section of the semiconductor device 100, the percentage of the total area of the conductive material C1 in the representative area divided by the total area of the representative area is the "content" of the conductive material C1 in the specific area. This definition also applies to the "content of conductive materials" described below.

Please refer to Fig. 2 again, the conductive material C1 of the first embodiment of the present invention is spherical or granular. The content of the conductive material C1 in the current conducting region 31 is 7% to 75%, so that the first bonding pad 112 and the third bonding pad 22 are electrically connected through the conductive material C1, and the second bonding pad 113 and the fourth bonding pad 23 are transmitted through The conductive materials C1 are electrically connected to each other to transfer the current of the carrier 2 to the semiconductor die 1. Furthermore, although the current isolation region 32 has a small amount of conductive material C1, the content of the conductive material C1 in the current isolation region 32 is not sufficient to enable the semiconductor die 1 and the carrier 2 to conduct current through the current isolation region 32, such as conductive material The content of C2 in the current isolation region 32 is 2%-50%, preferably 3%-10%; in detail, between the first bonding pad 112 and the second bonding pad 113, the third bonding pad 22 and the fourth bonding pad 113 The bonding pads 23, the first bonding pad 112 and the fourth bonding pad 23, and the second bonding pad 113 and the third bonding pad 22 cannot be connected to each other by the limited conductive material C1, so that the semiconductor The die 1 and the carrier board 2 are electrically isolated from each other in the current isolation region 32, and can effectively prevent current from conducting between the first bonding pad 112 and the second bonding pad 113, or bonding between the third bonding pad 22 and the fourth bonding pad 113 The pads 23 are conductive and short-circuited.

Further, the conductive material C1 of the first embodiment is a metal or metal alloy with a melting point higher than 300°C, for example, gold, copper, aluminum, nickel, silver or any two of gold, copper, aluminum, nickel, and silver An alloy composed of more than one type; the non-conductive material I1 can be a thermosetting or thermoplastic polymer material, for example, it can be selected from epoxy, silicone, polymethyl methacrylate (PMMA) and ring Groups of sulfides (episulfide), etc. The non-conductive material I1 of this embodiment is a thermosetting material and has a curing temperature, and the melting point of the conductive material C1 is higher than the curing temperature of the non-conductive material I1. In addition, the conductive material C1 of this embodiment is granular and has a particle size (ie, diameter), for example, between 5-50 μm. The shortest distance d between the first bonding pad 112 and the second bonding pad 113 is preferably greater than or equal to twice the particle size, so as to prevent the size of the conductive material C1 from being too large, during the heating and/or pressurizing process , The conductive material C1 itself contacts the first bonding pad 112 and the second bonding pad 113, so that the current is conducted between the first bonding pad 112 and the second bonding pad 113 to cause a short circuit. As mentioned above, in order to meet the application requirements of thinner electronic products, the shortest distance d should not exceed 150μm. The conductive material C1 is, for example, a core-shell structure. In one embodiment, the conductive material C1 includes a conductive core and an insulating layer covering the conductive core. The material of the insulating layer can be the same as the non-conductive material. I1 are the same or different, and there are no restrictions here. In another embodiment, the conductive material C1 includes an insulating core and a conductive layer covering the insulating core.

Please refer to FIG. 3, which is a cross-sectional view of a semiconductor device 100 according to a second embodiment of the present invention. The conductive bonding layer 3 of this embodiment includes a conductive material C2 and a non-conductive material I2, a current conducting region 31 and a current The isolation region 32 contains different contents of conductive material C2, the content of conductive material C2 in the current conducting region 31 is greater than 75% or preferably does not contain non-conductive material I2, and the content of conductive material C2 in the current isolation region 32 is less than 40%, In addition, the current isolation region 32 has a small amount of conductive material C2, and the content of the conductive material C2 in the current isolation region 32 is not 0. For example, the content of the conductive material C2 in the current isolation region 32 is 0.1%-40%, preferably 2% ~10%; the content of the non-conductive material I2 in the current isolation region 32 is greater than 60%, preferably 60% to 99.9%, more preferably 90% to 98%. In one embodiment, the current isolation area 32 has 10%-40% of conductive material C2 and 60%-90% of non-conductive material I2. Preferably, the current isolation area 32 has 20%-30% of conductive material C2. And 70%～80% non-conductive material I2. It should be noted here that the components of the semiconductor device 100 of this embodiment and their connection relationship are similar to those of the first embodiment in FIG. 2. However, the content of the conductive material C2 in the current isolation region 32 of this embodiment is higher than that of the first embodiment described above. The content of the conductive material C1 in the current isolation region 32 of an embodiment is low, so that the current conduction path in the conductive bonding layer 3 is more difficult to pass through the current isolation region 32. The conductive material C2 shown in FIG. The distribution is more sparse than the distribution of the conductive material C1 in the current isolation region 32 in Figure 2, so that the first bonding pad 112 and the second bonding pad 113, the third bonding pad 22 and the fourth bonding pad 23, and the first bonding pad 112 and the fourth bonding pad 23 and the second bonding pad 113 and the third bonding pad 22 cannot contact each other through a small amount of conductive material C2. Therefore, the insulation effect of the current isolation region 32 in the second embodiment is better.

In more detail, the conductive material C2 in the second embodiment has a metal or metal alloy with a melting point lower than 300°C. For example, it can be bismuth, tin, indium, or any two of bismuth, tin, silver, and indium. Two or more alloys, such as tin-bismuth-silver alloy. When the conductive material C2 is a metal alloy, the melting point of the conductive material C2 means the eutectic temperature of the metal alloy; the non-conductive material I2 is a thermosetting polymer material, for example, It is selected from the group consisting of epoxy, silicone, polymethylmethacrylate (PMMA) and episulfide. The non-conductive material I2 has a curing temperature, and the melting point of the conductive material C2 of this embodiment is lower than the curing temperature of the non-conductive material I2. When preparing the semiconductor device 100 of the present invention, a heating step is required. The detailed preparation method will be described later. Before heating the conductive bonding layer 3, the conductive material C2 in the conductive bonding layer 3 is granular and With a particle size, for example, between 5-50 μm, the shortest distance d between the first bonding pad 112 and the second bonding pad 113 is preferably greater than or equal to twice the particle size and not more than 150 μm. The reasons are as described above. In one embodiment, the conductive material C2 has a first metal and a second metal. In detail, the composition of a single particle in the conductive material C2 of FIG. 3 includes the first metal and the second metal, and the first metal The melting point of a metal is lower than the melting point of the second metal, and the content of the first metal is less than the second metal in the composition of the single particle conductive material C2. For example, the single-particle conductive material C2 contains 42% by weight of the first metal and 58% by weight of the second metal. The first metal is tin (melting point is about 231°C). The second metal is, for example, bismuth (melting point is about 271°C). The melting point of the conductive material C2 is the eutectic temperature of the two at about 139°C; in another embodiment, the conductive material C2 is an alloy of tin, silver, and copper. And has a eutectic temperature of 217° C.; in another embodiment, the conductive material C2 has a core-shell structure, including an insulating core and a metal layer sequentially covering the insulating core. The material of the above-mentioned insulating core can be the same as or different from the non-conductive material I2, and there are no restrictions here.

It is worth noting that, in the semiconductor device 100 of the second embodiment in FIG. 3, the conductive material C2 of the current conducting region 31 is in a block shape, and the conductive material C2 of the current isolation region 32 is in a granular shape; however, the second In the semiconductor device 100 of the first embodiment shown in the figure, the conductive material C1 in the current conducting region 31 and the current isolation region 32 are both granular. In detail, in the second embodiment, the conductive material C2 of the current conducting region 32 is continuously distributed between the first bonding pad 112 and the third bonding pad 22, the second bonding pad 113 and the fourth bonding pad 23, and is relatively The conductive material C1 of the current conducting region 32 of the first embodiment is closely arranged and contains few or almost no voids; on the contrary, compared to the bulk conductive material C2 in the second embodiment, it is heated and/or added. The pelletized conductive material C2 is eutecticized to form a granular shape that does not have the original conductive material C2, so that the conductive material C2 in the current conducting region 31 is continuously distributed between the bonding pads 112 and 22 and between the bonding pads 113 and 23 Since the current conduction region 32 of the first embodiment is formed by the conductive materials C1 physically contacting each other, the current conduction region 32 of the first embodiment has several voids formed by the incompatibility of the conductive materials C1. The difference in the shapes of the conductive materials C1 and C2 in the two embodiments is due to the difference in the material of the conductive bonding layer 3, so that the distribution mechanism of the conductive materials C1 and C2 in the preparation of the semiconductor device 100 is significantly different in the two embodiments. The distribution mechanism will be explained in detail later.

Please refer to FIG. 4, which is a cross-sectional view of the semiconductor device 100 of the third embodiment of the present invention. The components of the semiconductor device 100 of this embodiment and their combination relationship are similar to the semiconductor device 100 of the second embodiment described above. The difference is that the semiconductor device 100 of this embodiment further includes a reflective wall 24 protruding from the surface 21 of the carrier board 2. The reflective wall 24 surrounds the third bonding pad 22 and the fourth bonding pad 23 so that the reflective wall 24 and the carrier The surface 21 of the board 2 collectively surrounds a recess 25, and the semiconductor die 1 is arranged in the recess 25. When the semiconductor die 1 is a light-emitting die (the light-emitting die may be a light-emitting diode, for example), the reflective wall 24 has a reflectivity higher than 80% for the light emitted by the light-emitting die, and the reflective wall 24 can be its own The material or structure has high reflectivity to light. Alternatively, the reflective wall 24 can also be coated with a reflective material on the surface facing the recess 25 to generate high reflectivity for the light emitted by the light-emitting die, so as to radiate the light-emitting die The light is concentrated to increase the luminous intensity of the luminous crystal particles (Luminance). The material of the reflective wall 24 is, for example, a metal, an alloy, or a silica gel mixed with reflective particles. The reflective particles can be silicon oxide (SiOx), titanium oxide (TiOx), or boron nitride (BN), for example.

Please refer to FIG. 5, which is a perspective view of the fourth embodiment of the semiconductor device 100 of the present invention. The semiconductor device 100 of the fourth embodiment has a semiconductor die 1 and a carrier 2, a semiconductor die 1 and a carrier A conductive bonding layer 3 is provided between 2 to allow current to flow between the semiconductor die 1 and the carrier 2 through the conductive bonding layer 3. The semiconductor die 1 includes a surface 111 and a first bonding pad 112 and a second bonding pad 113 provided on the surface 111, the carrier 2 includes a surface 21 and a third bonding pad 22 and a fourth bonding pad 23 provided on the surface 21, and The conductive bonding layer 3 has a current conducting region 31 and a current isolation region 32. The current conducting region 31 is provided between the first bonding pad 112 and the third bonding pad 22, and between the second bonding pad 113 and the fourth bonding pad 23 , The current isolation area 32 is set outside the current conduction area 31. The components and their connection relationships in the semiconductor device 100 of the fourth embodiment are substantially the same as those of the second embodiment. For example, in the semiconductor device 100 of the fourth embodiment, the first bonding pad 112 has a first bonding surface 112a. The third bonding pad 22 has a second bonding surface 22a. The first bonding surface 112a and the second bonding surface 22a are respectively substantially parallel to the surface 111 of the semiconductor die 1 and the surface 21 of the carrier 2, and the current conducting region 31 It is set between the first bonding surface 112a and the second bonding surface 22a; however, the difference between this embodiment and the second embodiment is that the first bonding surface 112a of the first bonding pad 112 of the semiconductor die 1 and the carrier 2 The corresponding relationship between the second bonding surface 22a of the third bonding pad 22. In detail, in the second embodiment, the surface 11 of the semiconductor die 1 is substantially parallel to the surface 21 of the carrier board 2, so that the first normal direction a1 of the first bonding pad 112 and the first normal direction a1 of the third bonding pad 22 The two normal directions a2 are approximately parallel. However, in the fourth embodiment, the surface 111 of the semiconductor die 1 is not parallel to the surface 21 of the carrier 2, or the surface 111 of the semiconductor die 1 is perpendicular to the surface 21 of the carrier 2. , So that the first joint surface 112a and the second joint surface 22a have a different corresponding relationship from the second embodiment. Please refer to FIG. 6, the first bonding surface 112a of the first bonding pad 112 has a first normal direction a1, the second bonding surface 22a of the third bonding pad 22 has a second normal direction a2, and the first normal The line direction a1 and the second normal line direction a2 sandwich a first angle θ1, and the first angle θ1 is not 180 degrees. For example, the first angle θ1 is about 60 to 150 degrees. Preferably, the first angle θ1 is 80-100 degrees, more preferably, the first angle θ1 is about 90 degrees. In the semiconductor device 100 of this embodiment, even if the surface 111 of the semiconductor die 1 and the surface 21 of the carrier 2 are not parallel, so that the first normal direction a1 and the second normal direction a2 have an angle as described above, it can be A conductive bonding layer 3 is formed between the semiconductor die 1 and the carrier board 2, so that current is conducted between the first bonding pad 112 and the third bonding pad 22, and between the second bonding pad 113 and the fourth bonding pad 23, and The thickness of the semiconductor device 100 can be effectively reduced, and it is suitable for use in the application of a side backlight module where the volume of the semiconductor device 100 is strictly limited.

Please refer to FIGS. 5 and 6, which are respectively a three-dimensional appearance view of a semiconductor device 100 according to a fourth embodiment of the present invention and a cross-sectional view taken along the a-a' direction in FIG. 5. In detail, the semiconductor die 1 of this embodiment has a first side surface 114 and a second side surface 115 opposite to each other. The first side surface 114 and the second side surface 115 are connected to the surface 111, wherein the first side surface 114 and the second side surface 115 are connected to the surface 111. The side surface 114 is farther away from the carrier board 2 than the second side surface 115, and the second side surface 115 is directly connected to the surface 21 of the carrier board 2. The semiconductor die 1 further has a connection to the first side surface 114 and the second side surface 115 is one of the main light-emitting surfaces 116. A conductive bonding layer 3 is provided between the surface 21 of the carrier 2 and the surface 111 of the semiconductor die 1, wherein the current conducting region 31 of the conductive bonding layer 3 is provided between the first bonding pad 112 and the third bonding pad 22 , And between the second bonding pad 113 and the fourth bonding pad 23, and the current isolation region 32 of this embodiment is set outside the current conduction region 31 of the conductive bonding layer 3. Preferably, the current isolation region 32 includes It covers the outer side of the current conducting region 31. Referring to FIG. 6, the current conducting region 31 has, for example, a first conducting portion 311 and a second conducting portion 312. The first conducting portion 311 is provided between the first bonding pad 112 and the third bonding pad 22, and Between the second bonding pad 113 and the fourth bonding pad 23, the second conductive portion 312 is provided between a side surface 112b of the first bonding pad 112 and the third bonding pad 22, and a side surface of the second bonding pad 113 And the fourth bonding pad 23 (not shown), wherein the side surface 112b of the first bonding pad 112 is connected to the first bonding surface 112a and the second side surface 115, and preferably, the first conductive portion 311 is connected to the second conducting portion 312; the current isolation area 32 has, for example, a first insulating portion 321, a second insulating portion 322, and a third insulating portion 323. On the surface 111 of the bonding pad 112 and the second bonding pad 113, on the surface 21 where the third bonding pad 22 and the fourth bonding pad 23 are not provided, and between the current conducting region 31, the second insulating portion 322 covers the current On the outer side of the conducting region 31 (see Figure 6 for details), the third insulating portion 323 is provided between the second side surface 115 and the second joining surface 22a and adjacent to the second conducting portion 312. Preferably, the current is isolated The first insulating part 321, the second insulating part 322 and the third insulating part 323 of the area 32 are connected. As described in the second embodiment, the conductive bonding layer 3 includes a conductive material C3 and a non-conductive material I3, the current conducting region 31 and the current isolation region 32 have different contents of the conductive material C3, and the conductive material in the current conducting region 31 The content of the material C3 is greater than the current isolation region 32. In one embodiment, the content of the conductive material C3 in the current conducting region 31 is greater than 75%, and the content of the conductive material C3 in the current isolation region 32 is preferably less than 40%, for example, conductive The content of the material C3 in the current isolation area 32 is 0.1%-40%, or 2%-10%, and the conductive material C3 of this embodiment is preferably the same as the conductive material C2 of the second embodiment; The conductive material I3 is preferably the same as the non-conductive material I2 of the second embodiment. FIG. 6 shows that the junction between the current conducting region 31 and the first bonding pad 112 or the second bonding pad 113 of the semiconductor die 1 has a maximum height H, and the current conducting region 31 and the third bonding pad 22 of the carrier 21 or The joint of the fourth bonding pad 23 has a maximum width W. In one embodiment, the maximum height H is 130-200 μm, and the width W is 150-300 μm. Wherein, the non-conductive material content of the first insulating part 321, the second insulating part 322 and the third insulating part 323 is greater than 60%, preferably 60% to 99.9%, more preferably 90% to 98%. In an embodiment of the present invention, the second insulating portion 322 and the third insulating portion 323 do not include the conductive material C3. In an embodiment of the present invention, the second conductive portion 312 does not include the non-conductive material I3.

Please refer to FIG. 7, which is a flowchart of the manufacturing method of the semiconductor device 100 of the present invention. The manufacturing method of the semiconductor device of the present invention includes the following steps: Step a. Prepare a semiconductor die 1. The semiconductor die 1 includes a stacked structure 11, and the stacked structure 11 has a surface 111. The surface 111 is provided with a first bonding pad 112 and a second bonding pad 113, and the first The shortest distance between the bonding pad 112 and the second bonding pad 113 is less than 150 μm; Step b. Prepare a carrier board 2, the carrier board 2 has a surface 21, the surface 21 is provided with a third bonding pad 22 and a fourth bonding pad 23; Step c. Apply a conductive adhesive to the surface 111 of the semiconductor die 1 or the surface 21 of the carrier 2, wherein the conductive adhesive covers the first bonding pad 112 and the second bonding pad 113, or the third bonding pad 22 is covered with conductive glue And the fourth bonding pad 23; Step d. Place the first bonding pad 112 and the second bonding pad 113 of the semiconductor die 1 on the third bonding pad 22 and the fourth bonding pad 23 of the carrier 2 respectively; Step e. Curing the conductive adhesive to form a conductive bonding layer 3 between the surfaces 111 and 21 including a current conducting region 31 and a current isolation region 32, wherein the current conducting region 31 is provided between the first bonding pad 112 and the first bonding pad 112 Between the three bonding pads 22 and between the second bonding pad 113 and the fourth bonding pad 23, the current isolation region 32 is formed between the surfaces 111 and 21 and located outside the current conducting region 31.

Wherein, the above step c is preferably to simultaneously cover the surface of the semiconductor die 1 between the first bonding pad 112, the second bonding pad 113, and the first bonding pad 112 and the second bonding pad 113 with a conductive adhesive in a continuous block 111, or, simultaneously cover the third bonding pad 22, the fourth bonding pad 23, and the surface 21 of the carrier board 2 between the third bonding pad 22 and the fourth bonding pad 23 with conductive adhesive. Covering the above areas with continuous blocks has the advantage of simple manufacturing process, and is particularly suitable for making the shortest distance between the first bonding pad 112 and the second bonding pad 113 in order to make the produced semiconductor device 100 meet the requirements of thinning applications. The distance d is reduced to 15～150μm in the process requirements. In the embodiment of the present invention, in the above step c, the conductive adhesive can be applied to the first bonding pad 112 and the second bonding pad 113 in separate sections by a steel plate printing method with holes, and in the embodiment of the present invention The alignment between the steel plate opening and the first bonding pad 112 or the second bonding pad 113 can allow a large error, which can effectively reduce the yield loss caused by poor alignment, so it is applied to the preparation of miniaturized size The semiconductor device 100 is conducive to the improvement of the product yield. In addition, the curing of the conductive adhesive in the above step e can be achieved through many methods, such as heating, cooling, or adding factors that trigger the curing reaction, etc., and when necessary, an appropriate physical quantity (such as pressure) can also be applied to the The conductive adhesive, as long as the conductive adhesive is cured, can form the current conducting region 31 in the above-mentioned area, it is within the scope of the present invention.

In the method of manufacturing the semiconductor device 100 of the first embodiment of the present invention, step e is to cure the conductive adhesive or conductive film by heating and pressing simultaneously. Please refer to Figures 2 and 7, in the semiconductor device 100 of the first embodiment of the present invention, the conductive adhesive is cured to form the current conducting region 31 and the current isolation region 32, and the conductive material C1 of the current conducting region 31 The content is 7% to 75%, and the content of the conductive material C1 in the current isolation region 32 is 2% to 50%. The conductive adhesive of this embodiment includes a conductive material C1 and a non-conductive material I1. The characteristics of the conductive material C1 and the non-conductive material I1 are as described above. In short, the non-conductive material I1 in this embodiment is a thermosetting material and It has a curing temperature, and the melting point of the conductive material C1 is higher than the curing temperature of the non-conductive material I1, and preferably, the curing temperature of the non-conductive material I1 is higher than room temperature so that the conductive adhesive exhibits a flowable state at room temperature. Before curing the conductive adhesive, the conductive material C1 and the non-conductive material I1 are uniformly mixed; then the surface 111 of the semiconductor die 1 and the surface 21 of the carrier 2 are close to each other. At this time, due to the first bonding pad The distance between 112 and the third bonding pad 22 is less than the distance between the surface 111 of the semiconductor die 1 and the surface 21 of the carrier 2, or the distance between the second bonding pad 113 and the fourth bonding pad 23 is less than the distance between the semiconductor die 1 The distance between the surface 111 of the carrier board 2 and the surface 21 of the carrier board 2. Therefore, the application of pressure will cause the conductive adhesive located in the current conducting region 31 to be first by the bonding pads 112, 22 and 113, 23 of the semiconductor die 1 carrier board 2 aligned with each other. The clamping causes the volume to be reduced, so that the mutually aligned bonding pads 112, 22 and 113, 23 generate current conduction paths due to the conductive material C1 in them, thus forming a current conduction area 31; at the same time, because the current isolation area 32 is not The bonding pads 112, 113, 22, and 23 protruding from the surfaces 111, 21 are provided, and therefore have a larger space than the current conducting region 31, and the conductive material C1 is scattered in the current isolation region 32. A continuous current path is not formed between the bonding pads 112, 113, 22, and 23 so that the current cannot be conducted in this area, and thus a current isolation area 32 is formed. When the conductive adhesive is heated to a temperature higher than the curing temperature of the non-conductive material I1, the non-conductive material I1 is cured to confine the conductive material C1, thereby fixing the distribution of the conductive material C1 in the current conducting region 31 and the current isolation region 32. In another embodiment, the conductive adhesive can also be replaced by a conductive film that is solid at room temperature (not shown). The conductive film contains a conductive material and a non-conductive material like the above-mentioned conductive adhesive. However, the conductive film The difference with the conductive adhesive is: the non-conductive material in the conductive film is a thermoplastic material and has a melting point higher than room temperature, so the conductive film has been formed into a solid sheet at room temperature, and is further heated in step e. The conductive material is heated and melted and pressurized to bond the first bonding pad 112 and the third bonding pad 22, the second bonding pad 113 and the fourth bonding pad 23, and form a current conduction path between the current conduction regions 31, and then the temperature is lowered. The temperature of the non-conductive material is lower than its melting point, so that the conductive film is solidified again, thereby fixing the distribution of the conductive material in the current conducting region 31 and the current isolation region 32. The melting point of the conductive film is, for example, 140°C to 200°C. In addition, because the current isolation region 32 is filled with the non-conductive material I1, in addition to blocking current and avoiding unexpected conduction, the semiconductor device 100 can also increase the semiconductor device 100 through the non-conductive material I1 filled in the current isolation region 32 The structural strength of the semiconductor chip 1 is prevented from cracks or damage caused by external stress due to the gaps between the bonding pads 112, 113, 22, and 23 in the subsequent packaging process. In addition, when the conductive material C1 is a core-shell structure including a conductive core and an insulating layer covering the conductive core, the pressurizing process of curing the conductive adhesive can cause the insulating layer on the surface of the conductive material C1 to be squeezed and broken , The conductive core is exposed and contacted with the first bonding pad 112 and the second bonding pad 22 to conduct current, so as to enable the conductive material C1 to be evenly dispersed in the non-conductive material I1 before curing the conductive glue, and further Avoid unintended conduction in the unpressurized horizontal direction when the conductive adhesive is cured.

In the method of manufacturing the semiconductor device 100 of the second embodiment of the present invention, in step e, the conductive adhesive is cured by heating. In this embodiment, a pressurizing process can be selectively added to the manufacturing method as appropriate. Please refer to Figures 3 and 7, in the second embodiment of the present invention, the conductive adhesive includes a conductive material C2 and a non-conductive material I2. The materials of the conductive material C2 and the non-conductive material I2 are as described above. The melting point temperature of C2 is lower than the curing temperature of the non-conductive material I2, and the conductive adhesive of this embodiment uses this material characteristic to form a current conducting region 31 and a current isolation region 32 after the conductive adhesive is cured. In detail, before curing the conductive adhesive, the conductive material C2 and the non-conductive material I2 are uniformly mixed, and the conductive material C2 is granular. Then, the conductive adhesive is coated between the surfaces 111 and 21, and preferably Use a continuous block to simultaneously cover the first bonding pad 112, the second bonding pad 113, and the surface 111 of the semiconductor die 1 between the two, or simultaneously cover the third bonding pad 22 and the fourth bonding pad with a continuous block Pad 23 and the surface 21 of the carrier 2 between the two; then, heat is applied to heat the conductive adhesive to a temperature higher than the melting point of the conductive material C2. The heating temperature in this embodiment is between 140 and 180°C. The materials of the bonding pads 112, 113, 22, and 23 and the conductive material C2 are all metal or alloy materials, and the conductive material C2 is selected to have excellent surface wetting characteristics for the materials of the bonding pads 112, 113, 22, and 23 (wetting property), so when the heating temperature reaches the melting point of the conductive material C2 but does not reach the curing temperature of the non-conductive material I2, the conductive material C2 can flow freely in the conductive adhesive, and is affected by the surface wetting properties, making it originally located The conductive material C2 in the current isolation region 23 is attracted and concentrated between the first bonding pad 112 and the third bonding pad 22, and between the second bonding pad 113 and the fourth bonding pad 23, and is originally granular before curing. The conductive material C2 gathers together to form a block due to the melt flow, so that the content of the conductive material C2 in the current conducting region 31 is higher than 75%; however, the surface 111 of the bonding pads 112, 113, 22, and 23 is not provided , 21, because the conductive material C2 flows and gathers to the current conduction area 31, the content of the conductive material C2 contained in the area outside the current conduction area 31 is relatively low. The current isolation area 32 in the semiconductor device 100 of this embodiment is only Contains 0.1%-40% conductive material C2, and the remaining content is non-conductive material I2. Next, heat the conductive adhesive to reach the curing temperature of the non-conductive material I2 or higher, so that the non-conductive material I2 is cured. At this time, the conductive material C2 is already between the first bonding pad 112 and the third bonding pad 22 and the second bonding pad 113 and the fourth bonding pad 23 are gathered together, and the solidified non-conductive material I2 can confine the flow area of the conductive material C2 that is still molten, so that the distribution of the conductive material C2 in the current conduction area 31 and the current isolation area 32 is fixed.

Please refer to FIGS. 6 and 7, in the method of fabricating the semiconductor device of the fourth embodiment of the present invention, step c is preferably to simultaneously cover the first bonding pad 112 of the semiconductor die 1 with a continuous block of conductive glue , The second bonding pad 113 and the surface 111 of the semiconductor die 1 between the two, or a continuous block covering the third bonding pad 22, the fourth bonding pad 23 and the between the two at the same time The surface 21 of the carrier 2; step d is to make the semiconductor die 1 side and make the second side surface 115 facing the surface 21 of the carrier 2 align with the carrier 2, so that the conductive glue covers the second side surface 115, The side surfaces of the first bonding pad 112 and the second bonding pad 113 are correspondingly bonded to the surfaces of the third bonding pad 22 and the fourth bonding pad 23 of the carrier board 21, wherein the first normal direction a1 of the first bonding surface 112a and The second normal direction a2 of the second bonding surface 22a sandwiches the first angle θ1, and the conductive adhesive is covered between the second side surface 115 of the semiconductor die 1 and the carrier 21; step e is heating by heating The conductive adhesive is heated to 140~180°C to cure the conductive adhesive. The conductive adhesive of this embodiment includes conductive material C3 and non-conductive material I3. The material is preferably the same as that of the conductive adhesive of the second embodiment. Repeat. Similar to the second embodiment, since the conductive material C3 and the bonding pads 112, 113, 22, and 23 have good surface wetting characteristics, the conductive particles in the conductive material C3 are heated and melted and aggregated into each other and distributed in a piece. Between the first bonding pad 112 and the third bonding pad 22, and between the second bonding pad 113 and the fourth bonding pad 23; then, heating the conductive glue to a temperature above the curing temperature of the non-conductive material I3 to cure the non-conductive material I3 However, most of the conductive material C3 is confined between the first bonding pad 112 and the third bonding pad 22 and between the second bonding pad 113 and the fourth bonding pad 23 to form a current conducting region 32.

Please refer to FIG. 8, which is a cross-sectional view of a semiconductor device 100 according to a fifth embodiment of the present invention. The semiconductor device 100 includes a plurality of semiconductor dies 1 and a carrier 2, wherein the plurality of semiconductor dies 1 are light-emitting crystals. grain. In detail, the semiconductor device 100 includes a carrier 2, a first light-emitting die 1, a second light-emitting die 4, a third light-emitting die 5, and a reflective wall 26. The reflective wall 26 is protruding from the carrier. The surface 21 of the board 2 has a light reflection characteristic similar to the aforementioned reflective wall 24, and the reflective wall 26 surrounds the first light-emitting die 1, the second light-emitting die 4, and the third light-emitting die 5. The structures of the first light-emitting die 1, the second light-emitting die 4, and the third light-emitting die 5 are similar to the semiconductor die 1 of the first and second embodiments, and the surface 21 of the carrier 2 is provided with three groups The third bonding pad 22 and the fourth bonding pad 23, wherein the two bonding pads 112, 113 of the first light-emitting die 1 are correspondingly bonded to the carrier 2 through the bonding structure and method disclosed in the first or second embodiment. One set of bonding pads 22, 23 on the surface 21 of the, the second light-emitting die 4 and the third light-emitting die 5 are also provided on the surface 21 of the carrier board 2, the second light-emitting die 4 and the third light-emitting die 5 The two bonding pads can be respectively bonded to the other two groups of bonding pads on the carrier board 2 using the bonding structure and method disclosed in the first and second embodiments above, or they may be bonded to the carrier board 2 by wire bonding. The other two groups of bonding pads electrically connect the first light-emitting die 1, the second light-emitting die 4, and the third light-emitting die 5 to the carrier 2. When current flows between the carrier 2 and the first light-emitting die 1, the second light-emitting die 4, and the third light-emitting die 5, the first light-emitting die 1, the second light-emitting die 4, and the third light-emitting die 5 emit light. The die 5 emits a first light, a second light and a third light respectively, and the first light, the second light and the third light are mixed to form a white light. The second light-emitting die 4 shown in FIG. 8 includes a first light-emitting die 1 emitting first light and a second wavelength conversion layer 41 formed on the light-emitting surface of the corresponding first light-emitting die 1, and the third The light-emitting die 5 includes a first light-emitting die 1 emitting first light and a third wavelength conversion layer 51 formed on the light-emitting surface of the corresponding first light-emitting die 1, and the first light-emitting die 1, the second The light-emitting die 4 and the third light-emitting die 5 are both bonded to the carrier 2 with conductive glue. Among them, the first light-emitting die 1, the second light-emitting die 4, and the third light-emitting die 5 preferably do not have a substrate structure and are bonded to the carrier board 2 by flip-chip bonding, wherein The detailed structure of the first light-emitting die 1 will be described later. In one embodiment, the first light emitted by the first light-emitting die 1 is blue light; the second wavelength conversion layer 41 of the second light-emitting die 4 includes a material that can be excited by blue light and converted into green light, such as Is a phosphor or quantum dot, and the second light is green light; the third wavelength conversion layer 51 of the third light-emitting die 5 contains a material that can be excited by blue light and converted into red light, such as phosphor or quantum Point, and the third light is red light. It should be noted here that the semiconductor device 100 may optionally include a light-blocking wall B surrounding the second light-emitting die 4 and the third light-emitting die 5 respectively. Specifically, the light-blocking wall B surrounds the second light-emitting die. 4 and the sidewall of the second wavelength conversion layer 41, and the stacked structure surrounding the third light-emitting die 5 and the sidewall of the third wavelength conversion layer 51, thereby enhancing the second light-emitting die 4 and the third light-emitting The light emitted by the die 5 respectively transmits through the second wavelength conversion layer 41 and the third wavelength conversion layer 51 to perform wavelength conversion ratio, and prevents the first light leaking from the side of the second light-emitting die 4 from exciting the adjacent third The light-emitting die 5, or the first light leaking from the side of the third light-emitting die 5 excites the adjacent second light-emitting die 4 to mix with unexpected light colors.

FIG. 9 is a cross-sectional view of a semiconductor device 100 according to a sixth embodiment of the invention. This embodiment is similar to FIG. 8. The first light-emitting die 1 and the second light-emitting die 4 of the semiconductor device 100 are bonded to the carrier 2 using the bonding structure and method disclosed in the first and second embodiments above, and The difference between the embodiment in FIG. 8 is that the third light-emitting die 5 of this embodiment has a vertical structure, and has a first electrode 52 and a second electrode 53 disposed on opposite sides of the third light-emitting die 5. On the other hand, the second electrode 53 of the third light-emitting die 5 can be bonded to one of the bonding pads P1 on the carrier 2 through the bonding structure and method disclosed in the first and second embodiments, and the first electrode 52 Then, a metal wire 54 is electrically connected to a bonding pad P2 on the carrier 2 by face-up wire bonding; or, in another embodiment, when the third light-emitting die 5 When it is a horizontal structure and has the first electrode 52 and the second electrode 53 on the same side of the third light-emitting die 5 (not shown), the first electrode 52 and the second electrode 53 of the third light-emitting die 5 can be Two metal wires (not shown in the figure) are electrically connected to the corresponding two bonding pads on the carrier board 2 through a formal wire bonding method. The first light-emitting die 1, the second light-emitting die 4 and the third light-emitting die 5 respectively emit a first light, a second light and a third light, and the first light, the second light and the third light Mixed to form white light, the second light-emitting die 4 includes a first light-emitting die 1 that emits the first light and a second wavelength conversion layer is formed on the light-emitting surface of the corresponding first light-emitting die 1, and the third light-emitting die does not It has a third wavelength conversion layer 51 and can emit third light, where the first light is, for example, blue light, the second light is, for example, green light, and the third light is, for example, red light. In one embodiment, a recess formed by the reflective wall 26 and the surface 21 of the carrier 2 is filled with a transparent colloid 6 to protect the light-emitting dies 1, 4 and 5. The transparent colloid 6 may include but is not limited to Epoxy, acrylic, silicone, or a combination thereof. In another embodiment, the material of the transparent gel 6 includes the same material as the non-conductive materials I1 and I2 in the conductive gel, so that the transparent gel 6 and the non-conductive materials I1 and I2 have the same thermal expansion coefficient, preventing the semiconductor device 100 During operation, thermal expansion and contraction cause stress on the light-emitting dies 1, 4, and 5, which affects the bonding stability of the carrier board 2 and the light-emitting dies 1, 4, and 5.

Please refer to FIG. 10, which is a top view of the light emitting module 200 according to the first embodiment of the present invention. The light emitting module 200 includes a plurality of semiconductor devices 100 as shown in FIG. 8 or FIG. In one embodiment, a plurality of semiconductor devices 100 have a common carrier 2 and are arranged in a two-dimensional matrix, wherein the plurality of semiconductor devices 100 are connected to each other by a reflective wall 26, and the reflective wall 26 of each semiconductor device 100 The shape of the enclosed notch can be round as in this embodiment, or can be adjusted to other shapes such as square or strip according to display requirements. The single notch enclosed by the reflective wall 26 has a notch area D, and the concave The mouth area is preferably between 1-20 mm2. The light-emitting module 200 can be further applied to display devices, such as TV screens, mobile phone screens, billboards, or sports billboards. The light-emitting module 200 includes a plurality of semiconductor devices 100 as an array of pixels. The number, color, and arrangement of the light-emitting dies in the semiconductor device 100 and the distance between the semiconductor devices 100 will affect the viewing performance of the user. Visual characteristics, for example: a display device using a smaller size semiconductor device 100 can accommodate a larger number of semiconductor devices 100 than a larger size semiconductor device 100 under the same unit area, so that the display device has The greater the resolution.

Figures 11 and 12 show the light-emitting module 300 according to the second embodiment of the present invention. For example, it is an edge-type light-emitting module, which includes the fourth shown in Figure 5 and Figure 6 above. The semiconductor device 100, a light guide plate 301, and a diffusion plate 302 of the embodiment, wherein the light-emitting module 300 may include several semiconductor devices 100, the main light-emitting surface 116 of the semiconductor die 1 and the first electrode pad 112 and the first electrode pad 112 The surfaces 111 of the two electrode pads 113 are opposite, and the main light-emitting surface 116 is provided between the first side surface 114 and the second side surface 115; the light guide plate 301 has a light-emitting surface 301a and two opposite side surfaces 301b connected to the light-emitting surface 301a. The semiconductor devices 100 are respectively arranged with the main light-emitting surface 116 of the semiconductor die 1 facing the two side surfaces 301b of the light guide plate 301; the diffusion plate 302 is arranged on the light-emitting surface 301a of the light guide plate 301. The light emitted by the semiconductor die 1 enters the side 301b of the light guide plate 301 from the main light exit surface 116. The light guide plate 301 guides the light to the light exit surface 301a and enters the diffusion plate 302 to uniformly emit the light through the diffusion plate 302. The light-emitting module 300 preferably further includes a reflective layer 303 coupled to the surface of the light guide plate 301 opposite to the light-emitting surface 301a to reflect light through the reflective layer 303 and guide the light into the diffuser plate 302 to increase the light uniformity of the light-emitting module 300. The light-emitting module 300 may further include a supporting plate 304 so that the reflective layer 303, the light guide plate 301, the diffusion plate 302 and the semiconductor device 100 are all disposed on the supporting plate 304. Fig. 12 is a perspective view of the light emitting module 300 of Fig. 11. The semiconductor device 100 includes a plurality of semiconductor dies 1 arranged on a carrier 2 and the plurality of semiconductor dies 1 are along the side 301b of the light guide plate 301 They are arranged in a one-dimensional array. However, the number and arrangement of the semiconductor dies 1 in FIG. 12 are only examples and not limited thereto.

Please refer to FIG. 13, which is a cross-sectional view of a semiconductor die 1 according to an embodiment of the present invention. The semiconductor die 1 is a flip-chip type light-emitting device. The semiconductor die 1 of this embodiment is It can be used as the semiconductor die 1 in Figs. 1 to 6, the first light emitting die 1 and the second light emitting die 4 in Figs 8-9, and the third light emitting die 5 in Fig. 8. In detail, the semiconductor die 1 includes a stacked structure 11, a first bonding pad 112 and a second bonding pad 113 provided on the surface 111 of the stacked structure 11, and the stacked structure 11 includes a substrate 121 and a semiconductor stack 122. The substrate 121 is used to support and carry the semiconductor stack 122, and the first bonding pad 112 and the second bonding pad 113 are arranged on the same side of the semiconductor stack 122, which is a horizontal type semiconductor structure . In one embodiment, the semiconductor stack 122 is disposed between the bonding pads 112, 113 and the substrate 121, and the substrate 121 is a transparent substrate. After the semiconductor die 1 is bonded to the carrier 2, light can be emitted toward the substrate 121 The transparent substrate includes, but is not limited to, transparent materials such as sapphire, glass, and quartz.

The semiconductor stack 122 includes a first semiconductor layer 122a, a second semiconductor layer 122b, and an active layer 122c formed between the first semiconductor layer 122a and the second semiconductor layer 122b, and the second semiconductor layer 122b, the active layer 122c and the first semiconductor layer 122a are sequentially disposed on the substrate 121. The light-emitting stack 122 can be directly epitaxially grown on the substrate 121; or the light-emitting stack 122 can be epitaxially grown on a growth substrate and then The substrate transfer technology joins the light-emitting stack 122 to the substrate 121 and removes the growth substrate; or, in another embodiment, the stacked structure 11 may not include any substrate structure, and the light-emitting stack 122 is directly epitaxially grown After a growth substrate, the growth substrate is removed so that the laminated structure 11 does not have any substrate, so that the thickness of the semiconductor die 1 can be reduced to meet the requirements of thinner applications, such as backlights for mobile devices . The light-emitting stack 122 can be epitaxially grown on the substrate 121 or the growth substrate by methods such as metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE). , And the first semiconductor layer 122a and the second semiconductor layer 122b have a first conductivity type and a second conductivity type, respectively. The active layer 122c may include a single heterostructure, a double heterostructure, or Multiple quantum wells are used to emit light when driving. Among them, the first bonding pad 112 and the second bonding pad 113 are respectively disposed on the first semiconductor layer 122a and the second semiconductor layer 122b. The above-mentioned transparent substrate means that the energy gap of the material of the substrate 121 is greater than the energy gap of the active layer 122c. In order to have a high transmittance to the light generated by the active layer 122c. When the light-emitting stack 122 is bonded to the substrate 121 by substrate transfer technology, a transparent bonding layer (not shown) may be provided between the substrate 121 and the semiconductor stack 122. The bonding layer may be an organic polymer material or an inorganic material, such as Oxide, nitride or fluoride.

Please refer to FIG. 13 continuously. The stacked structure 11 further includes a reflective layer 15 disposed on the first semiconductor layer 122 a and an insulating layer 16 disposed on the reflective layer 15. The semiconductor die 1 is further provided with a first channel 13 and a second channel 14. The first channel 13 is formed by removing part of the insulating layer 16 during the manufacturing process to expose the reflective layer 15; the second channel 14 is formed in It is formed by removing part of the active layer 122c, the first semiconductor layer 122a, the reflective layer 15 and the insulating layer 16 during the process to expose the second semiconductor layer 122b. The first electrode pad 112 is electrically connected to the first semiconductor layer 122a through the first channel 13, the second electrode pad 113 is electrically connected to the second semiconductor layer 122b through the second channel 14, and the insulating layer 16 is electrically connected to the first channel 13 The opening area is smaller than the area of the first bonding pad 112, and the opening area of the insulating layer 16 in the second channel 14 is smaller than the area of the second bonding pad 113. In detail, the first bonding pad 112 and the second bonding pad 113 are electrically connected to the semiconductor stack 122 through the first channel 13 and the second channel 14, respectively, and the first channel 13 and the second channel 14 are through the insulating layer 16 The area of the opening in contact with the semiconductor stack 122 is smaller than the area of the first bonding pad 112 and the second bonding pad 113, respectively. The first bonding pad 112 and the second bonding pad 113 can allow the semiconductor die 1 to pass through a larger area of the second bonding pad. A bonding pad 112 and a second bonding pad 113 introduce current and thereby increase the heat dissipation capacity of the semiconductor die 1. The reflective layer 16 is used to reflect the light emitted from the active layer 122c in the direction of the first semiconductor layer 122a toward the substrate 121, thereby increasing the light extraction efficiency of the semiconductor die 1. The structure of the semiconductor die 1 described above is only a possible embodiment, but it is not intended to limit the structure of the semiconductor die 1, as long as the shortest distance between the first bonding pad 112 and the second bonding pad 113 of the semiconductor die 1 is The semiconductor die 1 with a distance of less than 150 μm can be covered and accommodated within the scope of this embodiment.

Please refer to FIG. 14, which is a cross-sectional view of a semiconductor die 1'according to another embodiment of the present invention. The semiconductor die 1'is a package including a chip-scale-package (chip-scale-package; CSP) technology. The grain of the material. The semiconductor die 1'includes a semiconductor die 1 as shown in FIG. 13 above, which has a first bonding pad 112 and a second bonding pad 113 provided on the surface 111, and the first bonding pad 112 has a first metal The extension portion 112E. The first metal extension portion 112E is provided with a first end 112T in the direction facing the second bonding pad 113, and the second bonding pad 113 has a second metal extension portion 113E, and the second metal extension portion 113E faces the first bonding pad. The direction of the pad 112 has a second end 113T, and the first end 112T of the first bonding pad 112 and the second end 113T of the second bonding pad 113 have a shortest distance d less than 150 μm. The semiconductor die 1'further includes a package body 19 to cover the semiconductor die 1, wherein the first metal extension 112E and the second metal extension 113E protrude from the surface of the semiconductor die 1 to extend to the package 19 The main light-emitting surface 116' is formed on the opposite surface of the surface 111 of the semiconductor die 1. The package body 19 may optionally include a wavelength conversion body 191 that can be excited by the light emitted by the semiconductor die 1 and convert the light emitted by the semiconductor die 1 into light of different wavelengths. The package 19 includes epoxy, silicone, polyimide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), Su8, and acrylic resin (Acrylic Resin) , Polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), or polyetherimide (Polyetherimide); the wavelength conversion body 191 contains one or more than two Types of inorganic phosphor (phosphor), organic fluorescent colorant (organic fluorescent colorant), semiconductor material (semiconductor), or a combination of the above materials. Inorganic phosphors include, but are not limited to, yellow-green phosphors and red phosphors. The composition of the yellow-green phosphor is aluminum oxide (YAG or TAG), silicate, vanadate, alkaline earth metal selenide, or metal nitride. The composition of the red phosphor is, for example, fluoride (K2TiF6:Mn4+, K2SiF6:Mn4+), silicate, vanadate, alkaline earth metal sulfide, metal oxynitride, or tungstomolybdate family mixture. The semiconductor material includes nano-crystal semiconductor materials, such as quantum-dot light-emitting materials. Quantum dot luminescent materials can be selected from zinc sulfide (ZnS), zinc selenide (ZnSe), zinc telluride (ZnTe), zinc oxide (ZnO), cadmium sulfide (CdS), cadmium selenide (CdSe), telluride Cadmium (CdTe), gallium nitride (GaN), gallium phosphide (GaP), gallium selenide (GaSe), gallium antimonide (GaSb), gallium arsenide (GaAs), aluminum nitride (AlN), aluminum phosphide (AlP), aluminum arsenide (AlAs), indium phosphide (InP), indium arsenide (InAs), tellurium (Te), lead sulfide (PbS), indium antimonide (InSb), lead telluride (PbTe), Lead selenide (PbSe), antimony telluride (SbTe), zinc cadmium selenium sulfide (ZnCdSeS), copper indium sulfide (CuInS), cesium lead chloride (CsPbCl3), cesium lead bromide (CsPbBr3), and cesium lead iodide (CsPbI3). The semiconductor die 1'of this embodiment may be the same as the semiconductor die 1 of the first embodiment, including a reflective layer 15 on the surface 111, the first bonding pad 112, and the second bonding pad 113, and the first metal extension 112E transmits and reflects One opening of the layer 15 is connected to the first bonding pad 112, and the second metal extension 113E is connected to the second bonding pad 113a through the other opening of the reflective layer 15. However, the reflective layer 15 of this embodiment is made of an insulating material to protect The light from the semiconductor die 1 ′ toward the surface 111 passes through the reflective layer 15 and is emitted toward the main light emitting surface 116 ′ of the package body 19.

The boundary of the current conducting region 31 described in the above embodiments is a continuous outer boundary formed by the continuous joining of the conductive materials C1, C2, C3 on the outer side of the current conducting region 31, such as the thick black line in Figure 2 As shown; the boundary of the current isolation region 32 described in the above embodiments is the outer boundary continuously formed by the non-conductive material on the outside of the current isolation region 32, which is described here. In addition, the above-mentioned embodiments are used to describe the technical content and the features of the invention, so that those skilled in the art can understand the content of the present invention and implement them accordingly, and are not intended to limit the scope of the present invention. In other words, any obvious modification or alteration made by anyone to the present invention does not depart from the spirit and scope of the present invention. For example, the electrical connection is not limited to series connection. It should be understood that the above-mentioned embodiments of the present invention can be combined or replaced with each other under appropriate circumstances, and are not limited to the specific embodiments described.

It is understandable that for those who are familiar with the art, different modifications or changes can be applied to the present invention without departing from the spirit and scope of the present invention. The foregoing description aims to cover the disclosure of modifications or alterations of the present invention within and equal to the scope of the present invention.

100: Semiconductor device 200, 300: light-emitting module 1: Semiconductor die, first light-emitting die 11: Laminated structure 111: Surface 112: first bonding pad 112a: first joint surface 112b: side surface 112E: The first metal extension 112T: first end 113: Second bonding pad 113E: second metal extension 113T: second end 114: First side surface 115: second side surface 116, 116’: Main light emitting surface: 121: substrate 122: semiconductor stack 122a: the first semiconductor layer 122b: second semiconductor layer 122c: active layer 13: First channel 14: Second channel 15: reflective layer 16: insulating layer 2: carrier board 21: Surface 22: Third bonding pad 22a: second joint surface 23: Fourth bonding pad 24: reflective wall 25: Notch 26: reflective wall 3: Conductive bonding layer 31: Current conduction area 311: The first conduction part 312: The second conduction part 32: Current isolation zone 321: The first insulating part 322: second insulating part 323: The third insulating part 4: The second light-emitting die 41: second wavelength conversion layer 5: The third light-emitting die 51: third wavelength conversion layer 52: first electrode 53: second electrode 54: Metal wire 6: Transparent colloid 301: light guide plate 302: diffuser 301a: Light emitting surface 303: reflective layer 304: support plate d: shortest distance C1, C2, C3: conductive material I1, I2, I3: non-conductive materials a1: the first normal direction a2: second normal direction θ1: the first angle H: Maximum height W: Maximum width P1, P2: Bonding pad B: Light barrier D: Notch area

FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the invention.

FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment of the invention.

FIG. 3 is a cross-sectional view of the semiconductor device according to the second embodiment of the invention.

FIG. 4 is a cross-sectional view of a semiconductor device according to a third embodiment of the invention.

FIG. 5 is a perspective view of a semiconductor device according to a fourth embodiment of the invention.

Fig. 6 is a cross-sectional view of the semiconductor device according to the fourth embodiment of the present invention taken along the a-a' section of Fig. 5.

FIG. 7 is a flowchart of the manufacturing method of the semiconductor device of the present invention.

FIG. 8 is a cross-sectional view of a semiconductor device according to a fifth embodiment of the invention.

FIG. 9 is a cross-sectional view of a semiconductor device according to a sixth embodiment of the invention.

FIG. 10 is a top view of the light emitting module according to the first embodiment of the invention.

FIG. 11 is a cross-sectional view of the light emitting module according to the second embodiment of the invention.

Figure 12 is a perspective view of a light emitting module according to a second embodiment of the invention.

FIG. 13 is a cross-sectional view of a semiconductor die according to an embodiment of the invention.

FIG. 14 is a cross-sectional view of a semiconductor die according to another embodiment of the invention.

no

100: Semiconductor device

1: Semiconductor die

11: Laminated structure

111: Surface

112: first bonding pad

112a: first joint surface

113: Second bonding pad

2: carrier board

21: Surface

22: Third bonding pad

22a: second joint surface

23: Fourth bonding pad

3: Conductive bonding layer

31: Current conduction area

32: Current isolation zone

d: shortest distance

a1: the first normal direction

a2: second normal direction

Claims (10)

A light-emitting module, including: A common carrier board; A plurality of semiconductor devices are formed on the common carrier, each of the plurality of semiconductor devices includes at least three semiconductor dies, and one of the at least three semiconductor dies includes: A laminated structure; and A first bonding pad and a second bonding pad are disposed on an upper surface of the laminated structure, and the first bonding pad Has a top surface away from the upper surface, wherein the shortest distance between the first bonding pad and the second bonding pad The distance is less than 150 μm; A carrier board with a surface; A third bonding pad and a fourth bonding pad are provided on the surface; and A conductive bonding layer, including: A first conductive portion is provided between the first bonding pad and the third bonding pad, and includes a A first conductive material in a first shape, and the first shape has a height; A second conductive portion is provided between the second bonding pad and the fourth bonding pad, and includes the first Conductive material; and A current isolation area, viewed from a cross-sectional view, covers the first conductive portion, and includes a Two-shaped second conductive material; Wherein, the second shape has a particle size, and the height is greater than the particle size. As for the light-emitting module described in item 1 of the scope of patent application, the current isolation region includes a non-conductive material. According to the light-emitting module described in claim 1, the laminated structure includes a semiconductor stack, and one of the at least three semiconductor dies further includes a first channel and a second channel, the first The bonding pad is electrically connected to the semiconductor stack through the first channel, wherein the contact area between the first channel and the semiconductor stack is smaller than the area of the first bonding pad. According to the light-emitting module described in item 1 of the scope of patent application, the plurality of semiconductor devices are arranged in a two-dimensional matrix on the common carrier. According to the light emitting module described in claim 1, wherein the shortest distance between the first bonding pad and the second bonding pad is 15-100 μm. According to the light-emitting module described in claim 1, wherein the shortest distance between the first bonding pad and the second bonding pad is greater than or equal to twice the particle size. According to the light-emitting module described in item 1 of the scope of patent application, the first conductive material includes a metal alloy composed of at least two materials among bismuth, tin, silver, and indium. According to the light-emitting module described in item 2 of the scope of patent application, the non-conductive material is a thermosetting material, and the curing temperature of the non-conductive material is higher than the melting point of the first conductive material. In the light emitting module described in the first item of the scope of patent application, the surface is provided with a reflective wall connected and protruding from the surface, and the reflective wall surrounds the at least three semiconductor dies. According to the light-emitting module described in claim 1, the current isolation region includes a first insulating portion and a second insulating portion, and the first insulating portion is provided on the one of the at least three semiconductor dies Between the upper surface, the surface of the carrier board, and the current conducting region, the second insulating portion covers the outer side of the current conducting region.

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