TW202023000A - Semiconductor package structure - Google Patents

Abstract

A semiconductor package structure includes a lead frame, a chip, an adhesive layer, and a molding compound. The lead frame includes a die pad and a plurality of leads. The die pad has an upper surface, a lower surface opposite to the upper surface, a side surface connecting the upper surface, and a first corner between the upper surface and the side surface. The chip is disposed on the upper surface of the die pad and electrically connected to the plurality of leads. The chip is adhered to the die pad through the adhesive layer. The adhesive layer covers the upper surface and a portion of the side surface of the die pad and covers the first corner of the die pad. The molding compound covers the lead frame, the chip and the adhesive layer.

Description

Semiconductor package structure

The present invention relates to a packaging structure, and more particularly to a semiconductor packaging structure.

Semiconductor packaging technology includes many packaging forms. Among them, the quad/double flat no-lead (QFN/DFN) package, which belongs to the flat package series, has a short signal transmission path and a relatively fast signal transmission speed, so the square/two The square flat no-lead package is suitable for high-frequency transmission chip packages and is one of the mainstream low pin count packages. Generally speaking, the lead frame used in the QFN/DFN package is manufactured by etching a thin metal plate into a chip carrier and a plurality of pins. The etching liquid flows from the bottom surface of the thin metal plate so that the finally formed bearing seat or pin has a slightly arc-shaped side wall, and a sharp angle is formed between the top surface of the bearing seat or the pin and the side wall, causing stress to be easily concentrated there. . In the subsequent Temperature Cycle Test (TCT) or actual product application, the molding compound covering the lead frame is likely to break due to thermal expansion and contraction from the sharp corners of the carrier or pins (crack), and even break to the outside of the semiconductor package, thereby reducing the reliability of the package. Therefore, how to overcome the above-mentioned technical problem that the semiconductor package is cracked after being heated has become one of the problems to be solved urgently.

The invention provides a semiconductor packaging structure with good reliability.

The semiconductor packaging structure of the present invention includes a lead frame, a chip, a glue layer and a packaging glue. The lead frame includes a bearing seat and a plurality of pins. The bearing seat has an upper surface, a lower surface opposite to the upper surface, a side surface connected to the upper surface, and a first corner between the upper surface and the side surface. The chip is arranged on the upper surface of the carrier and electrically connected to a plurality of pins. The chip is connected to the bearing seat through the adhesive layer. The adhesive layer covers the upper surface and part of the side surface of the bearing seat, and covers the first corner of the bearing seat. The packaging glue covers the lead frame, the chip and the glue layer.

In an embodiment of the present invention, the elastic modulus of the above-mentioned adhesive layer is smaller than the elastic modulus of the packaging glue.

In an embodiment of the present invention, the aforementioned wafer extends beyond the first corner of the carrier.

In an embodiment of the present invention, each of the above-mentioned pins has a top surface, a side wall connecting the top surface, and a second corner between the top surface and the side wall, and the chip and the adhesive layer extend to the top of a part of the plurality of pins. On the surface, the adhesive layer covers part of the second corners of the plurality of pins.

In an embodiment of the present invention, the aforementioned bearing seat further has a first recess. The first recess causes the side surface to include a first side surface and a second side surface, and the lower surface includes a first lower surface and a second lower surface. The first side surface is farther from the center of the bearing seat than the second side surface. The surface is farther from the upper surface than the first lower surface.

In an embodiment of the present invention, the above-mentioned adhesive layer covers the first side surface of the supporting base.

In an embodiment of the present invention, the above-mentioned adhesive layer further covers the first lower surface.

In an embodiment of the present invention, each of the aforementioned pins has a top surface, a bottom surface opposite to the top surface, a side wall connected to the top surface, a second corner between the top surface and the side wall, and a second recess. The second recess makes the side wall include a first side wall and a second side wall, and the bottom surface includes a first bottom surface and a second bottom surface. The second side wall is farther from the supporting seat than the first side wall, and the second bottom surface is farther from the top surface than the first bottom surface. The glue layer extends to a part of the top surface of the plurality of pins, and the glue layer covers a part of the second corners of the plurality of pins.

In an embodiment of the present invention, the above-mentioned adhesive layer covers the first side surface of the carrier and part of the first side walls of the plurality of pins.

In an embodiment of the present invention, the above-mentioned adhesive layer further covers the first bottom surface of the supporting base and the first bottom surface of the lead.

Based on the above, the semiconductor package structure of the present invention utilizes a rubber layer with better elasticity to cover the first corner of the carrier to help dissipate the stress that tends to concentrate on the first corner, so as to reduce the temperature cycle test or subsequent product operation of the package compound. The phenomenon of cracking from the first corner due to thermal expansion and contraction, thereby improving the reliability of the semiconductor packaging structure.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below and described in detail in conjunction with the accompanying drawings.

The invention will be explained more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various forms, and should not be limited to the embodiments described herein. The thickness, size or size of layers or regions in the drawings will be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

1 to 8 are schematic cross-sectional views of semiconductor package structures according to some embodiments of the invention. Please refer to FIG. 1 first, the semiconductor package structure 100 includes a lead frame 110, wherein the lead frame 110 includes a carrier 120 and a plurality of pins 130. The supporting seat 120 has an upper surface 121, a lower surface 122 opposite to the upper surface 121, a side surface 123 connected to the upper surface 121, and a first corner R1 between the upper surface 121 and the side surface 123. On the other hand, the pin 130 has a top surface 131, a bottom surface 132 opposite to the top surface 131, a side wall 133 connected to the top surface 131, and a second corner R2 between the top surface 131 and the side wall 133. In addition, a plurality of pins 130 are arranged around the supporting base 120 with a gap G. The plurality of pins 130 may be arranged on two opposite sides of the supporting base 120, or may surround the four sides of the supporting base 120, which is not limited in the present invention.

In this embodiment, the semiconductor package structure 100 further includes a wafer 140. The chip 140 is disposed on the upper surface 121 of the carrier 120. On the other hand, as shown in FIG. 1, the chip 140 may extend beyond the first corner R1 of the carrier 120, but does not contact the top surface 131 of the pin 130. In other words, the wafer 140 may only extend above the gap G. It is particularly noted that the present invention does not limit the type of the chip 140, which may be determined according to actual design requirements. In addition, as shown in FIG. 1, the chip 140 may be electrically connected to the pins 130 by wire bonding. For example, the wire 170 may connect a pad (not shown) on the active surface 141 of the chip 140 and the top surface 131 of the pin 130, where the active surface 141 of the chip 140 is away from the upper surface 121 of the carrier 120. In particular, the connection method of the above-mentioned wires can be adjusted according to actual process requirements.

In this embodiment, the semiconductor package structure 100 further includes an adhesive layer 150. The chip 140 is connected to the carrier 120 through the adhesive layer 150. The adhesive layer 150 covers the upper surface 121 and part of the side surface 123 of the supporting base 120 and covers the first corner R1 of the supporting base 120. In this embodiment, the adhesive layer 150 may be a highly elastic adhesive film, and the adhesive layer 150 may be formed on the back surface of the chip 140 (the surface opposite to the active surface 141), and may be heated during the chip bonding process. The pressing method makes the adhesive layer 150 cover the upper surface 121 and part of the side surface 123 of the carrier 120. In other words, the first corner R1 of the supporting base 120 is embedded in the adhesive layer 150. On the other hand, in this embodiment, the width of the adhesive layer 150 is equal to the width of the wafer 140, but the invention is not limited to this.

In this embodiment, the semiconductor packaging structure 100 further includes a packaging glue 160. The packaging glue 160 covers the lead frame 110, the chip 140 and the glue layer 150. Preferably, the modulus of elasticity of the adhesive layer 150 may be smaller than the modulus of elasticity of the encapsulation gel 160. For example, under a temperature condition of 25° C., the elastic modulus of the encapsulant 160 is, for example, greater than 15 GPa, and the elastic modulus of the adhesive layer 150 is, for example, less than 5 GPa. In other words, the adhesive layer 150 has better elasticity than the packaging adhesive 160. By covering the first corner R1 of the carrier 120 with the adhesive layer 150, it can help to dissipate the stress that tends to concentrate on the first corner R1 and reduce the temperature of the packaging adhesive 160. The phenomenon of cracking from the first corner R1 due to thermal expansion and contraction during the cycle test or subsequent product operation, thereby improving the reliability of the semiconductor packaging structure 100.

Please refer to FIG. 2, the semiconductor package structure 100A of this embodiment is slightly different from the semiconductor package structure 100 of the foregoing embodiment. Further, the chip 140A and the adhesive layer 150A of the semiconductor package structure 100A of this embodiment can extend to a part of the lead The top surface 131 of the pin 130, and the adhesive layer 150A further covers a part of the second corner R2 of the pin 130. Since the adhesive layer 150A also covers the second corner R2 of the pin 130, the stress concentrated at the second corner R2 can be dissipated by the adhesive layer 150A, which can further reduce the temperature cycle test of the packaging compound 160 or the subsequent product operation. The phenomenon of cracking from the second corner R2 due to thermal expansion and contraction further improves the reliability of the semiconductor packaging structure 100A.

Please refer to FIG. 3, the semiconductor package structure 100B of this embodiment is slightly different from the semiconductor package structure 100 of the above-mentioned embodiment. Furthermore, the carrier 120 of the semiconductor package structure 100B further has a first recess 124. The first recess 124 makes the side surface 123 include a first side surface 123a and a second side surface 123b, and the lower surface 122 includes a first lower surface 122a and a second lower surface 122b. The first side surface 123a is farther from the center of the carrier 120 than the second side surface 123b. The second lower surface 122b is farther away from the upper surface 121 than the first lower surface 122a. In this embodiment, the adhesive layer 150B covers the first side surface 123a of the carrier 120. Furthermore, the adhesive layer 150B partially covers the first side surface 123a of the carrier 120.

Please continue to refer to FIG. 3, there is a second recess 134 between the top surface 131 of the pin 130 and the side wall 133. The second recess 134 makes the side wall 133 include a first side wall 133a and a second side wall 133b, and the bottom surface 132 includes a first bottom surface 132a and a second bottom surface 132b. The second side wall 133b is farther away from the carrier 120 than the first side wall 133a. The second bottom surface 132b is farther away from the top surface 131 than the first bottom surface 132a. Since the packaging compound 160 can be filled into the first recess 124 and the second recess 134, the probability of the carrier 120 and the pin 130 falling off from the packaging compound 160 can be reduced.

Please refer to FIG. 4, the semiconductor package structure 100C of this embodiment is slightly different from the semiconductor package structure 100B of the foregoing embodiment. Furthermore, the adhesive layer 150C of the semiconductor package structure 100C further extends to cover the first side surface of the carrier 120 123a. Furthermore, the carrier 120 is generally square, and therefore has four first side surfaces 123a. FIG. 4 is a schematic cross-sectional view of the semiconductor package structure 100C, and only two of the first side surfaces 123a are schematically shown. In this embodiment, the adhesive layer 150C completely covers the four first side surfaces 123a of the carrier 120. In other embodiments, the number of the first side surface 123a covered by the adhesive layer 150C or the area covering the first side surface 123a can be adjusted as required, which is not limited in the present invention.

Referring to FIG. 5, the semiconductor package structure 100D of this embodiment is slightly different from the semiconductor package structure 100C of the above-mentioned embodiment. Furthermore, the adhesive layer 150D of the semiconductor package structure 100D further covers the first lower surface 122a of the carrier 120 . Furthermore, the adhesive layer 150D may completely cover the first lower surface 122 a of the supporting base 120 and partially cover the second side surface 123 b of the supporting base 120. Furthermore, the carrier 120 is generally square, and therefore has four first side surfaces 123a and four second side surfaces 123b. FIG. 5 is a schematic cross-sectional view of the semiconductor package structure 100D, and only two of them are shown schematically. One first side surface 123a and two second side surfaces 123b. In this embodiment, the adhesive layer 150D completely covers the four first side surfaces 123a of the supporting base 120, and partially covers the four second side surfaces 123b of the supporting base 120. In other embodiments, the number of the first side surface 123a and the second side surface 123b covered by the adhesive layer 150D or the area covering the first side surface 123a and the second side surface 123b can be adjusted as required.

Please refer to FIG. 6, the semiconductor package structure 100E of this embodiment is slightly different from the semiconductor package structure 100B of the above-mentioned embodiment. Further, the chip 140A and the adhesive layer 150E of the semiconductor package structure 100E of this embodiment can extend to a portion of the lead The top surface 131 of the pin 130 and the adhesive layer 150E covers a part of the second corner R2 of the pin 130. On the other hand, the adhesive layer 150E covers the first side surface 123a of the carrier 120 and part of the first sidewall 133a of the pin 130. It should be noted that the number of the first side surface 123a covered by the adhesive layer 150E or the area covering the first side surface 123a can be adjusted as required, which is similar to that described in FIG. 4 and will not be repeated here.

Please refer to FIG. 7, the semiconductor package structure 100F of this embodiment is slightly different from the semiconductor package structure 100E of the foregoing embodiment. Furthermore, the adhesive layer 150F of the semiconductor package structure 100F of this embodiment further completely covers the carrier 120 The first side surface 123 a and the first side wall 133 a of the pin 130. It should be noted that the number of the first side surface 123a covered by the adhesive layer 150F or the area covering the first side surface 123a can be adjusted as required, which is similar to that described in FIG. 4 and will not be repeated here.

Please refer to FIG. 8, the semiconductor package structure 100G of this embodiment is slightly different from the semiconductor package structure 100F of the above-mentioned embodiment. Furthermore, the adhesive layer 150G of the semiconductor package structure 100G of this embodiment further covers the first of the carrier 120 The bottom surface 122a and the first bottom surface 132a of a part of the pin 130. Furthermore, the adhesive layer 150G may partially cover the first bottom surface 132a of the pin 130. In this embodiment, the adhesive layer 150G completely covers the first bottom surface 122 a of the carrier 120 and partially covers the first bottom surface 132 a of the pin 130. It should be noted that the number of the first side surface 123a and the second side surface 123b covered by the adhesive layer 150G or the area covering the first side surface 123a and the second side surface 123b can be adjusted as required, similar to that described in FIG. 5, I will not repeat them here.

It is particularly noted that the present invention does not limit the extent of coverage of the adhesive layer. All the above embodiments can be combined. As long as the adhesive layer covers the first corner of the carrier, it falls within the scope of the present invention.

In summary, the semiconductor package structure of the present invention utilizes a rubber layer with better elasticity to cover the first corner of the carrier to help dissipate the stress that tends to concentrate on the first corner, so as to reduce the temperature cycle test of the package compound or subsequent products The phenomenon of cracking from the first corner due to thermal expansion and contraction during operation, thereby improving the reliability of the semiconductor packaging structure.

Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100, 100A~100G: semiconductor package structure 110: lead frame 120: carrier 121: upper surface 122: lower surface 122a: first lower surface 122b: second lower surface 123: side surface 123a: first side surface 123b: first Two side surfaces 124: first recess 130: pin 131: top surface 132: bottom surface 132a: first bottom surface 132b: second bottom surface 133: side wall 133a: first side wall 133b: second side wall 134: second recess 140, 140A : Chip 141: Active surface 150, 150A~150G: Adhesive layer 160: Packaging gel 170: Wire R1: First corner R2: Second corner G: Gap

1 to 8 are schematic cross-sectional views of semiconductor package structures according to some embodiments of the invention.

100: Semiconductor package structure

110: Lead frame

120: bearing seat

121: upper surface

122: lower surface

123: side surface

130: pin

131: top surface

132: Underside

133: Sidewall

140: chip

141: active surface

150: Glue layer

160: Encapsulation colloid

170: Wire

R1: first corner

R2: second corner

G: gap

Claims (10)

A semiconductor packaging structure includes: a lead frame, including a bearing seat and a plurality of pins, wherein the bearing seat has an upper surface, a lower surface opposite to the upper surface, a side surface connected to the upper surface, and The first corner between the upper surface and the side surface; a chip, arranged on the upper surface of the carrier and electrically connected to the plurality of pins; glue layer, the chip passes through the glue layer Connected to the supporting base, wherein the adhesive layer covers the upper surface and part of the side surface of the supporting base, and covers the first corner of the supporting base; and an encapsulating glue covering the wire Frame, the chip and the glue layer. In the semiconductor packaging structure described in item 1 of the scope of patent application, the elastic modulus of the adhesive layer is smaller than that of the packaging colloid. According to the semiconductor package structure described in claim 1, wherein the chip extends beyond the first corner of the carrier. According to the semiconductor package structure described in claim 3, each of the pins has a top surface, a side wall connecting the top surface, and a second corner between the top surface and the side wall, and The chip and the adhesive layer extend to a part of the top surface of the plurality of pins, and the adhesive layer covers a part of the second corners of the plurality of pins. According to the semiconductor package structure described in claim 1, wherein the carrier further has a first recess, the first recess makes the side surface include a first side surface and a second side surface, and the lower The surface includes a first lower surface and a second lower surface, wherein the first side surface is farther from the center of the bearing seat than the second side surface, and the second lower surface is farther from the first lower surface than the first lower surface. Upper surface. According to the semiconductor package structure described in item 5 of the scope of patent application, the adhesive layer covers the first side surface of the carrier. According to the semiconductor package structure described in item 6 of the scope of patent application, the adhesive layer further covers the first lower surface. The semiconductor package structure according to item 5 of the scope of patent application, wherein each of the pins has a top surface, a bottom surface opposite to the top surface, a side wall connecting the top surface, and is located between the top surface and the side wall The second corner and the second recess, the second recess makes the side wall include a first side wall and a second side wall, and the bottom surface includes a first bottom surface and a second bottom surface, wherein the second side wall is more The first side wall is farther away from the supporting seat, the second bottom surface is farther away from the top surface than the first bottom surface, and the chip and the adhesive layer extend to part of the top surface of the plurality of pins, The adhesive layer covers part of the second corners of the plurality of pins. The semiconductor package structure according to the 8th patent application, wherein the adhesive layer covers the first side surface of the carrier and a part of the first sidewalls of the plurality of pins. According to the semiconductor package structure described in claim 9, wherein the adhesive layer further covers the first bottom surface of the carrier and a part of the first bottom surface of the plurality of pins.

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