TW202024937A - Hard disk back board and control board - Google Patents

Abstract

The present invention provides a hard disk backplane and a control board. The hard disk backplane includes: a hard disk connection port connected to at least one hard disk, an integrated circuit bus bar communication interface for connecting to the motherboard, a control chip, one end of which is connected to the motherboard through the integrated circuit bus bar communication interface inserted into the integrated circuit bus line, the other end of which is connected to the hard disk port, receives communication transmission from the motherboard and the signal and the corresponding hard disk signal light are controlled according to the communication transmission signal. The communication transmission signal is generated by the motherboard according to the received serial general input and output signal. The invention removes the CPLD on the HDD backplane and adds only one control chip (PCA9555), which simplifies the design, reduces the material, reduces the cost, and reduces the occupied area of the PCB, especially the 1HDD backplane and the 2HDD backplane. The problem of backplane wiring is fundamentally solved.

Description

Hard disk backplane and control board

The invention relates to the technical field of servers, in particular to the technical field of server backplanes, in particular to a hard disk backplane and a control board.

HDD, the abbreviation of Hard Disk Drive, is the English name of the hard disk drive. The most basic computer memory, the computer hard disk C drive and D drive that we often say in our computers are all hard disk drives. At present, the common disk capacity of hard disk is 80G, 128G, 160G, 256G, 320G, 500G, 750G, 1TB, 2TB and so on. Hard disks can be divided into 3.5-inch, 2.5-inch, 1.8-inch, etc. according to the size; according to the number of revolutions, they can be divided into 5400 revolutions per minute (rpm)/7200rpm/10000rpm, etc.; according to the interface can be divided into parallel advanced accessories (Parallel Advanced Technology Attachment, PATA), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), etc. PATA and SATA are generally desktop applications with large capacity and relatively low price, which are suitable for home use; while SCSI is generally high-end applications such as servers and workstations, with relatively small capacity and more expensive, but with better performance and stability. high.

For the current HDD backplane design, the status and location information of the HDD needs to be sent from the integrated south bridge (PCH, Platform Controller Hub) or the host bus adapter (HBA, Host Bus Adapter) to send serial universal input and output signals (Serial General Purpose Input/Output, SGPIO) is analyzed, and then the corresponding status lights and locate lights are further illuminated. Therefore, the design of HDD backplanes has added a CPLD device, namely Complex Programmable Logic Device, which is complex and programmable. Logic device.

As shown in Figure 1, it is a schematic diagram of the connection between the hard disk backplane and the main logic board in the prior art. Since the hard disk backplane adds a CPLD (Complex Programmable Logic Device), it is necessary to add a CPLD The firmware (FW) has been written and managed. For a 1HDD backplane or a 2HDD backplane, due to the limited area of a printed circuit board (PCB), it is even difficult to put down the CPLD device. And for a simple HDD backplane, the cost is significantly increased due to the addition of CPLD.

In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a hard disk backplane and a control board to solve the problems of management, layout difficulties and high cost caused by the need to configure the CPLD for the hard disk backplane in the prior art.

In order to achieve the above and other related objects, the present invention provides a hard disk backplane. The hard disk backplane includes: a hard disk connection port connected to at least one hard disk; and an integrated circuit bus communication interface for Connected to the motherboard; a control chip, one end of which is connected to the motherboard through the integrated circuit bus communication interface inserted into the integrated circuit bus communication line, and the other end is connected to the hard disk port, from the The main board receives the communication transmission signal, and controls the corresponding hard disk signal light according to the communication transmission signal; wherein, the communication transmission signal is parsed and generated by the main board according to the received serial universal input and output signal.

In an embodiment of the present invention, the control chip receives a hard disk connection status signal from the hard disk connection port, and feeds the hard disk connection status signal back to the motherboard.

In an embodiment of the present invention, the hard disk backplane further includes at least one sensor, and the sensor is connected to the integrated circuit bus communication interface to transmit sensor detection data to the host board.

In an embodiment of the present invention, the sensor includes a temperature sensor and a voltage sensor.

In an embodiment of the present invention, the communication transmission signal includes a signal light control signal and a fuse control signal.

In an embodiment of the present invention, the hard disk backplane further includes: a power interface for connecting to a power supply; a first fuse, one end is connected to the power interface, and the other end is respectively connected to the control The chip is connected to the first voltage port of the hard disk connection port, and is used for fuse protection of the first voltage port according to the communication transmission signal received by the control chip; a second fuse, one end of which is connected to the power interface The other end is respectively connected to the second voltage port of the control chip and the hard disk connection port, and is used for fuse protection of the second voltage port according to the communication transmission signal received by the control chip.

The present invention also provides a control board. The control board includes: a motherboard that receives serial universal input and output signals, and analyzes the received serial universal input and output signals to generate a communication transmission signal; as above The hard disk backplane.

In an embodiment of the present invention, the main board is installed on a main logic board, and the main logic board further includes: a signal controller connected to the main board to generate the serial universal input and output Signal and send the serial universal input and output signals to the motherboard; a baseboard management controller is connected to the motherboard, and the baseboard management control signal is transmitted to the hard disk backplane through the motherboard.

In an embodiment of the present invention, the main logic board further includes: a first inter-board connection port; the hard disk backplane further includes: a second inter-board connection port for connecting to the first board Between the port connection.

In an embodiment of the present invention, the signal controller is an integrated south bridge or a host bus adapter.

As mentioned above, the hard disk backplane and control board of the present invention have the following beneficial effects: The present invention removes the CPLD on the HDD backplane, avoiding the firmware (FW) programming and firmware (FW) control of the CPLD, At the same time, the serial general-purpose input and output signal (SGPIO) connector and the joint test work group (Joint Test Action Group, JTAG) connector are removed, and only a control chip (PCA9555) is added, which simplifies the design, reduces materials and reduces It reduces the cost and reduces the footprint of the printed circuit board (PCB), especially the 1HDD backplane and the 2HDD backplane, which fundamentally solve the problem of backplane wiring.

The following describes the implementation of the present invention through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to Figure 2 to Figure 5. It should be noted that the structures, proportions, sizes, etc. shown in the accompanying drawings in this specification are only used to match the content disclosed in the specification for people familiar with this technology to understand and read, and are not intended to limit the implementation of the present invention Limiting conditions, so it has no technical substantive meaning. Any structural modification, proportional relationship change or size adjustment should still fall under the present invention without affecting the effects and objectives of the present invention. The disclosed technical content must be within the scope of coverage.

At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" cited in this specification are only for ease of description, not to limit the text. The scope of implementation of the invention, the change or adjustment of the relative relationship, shall be regarded as the scope of implementation of the invention without substantial changes to the technical content.

The purpose of the embodiments of the present invention is to provide a hard disk backplane and a control board to solve the problem that the prior art cannot effectively provide effective protection when the fan control system in the server is abnormal.

The principle and implementation of a hard disk backplane and control board of this embodiment will be described in detail below, so that those skilled in the art can understand the hard disk backplane and control board of this embodiment without creative work.

As shown in FIG. 2, the present invention provides a hard disk backplane 100. The hard disk backplane 100 includes a control chip 110, a hard disk connection port 120 and an integrated circuit bus communication interface 130.

In this embodiment, the hard disk connection port 120 is connected to at least one hard disk, and the hard disk connection port 120 has a plurality of insertion ports for inserting multiple hard disks.

In this embodiment, the integrated circuit bus communication interface 130 is used to connect to the motherboard 200. The integrated circuit bus communication interface 130 is an integrated circuit interface bus (I2C) communication interface.

In this embodiment, one end of the control chip 110 is connected to the motherboard 200 through the integrated circuit bus communication line inserted into the integrated circuit bus communication interface 130, and the other end is connected to the hard disk connection port 120 is connected, receives the communication transmission signal from the motherboard 200, and controls the corresponding hard disk signal light 180 according to the communication transmission signal; wherein, the communication transmission signal is shared by the motherboard 200 according to the received serial Input and output signal analysis and generation.

In this embodiment, the control chip 110 can use a variety of existing chips, for example, PCA series chips, such as PCA9555. In this embodiment, the PCA9555 control chip 110 is used as an example for illustration.

In this embodiment, the control chip 110 is used to replace the CPLD (Complex Programmable Logic Device) on the original hard disk backplane 100, which avoids the CPLD firmware (FW) programming and firmware ( FW) Control.

Moreover, the control chip 110 communicates with the motherboard 200 only through the integrated circuit bus communication line inserted into the integrated circuit bus communication interface 130, and the serial universal input on the original hard disk backplane is also removed. The output signal (SGPIO) connector and the joint test work group (JTAG) connector only add a control chip 110 (PCA9555), which simplifies the design, reduces materials, reduces costs, and reduces the printed circuit board (PCB) The occupied area, especially the 1HDD backplane and the 2HDD backplane, fundamentally solve the problem of backplane wiring.

In this embodiment, the control chip 110 receives the communication transmission signal from the motherboard 200, and controls the corresponding hard disk signal light 180 according to the communication transmission signal, wherein the communication transmission signal is transmitted by the motherboard The 200 is parsed and generated according to the received serial general input output signal (SGPIO).

In other words, the motherboard 200 first parses the serial general-purpose input and output signal (SGPIO), generates the communication transmission signal, and sends the communication transmission signal to the control chip 110 of the hard disk backplane 100. Yes, there is no need for the hard disk backplane 100 to analyze the serial general input output signal (SGPIO).

Wherein, the communication transmission signal includes, but is not limited to, a signal light control signal and a fuse control signal.

In other words, the hard disk backplane 100 removes the CPLD, and the CPLD on the motherboard 200 resolves the serial general-purpose input and output signal (SGPIO), and then transmits the LED through the integrated circuit interface bus (I2C) LED control signal and EFUSE control signal.

In this embodiment, the control chip 110 can also receive a hard disk connection status signal from the hard disk connection port 120 and feed the hard disk connection status signal back to the motherboard 200.

That is, the control chip 110 (PCA9555) on the hard disk backplane 100 collects hard disk information, such as hard disk connection status signals, and feeds the hard disk information back to the motherboard 200.

As shown in FIGS. 3 and 5, in this embodiment, the hard disk backplane 100 further includes at least one sensor 170 connected to the integrated circuit bus communication interface 130, The sensing data is transmitted to the motherboard 200.

Specifically, in this embodiment, the sensor 170 includes but is not limited to a temperature sensor and a voltage sensor, and may also include other sensors required by the hard disk backplane 100.

As shown in FIG. 3, in this embodiment, the hard disk backplane 100 further includes a power interface 140, a first fuse 150 and a second fuse 160.

The power interface 140 is used to connect to a power supply.

One end of the first fuse 150 is connected to the power supply interface 140, and the other end is respectively connected to the first voltage port of the control chip 110 and the hard disk connection port 120, and is used for receiving data from the control chip 110. The communication transmission signal performs fuse protection for the first voltage port.

One end of the second fuse 160 is connected to the power interface 140, and the other end is respectively connected to the second voltage port of the control chip 110 and the hard disk connection port 120, and is used for receiving according to the control chip 110 The communication transmission signal fuse protects the second voltage port.

As shown in FIG. 4, this embodiment also provides a control board, the control board includes: a motherboard 200 (CPLD) and the hard disk backplane 100 as described above.

The motherboard 200 receives the serial universal input and output signal, and parses the received serial universal input and output signal to generate the communication transmission signal.

Specifically, as shown in FIGS. 4 and 5, in this embodiment, the main board 200 is installed on a main logic board (MLB, Main Logic Board) 20, and the main logic board 20 further includes: The signal controller 210 and a baseboard management controller 220.

The signal controller 210 is connected to the motherboard 200 to generate the serial universal input and output signals and send the serial universal input and output signals to the motherboard 200.

Among them, in this embodiment, the signal controller 210 is an integrated south bridge (PCH, Platform Controller Hub) or a host bus adapter (HBA, Host Bus Adapter).

That is, in this embodiment, the serial general input output signal (SGPIO) sent from the south bridge or host bus adapter directly enters the motherboard 200 (CPLD) on the main logic board 20 (MLB, Main Logic Board). ), the motherboard 200 (CPLD) parses the received serial universal input and output signals, generates communication transmission signals such as signal light control signals and fuse control signals, and sends the signal light control signals and fuse control signals to In the control chip 110 of the hard disk backplane 100, the control chip 110 further lights up the corresponding status light and the locate light.

Therefore, the main board 200 analyzes the serial universal input and output signals to simplify the hard disk backplane 100.

In this embodiment, the baseboard management controller 220 is connected to the motherboard 200, and the baseboard management control signal is transmitted to the hard disk backplane 100 through the motherboard 200.

In this embodiment, the main logic board 20 further includes: a first inter-board connection port 230 (including the main logic board (MLB) board in FIG. 5 connected to the integrated south bridge (PCH) SATA CONN0 and SATA CONN1) The hard disk backplane 100 also includes: a second inter-board connection port 190 (including the hard disk backplane 100 in Figure 5 connected to the hard disk port 120 (HDD CONN) SATA CONN0 and SATA CONN1), with It is connected to the first inter-board connection port 230.

Among them, the software module that the motherboard 200 analyzes the serial universal input and output signals is named PCA9555 module, which simulates the PCA9555 module written by the motherboard 200, and the 4 Hz active (HZ ACTIVE) signal output by CPLD passes through The integrated circuit is connected to the bus (I2C) to the input/output pin (IO Pin) of the PCA9555 control chip 110, and the delay (delay) is less than 7 microseconds (ms), which fully meets the light emitting diode (LED) The lighting requirements also meet the 100mS EFUSE control delay (EFUSE control delay).

At the same time, we can further use the integrated circuit interface bus (I2C) of the CPLD of the main logic board (MLB) to connect to other devices on the 2HDD backplane, further reducing the number of pins for the cable.

In addition, in order to highlight the innovative part of the present invention, technical features that are not closely related to solving the technical problems proposed by the present invention are not introduced in this embodiment, but this does not indicate that there are no other structures and features in this embodiment. Functional characteristics.

It should be noted that the illustrations provided in this embodiment only illustrate the basic idea of the present invention in a schematic manner. The figures only show the components related to the present invention instead of the number, shape, and shape of the components in actual implementation. For the size drawing, the type, number, and ratio of each component can be changed at will during actual implementation, and the component layout type may be more complicated.

In summary, the present invention removes the CPLD on the HDD backplane, avoids the firmware (FW) programming and firmware (FW) control of the CPLD, and also removes the serial general input output signal (SGPIO) connector and The Joint Test Working Group (JTAG) connector only adds a control chip (PCA9555), which simplifies the design, reduces materials, reduces costs, and reduces the footprint of the printed circuit board (PCB), especially the 1HDD backplane and The 2HDD backplane fundamentally solves the problem of backplane wiring. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial value.

The above-mentioned embodiments only exemplarily illustrate the principles and effects of the present invention, and are not used to limit the present invention. Anyone familiar with this technology can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

100: hard disk backplane 110: control chip 120: Hard Disk Port 130: Integrated circuit bus communication interface 140: Power Interface 150: first fuse 160: second fuse 170: Sensor 180: Hard disk signal light 190: second inter-board connection port 20: Main logic board 200: Motherboard 210: Signal Controller 220: baseboard management controller 230: The first inter-board connection port 240: Integrated circuit bus communication interface MLB: main logic board PCH: Integrated South Bridge SGPIO: Serial general input and output signal I2C: Integrated circuit interface bus CPLD: Complex programmable logic device SATA: Serial Advanced Attachment SATA CONN0, SATA CONN1: the first inter-board port, the second inter-board port EFUSE: Fuse HDD CONN: Hard Disk Connector JTAG: Joint Test Working Group PCA9555: control chip

FIG. 1 shows the structure diagram of the connection principle between the hard disk backplane and the main logic board in the prior art. FIG. 2 is a schematic structural diagram of a hard disk backplane in an embodiment of the invention. FIG. 3 is a schematic diagram showing a specific principle structure of the hard disk backplane in an embodiment of the present invention. Fig. 4 shows a schematic diagram of the principle structure of a control board in an embodiment of the present invention. Fig. 5 is a schematic diagram of a specific logic principle of the control board in an embodiment of the present invention.

100: hard disk backplane

110: control chip

120: Hard Disk Port

130: Integrated circuit bus communication interface

140: Power Interface

150: first fuse

160: second fuse

170: Sensor

180: Hard disk signal light

190: second inter-board connection port

20: Main logic board

200: Motherboard

210: Signal Controller

220: baseboard management controller

230: The first inter-board connection port

240: Integrated circuit bus communication interface

I2C: Integrated circuit interface bus

SATA: Serial Advanced Attachment

Claims (10)

A hard disk backplane, characterized in that: the hard disk backplane includes: a hard disk connection port connected to at least one hard disk; an integrated circuit bus communication interface for connecting with a motherboard; A chip, one end of which is connected to the motherboard through an integrated circuit bus communication line inserted into the communication interface of the integrated circuit bus, and the other end is connected to the hard disk connection port to receive a communication from the motherboard Transmit signals, and control a corresponding hard disk signal light according to the communication transmission signal; wherein, the communication transmission signal is parsed and generated by the motherboard according to a series of general input and output signals received. The hard disk backplane described in item 1 of the patent application is characterized in that the control chip receives a hard disk connection status signal from the hard disk connection port, and feeds the hard disk connection status signal back to the The motherboard. The hard disk backplane described in item 1 of the scope of patent application is characterized in that: the hard disk backplane further includes at least one sensor, and the sensor is connected to the integrated circuit bus communication interface, Transmit a sensing data to the main board. The hard disk backplane described in item 3 of the scope of patent application is characterized in that the sensor includes a temperature sensor and a voltage sensor. The hard disk backplane described in item 1 of the scope of patent application is characterized in that: the communication transmission signal includes a signal light control signal and a fuse control signal. The hard disk backplane described in item 1 of the scope of patent application is characterized in that: the hard disk backplane further includes: a power interface for connecting with a power supply; a first fuse with one end connected to the The power interface is connected, and the other end is respectively connected to a first voltage port of the control chip and the hard disk connection port, and is used to fuse the first voltage port according to the communication transmission signal received by the control chip Protection; a second fuse, one end is connected to the power interface, the other end is respectively connected to the control chip, a second voltage port of the hard disk connection port, used for receiving the control chip according to the The communication transmission signal performs fuse protection for the second voltage port. A control board, characterized in that the control board comprises: a main board that receives a serial universal input and output signal, and analyzes the received serial universal input and output signal to generate a communication transmission signal; The hard disk backplane according to any one of claim 1 to claim 6. The control board described in item 7 of the scope of patent application is characterized in that: the main board is installed on a main logic board, and the main logic board further includes: a signal controller connected to the main board, Generating the serial universal input and output signal and sending the serial universal input and output signal to the motherboard; a baseboard management controller connected to the motherboard, and a baseboard management control signal through the motherboard Transfer to the hard disk backplane. The control board described in item 8 of the scope of patent application is characterized in that: the main logic board further includes: a first inter-board connection port; the hard disk backplane further includes: a second inter-board connection port, Used to connect with the first inter-board connection port. The control board described in item 8 of the scope of patent application is characterized in that: the signal controller is an integrated south bridge or a host bus adapter.

Images