TW202002289A - Semiconductor devices and methods for fabricating the same - Google Patents

Abstract

A semiconductor device includes a compound semiconductor layer disposed over a substrate, a protection layer disposed over the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode penetrating the protection layer and disposed over the compound semiconductor layer. The semiconductor device also includes a gate field plate connecting the gate electrode and disposed over a portion of the protection layer between the gate electrode and the drain electrode. The gate field plate has an extension portion extending into the protection layer.

Description

Semiconductor device and its manufacturing method

Embodiments of the present invention relate to semiconductor devices, and particularly to semiconductor devices having field plates and methods of manufacturing the same.

GaN-based semiconductor materials have many excellent material characteristics, such as high heat resistance, wide band-gap, and high electron saturation rate. Therefore, GaN-based semiconductor materials are suitable for high-speed and high-temperature operating environments. In recent years, GaN-based semiconductor materials have been widely used in light emitting diode (LED) devices and high-frequency devices, such as high electron mobility transistors (HEMTs) with heterointerface structures ).

The field plate is usually disposed in the high electric field area of the semiconductor device, which is used to reduce the peak electric field in the high electric field area, one of the field plates is a field plate electrically connected to the gate (ie, the gate field plate), It can reduce the electric field strength of the gate on the drain side. Therefore, the gate field plate can increase the breakdown voltage of the semiconductor device to allow the semiconductor device to be applied to high voltage operation.

With the development of gallium nitride-based semiconductor materials, these semiconductor devices using gallium nitride-based semiconductor materials are used in more severe working environments, such as higher frequencies, higher temperatures, or higher voltages. Therefore, the process conditions of semiconductor devices with gallium nitride-based semiconductor materials also face many new challenges.

Some embodiments of the present invention provide a semiconductor device in which a compound semiconductor layer is disposed on a substrate, a protective layer is disposed on the compound semiconductor layer, and a source electrode, a drain electrode, and a gate electrode pass through the protective layer and are disposed On the compound semiconductor layer. The semiconductor device further includes a gate field plate connected to the gate electrode and disposed on a portion of the protective layer between the gate electrode and the drain electrode. The gate field plate has an extension that extends into the protective layer.

Some embodiments of the present invention provide a method of manufacturing a semiconductor device. The method includes forming a compound semiconductor layer on a substrate, forming a first protective layer on the compound semiconductor layer, and forming a source electrode, a drain electrode, and The gate electrode is above the compound semiconductor layer, and a gate field plate is formed on the portion of the protective layer between the gate electrode and the drain electrode to connect the gate electrode, wherein the gate field plate has a protection extending to The extension in the layer.

100、200‧‧‧Semiconductor device

102‧‧‧ base

104‧‧‧buffer layer

106‧‧‧GaN semiconductor layer

108‧‧‧GaN aluminum semiconductor layer

109‧‧‧ Doped compound semiconductor block

110‧‧‧The first protective layer

112‧‧‧Second protective layer

114‧‧‧Source electrode

116‧‧‧Drain electrode

118‧‧‧The first depression

120‧‧‧Second depression

122‧‧‧The third depression

124‧‧‧Gate electrode

126‧‧‧Gate field plate

128‧‧‧Connect

130‧‧‧First Extension

132‧‧‧Second extension

134‧‧‧Interlayer dielectric layer

136‧‧‧ source contacts

138‧‧‧Drain contacts

140‧‧‧Gate contact

150‧‧‧The first patterned mask layer

152‧‧‧First opening

160‧‧‧Second patterned mask layer

162‧‧‧Second opening

164‧‧‧The third opening

170‧‧‧The third patterned mask layer

172‧‧‧ fourth opening

174‧‧‧ fifth opening

176‧‧‧Sixth opening

Through the following detailed description and examples in conjunction with the accompanying drawings, the embodiments of the present invention can be better understood. In order to make the diagram clear, the different elements in the diagram may not be drawn to scale, among which:

FIGS. 1A to 1H are schematic cross-sectional views illustrating various stages of forming a semiconductor device according to some embodiments of the present invention.

FIGS. 2A to 2H are schematic cross-sectional views illustrating various stages of forming a semiconductor device according to other embodiments of the present invention.

The following disclosure provides many embodiments or examples for implementing different elements of the provided semiconductor device. Specific examples of components and their configurations are described below to simplify the description of the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, if the first element is formed on the second element in the description, it may include an embodiment where the first and second elements are in direct contact, or may include additional elements formed between the first and second elements , So that they do not directly contact the embodiment. In addition, embodiments of the present invention may repeat reference numerals and/or letters in different examples. This repetition is for conciseness and clarity, not for expressing the relationship between the different embodiments discussed.

Some variations of the embodiments are described below. In different drawings and illustrated embodiments, similar element symbols are used to indicate similar elements. It can be understood that additional steps may be provided before, during, and after the method, and some of the described steps may be replaced or deleted for other embodiments of the method.

Embodiments of the present invention provide a semiconductor device and a manufacturing method thereof, which are particularly suitable for high electron mobility transistors (HEMT). Due to the high electric field strength between the gate electrode and the drain electrode, the material layer located near the drain side of the gate electrode may be punched through. In order to slow down the electric field gradient of the gate electrode near the side of the drain electrode, the embodiment of the present invention uses the formation of a gate field plate with an extension extending into the protective layer, which can slow down the gate electrode on the side near the drain electrode The electric field gradient at the edge increases the breakdown voltage of the semiconductor device, thereby improving the performance of the semiconductor device.

FIGS. 1A to 1H are schematic cross-sectional views at various stages of forming the semiconductor device 100 shown in FIG. 1H according to some embodiments of the present invention. Please refer to FIG. 1A to provide a substrate 102. Next, a buffer layer 104 is formed on the substrate 102, a gallium nitride (GaN) semiconductor layer 106 is formed on the buffer layer 104, and a gallium aluminum nitride (Al _x Ga _1-x N) is formed on the gallium nitride semiconductor layer 106 , Where 0<x<1) semiconductor layer 108. In some embodiments, a seed layer (not shown) may be formed between the substrate 102 and the buffer layer 104.

In some embodiments, the substrate 102 may be doped (eg, doped with p-type or n-type dopants) or undoped semiconductor substrates, such as a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, or the like Semiconductor substrate. In some embodiments, the substrate 102 may be a semiconductor-on-insulator substrate, such as a silicon on insulator (SOI) substrate. In some embodiments, the substrate 102 may be a glass substrate or a ceramic substrate, such as a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, or a sapphire (Sapphire) substrate.

The material of the seed layer can be formed of aluminum nitride (AlN), aluminum oxide (Al ₂ O ₃ ), aluminum gallium nitride (AlGaN), silicon carbide (SiC), aluminum (Al), or a combination of the foregoing, and the crystal The seed layer may be a single or multi-layer structure. The seed layer can be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (molecular beam epitaxy (MBE), a combination of the foregoing, or a similar method.

The buffer layer 104 can reduce the strain of the gallium nitride semiconductor layer 106 formed subsequently on the buffer layer 104 to prevent defects from being formed in the gallium nitride semiconductor layer 106 above. The strain is caused by the gallium nitride semiconductor layer 106 and the The mismatch between the substrates 102 is caused. In some embodiments, the material of the buffer layer 104 may be AlN, GaN, Al _x Ga _1-x N (where 0<x<1), a combination of the foregoing, or similar materials. The buffer layer 104 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), a combination of the foregoing, or similar methods. Although the buffer layer 104 has a single-layer structure in the embodiment shown in FIG. 1A, the buffer layer 104 may have a multi-layer structure. In addition, in some embodiments, the material of the buffer layer 104 is determined by the material of the seed layer and the gas introduced during the epitaxial process.

Two-dimensional electron gas (2DEG) (not shown) is formed on the hetero interface between the gallium nitride semiconductor layer 106 and the gallium aluminum nitride semiconductor layer 108. The semiconductor device 100 shown in FIG. 1H is a high electron mobility transistor (HEMT) using two-dimensional electron gas (2DEG) as a conductive carrier. In some embodiments, the gallium nitride semiconductor layer 106 and the gallium aluminum nitride semiconductor layer 108 are free of dopants. In some other embodiments, the gallium nitride semiconductor layer 106 and the gallium aluminum nitride semiconductor layer 108 may have dopants, such as n-type dopants or p-type dopants. The gallium nitride semiconductor layer 104 and the gallium aluminum nitride semiconductor layer 106 can be formed by epitaxial growth processes, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), and molecular beam epitaxy (MBE) ), the aforementioned combination or similar methods.

With continued reference to FIG. 1A, a first protective layer 110 is formed on the gallium aluminum nitride semiconductor layer 108. A second protective layer 112 is formed on the first protective layer 110. In some embodiments, the materials of the first protective layer 110 and the second protective layer 112 may be insulating materials or dielectric materials, such as silicon oxide (SiO ₂ ), silicon nitride (SiN), silicon oxynitride (SiON), Aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), magnesium oxide (MgO), magnesium nitride (Mg ₃ N ₂ ), zinc oxide (ZnO), titanium oxide (TiO ₂ ), or a combination of the foregoing. The first protective layer 110 and the second protective layer 112 are used to prevent the underlying gallium aluminum nitride semiconductor layer 108 from generating leakage current to the subsequently formed source electrode 114, drain electrode 116, and gate electrode 124 (shown in FIG. 1G ). The first protective layer 110 and the second protective layer 112 may be formed by chemical vapor deposition (CVD), plasma-assisted chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like .

In some embodiments, the material of the second protective layer 112 is different from the material of the first protective layer 110. For example, the lower first protective layer 110 may be selected from a high-quality oxide film such as a silicon oxide film grown through heat, and the upper second protective layer 112 may be selected from the first protective layer 110 with high etch selectivity Dielectric materials such as silicon nitride.

Although in the embodiment shown in FIG. 1A, two protective layers 110 and 112 are formed on the GaN aluminum semiconductor layer 108, in other embodiments, one or more protective layers may be formed On the GaN aluminum semiconductor layer 108.

Referring to FIG. 1B, a source electrode 114 and a drain electrode 116 are formed on the gallium aluminum nitride semiconductor layer 108, and the source electrode 114 and the drain electrode 116 pass through the second protective layer 112 and the first protective layer 110, To contact the gallium aluminum nitride semiconductor layer 108. In some embodiments, the materials of the source electrode 114 and the drain electrode 116 may be conductive materials, such as metal materials or semiconductor materials. The metal material can be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), similar materials, combinations of the foregoing, or multilayers of the foregoing. The semiconductor material may be doped polycrystalline silicon, polycrystalline germanium, or the like. The step of forming the source electrode 114 and the drain electrode 116 may include forming openings (not shown) for the source electrode 114 and the drain electrode 116 through an etching process, the openings passing through the second protective layer 112 and the first protective layer 110, and expose the upper surface of the gallium aluminum nitride semiconductor layer 108, deposit a conductive material layer (not shown) on the second protective layer 112 and fill these openings, and perform a patterning process on the conductive material layer to The source electrode 114 and the drain electrode 116 are formed. The deposition process for forming the source electrode 114 and the drain electrode 116 may be atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, or the like.

Referring to FIG. 1C, a first patterned mask layer 150 is formed on the second protective layer 112. The first patterned mask layer 150 has a first opening 152 that exposes the area on the upper surface of the second protective layer 112 where the gate electrode 124 (shown in FIG. 1G) is to be formed. In some embodiments, the first patterned mask layer 150 may be a patterned photoresist layer or a patterned hard mask layer.

Next, an etching process is performed on the second protective layer 112 and the first protective layer 110 through the first opening 152 of the first patterned mask layer 150. As shown in FIG. 1D, after the etching process, a first recess 118 is formed in the second protective layer 112 and the first protective layer 110. The first recess 118 passes through the second protective layer 112 and the first protective layer 110 to expose the upper surface of the gallium aluminum nitride semiconductor layer 108. In some embodiments, the etching process may be a dry etching process, a wet etching process, or a combination of the foregoing. The dry etching process may be, for example, reactive ion etching (RIE), electron cyclotron resonance (ERC) etching, inductively-coupled plasma (ICP) etching or similar dry etching Process. In the etching process, an appropriate etchant may be selected for the materials of the second protective layer 112 and the first protective layer 110. For example, in the embodiment where the second protective layer 112 is silicon nitride and the first protective layer 110 is silicon oxide, the portion of the second protective layer 112 exposed by the opening 152 can be removed first with phosphoric acid Until the upper surface of the first protective layer 110 is exposed, and then the portion of the first protective layer 110 exposed by the opening 152 is removed with dilute hydrofluoric acid (dHf).

Next, the first patterned mask layer 150 above the second protective layer 112 is removed. In some embodiments, the first patterned mask layer 150 may be removed using an ash process or a lift-off process.

Please refer to FIG. 1E, a second patterned mask layer 160 is formed on the second protection layer 112. The second patterned mask layer 160 has second openings 162 and third openings 164 exposing areas of the upper surface of the second protective layer 112, which are intended to form extensions 130 and 132 of the gate field plate 126 (shown in (Figure 1G). In some embodiments, the second patterned mask layer 160 may be a patterned photoresist layer or a patterned hard mask layer.

Next, an etching process is performed on the second protective layer 112 and the first protective layer 110 through the second opening 162 and the third opening 164 of the second patterned mask layer 160. As shown in FIG. 1F, after the etching process, the second recess 120 and the third recess 122 are formed in the second protective layer 112 and the first protective layer 110. The second recess 120 and the third recess 122 pass through the second protective layer 112 and extend into the first protective layer 110. The second recess 120 and the third recess 122 do not pass through the first protective layer 110, so the portion of the first protective layer 110 directly under the second recess 120 and the third recess 122 remains on the GaN-on-aluminum semiconductor layer 108 . In some embodiments, the etching process may include a main etching step for the second protective layer 112 to form the second recess 120 and the third recess 122 in the second protective layer 112, and include an over-etching step to remove the second The recess 120 and the third recess 122 extend into the first protective layer 110. For example, after the main etching of the second protective layer 112 is completed, the substrate 102 may not be removed from the etching equipment, and the over-etching of the first protective layer may be continuously performed for a period of time, for example, about 10% of the main etching time to About 30% (please confirm). In some embodiments, the etching process for forming the second recess 120 and the third recess 122 may be a dry etching process, a dry etching process, or a combination of the foregoing, and may be the same, similar, or different from the foregoing etching process for forming the first recess 118 .

Next, the second patterned mask layer 160 on the second protective layer 112 is removed. In some embodiments, the second patterned mask layer 160 may be removed using an ash process or a lift-off process.

Referring to FIG. 1G, a gate electrode 124 and a gate field plate 126 connected to the gate electrode 124 are formed on the second protective layer 112. The gate electrode 124 is filled in the first recess 118 and contacts the gallium aluminum nitride semiconductor layer 108. The gate field plate 126 has a connection portion 128 connected to the gate electrode 124, and a first extension portion 130 and a second extension portion 132 filled in the second recess 120 and the third recess 122, respectively. The connection portion 128 is located on the area of the upper surface of the second protection layer 112 between the gate electrode 124 and the drain electrode 116.

In some embodiments, the steps of forming the gate electrode 124 and the gate field plate 126 may include depositing a conductive material layer (not shown) on the second protective layer 112 and filling the first recess 118 and the second recess 120 And the third recess 122, and patterning the conductive material layer. The patterning of the conductive material layer may include forming a patterned mask layer (not shown) on the conductive material layer through a photolithography process, and performing an etching process such as dry etching or wet etching on the conductive material layer to remove the conductive material layer. The portion covered by the patterned mask layer, and then the patterned mask layer on the remaining part of the conductive material layer is removed. The conductive material layer may be a metal or semiconductor material. The metal can be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper ( Cu), similar materials, combinations of the foregoing, or multilayers of the foregoing. The semiconductor material may be doped polycrystalline silicon, polycrystalline germanium, or the like. The conductive material layer may be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering or the like.

Referring to FIG. 1H, an inter-layer dielectric layer (ILD layer) 134 is formed on the second protective layer 112. The inter-layer dielectric layer 134 covers the gate electrode 124, the gate field plate 126, and the source electrode 114和Drawpole electrode 116。 Next, a source contact 136 connected to the source electrode 114, a drain contact 138 connected to the drain electrode 116, and a gate contact 140 connected to the gate electrode 124 are formed in the interlayer dielectric layer 134. After forming the interconnect structure including the interlayer dielectric layer 134, the source contact 136, the drain contact 138 and the gate contact 140, the semiconductor device 100 is formed.

In some embodiments, the material of the interlayer dielectric layer 134 may be silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide, similar materials, combinations of the foregoing, or multiple layers of the foregoing. The interlayer dielectric layer 134 may be formed by chemical vapor deposition (CVD), plasma assisted chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like.

In some embodiments, the materials of the source contact 136, the drain contact 138, and the gate contact 140 may be metallic materials, such as gold (Au), nickel (Ni), platinum (Pt), palladium (Pd) , Iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), a combination of the foregoing, or a multilayer of the foregoing. The steps of forming the source contact 136, the drain contact 138, and the gate contact 140 may include forming openings (not shown) corresponding to the source electrode 114, the drain electrode 116, and the gate electrode 124 through a patterning process , Which passes through the interlayer dielectric layer 134 and exposes the source electrode 114, the drain electrode 116, and the gate electrode 124, deposits a metal material (not shown) on the interlayer dielectric layer 134 and fills the opening, and performs, for example The planarization process of chemical mechanical polishing (CMP) removes the metal material above the interlayer dielectric layer 130.

In the embodiment shown in FIG. 1H, the semiconductor device 100 includes a substrate 102 and a buffer layer 104, a gallium nitride semiconductor layer 106 and a gallium aluminum nitride semiconductor layer 108 sequentially stacked on the substrate 102. The semiconductor device 100 further includes a first protective layer 110 disposed on the gallium aluminum nitride semiconductor layer 108, a second protective layer 112 disposed on the first protective layer 110, and a source electrode 114, a drain electrode 116 and a gate The electrode 124 passes through the second protective layer 112 and the first protective layer 110 and contacts the gallium aluminum nitride semiconductor layer 108.

The semiconductor device 100 further includes a gate field plate 126 connected to the gate electrode 124. The gate field plate 126 has a connection portion 128 to connect the gate electrode 124, and the first extension portion 130 and the second extension portion 132 extend to the second protective layer 112 and the first protective layer 110. The connection portion 128 is located above the second protective layer 112 and extends from the gate electrode 124 toward the drain electrode 116. The first extension portion 130 and the second extension portion 132 are interposed between the gate electrode 124 and the drain electrode 116, and the upper surfaces of the first extension portion 130 and the second extension portion 132 and the gallium aluminum nitride semiconductor layer 108 are A protective layer 110 is separated.

Generally speaking, when an operating voltage is applied to the gate electrode and the drain electrode, due to the high electric field strength between the gate electrode and the drain electrode, the material layer located near the drain side of the gate electrode may be broken (punch through), especially at the corner of the gate electrode. It is worth noting that in the embodiment of the present invention, there is a gate field plate 126 connected to the gate electrode 124 between the gate electrode 124 and the drain electrode 116, which can slow the gate electrode 124 from approaching the drain electrode 116 Electric field gradient on the side. Furthermore, since the gate field plate 126 has the first extension portion 130 and the second extension portion 132 extending into the second protection layer 112 and the first protection layer 110, the electric field distribution under the connection portion 128 is concentrated to the extension portion 130 and 132, which can further slow down the electric field gradient of the gate electrode 124 near the side of the drain electrode 116. Therefore, the embodiment of the present invention utilizes the gate field plate, which has an extension portion extending into the protective layer, to improve the breakdown voltage of the semiconductor device, thereby improving the performance of the semiconductor device 100.

Although in the embodiment shown in FIG. 1H, the gate field plate 126 has two extensions 130 and 132 between the gate electrode 124 and the drain electrode 116, however, in other embodiments, the gate field The plate 126 may have one or more extensions between the gate electrode 124 and the drain electrode 116 to slow the electric field gradient of the gate electrode 124 near the side of the drain electrode 116. In addition, the widths of the first extension portion 130 and the second extension portion 132 and the spacing between the first extension portion 130 and the second extension portion 132 may depend on design requirements, and are not limited to the embodiment of FIG. 1H.

In addition, since the first extension portion 130 and the second extension portion 132 of the gate field plate 126 pass through the second protection layer 112 and extend into the first protection layer 110, the first extension of the gallium aluminum nitride semiconductor layer 108 is close to The portion 130 and the second extension portion 132 help the semiconductor device 100 to conduct heat energy generated during operation, so as to improve the performance of the semiconductor device 100.

FIGS. 2A-2H are cross-sectional schematic diagrams showing the semiconductor device 200 shown in FIG. 2H at various stages according to other embodiments of the present invention, wherein the same components as those in the foregoing embodiments of FIGS. 1A-1H use the same And its description is omitted. The difference between the embodiment shown in FIGS. 2A-2H and the previous embodiment shown in FIGS. 1A-1H is that the semiconductor device 200 in FIGS. 2A-2H further includes a doped compound semiconductor block 109 interposed between the GaN green semiconductor layer 108 and the gate electrode 124.

Please refer to FIG. 2A to provide the substrate 102. Next, a buffer layer 104, a gallium nitride semiconductor layer 106, and a gallium aluminum nitride semiconductor layer 108 are sequentially formed on the substrate 102. Next, a doped compound semiconductor block 109 is formed on the gallium aluminum nitride semiconductor layer 108. The doped compound semiconductor block 109 may be rectangular as shown in the figure, or may be other shapes, such as a trapezoid. In addition, the upper surface of the doped compound semiconductor block 109 may not be flat.

In the subsequent process, the gate electrode 124 (shown in FIG. 2G) will be formed on the doped compound semiconductor block 109. By disposing the doped compound semiconductor block 109 between the gate electrode 124 and the GaN-aluminum nitride semiconductor layer 108, the generation of two-dimensional electron gas (2DEG) under the gate electrode 124 can be suppressed to achieve the normal closing of the semiconductor device status. In some embodiments, the material of the doped compound semiconductor block 109 may be p-doped or n-doped GaN. The step of forming the doped compound semiconductor block 109 may include depositing a doped compound semiconductor layer (not shown) on the gallium aluminum nitride semiconductor layer 108 through an epitaxial growth process, and performing a patterning process on the doped compound semiconductor layer To form a doped compound semiconductor block 109 corresponding to the position where the gate electrode 124 is to be formed.

With continued reference to FIG. 2A, a first protective layer 110 is formed on the gallium aluminum nitride semiconductor layer 108, and the first protective layer 110 conformally extends on the sidewall and upper surface of the doped compound semiconductor block 109. Next, a second protective layer 112 is formed on the first protective layer 110. The first protective layer 110 and the second protective layer 112 are formed in conformity with the sidewalls and the top surface of the doped compound semiconductor block 109, so that the first protective layer 110 and the second protective layer 112 each have the doped compound semiconductor block 109 The horizontal part directly above. In some embodiments, the material of the second protective layer 112 is different from the material of the first protective layer 110.

Referring to FIG. 2B, a source electrode 114 and a drain electrode 116 are formed on the gallium aluminum nitride semiconductor layer 108. The source electrode 114 and the drain electrode 116 pass through the second protective layer 112 and the first protective layer 110. To contact the gallium aluminum nitride semiconductor layer 108.

Next, a planarization process is performed on the second protective layer 112, such as chemical mechanical polishing (CMP). As shown in FIG. 2C, after the planarization process, the horizontal portion of the second protective layer 112 directly above the doped compound semiconductor block 109 is removed. The horizontal portion of the first protective layer 110 directly above the doped compound semiconductor block 109 is exposed from the second protective layer 112, and the upper surface of the exposed horizontal portion of the first protective layer 110 and the second protective layer 112 The upper surface is coplanar.

Referring to FIG. 2D, a third patterned mask layer 170 is formed on the exposed horizontal portions of the second protective layer 112 and the first protective layer. The third patterned mask layer 170 has a third opening 172, a fourth opening 174, and a fifth opening 176. The third opening 172 corresponds to the exposed horizontal portion of the first protective layer 110. The fourth opening 174 and the fifth opening 176 expose areas of the upper surface of the second protective layer 112 which are intended to form extensions 130 and 132 of the gate field plate 126 (shown in FIG. 2G). In some embodiments, the material and forming method of the third patterned mask layer 170 may be the same as or similar to the aforementioned first patterned mask layer 150 in FIG. 1C.

Next, an etching process is performed on the first protective layer 110 through the third opening 172 of the third patterned mask layer 170. In detail, in this embodiment, the etching process may use an etchant, which has a higher etching rate for the first protective layer 110 than the second protective layer 112. Since the second protective layer 112 has a high etch selectivity with respect to the first protective layer 110, the etchant hardly etches the fourth opening 174 and the fifth opening 176 of the second protective layer 112 from the third patterned mask layer 170 The exposed part.

As shown in FIG. 2E, after the etching process, a first recess 118 is formed in the first protective layer 110, and the first recess 118 exposes the upper surface of the doped compound semiconductor block 109. Since the third opening 172 of the third patterned mask layer 170 corresponds to the horizontal portion of the first protective layer 110, the first recess 118 only passes through the first protective layer 110 and does not pass through the second protective layer 112.

Next, an etching process is performed on the second protective layer 112 and the first protective layer 110 through the fourth opening 174 and the fifth opening 176 of the third patterned mask layer 170. In detail, in this embodiment, the doped compound semiconductor block 109 has a high etching selectivity with respect to the second protective layer 112 and the first protective layer 110, so the etchant hardly etches the doped compound semiconductor region The portion of the block 109 exposed from the third opening 172 of the third patterned mask layer 170. Furthermore, in this embodiment, the etching process may include a main etching step for the second protective layer 112 and an over-etching step for the first protective layer 110.

As shown in FIG. 2F, after the etching process, second recesses 120 and third recesses 122 are formed in the second protective layer 112 and the first protective layer 110. The second recess 120 and the third recess 122 pass through the second protective layer 112 and extend into the first protective layer 110. The second recess 120 and the third recess 122 do not pass through the first protective layer 110, so the portion of the first protective layer 110 directly under the second recess 120 and the third recess 122 remains on the GaN-on-aluminum semiconductor layer 108 .

Next, the third patterned mask layer 170 on the first protective layer 110 and the second protective layer 112 is removed.

Referring to FIG. 2G, a gate electrode 124 and a gate field plate 126 connected to the gate electrode 124 are formed on the first protective layer 110 and the second protective layer 112. The gate electrode 124 fills the first recess 118 and contacts the doped compound semiconductor block 109. The gate field plate 126 has a connection portion 128 connected to the gate electrode 124, and a first extension portion 130 and a second extension portion 132 filled in the second recess 120 and the third recess 122, respectively. The connection portion 128 is located on the area of the upper surface of the second protection layer 112 between the gate electrode 124 and the drain electrode 116.

Referring to FIG. 2H, an interlayer dielectric layer 134 is formed on the first protective layer 110 and the second protective layer 112. The interlayer dielectric layer 134 covers the gate electrode 124, the gate field plate 126, the source electrode 114, and the drain极 electrode 116. Next, a source contact 136 connected to the source electrode 114, a drain contact 138 connected to the drain electrode 116, and a gate contact 140 connected to the gate electrode 124 are formed in the interlayer dielectric layer 134. After forming the interconnect structure including the interlayer dielectric layer 134, the source contact 136, the drain contact 138 and the gate contact 140, the semiconductor device 200 is formed.

In the embodiment shown in FIG. 2H, the semiconductor device 200 includes a substrate 102 and a buffer layer 104, a gallium nitride semiconductor layer 106, a gallium aluminum nitride semiconductor layer 108, and a doped compound sequentially stacked on the substrate 102 Semiconductor block 109. The semiconductor device 200 further includes a first protective layer 110 disposed on the gallium aluminum nitride semiconductor layer 108 and surrounding the sidewall of the doped compound semiconductor block 109, and a second protective layer 112 disposed on the first protective layer 110, The second protective layer 112 is not located directly above the doped compound semiconductor block 109. The semiconductor device 200 further includes a source electrode 114 and a drain electrode 116 passing through the second protective layer 112 and the first protective layer 110 and contacting the gallium aluminum nitride semiconductor layer 108.

The semiconductor device 200 further includes a gate electrode 124 that passes through the first protective layer 110 and contacts the doped compound semiconductor block 109, and a gate field plate 126 connected to the gate electrode 124. The gate field plate 126 has a connection portion 128 to connect the gate electrode 124, and the first extension portion 130 and the second extension portion 132 extend into the second protective layer 112 and the first protective layer 110. The connection portion 128 is located above the second protective layer 112 and extends from the gate electrode 124 toward the drain electrode 116. The first extension portion 130 and the second extension portion 132 are interposed between the gate electrode 124 and the drain electrode 116, and the upper surfaces of the first extension portion 130 and the second extension portion 132 and the gallium aluminum nitride semiconductor layer 108 are A protective layer 110 is separated.

In the embodiment shown in FIGS. 2A-2H, the first recess 118, the second recess 120, and the third recess 122 used to form the gate electrode 124 and the gate field plate 126 are formed by the same patterned mask layer 170 is formed, so the patterning process for forming a recess can be saved once, so that the manufacturing efficiency of the semiconductor device can be improved.

In summary, the embodiments of the present invention use the gate field plate to have an extension extending into the protective layer, which can slow down the electric field gradient of the gate electrode near the side of the drain electrode to increase the breakdown voltage of the semiconductor device ( breakdown voltage), thereby improving the performance of the semiconductor device.

The above summarizes several embodiments so that those with ordinary knowledge in the technical field to which the present invention pertains can better understand the viewpoints of the embodiments of the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and/or advantages as the embodiments described herein. Those with ordinary knowledge in the technical field to which the present invention belongs should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and they can do so without departing from the spirit and scope of the present invention, Make various changes, substitutions and replacements.

100‧‧‧Semiconductor device

102‧‧‧ base

104‧‧‧buffer layer

106‧‧‧GaN semiconductor layer

108‧‧‧GaN aluminum semiconductor layer

110‧‧‧The first protective layer

112‧‧‧Second protective layer

114‧‧‧Source electrode

116‧‧‧Drain electrode

118‧‧‧The first depression

120‧‧‧Second depression

122‧‧‧The third depression

124‧‧‧Gate electrode

126‧‧‧Gate field plate

128‧‧‧Connect

130‧‧‧First Extension

132‧‧‧Second extension

134‧‧‧Interlayer dielectric layer

136‧‧‧ source contacts

138‧‧‧Drain contacts

140‧‧‧Gate contact

Claims (19)

A semiconductor device includes: a compound semiconductor layer disposed on a substrate; a protective layer disposed on the compound semiconductor layer; a source electrode, a drain electrode and a gate electrode passing through the protection And disposed on the compound semiconductor layer; and a gate field plate connected to the gate electrode and disposed on a portion of the protective layer between the gate electrode and the drain electrode, wherein the gate The pole field plate has an extension extending into the protective layer. The semiconductor device as described in item 1 of the patent application range, wherein the extension of the gate field plate is separated from the compound semiconductor layer. The semiconductor device according to item 1 of the patent application scope, wherein the protective layer includes: a first protective layer disposed on the compound semiconductor layer; and a second protective layer disposed on the first protective layer, the The material of the first protective layer is different from the material of the second protective layer. The semiconductor device of claim 3, wherein the extension of the gate field plate passes through the first protective layer and extends into the second protective layer. The semiconductor device as described in item 1 of the patent application scope further includes: a doped compound semiconductor block disposed between the compound semiconductor layer and the gate electrode. The semiconductor device as described in item 5 of the patent application range, wherein the protective layer includes: a first protective layer surrounding the sidewall of the doped compound semiconductor block; and a second protective layer disposed on the first protective layer On the layer, the second protective layer is not directly above the doped compound semiconductor block, wherein the material of the first protective layer is different from the material of the second protective layer. The semiconductor device as described in item 6 of the patent application range, wherein the first protective layer has a horizontal portion above the doped compound semiconductor block, the upper surface of the horizontal portion of the first protective layer and the second The upper surface of the protective layer is coplanar. The semiconductor device as described in item 1 of the patent application range, wherein the semiconductor device is a high electron mobility transistor (HEMT). The semiconductor device as described in item 1 of the patent application range, wherein the gate field plate has another extension portion interposed between the extension portion and the drain electrode and extending into the protective layer. A manufacturing method of a semiconductor device, comprising: forming a compound semiconductor layer on a substrate; forming a protective layer on the compound semiconductor layer; forming a source electrode, a drain electrode and a gate through the protective layer A gate electrode on the compound semiconductor layer; and a gate field plate formed on a portion of the protective layer between the gate electrode and the drain electrode to connect the gate electrode, wherein the gate electrode The field plate has an extension extending into the protective layer. The method for manufacturing a semiconductor device as described in item 10 of the patent application range, wherein the step of forming the gate electrode and the gate field plate includes: forming a first recess and a second recess in the protective layer, wherein the The second recess is between the first recess and the drain electrode; forming a conductive material layer on the protective layer to fill the first recess and the second recess; and patterning the conductive material layer to form The gate electrode fills the first recess and the gate field plate is connected to the gate electrode and fills the second recess. The method for manufacturing a semiconductor device as described in item 11 of the patent application range, wherein the first recess exposes the compound semiconductor layer, and the second recess does not expose the compound semiconductor layer. The method for manufacturing a semiconductor device as described in item 12 of the patent application range, wherein the formation of the protective layer includes: depositing a first protective layer on the compound semiconductor layer; and depositing a second protective layer on the first protective layer Layer, wherein the material of the first protective layer is different from the material of the second protective layer. The method of manufacturing a semiconductor device as described in item 11 of the patent application range, wherein the steps of forming the first recess and the second recess include: forming a first patterned mask layer over the protective layer; A first opening of a patterned mask layer etches the protective layer to form the first recess to expose the compound semiconductor layer; remove the first patterned mask layer; form a second layer on the protective layer Patterned mask layer; etching the protective layer through a second opening of the second patterned mask layer to form the second recess in the protective layer without exposing the compound semiconductor layer; and removing the The second patterned mask layer. The method for manufacturing a semiconductor device as described in item 11 of the patent application scope further includes: after forming the compound semiconductor layer and before forming the protective layer, forming a doped compound semiconductor block, wherein the gate electrode Formed on the doped compound semiconductor block. The method for manufacturing a semiconductor device as described in item 15 of the patent application range, wherein the formation of the protective layer includes: depositing a first protective layer on the compound semiconductor layer to compliantly cover the doped compound semiconductor block And the upper surface of the first protective layer; and depositing a second protective layer on the first protective layer, wherein the material of the first protective layer is different from the material of the second protective layer. The method for manufacturing a semiconductor device as described in item 16 of the patent application scope further includes: after forming the second protective layer, performing a planarization process to remove the second protective layer located in the doped compound semiconductor block A portion directly above exposes a horizontal portion of the first protective layer directly above the doped compound semiconductor block. The method for manufacturing a semiconductor device as described in Item 17 of the patent application range, wherein the steps of forming the first recess and the second recess include: after the planarization process, in the first protective layer and the second protective layer Forming a third patterned mask layer thereon; etching the horizontal portion of the first protective layer through a third opening of the third patterned mask layer to form the first recess to expose the doped compound A semiconductor block; etching the second protective layer and the first protective layer through a fourth opening of the third patterned mask layer to form the second recess in the first protective layer and the second protective layer , And the compound semiconductor layer is not exposed; and the third patterned mask layer is removed. The method for manufacturing a semiconductor device as described in item 11 of the patent application range, wherein the step of forming the first recess and the second recess further comprises forming a third recess between the second recess and the drain electrode; The conductive material layer further fills the third recess; wherein after etching the conductive material layer, the gate field plate has another extension to fill the third recess.

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