TW202006842A - Semiconductor package structure and method for forming the same - Google Patents

Abstract

A method for forming a semiconductor package structure is provided. First, a plurality of dies with conductive bumps are disposed on a temporary carrier and a molding compound is formed on the carrier to cover the dies and wherein the conductive bumps are exposed. Then, a bridge interconnect structure is disposed between two adjacent dies and electrically connected with a part of conductive bumps of the two adjacent dies. Also, a plurality of conductive plugs are respectively and electrically connected to the other part of the conductive bumps of the dies. Then, a molding compound is further formed to cover the bridge interconnect structure and the conductive plugs, wherein the pad end of each conductive plug is exposed, and a redistribution layer is formed to fan out the pad ends for arranging the solder balls. Finally, the temporary carrier is removed and die saw is proceeded to form a plurality of semiconductor package structure. This method does not require the use of a package substrate, and the semiconductor package structure has the advantage of achieving high density and heterogeneous integration and reducing the package thickness.

Description

Semiconductor packaging structure and method for forming semiconductor packaging structure

The invention relates to a semiconductor packaging structure, in particular to a multi-die semiconductor packaging structure and a method of forming a semiconductor packaging structure.

With the demand for electronic products toward higher functionality, higher signal transmission speed and higher density of circuit components, the functions of semiconductor chips are becoming more powerful. Multi-chip packaging technology places semiconductor chips with different functions in the same package product, achieving high-capacity and multi-function operation in a single package product, and how to accommodate in a limited package space when electronic products emphasize light, thin and short The huge number of electronic components has become an urgent technical bottleneck for the electronic construction industry to solve and overcome.

The invention provides a method for forming a semiconductor package structure, which can perform multi-die packaging without using a package substrate, can realize high density and heterogeneous integration, and reduce package thickness and reduce the thickness of the semiconductor package structure.

The invention provides a semiconductor packaging structure, which has the advantages of multi-chip high-density packaging and reduced thickness.

The method for forming a semiconductor package structure provided by the present invention includes: providing a carrier board having an upper surface; providing at least a first die and at least a second die, the first die including a plurality of first conductive bumps , The second die includes a plurality of second conductive bumps; set the first die and the second die on the upper surface, and the first conductive bump and the second conductive bump face upwards away from the upper surface; set the first The molding material is on the upper surface and covers the first die and the second die, and exposes the first conductive bump and the second conductive bump; a bridge interconnect structure is provided to electrically couple a portion of the first conductive bump and a portion The second conductive bump and a plurality of conductive plugs are electrically coupled to another part of the first conductive bump and another part of the second conductive bump, each conductive plug has a pad end away from the first conductive bump And a second conductive bump; setting a second molding material on the first molding material, the second molding material covering the bridge interconnect structure and the conductive plug, and at least revealing the pad end of the conductive plug; The wiring layer is on the second molding material, and the redistribution layer is electrically coupled to the pad end; a plurality of solder balls are provided to electrically couple to the redistribution layer; and the carrier board is removed.

The semiconductor package structure provided by the present invention includes at least one first die and at least one second die in parallel, a bridge interconnect structure, a plurality of conductive plugs, a molding material, a redistribution layer, and a plurality of solder balls. The first die has opposite first top surface and first bottom surface, the second die has opposite second top surface and second bottom surface, the first bottom surface is provided with a plurality of first conductive bumps, and the second bottom surface is provided with A plurality of second conductive bumps; the bridge interconnect structure is disposed below the first die and the second die, and the bridge interconnect structure electrically couples a portion of the first conductive bump and a portion of the second conductive bump; a plurality of The conductive plug is electrically coupled to another part of the first conductive bump and another part of the second conductive bump, each conductive plug has a pad end away from the first conductive bump and the second conductive bump; molding The material covers part of the first die, part of the second die, the bridge interconnection structure and the conductive plug. The molding material includes relatively upper and lower surfaces, and the lower surface at least exposes the pad end of the conductive plug, the upper The surface reveals the first top surface of the first die and the second top surface of the second die; the redistribution layer is disposed on the lower surface of the molding material and is electrically coupled to the pad end; Sexually coupled to the redistribution layer.

In an embodiment of the invention, the first molding material and the second molding material are the same molding material.

In an embodiment of the invention, the method further includes grinding the first molding material covering the first die and the second die with a first grinding process to expose the first conductive bump and the second conductive bump .

In one embodiment of the present invention, the second molding process for grinding the second molding material covering the bridge interconnect structure and the conductive plug is further polished to expose the pad end of the conductive plug.

In an embodiment of the invention, the upper surface of the carrier plate has a release layer, and the first die and the second die are disposed on the release layer.

In an embodiment of the present invention, the above-mentioned conductive plug is formed by a through-mold (TMV) method.

In an embodiment of the invention, the above-mentioned carrier board is selected from one of glass, wafer, panel, and plastic board.

In an embodiment of the invention, the above-mentioned bridge interconnection structure is a silicon bridge structure. The bridge interconnection structure has a plurality of micro-bumps. The micro-bumps are electrically connected to a portion of the first conductive bumps and a portion of the second conductive bumps. Coupling.

In an embodiment of the invention, after removing the carrier board, a wafer dicing step is further included.

In an embodiment of the invention, the first top surface of the first die and the second top surface of the second die are coplanar.

The method for forming a semiconductor package structure of the present invention is to first place a plurality of dies with conductive bumps on a carrier board, and simultaneously mold a plurality of dies; then set up a bridge interconnect structure on two adjacent dies And electrically couple the two dies between them, and also set a plurality of conductive plugs to electrically couple the dies; after that, the conductive plugs and the bridge interconnection structure are molded again and the pad ends of the conductive plugs are exposed, and are provided The redistribution layer fanned out the pad ends to set up solder balls, and finally the carrier was removed. Therefore, the semiconductor package structure has the advantage that the package thickness can be reduced without using a package substrate.

To make the above and other objects, features, and advantages of the present invention more comprehensible, embodiments are described below in conjunction with the accompanying drawings, which are described in detail below.

The following description is a preferred embodiment of the present invention. Throughout the specification and the scope of the attached patent application, certain words are used to refer to specific components. Those skilled in the art should understand that manufacturers may use different terms to refer to the same component. This specification and the scope of patent application do not use differences in names as a way to distinguish components, but differences in functions of components as a basis for differentiation. In the drawings, the size of some components may be exaggerated rather than drawn to scale for illustrative purposes. The dimensions and relative dimensions in the drawings may or may not correspond to actual dimensions in the practice of the invention.

1A to 1H are cross-sectional views of various stages of forming a semiconductor package structure according to some embodiments of the present invention. Additional operations may be provided before, during, and/or after the stages described in FIGS. 1A to 1H. In order to simplify the drawings, only a part of the semiconductor package structure is shown in FIGS. 1A to 1H.

As shown in FIG. 1A, a carrier board 10 is provided, which is a temporary substrate and will be removed in a subsequent step. In some embodiments, the carrier board 10 is a wafer, a panel, or a substrate made of suitable materials such as glass or plastic. The carrier board 10 has an upper surface. In an embodiment, the carrier board 10 has a release layer 101 on the upper surface.

As shown in FIG. 1B, at least two dies are disposed on the release layer 101. The two dies are a first die 12 and a second die 14, respectively. The first die 12 and the second die 14 may be a system Chip, memory die, logic die, analog processor, digital processor, radio frequency component, or other suitable passive electronic components. The first die 12 and the second die 14 each have an active surface 121, 141, an inactive surface 122, 142, and side walls 123, 143. The side walls 123, 143 are substantially perpendicular to the active surface 121, 141, and the inactive surface 122. 142. The first die 12 includes a plurality of first conductive bumps 16 on the active surface 121, and the second die 14 includes a plurality of second conductive bumps 18 on the active surface 141. The first die 12 and the second die 14 are disposed on the release layer 101 of the carrier board 10, wherein the first die 12 and the second die 14 are juxtaposed, and the inactive surfaces 122 and 142 and the release layer 101 Contact, and the first conductive bump 16 and the second conductive bump 18 face upward away from the carrier board 10. In one embodiment, the first die 12 and the second die 14 may have the same or different sizes, and the first die 12 and the second die 14 may have the same or different functions. In an embodiment, the first conductive bump 16 and the second conductive bump 18 may be micro bumps, conductive balls or conductive pillars, the first conductive bumps 16 and the second The material of the conductive bump 18 is, for example, copper. For the convenience of description and understanding, the first conductive bump 16 is divided into two regions, namely the first conductive bump 16a of the first inner connecting region and the first conductive bump 16b of the first outer connecting region; The two conductive bumps are also divided into two regions, which are the second conductive bump 18a in the second inner connecting region and the second conductive bump 18b in the second outer connecting region, respectively. Wherein, the first conductive bump 16a of the first interconnected area is close to the second conductive bump 18a of the second interconnected area.

As shown in FIG. 1C, a first molding compound 20 is formed on the release layer 101 of the carrier plate 10, the first molding material 20 covers the first die 12 and the second die 14, and The first conductive bump 16 and the second conductive bump 18 are exposed. In one embodiment, after the first molding material 20 completely covers the first die 12 and the second die 14, the first grinding process is used to thin the first molding material 20 to make the first mold The plastic material 20 is thinned to expose a part of the first conductive bump 16 and the second conductive bump 18.

As shown in FIG. 1D, a plurality of conductive plugs 22 are provided on the first molding material 20, wherein one end of the plurality of conductive plugs 22 are respectively connected to the first conductive bumps 16b and the second external connection of the first external connection area The second conductive bump 18b of the region is electrically coupled, and the other end of the conductive plug 22 is away from the first conductive bump 16b and the second conductive bump 18b and serves as a pad end 221. In one embodiment, the conductive plug 22 is formed by a through-mold conductor through-hole (TMV) method, for example, by laser perforating the surface of the first molding material 20, and then the conductive plug 22 and the first conductive bump 16b It is connected to the second conductive bump 18b. The material of the conductive plug 22 is, for example, copper.

As shown in FIG. 1E, a bridge interconnection structure 24 is disposed on the first molding material 20. The bridge interconnection structure 24 has a plurality of micro-bumps 26, and the bridge interconnection structure 24 spans the adjacent first die 12 and the second die 14, and the micro-bumps 26 are electrically coupled to the first conductive bump 16a of the first interconnection area and the second conductive bump 18a of the second interconnection area, respectively. Also, although the above drawing in FIGS. 1D and 1E is to first set a plurality of conductive plugs 22 and then the bridge interconnection structure 24, it can be understood that the arrangement of the conductive plugs 22 and the bridge interconnection structure 24 is not sequential. In addition, the bridge interconnection structure 24 may also be provided first, followed by the conductive plug 22. In one embodiment, the bridge interconnect structure 24 is a silicon bridge structure, and its fabrication is mainly formed by forming metal pillars (VIA) in a silicon substrate and providing a redistribution layer and micro bumps.

As shown in FIG. 1F, the second molding material 28 is formed on the first molding material 20. The second molding material 28 covers the conductive plug 22 and the bridge interconnection structure 24, and reveals the connection of the conductive plug 22垫端221. In one embodiment, after the second molding material 24 completely covers the conductive plug 22 and the bridge interconnection structure 24, the second molding material 24 is thinned by the second grinding process to make the second molding The material 24 is thinned to expose the pad end 221 of the conductive plug 22. In another embodiment, a surface of the bridge interconnect structure 24 away from the first die 12 and the second die 14 may also be exposed through the thinning process. In another embodiment, the second molding material 20 and the first molding material 28 are the same molding material.

As shown in FIG. 1G, the redistribution layer 30 is formed on the second molding material 28 and the conductive plug 22, and the redistribution layer 30 is electrically coupled to the pad terminal 221 and fan-out the pad terminal 221. In one embodiment, the redistribution layer 30 may include at least one dielectric layer 301, at least one metal layer 302, a redistribution pad 303 and a protective layer 304 located on a side away from the second molding material 28, wherein the metal layer 302 is electrically coupled to the pad end 221 and the redistribution pad 303, as shown in FIG. 1G, and a plurality of solder balls 32 are provided to electrically couple the redistribution pad 303 of the redistribution layer 30, respectively. Then, as shown in FIG. 1H, the carrier board 10 is removed, so that the inactive surfaces 122 and 142 of the first die 12 and the second die 14 are exposed. In some embodiments, after removing the carrier board 10, a wafer sawing step (die saw) is performed. For example, the redistribution layer 30, the first molding material 20, and the second molding material 28 may be cut, so several The semiconductor package structure 40 is formed.

As shown in FIG. 1H, each semiconductor package structure 40 includes a first die 12, a second die 14, a bridge interconnect structure 24, a conductive plug 22, a molding material 42, a redistribution layer 30, and a plurality of solder balls 32. The first die 12 and the second die 14 are arranged in a side-by-side relationship. The first die 12 has opposite first top surface (eg, inactive surface 122) and first bottom surface (eg, active surface 121), and the second crystal The grain 14 has a second top surface (eg, inactive surface 142) and a second bottom surface (eg, active surface 141) opposite to each other. The active surface 121 of the first grain 12 and the active surface 141 of the second grain 14 are respectively provided with A first conductive bump 16 and a plurality of second conductive bumps 18. Wherein, due to the use of the carrier board 10 in the process of forming the semiconductor package structure, the inactive surface 122 of the first die 12 and the inactive surface 142 of the second die 14 are coplanar.

Following the above description, the bridge interconnect structure 24 is disposed below the first die 12 and the second die 14 and is located between the first die 12 and the second die 14, and bridges the micro bumps 26 of the interconnect structure 24 Electrically coupled to a portion of the first conductive bump 16a and a portion of the second conductive bump 18a; yet another portion of the first conductive bump 16b and the second conductive bump 18b are provided with a conductive plug 22, each A conductive plug 22 has a pad end 221 away from the first conductive bump 16b and the second conductive bump 18b. In one embodiment, the pad ends 221 of the plurality of conductive plugs 22 are located at the same height.

Please continue to refer to FIG. 1H. The molding material 42 (that is, the assembly of the first molding material 20 and the second molding material 28) covers part of the first die 12, part of the second die 14, and bridge junction interconnection Structure 24 and conductive plug 22. The molding material 42 includes opposite upper surface 421 and lower surface 422. In one embodiment, the molding material 42 does not cover the inactive surface 122 of the first die 12 and the inactive surface 142 of the second die 14 Therefore, the upper surface 421 of the molding material 42 reveals the inactive surfaces 122 and 142, and the molding material 42 does not cover the pad end 221 of the conductive plug 22, so the lower surface 422 of the molding material 42 exposes the pad end 221 . The redistribution layer 30 is disposed on the lower surface 422 of the molding material 42 and electrically coupled to the pad end 221. The plurality of solder balls 32 are respectively disposed on the redistribution pad 303 of the redistribution layer 30 and electrically coupled to the redistribution pad 303.

In the semiconductor package structure of the embodiment of the present invention, multi-die is arranged in the same package structure, which can realize high-capacity and multi-function operation in a single package product. Since the use of the package substrate is reduced, the thickness of the semiconductor package structure can be effectively reduced, which has the advantage of reducing the package size.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined in the appended patent application.

10‧‧‧Carrier plate 101‧‧‧ Release layer 12‧‧‧ First grain 14‧‧‧Second grain 121, 141‧‧‧ Active surface 122, 142‧‧‧ Inactive surface 123, 143‧ ‧‧Side wall 16, 16a, 16b ‧‧‧ First conductive bump 18, 18a, 18b ‧‧‧ Second conductive bump 20‧‧‧ First molding material 22‧‧‧Conductive plug 221‧‧‧ Pad end 24‧‧‧Bridge interconnect structure 26‧‧‧Micro bump 28‧‧‧Second molding material 30‧‧‧Rewiring layer 301‧‧‧Dielectric layer 302‧‧‧Metal layer 303‧‧‧ Heavy cloth pad 304‧‧‧protective layer 32‧‧‧solder ball 40‧‧‧semiconductor packaging structure 42‧‧‧molding material 421‧‧‧upper surface 422‧‧‧lower surface

1A to 1H are cross-sectional views of various stages of forming a semiconductor package structure according to some embodiments of the present invention.

12‧‧‧First grain

14‧‧‧Second grain

121, 141‧‧‧ Active surface

122,142‧‧‧Inactive surface

16a, 16b‧‧‧First conductive bump

18a, 18b‧‧‧second conductive bump

20‧‧‧The first molding material

22‧‧‧Conductive plug

221‧‧‧ Pad end

24‧‧‧Bridge interconnect structure

26‧‧‧Micro bumps

28‧‧‧The second molding material

30‧‧‧Rewiring layer

32‧‧‧solder ball

40‧‧‧Semiconductor packaging structure

42‧‧‧Molding materials

421‧‧‧Upper surface

422‧‧‧Lower surface

Claims (12)

A method for forming a semiconductor package structure includes: providing a carrier board having an upper surface; providing at least a first die and at least a second die, the first die including a plurality of first conductive bumps, the The second die includes a plurality of second conductive bumps; the first die and the second die are disposed on the upper surface, and the first conductive bumps and the second conductive bumps face upwards away from The upper surface; setting a first molding material on the upper surface and covering the first die and the second die, and exposing the first conductive bumps and the second conductive bumps; setting a The bridge interconnect structure electrically couples a portion of the first conductive bumps and a portion of the second conductive bumps, and a plurality of conductive plugs are provided, which are respectively connected to another portion of the first conductive bumps and another portion of the ones The second conductive bumps are electrically coupled, and each of the conductive plugs has a pad end away from the first conductive bumps and the second conductive bumps; a second molding material is disposed on the first mold On the plastic material, the second molding material covers the bridge interconnection structure and the conductive plugs, and at least exposes the pad ends of the conductive plugs; a heavy wiring layer is provided on the second molding material And the redistribution layer is electrically coupled to the pad ends; a plurality of solder balls are provided to electrically couple the redistribution layer; and the carrier board is removed. The method for forming a semiconductor package structure according to claim 1, wherein the first molding material and the second molding material are the same molding material. The method for forming a semiconductor package structure according to claim 1, further comprising grinding the first molding material covering the first die and the second die with a first grinding process to expose the The first conductive bump and the second conductive bumps. The method for forming a semiconductor package structure according to claim 1, further comprising grinding the second molding material covering the bridge interconnect structure and the conductive plugs with a second grinding process to expose the ones The pad ends of the conductive plug. The method for forming a semiconductor package structure according to claim 1, wherein the upper surface of the carrier board has a release layer, and the first die and the second die are disposed on the release layer. The method for forming a semiconductor package structure as described in claim 1, wherein the conductive plugs are formed by a through-mold conductor through-hole (TMV) method. The method for forming a semiconductor package structure according to claim 1, wherein the carrier board is selected from one of glass, wafer, panel, and plastic board. The method for forming a semiconductor package structure according to claim 1, wherein the bridge interconnect structure is a silicon bridge structure, the bridge interconnect structure has a plurality of micro bumps, the micro bumps and a portion of the first conductive The bump and a portion of the second conductive bumps are electrically coupled. The method for forming a semiconductor package structure according to claim 1, wherein after removing the carrier board, a wafer cutting step is further included. A semiconductor package structure includes: at least one first die and at least one second die juxtaposed, the first die has a first top surface and a first bottom surface opposite, the second die has a second opposite A top surface and a second bottom surface, the first bottom surface is provided with a plurality of first conductive bumps, the second bottom surface is provided with a plurality of second conductive bumps; a bridge interconnection structure is provided on the first die and the Below the second die, the bridge interconnect structure electrically couples a portion of the first conductive bumps and a portion of the second conductive bumps; a plurality of conductive plugs, respectively, and another portion of the first conductive bumps Block and another part of the second conductive bumps are electrically coupled, each of the conductive plugs has a pad end away from the first conductive bumps and the second conductive bumps; a molded material, including Covering part of the first die, part of the second die, the bridge interconnection structure and the conductive plugs, the molding material includes opposite upper and lower surfaces, the lower surface reveals at least the conductive plugs The pad ends of the plug, the upper surface reveals the first top surface of the first die and the second top surface of the second die; a redistribution layer is provided on the lower surface of the molding material And are electrically coupled to the pad ends; and a plurality of solder balls are electrically coupled to the redistribution layer. The semiconductor package structure according to claim 10, wherein the bridge interconnect structure is a silicon bridge structure, the bridge interconnect structure has a plurality of micro bumps, the micro bumps and a portion of the first conductive bumps and A portion of the second conductive bumps are electrically coupled. The semiconductor package structure of claim 10, wherein the first top surface and the second top surface are coplanar.

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