TW201941594A - Image processing device and method for operating image processing device - Google Patents

Abstract

An image processing device and method for operating image processing device are provided. The image processing device includes a multimedia intellectual property (IP) block which processes image data including a first component and a second component; a memory; and a frame buffer compressor (FBC) which compresses the image data to generate compressed data and stores the compressed data in the memory. The frame buffer compressor includes a logic circuit which controls a compression sequence of the first component and the second component of the image data.

Description

Image processing device and method for operating image processing device

The present disclosure relates to an image processing apparatus and an operation method of the image processing apparatus.

More and more applications require high-resolution video images and high frame rate images. Therefore, the amount of data accessed from the memory (ie, bandwidth) that stores these images through various multimedia Intellectual Property (IP) blocks of the image processing device has greatly increased.

The processing power of each image processing device is limited. When the bandwidth increases, the processing power of the image processing device may reach this limit. As a result, users of image processing devices may experience slower speeds when recording or playing video images.

The aspect of the present disclosure provides an image processing apparatus that performs compression of image data with excellent compression quality.

Another aspect of the present disclosure provides an operation method of an image processing apparatus that performs compression of image data with excellent compression quality.

According to aspects of the present disclosure, an image processing device is provided. The image processing device includes: a multimedia intellectual property (IP) block configured to process image data including a first component and a second component; a memory; and a map A frame buffer compressor (FBC) configured to compress the image data to generate compressed data and store the compressed data in the memory, wherein the frame buffer compressor includes a logic circuit The logic circuit is configured to control a compression order of the first component and the second component of the image data.

According to another aspect of the present disclosure, an image processing device is provided. The image processing device includes: a multimedia intellectual property (IP) block configured to process image data conforming to the YUV format; memory; and frame buffer compression A buffer (FBC) configured to compress the image data to generate compressed data and store the compressed data in the memory, wherein the frame buffer compressor includes a logic circuit, and the logic circuit is configured The compression order is controlled so that the compression of the chrominance component of the Cb component and the Cr component of the YUV format including the image data is performed before the luminance component of the Y component of the YUV format including the image data is compressed.

According to another aspect of the present disclosure, an operation method of an image processing apparatus is provided, including: calculating a total target bit based on a target compression ratio of image data conforming to the YUV format; and calculating a Cb component for compressing the YUB format. And the chrominance component target bit of the chrominance component of the Cr component; allocating the chrominance component target bit to compress the chrominance component; the chrominance component of the compressed data using the chrominance component uses the bit to Calculating a lightness component target bit including a lightness component of the Y component of the YUV format; allocating the lightness component target bit to compress the lightness component; and when the lightness of the compressed data of the lightness component is the lightness When the total of the component use bit and the chrominance component use bit is less than the total target bit, a dummy bit is added after the compressed data of the lightness component.

The aspect of the present disclosure is not limited to the aspect mentioned above, and a person with ordinary knowledge in the art clearly understands another aspect not mentioned according to the following description.

1 to 3 are block diagrams for explaining an image processing apparatus according to an exemplary embodiment of the inventive concept.

Referring to FIG. 1, an image processing device according to an exemplary embodiment of the inventive concept includes multimedia IP (Intellectual Property Right) 100 (eg, IP blocks and IP cores, circuits, etc.), frame buffer compressor (FBC) 200 (eg, circuits , Digital signal processor, etc.), memory 300 and system bus 400.

In an embodiment, the multimedia IP 100 is a part of an image processing device, which directly performs image processing of the image processing device. The multimedia IP 100 may include a plurality of modules for recording and reproducing images, such as camera coding and playback of video images.

The multimedia IP 100 receives first data (eg, video data) from an external source such as a camera, and converts the first data into second data. For example, the first data may be moving image data or original image data. The second data is data generated by the multimedia IP 100, and may include data generated by the multimedia IP 100 that processes the first data. The multimedia IP 100 can repeatedly store the second data in the memory 300 and update the second data through multiple steps. The second data may contain all the data used in these steps. The second data may be stored in the memory 300 in the form of the third data. Therefore, the second data may be data before being stored in the memory 300 or after being read from the memory 300. This will be explained in more detail below.

In the exemplary embodiment, the multimedia IP 100 includes an image signal processor ISP 110, an oscillation correction module G2D 120, a multi-format codec MFC 130, a GPU 140, and a display 150. However, the inventive concept is not limited thereto. That is, the multimedia IP 100 may include at least one of an image signal processor 110, an oscillation correction module 120, a multi-format codec 130, a GPU 140, and a display 150. The multimedia IP 100 may be implemented by a processing module (such as a processor) that accesses the memory 300 to process data representing a moving image or a still image.

The image signal processor 110 receives the first data and pre-processes the first data to convert the first data into the second data. In an exemplary embodiment, the first data is RGB-type image source data. For example, the image signal processor 110 may convert the first data of the RGB type into the second data of the YUV type.

In the embodiment, the RGB type data means a data format representing colors based on the three primary colors of light. That is, it uses three types of colors, namely red (RED), green (GREEN), and blue (BLUE) to indicate the type of image. In contrast, the YUV type means a data type that separately represents brightness, that is, a luminance signal and a chrominance signal. That is, Y means a luma signal, and U (Cb) and V (Cr) respectively mean a chroma signal. U means the difference between the lightness signal and the blue signal component, and V means the difference between the lightness signal and the red signal component.

YUV type data can be obtained by converting RGB type data using a conversion formula. For example, conversion formulas such as Y = 0.3R + 0.59G + 0.11B, U = (BY) x0.493, V = (RY) x0.877 can be used to convert RGB data to YUV data .

Since the human eye is sensitive to lightness signals and less sensitive to color signals, it is easier to compress YUV-type data than RGB-type data. Therefore, the image signal processor 110 can convert the first data of the RGB type into the second data of the YUV type.

The image signal processor 110 converts the first data into the second data, and then stores the second data in the memory 300.

The oscillation correction module 120 may perform oscillation correction of still image data or moving image data. The oscillation correction module 120 may perform the oscillation correction by reading the first data or the second data stored in the memory 300. In an embodiment, the oscillation correction means detecting the oscillation from the camera of the moving image data and removing the oscillation from the moving image data.

The oscillation correction module 120 may correct the oscillation of the first data or the second data to update the first data or the second data and store the updated data in the memory 300.

The multi-format codec 130 may be a codec for compressing moving image data. In general, since the size of moving image data is very large, a compression module that reduces its size is necessary. The moving image data can be compressed through association between multiple frames, and this compression can be performed by the multi-format codec 130. The multi-format codec 130 can read and compress the first data or the second data stored in the memory 300.

The multi-format codec 130 may compress the first data or the second data to generate new second data or update the second data to store it in the memory 300.

A graphics processing unit (GPU) 140 may perform arithmetic processing and generation of two-dimensional graphics or three-dimensional graphics. The GPU 140 may perform arithmetic processing on the first data or the second data stored in the memory 300. The GPU 140 may be specifically used for graphics data processing to process graphics data in parallel.

The GPU 140 may compress the first data or the second data to generate updated first data or updated second data, and store the updated data in the memory 300.

The display 150 may display the second data stored in the memory 300 on the screen. The display 150 may display image data processed by the components of the multimedia IP 100, which are an image signal processor 110, an oscillation correction module 120, a multi-format codec 130, and a GPU 140. However, the inventive concept is not limited to these examples.

The video signal processor 110, the oscillation correction module 120, the multi-format codec 130, the GPU 140, and the display 150 of the multimedia IP 100 can be separately operated. That is, the image signal processor 110, the oscillation correction module 120, the multi-format codec 130, the GPU 140, and the display 150 can individually access the memory 300 to write or read data.

In an embodiment, the frame buffer compressor 200 compresses the second data to convert the second data into the third data before the multimedia IP 100 separately accesses the memory 300. The frame buffer compressor 200 transmits the third data to the multimedia IP 100, and the multimedia IP 100 transmits the third data to the memory 300.

Therefore, the third data compressed by the frame buffer compressor 200 is stored in the memory 300. In contrast, the third data stored in the memory 300 can be loaded by the multimedia IP 100 and transmitted to the frame buffer compressor 200. In an embodiment, the frame buffer compressor 200 decompresses the third data to convert the third data into the second data. The frame buffer compressor 200 may transmit the second data (that is, the decompressed data) to the multimedia IP 100.

In the embodiment, whenever the video signal processor 110, the oscillation correction module 120, the multi-format codec 130, the GPU 140, and the display 150 of the multimedia IP 100 individually access the memory 300, the frame buffer compressor 200 That is, the second data is compressed into the third data, and the third data is transmitted to the memory 300. For example, after one of the components of the multimedia IP 100 generates the second data and stores the second data in the memory 300, the frame buffer compressor 200 can compress the stored data and store the compressed data to the memory 300. in. In the embodiment, each time a data request is transmitted from the memory 300 to the image signal processor 110, the oscillation correction module 120, the multi-format codec 130, the GPU 140, and the display 150 of the multimedia IP, the frame buffer compressor 200 decompresses the third data into second data, and transmits the second data to the image data processor 110, the oscillation correction module 120, the multi-format codec 130, the GPU 140, and the display 150 of the multimedia IP 100, respectively.

The memory 300 stores the third data generated by the frame buffer compressor 200, and may provide the stored third data to the frame buffer compressor 200 so that the frame buffer compressor 200 can decompress the third data.

In the embodiment, the multimedia IP 100 and the memory 300 are connected to the system bus 400. Specifically, the image signal processor 110, the oscillation correction module 120, the multi-format codec 130, the GPU 140, and the display 150 of the multimedia IP 100 may be separately connected to the system bus 400. The system bus 400 may be a path, and the image signal processor 110, the oscillation correction module 120, the multi-format codec 130, the GPU 140, the display 150, and the memory 300 of the multimedia IP 100 transmit data to each other through the path.

The frame buffer compressor 200 is not connected to the system bus 400, and when the image signal processor 110, the oscillation correction module 120, the multi-format codec 130, the GPU 140, and the display 150 of the multimedia IP 100 respectively access the memory , And perform operations of converting the second data into the third data and converting the third data into the second data.

Next, referring to FIG. 2, the frame buffer compressor 200 of the image processing apparatus according to an exemplary embodiment of the inventive concept is directly connected to the system bus 400.

The frame buffer compressor 200 is not directly connected to the multimedia IP 100, and is connected to the multimedia IP 100 via the system bus 400. Specifically, each of the image signal processor 110, the oscillation correction module 120, the multi-format codec 130, the GPU 140, and the display 150 of the multimedia IP 100 can transmit data to the frame buffer via the system bus 400. The compressor 200 and the frame buffer compressor 200 transmit data, and thus the data can be transmitted to the memory 300.

That is, during the compression process, each of the image signal processor 110, the oscillation correction module 120, the multi-format codec 130, the GPU 140, and the display 150 of the multimedia IP 100 may transfer the second through the system bus 400. The data is transmitted to the frame buffer compressor 200. Then, the frame buffer compressor 200 can compress the second data into the third data, and transmit the third data to the memory 300 via the system bus 400.

Similarly, even during the decompression process, the frame buffer compressor 200 may receive the third data stored in the memory 300 via the system bus 400 and may decompress it into the second data. Then, the frame buffer compressor 200 can transmit the second data to the image signal processor 110, the oscillation correction module 120, the multi-format codec 130, the GPU 140, and the display 150 of the multimedia IP 100 via the system bus 400.

Referring to FIG. 3, in an image processing apparatus according to an exemplary embodiment of the inventive concept, a memory 300 and a system bus 400 are connected to each other via a frame buffer compressor 200.

That is, the memory 300 is not directly connected to the system bus 400, but is only connected to the system bus 400 via the frame buffer compressor 200. In addition, the image signal processor 110, the oscillation correction module 120, the multi-format codec 130, the GPU 140, and the display 150 of the multimedia IP 100 are directly connected to the system bus 400. Therefore, the image signal processor 110, the oscillation correction module 120, the multi-format codec 130, the GPU 140, and the display 150 of the multimedia IP 100 access the memory 300 only through the frame buffer compressor 200.

In the present specification, the second data is referred to as video data 10 and the third data is referred to as compressed data 20.

FIG. 4 is a block diagram for explaining the frame buffer compressor of FIGS. 1 to 3 in detail.

Referring to FIG. 4, the frame buffer compressor 200 includes an encoder 210 (eg, an encoding circuit) and a decoder 220 (eg, a decoding circuit).

The encoder 210 may receive the image data 10 from the multimedia IP 100 to generate the compressed data 20. The image data 10 can be transmitted from each of the image signal processor 110, the oscillation correction module 120, the multi-format codec 130, the GPU 140, and the display 150 of the multimedia IP 100. The compressed data 20 can be transmitted to the memory 300 via the multimedia IP 100 and the system bus 400.

Instead, the decoder 220 can decompress the compressed data 20 stored in the memory 300 into the image data 10. The image data 10 can be transmitted to the multimedia IP 100. The image data 10 can be transmitted to each of the image signal processor 110, the oscillation correction module 120, the multi-format codec 130, the GPU 140, and the display 150 of the multimedia IP 100.

FIG. 5 is a block diagram for explaining the encoder of FIG. 4 in detail.

Referring to FIG. 5, the encoder 210 includes a first mode selector 219 (such as a logic circuit), a prediction module 211 (such as a logic circuit), a quantization module 213 (such as a logic circuit), and an entropy coding module 215 (such as a logic circuit). And filling module 217 (such as a logic circuit).

In an embodiment, the first mode selector 219 determines whether the encoder 210 operates in a lossless mode or a lossy mode. When the encoder 210 operates in the lossless mode according to the first mode selector 219, the image data 10 is compressed along the lossless path of FIG. 5, and when the encoder 210 operates in the lossy mode, it follows the lossy path ( Lossy) compressed image data10.

The first mode selector 219 may receive a signal from the multimedia IP 100 for determining whether to perform lossless compression or perform lossy compression. Lossless compression means compression without loss of data. The compression ratio can vary depending on the lossless compressed data. Different from lossless compression, lossy compression is the loss of data. Compared with lossless compression, lossy compression has a higher compression ratio and can have a fixed compression ratio set in advance.

In the case of the lossless mode, the first mode selector 219 enables the image data 10 to flow to the prediction module 211, the entropy encoding module 215, and the padding module 217 along a lossless path. In contrast, in the lossy mode, the first mode selector 219 enables the image data 10 to flow along the lossy path to the prediction module 211, the quantization module 213, and the entropy coding module 215.

The prediction module 211 can compress the image data 10 by dividing the image data 10 into prediction data and residual data. The prediction data and the residual data together occupy less space than the image data10. In an embodiment, the prediction data is image data of one pixel of the image data, and the residual data is generated from the difference between the prediction data of the pixels of the image data adjacent to one pixel and the image data. For example, if the image data of a pixel has a difference between 0 and 255, it may take 8 bits to represent this value. When the adjacent pixel and the image data of one pixel have similar values, the residual data of each of the adjacent pixels is much smaller than the predicted data, and therefore the number of data bits representing the image data can be greatly reduced. For example, when the pixels with values of 253, 254, and 255 are continuous, if the prediction data is set to 253, it means that (253 (forecast), 1 (residual), and 2 (residual)) residual data is sufficient, And the number of bits per pixel used to represent these residual data can be greatly reduced from 8 bits to 2 bits. For example, the 24-bit data of 253, 254, and 255 are attributed to the 8-bit forecast of 253 (11111101), the 2-bit residual data of 254-251 = 1 (01), and 255-253 = 2 (10) 2-bit residual data can be reduced to 12 bits.

Therefore, the prediction module 211 can compress the total size of the image data 10 by dividing the image data 10 into prediction data and residual data. Various methods can be used to set the type of prediction data.

The prediction module 211 may perform prediction based on pixels, or may perform prediction based on blocks. In this case, a block may mean an area formed by a plurality of adjacent pixels. For example, pixel-based prediction may mean that all residual data is generated from one of the pixels, and block-based prediction may mean that residual data is generated for each block from the pixels corresponding to the block.

The quantization module 213 can further compress the image data 10 compressed by the prediction module 211. In the exemplary embodiment, the quantization module 213 removes the lower bits of the image data 10 via a preset quantization coefficient. Specifically, the representative value is selected by multiplying the data by the quantization coefficient, but a loss may occur by truncating the decimal part. If the value of the pixel data is between 0 and 2 ⁸ -1 (= 255), the quantization coefficient can be defined as / (2 ⁿ -1) 12 (n-1) (where n is an integer equal to or less than 8) . However, the embodiments of the present invention are not limited thereto. For example, if the prediction data is 253 (11111101), the prediction data can be reduced from 8 bits to 6 bits by removing the lower 2 bits, which results in (111111) 252 prediction data.

However, the removed lower bits were not recovered later, and were therefore lost. Therefore, the quantization module 213 is used only in the lossy mode. However, since the lossy mode has a relatively higher compression ratio than the lossless mode and may have a fixed compression ratio set in advance, information on the compression ratio is not required separately later.

The entropy coding module 215 can compress the image data 10 compressed by the quantization module 213 in a lossy mode or the image data 10 compressed by the prediction module 211 through the entropy coding in a lossless mode. In an embodiment, the entropy coding uses a method of assigning the number of bits to a video rate.

In the exemplary embodiment, the entropy encoding module 215 uses Huffman encoding to compress the image data 10. In an alternative embodiment, the entropy encoding module 215 compresses the image data 10 via exponential golomb encoding or golomb rice encoding. In the exemplary embodiment, the entropy encoding module 215 determines the entropy encoding value (for example, the k value) according to the data to be compressed, generates a graph according to the k value, and uses the graph to compress the image data 10.

The padding module 217 may perform padding on the image data 10 compressed by the entropy encoding module 215 in a lossless mode. In this article, padding can mean adding meaningless data to match a particular size. This will be explained in more detail below.

The padding module 217 can be enabled not only in a lossless mode but also in a lossy mode. In the lossy mode, when compressed by the quantization module 213, the image data 10 can be further compressed than the required compression ratio. In this case, even in the lossy mode, the image data 10 can be converted into compressed data 20 via the padding module 217 and transmitted to the memory 300. In the exemplary embodiment, the padding module 217 is omitted so that padding is not performed.

The compression management module 218 controls the compression order of the first component and the second component of the image data 10. Herein, the image data 10 may be image data conforming to the YUV format.

In this case, the first mode selector 219 determines that the encoder 210 operates in a lossy mode, and thus the image data 10 is compressed along the lossy path (Lossy) of FIG. 5. That is, the compression management module 218 controls the arrangement of the compression order of the first component and the second component of the image data 10 on the premise that the frame buffer compressor 200 uses the lossy compression algorithm to compress the image data 10.

Specifically, the image data 10 may include a first component and a second component. Herein, the first component may include, for example, a lightness component (corresponding to the aforementioned “luminance signal”) including a Y component in the YUV format, and the second component may include, for example, a chroma component including the Cb component and the Cr component in the YUV format ( (Corresponding to the aforementioned "color difference signal").

The compression management module 218 determines the compression order of the first component and the second component of the image data 10, and the frame buffer compressor 200 decompresses the first component and the second component according to the compression order determined by the compression management module 218. .

That is, if the compression management module 218 determines the compression order of the first and second components of the image data 10, the frame buffer compressor 200 uses the prediction module 211, quantization module 213, and The entropy coding module 215 is used to compress the image data 10.

Thereafter, the frame buffer compressor 200 combines the compressed data of the first component and the compressed data of the second component to generate a single bit stream, and the generated single bit stream can be written into the memory 300. In addition, the frame buffer compressor 200 can read a single bit stream from the memory 300, and can decompress the read single bit stream to provide the decompressed data to the multimedia IP 100.

More details of the compression management module 218 for performing this operation will be described later with reference to FIGS. 9 to 15.

FIG. 6 is a block diagram for explaining the decoder of FIG. 4 in detail.

Referring to FIG. 6, the decoder 220 includes a second mode selector 229 (such as a logic circuit), an unfilled module 227 (such as a logic circuit), an entropy decoding module 225 (such as a logic circuit), and an inverse quantization module 223 (such as a logic Circuit) and predictive compensation module 221 (such as a logic circuit).

The second mode selector 229 determines whether the compressed data 20 stored in the memory 300 has been compressed in a lossless manner or a lossy manner. In the exemplary embodiment, the second mode selector 229 determines whether the compressed data 20 has been compressed in a lossless mode or a lossy mode via the presence or absence of a header. This will be explained in more detail below.

In the case of the lossless mode, the second mode selector 229 enables the compressed data 20 to flow along the lossless path to the unfilled module 227, the entropy decoding module 225, and the prediction compensation module 221. In contrast, in the case of a lossy mode, the second mode selector 229 enables the compressed data 20 to flow along the lossy path (Lossy) to the entropy decoding module 225, the inverse quantization module 223, and the prediction compensation module 221.

The unfilled module 227 removes the padded portion of the data filled by the padded module 217 of the encoder 210. When the filling module 217 is omitted, the unfilled module 227 may be omitted.

The entropy decoding module 225 can decompress the data compressed by the entropy encoding module 215. The entropy decoding module 225 may perform decompression via Huffman coding, exponential Columbus coding, or Columbus coding. Since the compressed data 20 includes a k value, the entropy decoding module 225 may use the k value to perform decoding.

The inverse quantization module 223 can decompress the data compressed by the quantization module 213. The inverse quantization module 223 can recover the compressed data 20 compressed using the quantization coefficient determined by the quantization module 213, but it is impossible to completely recover the part lost during the compression process. Therefore, the inverse quantization module 223 is used only in the lossy mode.

The prediction compensation module 221 can recover data represented by the prediction data and residual data generated by the prediction module 211. The predictive compensation module 221 may, for example, convert residual data representations (253 (forecast), 1 (residual), and 2 (residual)) into 253, 254, and 255. For example, the prediction compensation module 221 may recover data by adding residual data to the prediction data.

The prediction compensation module 221 may recover the prediction performed in units of pixels or blocks according to the prediction module 211. Therefore, the compressed data 20 can be restored or decompressed and transmitted to the multimedia IP 100.

When the compressed data 20 is decompressed, the decompression management module 228 may execute the image data 10 that can appropriately reflect the combined order of the first component and the second component determined by the compression management module 218 described above with reference to FIG. 5. Compression work.

The image data 10 of the image processing apparatus according to an exemplary embodiment of the present inventive concept is a YUV type data. For example, YUV type data may have a YUV 420 format or a YUV 422 format.

FIG. 7 is a diagram for explaining three operation modes of a YUV 420 format material of an image processing apparatus according to an exemplary embodiment of the inventive concept.

Referring to FIGS. 1 to 7, the encoder 210 and the decoder 220 of the frame buffer compressor 200 may have three operation modes. The image data 10 in YUV 420 format may have a luminance signal block Y of 16 × 16 size, and a first color difference signal block Cb or U and a second color difference signal block Cr or V of each of 8 × 8 sizes. . In this article, the size of each block means whether or not pixels are arranged in rows and columns, and the size of 16 × 16 means the size of a block composed of multiple pixels having 16 rows and 16 columns.

The frame buffer compressor 200 may include three operation modes, namely (1) cascade mode, (2) partial cascade mode, and (3) separate mode. The three modes are about the compression format of the data, and may be operation modes that are respectively determined according to the lossy mode and the lossless mode.

First, the cascade mode (1) is an operation mode for compressing and decompressing all the luminance signal blocks Y, the first color difference signal block Cb, and the second color difference signal block Cr. That is, as shown in FIG. 5, in the cascade mode (1), the compressed unit block is a combination of a luminance signal block Y, a first color difference signal block Cb, and a second color difference signal block Cr. Block. Therefore, the size of the compressed unit block can be 16´24. For example, in the cascade mode, all blocks (such as Y block, Cb block, and Cr block) are combined into a single larger block, and a single compression operation is performed on the single larger block.

In the partial cascade mode (2), the luminance signal block Y is compressed and decompressed respectively, and the first color difference signal block Cb and the second color difference signal block Cr are merged with each other, and can be collectively compressed and decompressed compression. Therefore, the original size of the luminance signal block Y is 16´16, and the combined block of the first color difference signal block Cb and the second color difference signal block Cr is 16´8. For example, in the partial cascade mode, 8´8 Cr block and 8´8 Cb block are merged into the second block, the first compression operation is performed on the Y block, and the second block is performed separately. Second compression operation.

The separation mode (3) is an operation mode of compressing and decompressing all the luminance signal blocks Y, the first color difference signal block Cb, and the second color difference signal block Cr separately. For example, in the split mode, a first compression operation is performed on the Y block, a second compression operation is performed on the Cb block, and a third compression operation is performed on the Cr block. In the exemplary embodiment, in order to make the compressed and decompressed unit blocks the same size, the luminance signal block Y is maintained at the original size of 16´16, and the first color difference signal block Cb and the second color difference signal block Cr Increase to 16´16 size. For example, the Cb block and the Cr block can be enlarged to make them the same size as the Y block.

Therefore, if the number of blocks Y of the luminance signal is N, the number of the first color difference signal blocks Cb and the number of the second color difference signal blocks Cr can be reduced to N / 4, respectively.

When the frame buffer compressor 200 of the image processing apparatus according to an exemplary embodiment of the inventive concept operates in the cascade mode (1), all required data can be read via a single access request to the memory 300 . In particular, when RGB-type data is needed instead of YUV-type data in the multimedia IP 100, the frame buffer compressor 200 can operate more efficiently in the cascade mode (1). This is because it is possible to obtain the luminance signal block Y, the first color difference signal block Cb, and the second color difference signal block Cr at the same time in the cascade mode (1), and in order to obtain RGB data, all the luminance signal blocks Y, a first color difference signal block Cb, and a second color difference signal block Cr.

When the compressed unit block becomes smaller than in cascade mode (1), detached mode (3) may require lower hardware resources. Therefore, when YUV type data is needed in the multimedia IP 100 instead of RGB type data, the frame buffer compressor 200 can operate more efficiently in the separation mode (3).

Finally, part of the cascade mode (2) is a mode where there is a compromise between the cascade mode (1) and the separation mode (3). Even when RGB data is required, some cascade modes (2) require lower hardware resources than cascade mode (1). In the partial cascade mode (2), the access request to the memory 300 may be fewer (twice) times than in the detached mode (3).

The first mode selector 219 can select to compress the image data 10 in any one of three modes, that is, a cascade mode (1), a partial cascade mode (2), or a separate mode (3). The first mode selector 219 may receive a signal from the multimedia IP 100, and instruct the frame buffer compressor 200 to give a given one of the available modes of the cascade mode (1), the partial cascade mode (2), and the split mode (3) Person to operate.

The second mode selector 229 may decompress the compressed data 20 according to the compression mode of the first mode selector 219 among the cascade mode (1), the partial cascade mode (2), and the separation mode (3). For example, if the frame buffer compressor 200 was recently used to compress data in partial cascade mode (2), the second mode selector 229 may assume that the partial cascade mode (2) is used to compress the data to be decompressed .

FIG. 8 is a conceptual diagram for explaining three operation modes of a YUV 422 format material of an image processing apparatus according to an exemplary embodiment of the inventive concept.

Referring to FIG. 1 to FIG. 6 and FIG. 8, the encoder 210 and the decoder 220 of the frame buffer compressor 200 also have three operation modes in the YUV 422 format. The YUV 422 format image data 10 may have a luminance signal block Y of 16 × 16 size, and a first color difference signal block (Cb or U) and a second color difference signal block ( Cr or V).

In the cascade mode (1), the compressed unit block is a block in which the luminance signal block Y, the first color difference signal block Cb, and the second color difference signal block Cr are combined into a single larger block. Therefore, the size of the compressed unit block can be 16 × 32.

In the partial cascade mode (2), the luminance signal block Y is compressed and decompressed, respectively, and the first color difference signal block Cb and the second color difference signal block Cr are merged with each other, and are collectively compressed and decompressed. . Therefore, the luminance signal block Y is maintained at its original size of 16 × 16, and the block in which the first color difference signal block Cb and the second color difference signal block Cr are coupled may be 16 × 16. Therefore, the size of the combined block of the luminance signal block Y, the first color difference signal block Cb, and the second color difference signal block Cr may be the same.

The separation mode (3) is an operation mode of compressing and decompressing all the luminance signal blocks Y, the first color difference signal block Cb, and the second color difference signal block Cr separately. In the embodiment, in order to make the compressed and decompressed unit blocks the same size, the luminance signal block Y is maintained at the original size of 16 × 16, and the first color difference signal block Cb and the second color difference signal block Cr are increased to 16 × 16 size.

Therefore, when the number of the luminance signal blocks Y is N, the number of the first color difference signal blocks Cb and the number of the second color difference signal blocks Cr can be reduced to N / 2, respectively.

The operation of the image processing apparatus described above will now be described with reference to FIGS. 9 to 15. The operation of the image processing apparatus described below may be performed in the cascade mode (1) described above with reference to FIGS. 7 and 8.

9 to 11 are diagrams for explaining an operation of an image processing apparatus for YUV 420 format data according to an exemplary embodiment of the inventive concept.

FIGS. 9 and 10 show the case where the image data 10 conforms to the YUV 420 format, the target compression ratio of the image data 10 is 50%, and the color depth is 8 bits.

Referring to FIG. 9, the first component (ie, the lightness component) of the image data 10 corresponds to the Y plane 510Y of the image data 10, and the second component (ie, the chroma component) of the image data 10 corresponds to the Cb plane of the image data 10 510Cb and Cr plane 510Cr.

For the Y-plane 510Y, since the target compression ratio is 50% and the color depth is 8 bits, the target bit of the lightness component can be calculated as follows.

Lightness component target bit = 16 × 16 × 8 × 0.5 bit = 128 × 8 bit

For the Cb plane 510Cb and the Cr plane 510Cr, the Cb plane component target bit and the Cr plane component target bit can be calculated as follows.

Cb plane component target bit = 8 × 8 × 8 × 0.5 bits = 32 × 8 bits

Cr plane component target bit = 8 × 8 × 8 × 0.5 bits = 32 × 8 bits

Therefore, the chrominance component target bit obtained by combining the Cb plane component target bit and the Cr plane component target bit is 64 × 8 bits.

When the lightness component and the chroma component are compressed based on the target bit calculated in this way, both the lightness component and the chroma component are compressed at the same compression ratio of 50%.

The compressed bit stream 512 corresponding to the compression result may be formed as a single bit stream having an order of, for example, a Y component bit stream 512Y, a Cb component bit stream 512Cb, and a Cr component bit stream 512Cr. However, the scope of the concept of the present invention is not limited thereto, and the frame buffer compressor 200 may use a different order from the compression order of the first component (such as the lightness component) and the second component (such as the chroma component) The one-component compressed data and the second-component compressed data are combined to generate a compressed bit stream 512. That is, the order of the Y component bit stream 512Y, the Cb component bit stream 512Cb, and the Cr component bit stream 512Cr in the compressed bit stream 512 may be different from the order shown in FIG. 9.

In an exemplary embodiment of the inventive concept, the frame buffer compressor 200 interleaves and combines the compressed data of the first component and the compressed data of the second component to generate a compressed bit stream 512. That is, in the compressed bit stream 512, for example, a Y component bit stream 512Y, which is a bit stream in which Y components, Cb components, and Cr components that are repeated in units of pixels of the image data 10 are mixed in an arbitrary order, The Cb component bit stream 512Cb and the Cr component bit stream 512Cr.

For example, the compressed bit stream 512 may be the Y component bit stream of the first pixel of the image data 10, the Cb component bit stream of the first pixel, the Cr component bit stream of the first pixel, The Y component bit stream of two pixels, the Cb component bit stream of the second pixel, and the Cr component bit stream of the second pixel are interleaved and merged in the order of connection, and the Y component, Cb component, and Interlaced order of Cr components.

In general, the human eye is more sensitive to changes in brightness than changes in color. Therefore, in the image data 10 according to the YUV format, the brightness component may be more important than the chroma component.

However, when compressing the image data 10 according to the YUV format, since the pixel correlation of the chroma component is higher than the lightness component, prediction is easier, and therefore, the compression efficiency of the chroma component becomes higher than the lightness component.

Therefore, in order to further improve the quality of the compressed data 20 obtained by compressing the image data 10, the relative can be applied by allocating more bits to the lightness component with lower compression efficiency than the chroma component with good compression efficiency. Method to increase compression ratio.

Referring to FIG. 10, a first component (ie, a lightness component) of the image data 10 corresponds to a Y plane 520Y of the image data 10, and a second component (ie, a chroma component) of the image data 10 corresponds to a Cb plane of the image data 10 520Cb and Cr plane 520Cr.

In this embodiment, the compression management module 218 controls the compression sequence so that the frame buffer compressor 200 first compresses the chrominance component and then compresses the lightness component. To this end, the compression management module 218 calculates a chrominance component target bit before calculating a lightness component target bit.

For the Cb plane 520Cb and the Cr plane 520Cr, each of the Cb plane component target bit and the Cr plane component target bit can be calculated as follows.

Cr plane component target bit = 8 × 8 × 8 × 0.5 bits = 32 × 8 bits

Cr plane component target bit = 8 × 8 × 8 × 0.5 bits = 32 × 8 bits

The compression management module 218 allocates a chrominance component target bit to perform compression on the chrominance component before calculating the lightness component target bit. Specifically, the compression management module 218 determines a quantization parameter (QP) value and an entropy k value, so that the chroma component uses bit values that are smaller than and closest to the chroma target bit, thereby determining the The components perform compression.

Therefore, we assume that 28 × 8 bits are used for compression of the Cb plane component, and 30 × 8 bits are used for compression of the Cb plane component. That is, in the embodiment of the present invention, the chroma component use bit ((28 + 30) × 8 bits) is smaller than the chroma component target bit ((32 + 32) × 8) bits).

The compression management module 218 uses the chrominance component bit of the compressed data on the chrominance component to calculate the lightness component target bit on the lightness component.

The compression management module 218 can calculate the lightness component target bits as follows.

Lightness component target bit = total target bit-chroma component use bit = 192 × 8 bits-(28 + 30) × 8 bits = 132 × 8 bits

In this paper, for the 16 × 16 size Y plane (520Y), the 8 × 8 size Cb plane (520Cb), and the 8 × 8 size Cr plane (520Cr), the total target bit is 16 + 8) × 16 × 0.5 = 192 multiplied by a color depth value of 8. In addition, 0.5 means the target compression ratio.

The compression management module 218 assigns the calculated lightness component target bit to compress the lightness component.

According to this embodiment, it is different from FIG. 9 including a 128-bit Y-component bit stream 512Y, a 32-bit Cb component bit stream 512Cb, and a 32-bit Cr component bit stream 512Cr. The compressed bit stream 522 including the 28-bit Cb component bit stream 522Cb, the 30-bit Cr component bit stream 522Cr, and the 134-bit Y component bit stream 522Y becomes a compressed result.

As described above, the frame buffer compressor 200 may divide the compressed data of the first component and the first component in an arbitrary order different from the compression order of the first component (such as the luma component) and the second component (such as the chroma component). The two-component compressed data is combined to generate a compressed bit stream 522. That is, the order of the Y component bit stream 522Y, the Cb component bit stream 522Cb, and the Cr component bit stream 522Cr in the compressed bit stream 522 may be different from the order shown in FIG. 10.

In an exemplary embodiment of the inventive concept, the frame buffer compressor 200 interleaves and combines the compressed data of the first component and the compressed data of the second component to generate a compressed bit stream 522. That is, in the compressed bit stream 522, for example, the Y component bit stream 522Y may be generated in the form of a bit stream in which the Y component, the Cb component, and the Cr component repeated in units of pixels of the image data 10 are mixed in an arbitrary order. The Cb component bit stream 522Cb and the Cr component bit stream 522Cr. In this way, within the same overall target bit, by allocating more bits to lightness components with higher importance and relatively lower compression efficiency, and by allocating fewer bits to relatively different colors The degree component can improve the compression quality of the compressed data 20 obtained by compressing the image data 10.

Next, referring to FIG. 11, the first component (ie, the lightness component) of the image data 10 corresponds to the Y-plane 530Y of the image data 10, and the second component (ie, the chroma component) of the image data 10 corresponds to the Cb plane 530 Cb and Cr plane 530Cr.

In this embodiment, the compression management module 218 controls the compression sequence so that the frame buffer compressor 200 first compresses the chrominance component and then compresses the lightness component. To this end, the compression management module 218 calculates a chrominance component target bit before calculating a lightness component target bit. However, the difference from the embodiment of FIG. 10 is that the compression management module 218 may previously set the compression ratio of the chrominance component to, for example, 40.625% less than 50%.

Therefore, for the Cb plane 530Cb and the Cr plane 530Cr, the Cb plane component target bit and the Cr plane component target bit can be calculated as follows.

Cb plane component target bit = 8 × 8 × 8 × 0.40625 bits = 26 × 8 bits

Cr plane component target bit = 8 × 8 × 8 × 0.40625 bit = 26 × 8 bit

The compression management module 218 first performs compression on the chrominance component according to a compression ratio set in advance to, for example, 40.625%. Specifically, the compression management module 218 determines that the QP value and the entropy k value conform to a preset compression ratio, and performs compression on the chrominance component. Therefore, 26 × 8 bits are used to compress the Cb plane component, and 26 × 8 bits are used to compress the Cb plane component.

The compression management module 218 can calculate the lightness component target bits as follows.

Lightness component target bit = total target bit-chroma component target bit according to a preset compression ratio = 192 × 8 bits-(26 + 26) × 8 bits = 140 × 8 bits

In this paper, for the 16 × 16 size Y plane (530Y), the 8 × 8 size Cb plane (530Cb), and the 8 × 8 size Cr plane (530Cr), the total target bit is 16 + 8) × 16 × 0.5 = 192 multiplied by a color depth value of 8. In addition, 0.5 means the target compression ratio.

The compression management module 218 assigns the calculated lightness component target bit to compress the lightness component.

Therefore, in at least one embodiment of the inventive concept, when the image data 10 conforms to the YUV 420 format, the chroma component target bit can be calculated by the compression management module 218 as the total target bit / 3 × W (here, W is a positive real number equal to or less than 1). For example, the embodiment of FIG. 11 shows a case where the value of W is 0.40625.

According to this embodiment, it is different from FIG. 9 including a 128-bit Y-component bit stream 512Y, a 32-bit Cb component bit stream 512Cb, and a 32-bit Cr component bit stream 512Cr. The compressed bit stream 532 including the 26-bit Cb component bit stream 532Cb, the 26-bit Cr component bit stream 532Cr, and the 140-bit Y component bit stream 532Y becomes a compressed result.

As described above, the frame buffer compressor 200 may divide the compressed data of the first component and the first component in an arbitrary order different from the compression order of the first component (such as the luma component) and the second component (such as the chroma component). The two-component compressed data is combined to generate a compressed bit stream 532. That is, the order of the Y component bit stream 532Y, the Cb component bit stream 532Cb, and the Cr component bit stream 532Cr in the compressed bit stream 532 may be different from the order shown in FIG. 11.

In an exemplary embodiment of the inventive concept, the frame buffer compressor 200 generates a compressed bit stream 532 by interleaving and combining compressed data of a first component and compressed data of a second component. That is, the Y component bit stream 532Y can be generated in the compressed bit stream 532 in the form of a bit stream in which the Y component, the Cb component, and the Cr component that are repeated in units of pixels of the image data 10 are mixed in an arbitrary order, The Cb component bit stream 532Cb and the Cr component bit stream 532Cr.

As described above, within the same overall target bit, by allocating more bits to a lightness component with higher importance and relatively lower compression efficiency, and by allocating fewer bits to relatively different The chrominance component can improve the compression quality of the compressed data 20 obtained by compressing the image data 10.

12 to 14 are diagrams for explaining an operation of an image processing apparatus for YUV 422 format data according to an exemplary embodiment of the inventive concept.

FIG. 12 and FIG. 13 show the case where the image data 10 conforms to the YUV 422 format, the target compression ratio of the image data 10 is 50%, and the color depth is 8 bits.

Referring to FIG. 12, the first component (ie, the lightness component) of the image data 10 corresponds to the Y plane 540Y of the image data 10, and the second component (ie, the chroma component) of the image data 10 corresponds to the Cb plane of the image data 10 540Cb and Cr plane 540Cr.

For the Y-plane 540Y, since the target compression ratio is 50% and the color depth is 8 bits, the target bit of the lightness component can be calculated as follows.

Lightness component target bit = 16 × 16 × 8 × 0.5 bit = 128 × 8 bit

For the Cb plane 540Cb and the Cr plane 540Cr, the Cb plane component target bit and the Cr plane component target bit can be calculated as follows.

Cb plane component target bit = 16 × 8 × 8 × 0.5 bits = 64 × 8 bits

Cr plane component target bit = 16 × 8 × 8 × 0.5 bits = 64 × 8 bits

Therefore, the chrominance component target bit obtained by adding the Cb plane component target bit and the Cr plane component target bit is 128 × 8 bits.

When the lightness component and the chroma component are compressed based on the target bit calculated in this way, both the lightness component and the chroma component are compressed at the same compression ratio of 50%.

The compressed bit stream 542 corresponding to the compression result may be formed as a single bit stream having an order of, for example, a Y component bit stream 542Y, a Cb component bit stream 542Cb, and a Cr component bit stream 542Cr. However, the scope of the inventive concept is not limited thereto. For example, the frame buffer compressor 200 may divide the compressed data of the first component and the second component in an arbitrary order different from the compression order of the first component (such as the luma component) and the second component (such as the chroma component). The compressed data of the components are combined to generate a compressed bit stream 542. That is, the order of the Y component bit stream 542Y, the Cb component bit stream 542Cb, and the Cr component bit stream 542Cr in the compressed bit stream 542 may be different from the order shown in FIG. 12.

In an exemplary embodiment of the inventive concept, the frame buffer compressor 200 generates a compressed bit stream 542 by interleaving and combining compressed data of a first component and compressed data of a second component. That is, the Y-bit bit stream 542Y can be generated in the compressed bit stream 542 in the form of a bit stream in which the Y component, the Cb component, and the Cr component that are repeated in units of pixels of the image data 10 are mixed in an arbitrary order, The Cb component bit stream 542Cb and the Cr component bit stream 542Cr.

For example, the compressed bit stream 542 may be the Y component bit stream of the first pixel of the image data 10, the Cb component bit stream of the first pixel, the Cr component bit stream of the first pixel, the image data 10 The Y component bit stream of the second pixel, the Cb component bit stream of the second pixel, and the Cr component bit stream of the second pixel are interleaved and merged in the order of connection, and the Y component and Cb component can also be determined in any order. And the staggered order of the Cr components.

Referring to FIG. 13, the first component (ie, the lightness component) of the image data 10 corresponds to the Y-plane 550Y of the image data 10, and the second component (ie, the chroma component) of the image data 10 corresponds to the Cb plane of the image data 10 550 Cb and Cr plane 550Cr.

In this embodiment, the compression management module 218 controls the compression sequence so that the frame buffer compressor 200 first compresses the chrominance component and then compresses the lightness component. To this end, the compression management module 218 first calculates the chrominance component target bit before calculating the lightness component target bit.

For the Cb plane 550Cb and the Cr plane 550Cr, the Cb plane component target bit and the Cr plane component target bit can be calculated as follows.

Cb plane component target bit = 16 × 8 × 8 × 0.5 bits = 64 × 8 bits

Cr plane component target bit = 16 × 8 × 8 × 0.5 bits = 64 × 8 bits

The compression management module 218 allocates a chrominance component target bit to perform compression on the chrominance component before calculating the lightness component target bit. Specifically, the compression management module 218 determines the QP value and the entropy k value so that the chroma component use bit becomes a value smaller than and closest to the chroma target bit, and performs compression on the chroma component.

Therefore, we assume that 62 × 8 bits are used for compression of the Cb plane component, and 60 × 8 bits are used for compression of the Cb plane component. That is, in the embodiment of the present invention, the chroma component use bit ((62 + 60) × 8 bits) is smaller than the chroma component target bit ((64 + 64) 0 × 8) bits).

The compression management module 218 uses the chrominance component bit of the compressed data on the chrominance component to calculate the lightness component target bit of the lightness component.

The compression management module 218 can now calculate the lightness target bit as follows.

Luminous component target bit = total target bit-chroma component used bit = 256 × 8 bits-(62 + 60) × 8 bits = 134 × 8 bits.

In this paper, for the 16 × 16 size Y plane 550Y, the 8 × 8 size Cb plane 550Cb, and the 8 × 8 size Cr plane 550Cr, the total target bits are obtained by making the total size (16 + 8 + 8 ) × 16 × 0.5 = 256 times the color depth value of 8. In addition, 0.5 means the target compression ratio.

The compression management module 218 assigns the calculated lightness component target bit to compress the lightness component.

According to the embodiment of the present invention, the compressed bit stream including the 128-bit Y component bit stream 542Y, the 64-bit Cb component bit stream 542Cb, and the 64-bit Cr component bit stream 542Cr is different from FIG. 542. The compressed bit stream 552 including a Cb component bit stream 552Cb of 62 bits, a Cr component bit stream 552Cr of 60 bits, and a 134 bit Y component bit stream 552Y becomes a compressed result.

As described above, the frame buffer compressor 200 may divide the compressed data of the first component and the first component in an arbitrary order different from the compression order of the first component (such as the luma component) and the second component (such as the chroma component). The two-component compressed data is combined to generate a compressed bit stream 552. That is, the order of the Y component bit stream 552Y, the Cb component bit stream 552Cb, and the Cr component bit stream 552Cr in the compressed bit stream 552 may be different from the order shown in FIG. 13.

In an exemplary embodiment of the inventive concept, the frame buffer compressor 200 generates a compressed bit stream 552 by interleaving and combining compressed data of a first component and compressed data of a second component. That is, in the compressed bit stream 552, the Y component bit stream 552Y, for example, can be generated in the form of a bit stream in which Y components, Cb components, and Cr components that are repeated in pixels of the image data 10 are mixed in any order. The Cb component bit stream 552Cb and the Cr component bit stream 552Cr.

In this way, within the same overall target bit, by allocating more bits to lightness components with higher importance and relatively lower compression efficiency, and by allocating fewer bits to relatively different colors The degree component can improve the compression quality of the compressed data 20 obtained by compressing the image data 10.

Next, referring to FIG. 14, the first component (ie, the lightness component) of the image data 10 corresponds to the Y-plane 560Y of the image data 10, and the second component (ie, the chroma component) of the image data 10 corresponds to the Cb plane 560Cb and Cr plane 560Cr.

In the embodiment of the present invention, the compression management module 218 controls the compression sequence, so that the frame buffer compressor 200 first compresses the chrominance component and then compresses the lightness component. To this end, the compression management module 218 first calculates the chrominance component target bit before calculating the lightness component target bit. However, the difference from the embodiment of FIG. 13 is that the compression management module 218 previously set the compression ratio of the chrominance component to, for example, 40.625% less than 50%.

Therefore, for the Cb plane 560Cb and the Cr plane 560Cr, the Cb plane component target bit and the Cr plane component target bit can be calculated as follows.

Cb plane component target bit = 16 × 8 × 8 × 0.40625 bit = 52 × 8 bit

Cr plane component target bit = 16 × 8 × 8 × 0.40625 bit = 52 × 8 bit

The compression management module 218 first performs compression on the chrominance component according to a compression ratio set in advance to, for example, 40.625%. Specifically, the compression management module 218 determines that the QP value and the entropy k value conform to a preset compression ratio, and performs compression on the chrominance component. Therefore, 52 × 8 bits are used to compress the Cb plane component, and 52 × 8 bits are used to compress the Cb plane component.

The compression management module 218 can now calculate the lightness target bit as follows.

Lightness component target bit = total target bit-chroma component target bit according to a preset compression ratio = 256 × 8 bits-(52 + 52) × 8 bits = 152 × 8 bits.

In this paper, for the 16 × 16 size Y-plane 560Y, 8 × 8 size Cb-plane 560Cb, and 8 × 8 size Cr-plane 560Cr, the total target bit is ) × 8 = 256 times the color depth value of 8. In addition, 0.5 means the target compression ratio.

The compression management module 218 assigns the calculated lightness component target bit and compresses the lightness component.

Therefore, in at least one embodiment of the inventive concept, when the image data 10 conforms to the YUV 422 format, the compression management module 218 can calculate the chrominance component target bit to be the total target bit / 2 × W (here, W is a positive real number equal to or less than 1). For example, the embodiment of FIG. 14 shows a case where the value of W is 0.5.

According to the embodiment of the present invention, the compressed bit stream including the 128-bit Y-component bit stream 542Y, the 64-bit Cb component bit stream 542Cb, and the 64-bit Cr component bit stream 542Cr is different from FIG. 12. 542. The compressed bit stream 562 including a 52-bit Cb component bit stream 562Cb, a 52-bit Cr component bit stream 562Cr, and a 152-bit Y component bit stream 562Y becomes a compressed result.

As described above, the frame buffer compressor 200 may divide the compressed data of the first component and the first component in an arbitrary order different from the compression order of the first component (such as the luma component) and the second component (such as the chroma component). The two-component compressed data is combined to generate a compressed bit stream 562. That is, the order of the Y component bit stream 562Y, the Cb component bit stream 562Cb, and the Cr component bit stream 562Cr in the compressed bit stream 562 may be different from the order shown in FIG. 14.

In an exemplary embodiment of the inventive concept, the frame buffer compressor 200 generates a compressed bit stream 562 by interleaving and combining compressed data of a first component and compressed data of a second component. That is, the Y-component bit stream 562Y can be generated in the compressed bit stream 562 in the form of a bit stream in which the Y component, the Cb component, and the Cr component that are repeated in units of pixels of the image data 10 are mixed in any order. The Cb component bit stream 562Cb and the Cr component bit stream 562Cr.

In this way, within the same overall target bit, by allocating more bits to lightness components with higher importance and relatively lower compression efficiency, and by allocating fewer bits to relatively different colors The degree component can improve the compression quality of the compressed data 20 obtained by compressing the image data 10.

FIG. 15 is a flowchart illustrating a method of operating an image processing apparatus according to an exemplary embodiment of the inventive concept.

Referring to FIG. 15, an operation method of an image processing apparatus according to an exemplary embodiment of the inventive concept includes calculating a target bit of a chroma component (S1501).

Specifically, before calculating the target bit of the chroma component, the image processing device calculates the total target bit based on the target compression ratio of the image data 10 conforming to the YUV format, and then calculates a Cb component for compressing the Cb component including the YUV format. And the chrominance component target bit of the chrominance component of the Cr component.

In addition, the method includes allocating a chroma component target bit to compress the chroma component (S1503).

In addition, the method includes obtaining the number of compressed bits of the chroma component (S1505). The number of compressed bits of the chrominance component may be referred to as the chrominance component chrominance component use bit.

The method further includes calculating a target bit of a lightness component (eg, a target bit of a lightness component) (S1507). The lightness component is the Y component in YUV format.

In addition, the method includes allocating a lightness component target bit to compress the lightness component (S1509).

In addition, when the sum of the luma component use bits and the chroma component use bits of the luma component compression data is less than the total target bit, the method may further include adding a virtual bit after the luma component compression data,

Those of ordinary skill in the art will appreciate that many variations and modifications can be made to the exemplary embodiments without substantially departing from the principles of the inventive concept.

10‧‧‧Image data

20‧‧‧ Compressed data

100‧‧‧Multimedia IP

110‧‧‧Image Signal Processor

120‧‧‧Oscillation Correction Module

130‧‧‧Multi-format codec

140‧‧‧Graphics Processing Unit

150‧‧‧ Display

200‧‧‧Frame buffer compressor

210‧‧‧ Encoder

211‧‧‧ Forecast Module

213‧‧‧Quantitative module

215‧‧‧Entropy coding module

217‧‧‧ Fill module

218‧‧‧Compression Management Module

219‧‧‧Mode selector

220‧‧‧ decoder

221‧‧‧ Forecast Compensation Module

223‧‧‧Inverse quantization module

225‧‧‧ Entropy Decoding Module

227‧‧‧Unfilled Module

228‧‧‧Unzip Management Module

229‧‧‧Mode selector

300‧‧‧Memory

400‧‧‧System Bus

510Cb, 520Cb, 530Cb, 540Cb, 550Cb, 560Cb‧‧‧Cb plane

510Cr, 520Cr, 530Cr, 540Cr, 550Cr, 560Cr‧‧‧Cr plane

510Y, 520Y, 530Y, 540Y, 550Y, 560Y‧‧‧Y plane

512, 522, 532, 542, 552, 562‧‧‧compressed bitstream

512Cb, 522Cb, 532Cb, 542Cb, 552Cb, 562Cb‧‧‧Cb component bit streams

512Cr, 522Cr, 532Cr, 542Cr, 552Cr, 562Cr‧‧‧Cr component bit stream

512Y, 522Y, 532Y, 542Y, 552Y, 562Y‧‧‧Y component bit streams

S1501‧‧‧step

S1503‧‧‧step

S1505‧‧‧step

S1507‧‧‧step

S1509‧‧‧step

The present invention will become clearer by describing its exemplary embodiments in detail with reference to the accompanying drawings, in which: FIGS. 1 to 3 are block diagrams for explaining an image processing apparatus according to some embodiments of the inventive concept. FIG. 4 is a block diagram for explaining the frame buffer compressor of FIGS. 1 to 3 in detail. FIG. 5 is a block diagram for explaining the encoder of FIG. 4 in detail. FIG. 6 is a block diagram for explaining the decoder of FIG. 4 in detail. FIG. 7 is a conceptual diagram for explaining three operation modes of a YUV 420 format material of an image processing apparatus according to an exemplary embodiment of the inventive concept. FIG. 8 is a conceptual diagram for explaining three operation modes of a YUV 422 format material of an image processing apparatus according to an exemplary embodiment of the inventive concept. 9 to 11 are diagrams for explaining an operation of an image processing apparatus for YUV 420 format data according to an exemplary embodiment of the inventive concept. 12 to 14 are diagrams for explaining an operation of an image processing apparatus for YUV 422 format data according to an exemplary embodiment of the inventive concept. FIG. 15 is a flowchart illustrating a method of operating an image processing apparatus according to an exemplary embodiment of the inventive concept.

Claims (20)

An image processing device includes: a multimedia intellectual property (IP) block configured to process image data including a first component and a second component; a memory; and a frame buffer compressor (FBC) configured to compress all The image data to generate compressed data and store the compressed data in the memory, wherein the frame buffer compressor includes a logic circuit configured to control the first step of the image data The compression order of a component and the second component. The image processing device according to item 1 of the scope of patent application, wherein after compressing the first component and the second component according to the compression order determined by the logic circuit, the frame buffer compressor The compressed data of the first component and the compressed data of the second component are combined to generate a single bit stream. The image processing device according to item 2 of the scope of patent application, wherein the frame buffer compressor divides the first component in an arbitrary order different from the compression order of the first component and the second component. The compressed data of is combined with the compressed data of the second component to generate the single bit stream. The image processing device according to item 2 of the scope of patent application, wherein the frame buffer compressor interleaves and merges the compressed data of the first component and the compressed data of the second component to generate The single bit stream. The image processing device according to item 1 of the scope of patent application, wherein the image data is image data conforming to the YUV format, the first component includes a lightness component, and the lightness component includes a Y component in the YUV format, And the second component includes a chrominance component, and the chrominance component includes a Cb component and a Cr component in the YUV format. The image processing device according to item 5 of the scope of patent application, wherein the logic circuit controls the compression order so that the frame buffer compressor compresses the chrominance component first, and then compresses the lightness component. The image processing device according to item 6 of the patent application scope, wherein the logic circuit calculates a total target bit and a chrominance component target bit of the chrominance component based on a target compression ratio of the image data, and allocates the The chroma component target bit to compress the chroma component, use the chroma component of the compressed data of the chroma component to use a bit to calculate a light component target bit of the light component, and allocate the The lightness component target bit is described to compress the lightness component. The image processing device according to item 7 of the scope of patent application, wherein the chroma component use bit is smaller than the chroma component target bit. The image processing device according to item 7 of the scope of patent application, wherein when the image data conforms to the YUV 420 format, the chrominance component target bit is set to the total target bit / 3 × W, where W is a positive real number <= 1. The image processing device according to item 7 of the scope of patent application, wherein when the image data conforms to the YUV 422 format, the chrominance component target bit is set to the total target bit / 2 × W, where W is a positive real number <= 1. The image processing device according to item 7 of the scope of patent application, wherein the luma component target bit is calculated by subtracting the chrominance component bit from the total target bit. An image processing device includes: a multimedia intellectual property (IP) block configured to process image data conforming to the YUV format; a memory; and a frame buffer compressor (FBC) configured to compress the image data to Generating compressed data and storing the compressed data in the memory, wherein the frame buffer compressor includes a logic circuit configured to control a compression sequence so that the image data including the image data is compressed during compression; The lightness component of the Y component of the YUV format is previously compressed with the chrominance component of the Cb component and the Cr component of the YUV format including the image data. The image processing device according to item 12 of the patent application scope, wherein the logic circuit calculates a total target bit and a chroma component target bit of the chroma component based on a target compression ratio of the image data, and allocates the The chroma component target bit to compress the chroma component, use the chroma component of the compressed data of the chroma component to use a bit to calculate a light component target bit of the light component, and allocate the The lightness component target bit is described to compress the lightness component. The image processing device according to item 13 of the application, wherein the chrominance component use bit is smaller than the chrominance component target bit. The image processing device according to item 14 of the scope of patent application, wherein the logic circuit determines a quantization parameter (QP) value and an entropy k-coding value, so that the chrominance component uses a bit smaller than and closest to the color The value of the degree target bit. The image processing device according to item 13 of the patent application scope, wherein when the image data conforms to the YUV 420 format, the chrominance component target bit is set to the total target bit / 3 × W, where W is a positive real number> = 1. The image processing device according to item 13 of the scope of patent application, wherein when the image data conforms to the YUV 422 format, the chrominance component target bit is set to the total target bit / 2 × W, where W is a positive real number <= 1. The image processing device according to item 13 of the scope of patent application, wherein the luma component target bit is calculated by subtracting the chrominance component bit from the total target bit. The image processing device according to item 13 of the scope of patent application, wherein when the sum of the brightness component use bits and the chroma component use bits of the compressed data of the brightness component is less than the total target In the case of a bit, the logic circuit adds a virtual bit after the compressed data of the lightness component. An operating method of an image processing device, the method comprising: calculating a total target bit based on a target compression ratio of image data conforming to the YUV format; calculating a chrominance component for compressing a Cb component and a Cr component including the YUV format The chroma component target bit; assigning the chroma component target bit to compress the chroma component; using the chroma component of the compressed data of the chroma component to use the bit to calculate the A lightness component target bit of a lightness component of the Y component; allocating the lightness component target bit to compress the lightness component; and when the lightness component of the compressed data of the lightness component uses a bit and the When the sum of the used bits of the chrominance component is smaller than the total target bit, a virtual bit is added after the compressed data of the luma component.