TW201947391A - Mapping a computer code to wires and gates - Google Patents

Abstract

Methods and systems for mapping computer code to wires and gates are disclosed. An example method may include acquiring a code written in a programming language and generating, based on the code, a finite state machine (FSM). The method may further include generating, based on the FSM, a wires and gates representation, the wires and gates representation including a plurality of wires and a plurality of combinatorial logics. The method may further include configuring, based on the wires and gates representation, a field-programmable gate array. Input of each of the plurality of wires may represent a symbol selected from a set of symbols of a structured data packet. The size of the symbol can be equal to a number of bits of the structured data packet transferred per a clock cycle according to a data transmission protocol.

Description

Map computer codes to lines and gates

The present invention relates generally to data processing, and more specifically to methods and systems for mapping a computer code to lines and gates.

The methods described in this section can be pursued, but they are not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated, any one of the methods described in this section should not be assumed to qualify as prior art simply by virtue of its inclusion in this section.

Integrated circuits such as field programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs) can be used in many computing applications. For example, integrated circuits can be used in servers and computing clouds to handle Hyper File Transfer Protocol (HTTP) and other requests from client devices, which can provide a faster response than standard software-based applications. Despite the advantages of using integrated circuits in computing applications, designing, programming, and configuring integrated circuits is still a difficult task.

This [Summary of the Invention] is provided in a simplified form to introduce one of the concepts described further in [Embodiment] below. This [Summary of the Invention] is neither intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the category of the claimed subject matter.

The embodiments disclosed herein relate to methods and systems for mapping a computer code to lines and gates. According to an example embodiment, a method includes obtaining a code written in a programming language. The method may further include generating a finite state machine (FSM) based on the code. The method may further include generating a line and gate representation based on the FSM. The line and gate representation can include multiple lines and multiple combinational logic.

The method may further include configuring a programmable gate array based on the line and gate representation. The method may also include determining that one or more of the plurality of combinational logics does not depend on an input from a line of the plurality of lines. The method may further include storing the one or more combinational logics in a shift register in response to determining that one or more combinational logics of the plurality of combinational logics do not depend on inputs from the plurality of lines in.

The method may further include determining that one or more of the plurality of combinational logic depends on an input from a line of the plurality of lines. The method may further include storing the one or more combinational logics in a flip-flop in response to determining that one or more combinational logics of the plurality of combinational logics depend on an input from a line of the plurality of lines.

In a particular embodiment, the input of each of the plurality of lines may represent a symbol selected from a group of symbols of a structured data packet. The size of the symbol can be selected to be equal to the number of bits of the structured data packet transmitted per clock cycle according to a data transmission protocol. The number of gates and one line in the line and gate representation can be optimized based on a bit rate transmitted per clock cycle of the transmission protocol or the structure of the structured data packet. The structured data packet may include an Ethernet packet, an optical transport network packet, or a peripheral component fast interconnect packet.

The programming language may include a high-level programming language, such as JavaScript, C, C ++, or a domain-specific language. The method may further include optimizing the FSM before generating the line and gate representation. Optimizing the FSM includes minimizing the number of states in the FSM.

According to an example embodiment of the present invention, a system for mapping a computer code to a line and a gate is provided. The system may include at least one processor and a memory storing processor-executable code, wherein the at least one processor may be configured to implement the operations of the above method for mapping a computer code to a circuit and a gate.

According to another example embodiment of the present invention, the steps of the method for mapping a computer code to a circuit and a gate are stored on a machine-readable medium including instructions, which are executed by one or more processors Perform the steps described during implementation.

Cross-reference to related applications

This application was filed on June 6, 2017 and was issued on June 12, 2018 as U.S. Patent No. 9,996,328 with the title `` Compiling and Optimizing a Computer Code by Minimizing a Number of States in a Finite Machine Corresponding to the Computer Code "continues to be part of US Patent Application No. 15 / 630,691, the subject matter of which is incorporated herein for all purposes.

The following [Embodiment] contains references to accompanying drawings forming part of the [Embodiment]. The drawing shows a drawing according to an exemplary embodiment. These illustrative embodiments (also referred to herein as "examples") are described in sufficient detail to enable those skilled in the art to practice the subject matter. The embodiments may be combined, other embodiments may be used, or structural, logical, and electrical changes may be made without departing from the scope of the claimed content. Therefore, the following [embodiments] should not be understood in a limiting sense, and the scope is defined only by the scope of the accompanying invention application patent and its equivalent.

The techniques described in this article allow the translation of a computer code from a high-level programming language into a circuit and gate representation. Some embodiments of the invention may facilitate optimizing the source code according to the requirements of a hardware description. Embodiments of the present invention further allow configuration of programmable integrated circuits based on line and gate representations.

According to an example embodiment, a method for mapping a computer code to a line and a gate may include obtaining a code written in a programming language and generating an FSM based on the obtained code. The method may further include generating a line and gate representation based on the FSM. The line and gate representation can include multiple lines and multiple combinational logic. The method may further include configuring a field programmable gate array based on the line and gate representation.

FIG. 1 is a block diagram illustrating an exemplary system 100 for compiling source code according to some example embodiments. The exemplary system 100 may include a parsing presentation grammar (PEG) module 110, a converter 120 between an abstract syntax tree (AST) and an uncertain finite state machine (NFSM), an NFSM and a deterministic finite state machine (DFSM) ) Between a converter 130 and an optimizer 140. The system 100 can be implemented using a computer system. An exemplary computer system is described below with reference to FIG. 4.

In some embodiments of the present invention, the PEG module 110 may be configured to receive an input code 105. In some embodiments, the input code 105 can be written in an input programming language. The input programming language may be associated with a grammar 170. In some embodiments, the grammar 170 may be determined by an extended Backus-Naur form (ABNF). The PEG module can be configured to convert the input code 105 to an AST 115 based on the grammar 170. The AST 115 may be further provided to the converter 120.

In some embodiments of the invention, the converter 120 may be configured to transform the AST 115 into an NFSM 125. Thereafter, the NFSM 125 may be provided to the converter 130. The converter 130 may be configured to translate the NFSM 125 into a DFSM 135. The DFSM 135 may be provided to the optimizer 140.

In some embodiments, the optimizer 140 may be configured to optimize the DFSM 135 to obtain a DFSM 145. In some embodiments, the optimization may include minimizing the number of one of the DFSM 135 states. In various embodiments, optimization can be performed by an implied graph method, Hopcroft's algorithm, Moore's simplified procedure, Brzozowski's algorithm, and other techniques. Brzozowski's algorithm involves inverting the edges of a DFSM to generate an NFSM and converting this NFSM to a DFSM by constructing only the reachable state of the transformed DFSM using a standard powerset construction. Repeating the inversion again produces a DFSM with a provable minimum number of states.

In some embodiments, DFSM 145 (which is optimized DFSM 135) may be further provided to converter 130. The converter 130 may be configured to translate the DFSM 145 into an NFSM 150. The NFSM 150 may be further provided to the converter 120. The converter 120 may be configured to translate the NFSM 150 into an AST 155. AST 155 can be further provided to the PEG module 110.

In some embodiments, the PEG module 110 may be configured to convert the AST 155 to an output code 160 based on a grammar 180. The grammar 180 may specify an output programming language.

In some embodiments, the input or output language may include one of high-level programming languages, such as, but not limited to, C, C ++, C #, JavaScript, PHP, Python, Perl, and the like. In various embodiments, the input code and output source code can be optimized to operate on various hardware platforms such as advanced RISC machines (ARM), x86 to x64 graphics processing units (GPUs), and a programmable gate array (FPGA). ) Or a custom application specific integrated circuit (ASIC)). In various embodiments, the input code or source code can be optimized to work on various operating systems and platforms (such as Linux, Windows, Mac OS, Android, iOS, OpenCL / CUDA, bare metal, FPGA, and a custom ASIC). Run on.

In a particular embodiment, the output programming language may be the same as the input programming language. In these embodiments, the system 100 may be used to convert the optimized DFSM 135 into the output code 160 by converting the input code 105 to DFSM 135, optimizing the DFSM 135 in terms of the number of states, and in the original programming language Optimize the input code 105.

In some other embodiments, the input programming language may include a domain-specific language (DSL), which is determined by a strict grammar (ie, ABNF). In these embodiments, the system 100 can be used to convert a document written in a DSL into an output code 160 written in a high-level programming language or a code written in a low-level programming language. In a specific embodiment, the input code 105 or the output code 160 can be written in a presentation language (including but not limited to HTML, XML, and XHTML). In some embodiments, the input code 105 or the output code 160 may include CSS.

In some embodiments, the system 100 may further include a database. The database can be configured to store frequently occurring patterns in the input code written in a specific programming language and an optimized DFSM portion corresponding to the frequently occurring patterns. In these embodiments, the system 100 may include an additional module for finding a specific pattern of the input code 105 in the database. If the database contains an entry containing a specific pattern and a corresponding portion of DFSM, the system 100 may be configured to directly use the corresponding portion of DFSM and by skipping to convert a specific pattern to an AST and generate NFSM and DFSM steps instead of specific patterns.

In some embodiments, the input code or output code may include a binary assembly executable by a processor.

In some embodiments, the input code 105 or output code 160 may be written in an HDL (such as SystemC, Verilog, and Very High Speed Integrated Circuit Hardware Description Language (VHDL)). The input code 105 or output code 160 may contain bits native to an FPGA that is programmed using the Joint Test Action Group (JTAG) standard. In a particular embodiment, a constraint solver can be used to optimize the DFSM 135. The constraint solver may contain some requirements for a hardware platform described by HDL. For example, requirements may include requirements for the runtime, power usage, and cost of one of the hardware platforms. One of the limitations that can be optimized to meet DFSM 135 requirements. In a particular embodiment, optimization of the DFSM may be performed to satisfy several required constraints using the weights assigned to each of the constraints. In some embodiments, the DFSM 135 may be formally verified according to a formal specification to detect software related security vulnerabilities, including but not limited to memory leaks, division by zero, out-of-bounds array access, and the like.

In a specific embodiment, the input source can be written according to a technical specification. An exemplary technical specification may include a request for comment (RFC). In some embodiments, a technical specification may be associated with a particular grammar. Using specific grammars, input codes written in accordance with technical specifications can be translated into AST 115 and further into DFSM 135. In some embodiments, a constraint solver may be used to optimize the DFSM 135. Constraint solvers can contain the restrictions described in the technical specifications.

FIG. 2 is a block diagram illustrating an exemplary system 200 for processing HTTP requests according to an example embodiment. The system 200 may include a client 210, a system 100 for compiling source code, and an FPGA 240.

In a particular embodiment, the system 100 may be configured to receive one of the Internet Protocol (IP), Transmission Control Protocol (TCP), and HTTP RFC 105. System 100 can be configured to program the RFC into a VHDL code, and then compile the VHDT code into bit 235 native to FPGA 240. FPGA 240 can be programmed with bit 235. In an example shown in FIG. 2, the FPGA 240 includes a finite state machine (FSM) 225 corresponding to the bit 235. In other embodiments, bit 235 may be stored in a flash memory, and FPGA 240 may be configured to request bit 235 from flash memory after startup.

In some embodiments, the client 210 may be configured to send an HTTP request 215 to the FPGA 240. In some embodiments, the HTTP request 215 can be read by the FPGA 240. The FSM 225 may be configured to recognize the HTTP request 215 and return an HTTP response 245 corresponding to one of the HTTP requests 215 to the client 210. In a particular embodiment, the FPGA 240 may include one of the FSMs 250 to 260 to maintain application logic for identifying clients with different HTTP requests and providing different HTTP responses.

The system 200 can be an improvement over one of the conventional HTTP servers because the system 200 does not require a large amount of computing resources and maintenance of software that handles HTTP requests. The system does not need to be physically larger and requires a smaller amount of power compared to conventional HTTP servers.

FIG. 3 shows a flowchart of a method 300 for compiling source code according to an example embodiment. The method 300 may be implemented using a computer system. An exemplary computer system is described below with reference to FIG. 4.

The method 300 may begin at block 302 by obtaining a first code, which is written in a first language. In block 304, the method 300 may include parsing the first code based on a first grammar associated with the first language to obtain a first AST. In block 306, the method 300 may include converting the first AST to an NFSM. In block 308, the method 300 may include converting the first NFSM to a first DFSM. In block 310, the method 300 may include optimizing the first DFSM to obtain a second DFSM. In block 312, the method may include converting the second DFSM to a second NFSM. In block 314, the method 300 may include converting the second NFSM to a second AST. In block 316, the method 300 may include recompiling the AST into a second code based on a second grammar associated with a second language, the second code being written in the second language.

FIG. 4 shows a diagram of a computing device for a machine in the exemplary electronic form of a computer system 400 within which one or more of the methodologies discussed herein can be executed An instruction set. In various exemplary embodiments, the machine operates as a stand-alone device or can be connected (eg, a network link) to other machines. In a network deployment, the machine can operate as a server or a client machine in a server-client network environment, or as a peer in a peer-to-peer (or decentralized) network environment machine. The machine may be a server, a personal computer (PC), a tablet PC, a set-top box (STB), a PDA, a cellular phone, a digital camera, a portable music player (e.g., a Portable hard disk audio devices, such as an animation expert group audio layer 3 (MP3) player), a network appliance, a network router, a switch, a bridge, or one of those capable of performing the actions specified by the machine An instruction set (sequential or otherwise) for any machine. In addition, although only a single machine is shown, the term "machine" should also be considered to include one or more instruction sets executed individually or jointly to perform any one or more of the methodologies discussed herein. Any machine collection.

The exemplary computer system 400 includes a processor or processors 402, a hard disk drive 404, a main memory 406, and a static memory 408, which communicate with each other via a bus 410. The computer system 400 may also include a network interface device 412. The hard drive 404 may include a computer-readable storage medium 420 that stores one or more sets of instructions 422 that embody or are utilized by any one or more of the methodologies or functions described herein. The instructions 422 may also reside entirely or at least partially within the main memory 406 and / or the processor 402 during execution by the computer system 400. The main memory 406 and the processor 402 also constitute a machine-readable medium.

Although the computer-readable medium 420 is shown as a single medium in an exemplary embodiment, the term "computer-readable medium" should be considered to include a single medium or multiple media storing one or more instruction sets (e.g., , A centralized or decentralized database and / or associated caches and servers). The term "computer-readable medium" should also be considered to include any one or more of the methodologies capable of storing, encoding, or carrying an instruction set for execution by a machine and causing the machine to execute this application, or capable of storing, encoding, or carrying Send any medium of a data structure utilized by or associated with this instruction set. The term "computer-readable medium" should therefore be considered to include, but not be limited to, solid-state memory and optical and magnetic media. These media may also include, but are not limited to, hard drives, floppy drives, NAND or NOR flash memory, digital video discs, RAM, ROM, and the like.

The exemplary embodiments described herein may be implemented in an operating environment including computer-executable instructions (eg, software) installed on a computer, in hardware, or in a combination of software and hardware. Computer-executable instructions can be written in a computer programming language or embodied in firmware logic. If written in a programming language that meets one of the accepted standards, these instructions can be executed on multiple hardware platforms and used to interface with multiple operating systems. Although not limited to this, the computer software program used to implement the method may be any number of suitable programming languages such as, for example, C, Python, Javascript, Go, or other compilers, translators, interpreters Or other computer languages or platforms).

FIG. 5 shows a block diagram of an exemplary system 500 for mapping a computer code to lines and gates according to some example embodiments. The exemplary system 500 may include a parsing presentation grammar (PEG) module 110, a converter 120 that converts between AST and NFSM, a converter 130 that converts between NFSM and DFSM, an optimizer 140, and Translator 510 that translates from DFSM to lines and gates. The system 500 can be implemented with a computer system. An example computer system is described above with reference to FIG. 4.

The PEG module 110, the converter 120, the converter 130, and the optimizer 140 are described above with respect to the system 100 of FIG. The PEG module 110 can receive an input code 105 written in an input programming language. The input programming language may be associated with a grammar 170. The PEG module can be configured to convert the input code 105 into an AST 115. The converter 120 further converts the AST 115 into an NFSM 125. The converter 130 may be configured to translate the NFSM 125 into a DFSM 135. The optimizer 140 may further optimize the DFSM 135 to obtain a DFSM 145, which is optimized by the DFSM 135.

In some embodiments, the DFSM 145 may be further provided to the translator 510. The translator 510 may be configured to translate the optimized DFSM 145 into a set of lines and gates 520. The edges of DFSM 145 can be represented as lines. State can be expressed as a combination of lines or a simple gate. This set of lines and gates 520 can be used to match inputs, internal states and outputs. This set of lines and gates 520 can also be used to design, program, or configure integrated circuits (such as but not limited to FPGAs and ACIS). For example, this set of lines and gates 520 can be used to configure the programmable logic blocks of FPGA 240 and reconfigurable reconnections (shown in Figure 2) to handle HTTP requests.

Integrated circuits (eg, FPGAs) can receive packets via a network. The packet may include an Ethernet packet, an Optical Transport Network (OTN) packet, a Peripheral Component Interconnect Express (PCIE) packet, or the like. The packet contains a set of ordered inputs with a defined beginning, a number of input symbols, and an end according to time. For example, a packet may include a leading start frame delimiter, a header, protocol-specific data, and a cyclic redundancy check. The FPGA can be configured to perform operations contained in the initial computer code on a line and gate basis. For example, the FPGA may be configured to send a reply to a received data packet. In another example, the FPGA can be configured to match or filter data packets, forward data packets, or store data packets in the FPGA. In yet another example, the FPGA may be reconfigured based on the information contained in the received data packet.

Depending on a data transfer protocol, the data in the packet is timed at a specific rate. For each clock, only a specific input block of a data packet can be received by an FPGA, so that only a specific number of lines can be used in the FPGA. There is a strong correlation between the number of bits in the input and the number of corresponding lines and gates. For the same computer code, a larger number of bits in the input requires fewer gates and lines. If the length of a data packet is measured as the number of symbols in the packet, there is a linear dependency between the length of the packet and the number of gates and lines. The number of symbols in a packet is inversely related to the number of bits in the input. For example, using one-hot encoding, an 8-bit input and 256 individual lines can represent one of the possible 0-255 numbers of the input. If the data in the packet is transmitted through a Gigabit Media Independent Interface (GMII) interface, each input block is a single 8-bit / 8-line input at each clock cycle.

When using one-hot coding and 84 states, a single line for each state can represent a symbol from 0 to 83. Transitioning from one state to another can occur when 0 or 1 possible input matches each state. When the input fails to match the entire pattern, the state does not advance. Assuming there are only 84 possible states and 0 or 1 possible inputs per state, a maximum of 84 of the 256 individual lines can be used. In practice, the same input value can be used multiple times. For example, 0x55 may appear 7 times at the beginning of a packet. Because one input line can be used multiple times and because, for example, there is a state with 0 possible inputs in the packet ID field, the number of unique input lines used tends to be small. For common cases, the number of unique input lines can be 20 lines or less.

In the states arranged in parallel, a single 8-bit symbol or unsigned is matched by combining the signal from the line or the beginning of the packet from the previous state with the line corresponding to the input sign or unsigned. Each state can be expressed as one of the following:

1.

2. . No input is required or any of the cases when the input is acceptable.

3.

4. . No input is required or any of the cases are acceptable.

In a general case, May be the zeroth state, which causes the initial first state. For any of these inputs to be acceptable, there are no input lines to look for. Multiple states that do not look for input lines can be implemented as a shift register. Any state that is not stored in a flip-flop can be stored in a shift register because these states are not individually accessed.

In the case where the data in the packet is transmitted via a Gigabit Media Independent Interface (XGMII) interface, each symbol can be represented as 32 bits at each transition of a clock. When using a one-hot coding representation, the maximum number of lines representing all possible 32-bit symbols exceeds 4 billion lines. However, the length of the data packet is the same as in the case of a GMII interface. Assumed to exist only Possible state and an input symbol size is 4 times that in the GMII interface, the number of lines is limited to the packet's symbol count length, a minimum size of 84 bytes or 1/4 as a 32-bit symbol, 64 bits 1/8 of the symbol. Due to redundancy, there may be a smaller number.

Similar considerations can be used when using higher speed / symbol size inputs (such as in transmission protocols with rates of 25 MHz, 125 MHz, 156.25 MHz, 644.53125 MHz, 1.5625 GHz, etc.). In general, as the width of an input increases, the number of gates decreases.

When multiple similar packets match, the decision can form a tree. Share the earlier state in the tree. Each unique type of a packet to be matched requires at least one additional gate to uniquely match packets and gates and match the maximum number of states that are not shared with other similar types of packets. In general, when the number of packet matching rules exceeds one hundred, as few as one or two additional gates are required to match a packet. In most cases, each additional matching rule requires only 1 additional gate.

FIG. 6 is a flowchart illustrating a method 600 for mapping a computer code to a line and a gate according to some example embodiments. The method 600 may be implemented using a computer system. An exemplary computer system is described above with reference to FIG. 4.

The method 600 may begin at block 602 with obtaining a code. The code can be written in a programming language. The programming language may be a high-level programming language such as, for example, JavaScript, C, C ++, domain-specific languages, and the like. The code can be written according to a technical specification. An exemplary technical specification may include an RFC.

In block 604, the method 600 may generate an FSM based on the code. At block 606, the method 600 may continue based on the FSM generating a line and gate representation. The line and gate representation can include multiple lines and multiple combinational logic. An input of each of the plurality of lines may represent a symbol from a group of symbols in a structured data packet. The size of the symbol may be equal to the number of bits of a structured data packet transmitted per clock cycle according to a data transmission protocol. The packet can include an Ethernet packet, an OTN packet, or a PCIE packet. The data transfer protocol may include a GMII, XGMII, and so on. If the individual states from the flip-flop are not directly needed, the states resulting from the combinational logic can be stored in the flip-flop or alternatively in the shift register.

In block 608, the method 600 may include configuring a field programmable gate array based on the line and gate representations. Combinational logic that can be implemented in a shift register and does not depend on inputs from multiple lines. Other combinational logic can be stored in the flip-flop.

Therefore, a system and method for mapping a computer code to a line and a gate are disclosed. Although the embodiments have been described with respect to specific example embodiments, it will be apparent that various modifications and changes can be made to these example embodiments without departing from the broader spirit and scope of this application. Accordingly, the description and drawings are to be regarded as illustrative rather than restrictive.

100‧‧‧ system

105‧‧‧Input Code / Request for Comments (RFC)

110‧‧‧Analysis of Expression Grammar (PEG) Module

115‧‧‧Abstract Syntax Tree (AST)

120‧‧‧ converter

125‧‧‧Uncertain Finite State Machine (NFSM)

130‧‧‧ converter

135‧‧‧Deterministic Finite State Machine (DFSM)

140‧‧‧ Optimizer

145‧‧‧Deterministic Finite State Machine (DFSM)

150‧‧‧Uncertain Finite State Machine (NFSM)

155‧‧‧Abstract Syntax Tree (AST)

160‧‧‧Output code

170‧‧‧ Grammar

180‧‧‧ Grammar

200‧‧‧ system

210‧‧‧Client

215‧‧‧ Hyper File Transfer Protocol (HTTP) request

225‧‧‧Finite State Machine (FSM)

235‧‧‧bit

240‧‧‧ Field Programmable Gate Array (FPGA)

245‧‧‧ Hyper File Transfer Protocol (HTTP) response

250‧‧‧ Finite State Machine (FSM)

260‧‧‧Finite State Machine (FSM)

300‧‧‧ Method

302‧‧‧block

304‧‧‧box

306‧‧‧block

308‧‧‧box

310‧‧‧block

312‧‧‧block

314‧‧‧block

316‧‧‧block

400‧‧‧Computer System

402‧‧‧Processor

404‧‧‧HDD

406‧‧‧Main memory

408‧‧‧Static memory

410‧‧‧Bus

412‧‧‧ network interface device

420‧‧‧Computer-readable storage media

422‧‧‧Instruction

500‧‧‧ system

510‧‧‧ translator

520‧‧‧One line and gate

600‧‧‧ Method

602‧‧‧box

604‧‧‧box

606‧‧‧block

608‧‧‧box

The embodiments are illustrated by way of example and not limitation in the accompanying drawings, in which the same element symbols indicate similar elements.

FIG. 1 is a block diagram illustrating a system for compiling source code according to some example embodiments.

FIG. 2 is a block diagram illustrating an exemplary system for processing a Hyper File Transfer Protocol (HTTP) request according to an example embodiment.

FIG. 3 is a flowchart illustrating a method for compiling source code according to an example embodiment.

FIG. 4 shows a diagram of a computing device for a machine in an exemplary electronic form of a computer system, within which a machine may be executed to cause the machine to perform any one or more of the methodologies discussed herein. An instruction set.

FIG. 5 shows a block diagram of a system for mapping a computer code to a line and a gate according to some example embodiments.

FIG. 6 is a flowchart illustrating a method for mapping a computer code to a line and a gate according to an example embodiment.

Claims (20)

A computer-implemented method for configuring at least one integrated circuit by mapping a computer code to a line and a gate. The method includes: Obtaining a first code, which is written in a first language; Parsing the first code through one or more parsing expression grammar (PEG) modules based on a first grammar associated with the first language to convert the first code into a first abstract syntax tree ( AST); Transforming the first AST into a first uncertain finite state machine (NFSM); Converting the first NFSM into a first deterministic finite state machine (DFSM); Optimizing the first DFSM to obtain a second DFSM; Converting the second DFSM into a second code through at least the one or more PEG modules, the second code is written in a second language, wherein the second code is one of the first codes Translation Generating a line and gate representation based on the second DFSM, the line and gate representation including a plurality of lines and a plurality of combinational logic; and Configure at least one integrated circuit based on the line and gate representation. The method of claim 1, wherein the at least one integrated circuit includes a field programmable gate array or an application-specific integrated circuit. The method of claim 2, further comprising: Determine that one or more combinational logics of the plurality of combinational logics are not dependent on an input from a line of the plurality of lines; and In response to the determination, the one or more combinational logics are stored in a shift register. The method of claim 2, further comprising: Determining one or more combinational logics of the plurality of combinational logics is dependent on an input from a line of the plurality of lines; and In response to the determination, the one or more combinational logics are stored in a flip-flop. The method of claim 1, wherein the input of each of the plurality of lines represents a symbol from a group of symbols of a structured data packet, and the size of one of the symbols is equal to that transmitted according to a data transmission protocol every clock cycle. The number of bits in the structured data packet. The method of claim 5, wherein the number of gates and the number of gates in the line and gate representation are optimized based on a transmission protocol rate or a structure of the structured data packet. The method of claim 5, wherein the structured data packet includes an Ethernet packet, an optical transport network packet, or a peripheral component fast interconnect packet. The method of claim 1, wherein the first language includes a high-level programming language. The method of claim 1, further comprising optimizing the first DFSM before generating the line and gate representation. The method of claim 9, wherein optimizing the first DFSM includes minimizing a number of states in a finite state machine. A system for configuring at least one integrated circuit by mapping a computer code to a line and a gate. The system includes: At least one processor; and A memory communicatively coupled to the at least one processor, the memory storing instructions, the instructions executing a method when executed by the at least one processor, the method comprising: Obtaining a first code, which is written in a first language; Parsing the first code through one or more parsing expression grammar (PEG) modules based on a first grammar associated with the first language to convert the first code into a first abstract syntax tree ( AST); Transforming the first AST into a first uncertain finite state machine (NFSM); Converting the first NFSM into a first deterministic finite state machine (DFSM); Optimizing the first DFSM to obtain a second DFSM; Converting the second DFSM into a second code through at least the one or more PEG modules, the second code is written in a second language, wherein the second code is one of the first codes Translation Generating a line and gate representation based on the second DFSM, the line and gate representation including a plurality of lines and a plurality of combinational logic; and An integrated circuit is configured based on the line and the gate representation. The system of claim 11, wherein the at least one integrated circuit comprises a programmable gate array or an application-specific integrated circuit. The system of claim 12, wherein the at least one processor is configured to: Determine that one or more combinational logics of the plurality of combinational logics are not dependent on an input from a line of the plurality of lines; and In response to the determination, the one or more combinational logics are stored in a shift register. The system of claim 12, wherein the at least one processor is configured to: Determining one or more combinational logics of the plurality of combinational logics is dependent on an input from a line of the plurality of lines; and In response to the determination, the one or more combinational logics are stored in a flip-flop. If the system of claim 11, wherein one of each of the plurality of lines enters a symbol selected from a group of symbols of a structured data packet, and the size of one of the symbols is equal to one clock cycle according to a data transmission protocol The number of bits of the structured data packet transmitted. The system of claim 15, wherein the number of gates and the number of lines in the line and gate representation are optimized based on a transmission protocol rate or a structure of the structured data packet. The system of claim 15, wherein the structured data packet includes an Ethernet packet, an optical transport network packet, or a peripheral component fast interconnect packet. The system of claim 11, wherein the first language is a high-level programming language. The system of claim 11, wherein the at least one processor is configured to optimize the first DFSM before generating the line and gate representation. A non-transitory computer-readable storage medium on which existing instructions are executed which, when executed by one or more processors, are used to configure at least one product by mapping a computer code to a line and a gate. One method of the body circuit, the method includes: Obtaining a first code, which is written in a first language; Parsing the first code through one or more parsing expression grammar (PEG) modules based on a first grammar associated with the first language to convert the first code into a first abstract syntax tree ( AST); Transforming the first AST into a first uncertain finite state machine (NFSM); Converting the first NFSM into a first deterministic finite state machine (DFSM); Optimizing the first DFSM to obtain a second DFSM; Converting the second DFSM into a second code through at least the one or more PEG modules, the second code is written in a second language, wherein the second code is one of the first codes Translation Generating a line and gate representation based on the second DFSM, the line and gate representation including a plurality of lines and a plurality of combinational logic; and Configure at least one integrated circuit based on the line and gate representation.