TW201946171A - Chip for board evaluation and board evaluating apparatus - Google Patents

Abstract

The substrate evaluation device (1) is a test for evaluating the thermal characteristics of the ceramic wiring board (30) in a state where the simulated heating chip (40) is mounted on the surface of a ceramic wiring board (30) capable of mounting power semiconductors. The substrate evaluation device (1) is provided with a load control unit (10), which is provided to apply a load via a plurality of electrode pad bonding patterns (34ep) to press the ceramic wiring substrate (30) against the heat sink (100). A plurality of electrode rods (130); a heating power source (14) for heating the heating pattern (46) of the analog heating chip (40) via any of the plurality of electrode rods (130); and temperature sensing The device (16) is used to measure the surface temperature of the simulated heating chip (40) by using the temperature measurement pattern (48) through any one of the plurality of electrode rods (130), and according to the temperature measurement sensor (16) As a result of the measurement of the measured surface temperature, the thermal characteristics of the ceramic wiring board (30) were evaluated.

Description

   Wafer for substrate evaluation and substrate evaluation device   

The present invention relates to a substrate evaluation wafer and a substrate evaluation device for evaluating thermal resistance characteristics of a ceramic wiring board capable of mounting, for example, a next-generation wide band gap (WBG) power semiconductor.

As a method for evaluating the thermal resistance characteristics and the like of a ceramic wiring board capable of mounting insulation of a power semiconductor, a steady-state thermal resistance measurement method (Japan Electronics Packaging and Circuits Association; JPCA) is known. )) (See Non-Patent Document 1). This steady-state thermal resistance measurement method is a standardization test method for measuring the thermal resistance of a high-luminance light-emitting diode (Light Emitting Diode; LED) electronic circuit board.

    [Prior technical literature]         [Patent Literature]    

Non-Patent Document 1: Test Methods for Electronic Circuit Boards for High-Brightness LEDs

In addition, for power semiconductors such as high-brightness LEDs, some people have proposed the use of insulating substrates such as SiC, GaN, and Ga ₂ O ₃ with good heat resistance. When these power semiconductors are mounted on a mounting substrate to form power modules, heat resistance is required 、 Mounting board with good heat dissipation.

Typical mounting substrates used to mount power semiconductors are known as direct-bonded copper (DBC) substrates, direct-bonded aluminum (DBA) substrates, and active metal bonding (AMB) substrates. Ceramic wiring board.

Until now, ceramic wiring boards have mainly used alumina (Al ₂ O ₃ ) as the ceramic material, but aluminum nitride (AlN) with higher thermal conductivity and silicon nitride (Si ₃ N) with higher toughness have been used. ₄ ) It also attracted much attention.

Such a ceramic wiring board has thermal resistance at the bonding interface and is subject to the effects of thermal expansion and stress due to temperature changes. Therefore, evaluation of the thermal characteristics of the entire substrate becomes important. In particular, there is an urgent need to establish a standard method capable of accurately evaluating the thermal characteristics of a state close to the state of a power module on which a power semiconductor is mounted.

The present invention was made in view of the above-mentioned circumstances, and an object thereof is to provide a substrate evaluation wafer and a substrate evaluation device that can be easily standardized, to make the substrate evaluation wafer generate heat as uniformly as possible, and to measure the mounting substrate more accurately Temperature, the thermal characteristics of the mounting substrate can be accurately evaluated.

In order to achieve the above object, a first aspect of the present invention is a wafer for substrate evaluation, which is a test required for evaluating the thermal characteristics of a mounting substrate on which a power semiconductor can be mounted. The wafer for substrate evaluation includes an insulating substrate. The substrate is bonded to the mounting substrate; and the pattern for heating is formed on the surface of the insulating substrate using a metal film, and is arranged to have a predetermined shape optimized for uniformly heating the insulating substrate. The wafer for substrate evaluation preferably further includes a pattern for temperature measurement, which is formed on the surface of the insulating substrate by a metal film, and is used to measure the temperature of the insulating substrate heated by the heating pattern.

According to the first aspect of the present invention, not only the next-generation power semiconductor is simulated, but also a wafer for substrate evaluation that is specialized in heat generation control and temperature measurement can be realized. That is, since the wafer for substrate evaluation can be heated approximately uniformly by the heating pattern, the rising temperature of the insulating substrate can be measured more accurately. Therefore, the method is not limited to an actual power module, and the thermal characteristics of the mounting substrate can be evaluated with high accuracy, and a standard for evaluation can be easily established.

The insulating substrate preferably has a thermal conductivity of 250 W / mK or more.

In this way, almost all the heat generated by the heat can be efficiently conducted to the mounting substrate mounted on the substrate evaluation wafer.

The insulating substrate is preferably a substrate having an insulating film formed on a surface of a SiC-based single crystal substrate.

As described above, even when the insulating substrate is assumed to be an non-essential semiconductor (SiC single crystal substrate), the insulating film is formed on the surface, so that the withstand voltage of the insulating substrate can be easily ensured.

The mounting substrate is preferably a ceramic wiring substrate.

This makes it possible to accurately evaluate the thermal resistance of the entire insulating substrate.

In addition, a second aspect of the present invention is a substrate evaluation device for performing a test for evaluating the thermal characteristics of the mounting substrate in a state where the wafer for substrate evaluation is mounted on a surface of a mounting substrate on which a power semiconductor can be mounted. This substrate evaluation device includes a substrate evaluation wafer, which includes an insulating substrate bonded to a mounting substrate, is formed on the surface of the insulating substrate with a metal film, and is formed to have an optimized substrate for uniform heating of the insulating substrate. A heating pattern having a predetermined shape and a temperature measurement pattern formed on the surface of the insulating substrate by a metal film and used to measure the temperature of the insulating substrate heated by the heating pattern. The mounting substrate includes: A pattern for bonding wafers and a plurality of patterns for bonding electrode pads to which the respective electrode pads for heating patterns and temperature measurement patterns are connected; a cooling section for cooling the mounting substrate; and a load applying section for passing through a plurality of The electrode pad bonding pattern presses the mounting substrate against a plurality of terminal electrodes in the cooling section; the heating section is a The heating pattern of the substrate evaluation wafer is heated through any one of the plurality of terminal electrodes, thereby increasing the temperature of the insulating substrate of the substrate evaluation wafer; and the measurement unit is configured to pass any one of the plurality of terminal electrodes. The temperature of the insulating substrate was measured using the temperature measurement pattern of the substrate evaluation wafer, and the thermal characteristics of the mounting substrate were evaluated based on the measurement results of the measurement unit.

According to the second aspect of the present invention, in a state where the wafer for substrate evaluation is mounted on the surface of a mounting substrate on which power semiconductors can be mounted, the mounting substrate can be pressed against the cooling portion controlled to a constant temperature by the load application portion to cool it At the same time, the heating pattern is used to heat the heating pattern with high accuracy, and the mounting substrate is heated indirectly. Therefore, the steady-state thermal resistance value can be obtained based on the steady-state power for heating the heating pattern and the rising temperature of the substrate evaluation wafer, thereby accurately evaluating the thermal characteristics of the mounting substrate.

Among the terminal electrodes, it is preferable that the contact portions that are in contact with the plurality of electrode pad bonding patterns of the mounting substrate have a hemispherical shape.

In this way, since the electrical and thermal contact between each terminal electrode and each electrode pad bonding pattern on the mounting substrate becomes point contact, the accuracy of the evaluation of the thermal characteristics can be improved.

The plurality of terminal electrodes are preferably supported in common by an insulating support member, and the support member preferably includes a load detection section that detects that the mounting substrate is pressed against the cooling section by the load applied by the load application section. Global load.

In this way, since the load against the mounting substrate can be accurately detected, the thermal resistance at the interface between the cooling section and the mounting substrate can be easily controlled.

According to the first aspect and the second aspect of the present invention, it is possible to provide uniform heating of the wafer for substrate evaluation as much as possible, more accurately measure the rising temperature of the mounting substrate, and accurately evaluate the heat of the mounting substrate. Characteristics and a wafer for substrate evaluation and a substrate evaluation device that can be easily standardized.

1‧‧‧ substrate evaluation device

10‧‧‧Load control section (load application section)

12‧‧‧ Cooling device

14‧‧‧Heating Power Supply (Heating Section)

16‧‧‧Temperature sensor (measurement department)

18‧‧‧ load sensor indicator

18a‧‧‧load sensor element (load detection section)

20‧‧‧ Evaluation sample

22‧‧‧Silver Paste

24‧‧‧ Thermal Paste

30‧‧‧Ceramic wiring board (mounting board)

32‧‧‧ceramic plate (thin plate)

34‧‧‧Surface-side electrode pattern

34dp ‧‧‧ Wafer Bonding Pattern

34ep‧‧‧Pattern for electrode pad bonding

36‧‧‧Back side electrode pattern

40‧‧‧Simulated heating wafer (wafer for substrate evaluation)

40A‧‧‧Analog heating chip

42‧‧‧ Insulating substrate

44‧‧‧ insulating film

46‧‧‧Heating pattern (heater pattern)

46A‧‧‧Heating pattern

46B‧‧‧Finished heating pattern

47‧‧‧ fins

48‧‧‧Pattern for temperature measurement (Pattern for probe)

50a, 50b, 52a, 52b ‧‧‧ electrode section (electrode pad)

54, 59‧‧‧ titanium film

55, 57‧‧‧chrome film

56‧‧‧copper film

58‧‧‧Gold Film

60‧‧‧Silver film

100‧‧‧ heat sink (cooling section)

102‧‧‧Circular Road

104‧‧‧ Pillar

106, 114, 136‧‧‧ Nuts

110‧‧‧ support board

112‧‧‧through hole

120‧‧‧Metal plate (rigid body)

122‧‧‧ opening

130‧‧‧ electrode rod (terminal electrode)

132‧‧‧ abutment department

134‧‧‧Double nut

140‧‧‧ Support rigid body (supporting member)

150‧‧‧Screw

152‧‧‧Mounting Department

154‧‧‧Handle

BW‧‧‧conductor (gold wire)

Q‧‧‧ Steady Power

Rcalc‧‧‧Thermal resistance (calculated value)

Rth‧‧‧Thermal resistance

△ T‧‧‧Rising temperature

Md‧‧‧Arrow

Hd‧‧‧Heat density

Fig. 1 (a) is a schematic plan view showing a configuration example of a substrate evaluation device according to the embodiment, and Fig. 1 (b) is a schematic cross-sectional view taken along line a1-a1 of Fig. 1 (a).

Fig. 2 is an enlarged view of a main part of a measurement system of the substrate evaluation device shown in Fig. 1 (b).

FIG. 3 is a perspective view of an evaluation sample used in the substrate evaluation device of the embodiment.

Figures 4 (a) to (d) are perspective views showing an example of a mounting substrate for a sample for evaluation.

Fig. 5 is a perspective view showing the outline of a simulated heating wafer as a wafer for substrate evaluation in the embodiment.

Fig. 6 (a) is a schematic plan view of the simulated heating chip shown in Fig. 5, and Fig. 6 (b) is a schematic cross-sectional view taken along line b1-b1 of Fig. 6 (a), and Fig. 6 ( c) A schematic sectional view taken along line b2-b2 of Fig. 6 (a).

(A) and (b) of FIG. 7 are figures which show an example of the simulated heat generating wafer shown in FIG.

Fig. 8 is a perspective view schematically showing a configuration of a pseudo heat generating wafer of a comparative example.

Fig. 9 (a) is a graph showing a simulation result showing the relationship between the thermal resistance of the simulated heating chip and the probe temperature of the embodiment, and Fig. 9 (b) is the thermal resistance and probe of the simulated heating chip 40A of the comparative example A graph of the simulation results of the relationship of temperature.

Fig. 10 is a graph showing the relationship between the thermal resistance and the calculated thermal resistance (calculated value) for the characteristics of the simulated heating chip of the embodiment and the simulated heating chip of the comparative example.

FIG. 11 is a schematic diagram showing a configuration example of a heating pattern with fins.

Fig. 12 (a) is a temperature distribution diagram of the upper surface side and the lower surface side of the simulated heating wafer in which the heating pattern of the embodiment is arranged, and Fig. 12 (b) is provided with the finned heating of Fig. 11 The temperature distribution diagrams of the upper and lower surface sides of the heat-generating wafer are simulated using a pattern.

Hereinafter, embodiments will be described using drawings.

(Configuration of the substrate evaluation device 1)

Fig. 1 (a) is a schematic plan view showing a configuration example of the substrate evaluation device 1 of the embodiment, and Fig. 1 (b) is a schematic cross-sectional view taken along line a1-a1 of Fig. 1 (a).

The substrate evaluation apparatus 1 of the embodiment is a test for evaluating the thermal characteristics of the mounting substrate 30 by using an evaluation sample 20 on which the wafer 40 for substrate evaluation is mounted on the surface of the mounting substrate 30. The mounting substrate 30 is, for example, Substrates for next-generation WBG power semiconductors, such as electronic circuit boards for brightness LEDs. The substrate evaluation device 1 includes a load control section (sample holding section) 10 as a load application section, a cooling device 12, a heating power source 14 as a heating section, and a temperature sensor 16 as a measurement section. The details of the evaluation sample 20 will be described later.

The load control unit 10 includes, for example, a water-cooled heat sink (cooling unit) 100 for cooling the evaluation sample 20. The heat sink 100 is a cold plate having a circulation path 102, and a refrigerant (cooling water) controlled to a predetermined temperature by the cooling device 12 is circulated in the circulation path 102. As the cooling device 12, a device having a sufficient cooling capacity (for example, 250 W, 5.4 L / min) with respect to the heat generation amount of the evaluation sample 20 to be described later can be used.

The heat sink 100 is provided with a plurality of pillars 104, and the plurality of pillars (eight in the embodiment) are arranged around the evaluation sample 20 at approximately regular intervals. With these eight pillars 104, an insulating (for example, acrylic) support plate 110 is supported above the evaluation sample 20. The support plate 110 is fixed to each pillar 104 by a nut 106.

A metal plate (rigid body) 120 may be provided on the support plate 110. The metal plate 120 has an opening portion 122 for avoiding the electrode rod (terminal electrode) 130 and the screw 150 for load control, and is fixed to each pillar 104 by a nut 106. The metal plate 120 is used to prevent the support plate 110 from being deformed (bent) due to the stress applied to the rigid body 140 by the screw 150. Therefore, when the support plate 110 has sufficient rigidity, the metal plate 120 may be omitted. .

The support plate 110 is embedded with a nut 114 near the center portion thereof, and the screw 150 is supported by the nut 114. That is, the screw 150 is supported to rotate up and down relative to the support plate 110.

A load sensor element 18 a serving as a load detection portion is mounted on the lower end portion of the front end side of the screw 150. In addition, an insulating (for example, acrylic) supporting rigid body 140 is attached as a supporting member via the load sensor element 18 a. In addition, a plurality of (four in the embodiment) electrode rods 130 are fixedly supported by the supporting rigid body 140 in common.

The load sensor element 18a is, for example, an ultra-compact compression type load cell. The load sensor element 18a is connected to a load sensor indicator 18 (for example, a digital indicator that maintains a peak at a high speed) as a force gauge indicator.

The upper end of the rear end side of the screw 150 is mounted with an operation handle 154 for an operator to operate via a mounting portion 152. That is, when the operation handle 154 is operated by the operator and the screw 150 is rotated in the direction of the arrow Md shown in the figure, a load corresponding to the operation of the operation handle 154 will be applied to the support rigid body 140. The load applied to the supporting rigid body 140 is detected by the load sensor element 18a, and the value is displayed by the load sensor indicator 18 so that the operator can see it at a glance.

Each electrode rod 130 is fixed to the support rigid body 140 with the nut 136, for example, in a state penetrating the support rigid body 140. In addition, the rear end side of each electrode rod 130 is inserted into the through hole 112 of the support plate 110. Each electrode rod 130 is provided with a double nut 134 in the vicinity of the upper end portion on the rear end side above the support plate 110 to restrict the downward movement (load) of the electrode rod 130.

A hemispherical abutment portion 132 is provided at the lower end portion of the front end side of each electrode rod 130 as a contact surface with a contact portion with the evaluation sample 20.

As a load is applied to the supporting rigid body 140 by the screw 150, the contact portion 132 provided on each electrode rod 130 presses the back side of the evaluation sample 20 against the upper surface of the heat sink 100. At this time, since the abutting portion 132 is formed as a hemispherical curved surface, the area of contact with the flat surface of the evaluation sample 20 is minimized.

In the embodiment, for example, four electrode rods 130 are used as terminal electrodes for pressing the evaluation sample 20 against the heat sink 100 for cooling, and two of them are connected to the heating power source 14 and the remaining two are connected. To the temperature sensor 16.

That is, while the evaluation sample 20 is pressed against the heat sink 100 by the four electrode rods 130, the steady-state power Q for heating the evaluation sample 20 is performed by the two electrode rods 130 connected to the heating power source 14 It is supplied (energized), and the rising temperature of the evaluation sample 20 is measured using two electrode rods 130 (also referred to as temperature measuring probes) connected to the temperature measuring sensor 16.

Fig. 2 is an enlarged view of a main part of the measurement system of the substrate evaluation device 1 shown in Fig. 1 (b).

As shown in FIG. 2, the back side of the evaluation sample 20 (the back side electrode pattern 36 of the ceramic wiring board 30) is disposed on the upper surface of the heat sink 100 with the heat sink paste 24 interposed therebetween, for example. The thermal paste 24 is used as a thermal interface material (TIM), such as a nano-diamond thermal paste, to reduce the interface thermal resistance (Rth) with the thermal base 100.

As shown in FIGS. 2 and 3, the evaluation sample 20 includes a ceramic wiring substrate 30 as a mounting substrate, and a simulated heat-emitting wafer (substrate evaluation) mounted on the surface of the ceramic wiring substrate 30 with, for example, a silver paste 22 for bonding. Wafer) 40 and bonding wires BW (gold wire, etc.).

In the evaluation (test), a predetermined load is applied to the contact portion 132 of the electrode rod 130 to press the ceramic wiring board 30 of the evaluation sample 20 against the heat sink 100, and the simulated heating chip 40 is used as a test. Test Engineering Group (TEG) chips actually drive control. At this time, the simulated heating chip 40 is driven by a predetermined steady-state power Q (Q = I × V) supplied from the self-heating power source 14 to a heating density Hd (also referred to as a load heating amount per load of 200 W / 25 mm ² per unit). Steady-state power Q (W) per unit area (mm ² ).

In the evaluation, the cooling device 12 is used to perform constant temperature control to control the temperature of the heat sink 100 to a predetermined temperature (for example, 25 ° C.).

(Details of Evaluation Sample 20)

As shown in FIGS. 2 and 3, the sample 20 for evaluation of the embodiment is provided with a ceramic wiring board 30 and a pseudo heating chip 40 mounted on the surface of the ceramic wiring board 30.

In the evaluation sample 20, the ceramic wiring substrate 30 is, for example, a DBC (Direct Bonded Copper) substrate capable of mounting a next-generation WBG power semiconductor, and includes a ceramic thin plate 32 (hereinafter also referred to as a ceramic plate) and a ceramic plate 32 A front-side electrode pattern 34 on one side (front surface) of the rear surface and a back-side electrode pattern 36 formed on the other side (back surface) of the ceramic plate 32.

The ceramic plate 32 is made of, for example, Si ₃ N ₄ , AlN, Al ₂ O _3, or the like.

The front-side electrode pattern 34 is made of a copper thin film, and includes a wafer bonding pattern 34dp (also referred to as a pedestal) to which the simulated heating wafer 40 is bonded, and abutting portions 132 of each electrode rod 130 to abut, and Gold wire BW wire bonding electrode pad bonding pattern 34ep.

As shown in FIG. 4 (a), for example, the surface-side electrode pattern 34 can be arranged on the central portion of the ceramic plate 32 with a wafer size of approximately 34 dp, and the four electrode pad bonding patterns 34 ep can be arranged on the ceramic plate. The corners of the peripheral portions other than the central portion of 32.

That is, as shown in FIG. 3, for example, the evaluation sample 20 is used to bond the simulated heat-generating wafer 40 to the wafer bonding pattern 34dp with the silver paste 22. In addition, each electrode pad bonding pattern 34ep is connected to each electrode portion (electrode pad) 50a, 50b, 52a, 52b of the analog heating chip 40 through a gold wire BW, and is provided with a contact portion 132 of a certain electrode rod 130 Abut.

In the sample 20 for evaluation in the embodiment, the size of the ceramic wiring board 30 is approximately 30 mm × 30 mm, the size of the pseudo heating chip 40 is approximately 5 mm × 5 mm, and the thickness of the pseudo heating chip 40 is approximately 0.33 mm.

In addition, each gold wire BW is displayed as a single line for the convenience of display. However, in order to withstand a large current during heat generation, a plurality of (for example, ten) wires may be connected to disperse the current.

In addition, in the sample 20 for evaluation of the embodiment, the influence of the thermal flow path in the ceramic wiring substrate 30 that changes depending on the pattern shape of the front-side electrode pattern 34 is taken into consideration as shown in Figs. 4 (a) to (d). The most suitable design is adopted among the plurality of ceramic wiring boards 30 having different pattern shapes (designs) of the surface-side electrode patterns 34 shown.

That is, in consideration of the influence of the thermal flow path in the ceramic wiring substrate 30 which is thought to change depending on the pattern shape of the front-side electrode pattern 34, for example, a configuration having a cross shape as shown in FIG. 4 (b) may be adopted. A wafer bonding pattern 34dp on the central portion of the ceramic plate 32 having a size substantially the same as that of the ceramic plate 32; and four electrode pad bonding patterns 34ep arranged on the corners of the peripheral portions other than the central portion on the front side Electrode pattern 34.

Alternatively, as shown in Figs. 4 (c) and 4 (d), one wafer bonding pattern 34dp may be arranged on the central portion of the ceramic plate 32, and four electrode pad bondings may be arranged on the peripheral portion surrounding the central portion. The pattern-side electrode pattern 34 is a plurality of patterns of the pattern 34ep.

In FIGS. 4 (a) to (d), illustration of the back-side electrode pattern 36 is omitted. Furthermore, a case where four electrode pad bonding patterns 34ep are arranged for the number of electrode rods 130 of “4” is exemplified.

The ceramic wiring substrate 30 is not limited to a DBC substrate, and may be, for example, a DBA (Direct Bonded Aluminum) substrate, an AMB (Active Metal Bonding) substrate, or the like.

On the other hand, in the evaluation sample 20, as shown in FIG. 5, the simulated heat-generating wafer 40 includes, for example, a flat heating pattern (heater pattern) formed of a metal film such as a platinum film on the surface of the insulating substrate 42 ) 46 and temperature measurement pattern (probe pattern) 48. In addition, each electrode portion 50a, 50b of the heating pattern 46 and each electrode portion 52a, 52b of the temperature measurement pattern 48 are provided on the surface of the insulating substrate 42.

The insulating substrate 42 has a thermal conductivity of 250 W / mK or more, and preferably about 400 W / mK, thereby effectively transmitting almost all the heat generated by the heat to the ceramic wiring substrate 30.

The insulating substrate 42 is preferably a SiC-based intrinsic semiconductor (high-quality wafer), but may be an n-doped SiC-based single crystal substrate (for example, an n-doped 4H SiC wafer). By forming an insulating film (for example, an Al ₂ O ₃ film) 44 on the surface portion of the SiC-based single crystal substrate, the withstand voltage of the insulating substrate 42 can be ensured.

That is, as shown in FIGS. 6 (a) to (c), the simulated heating chip 40 of the embodiment includes an insulating substrate 42 composed of an n-doped SiC single crystal substrate; and the insulating substrate 42 surface about 5μm Al ₂ O ₃ film film thickness 44; via a titanium film of approximately 30nm thickness on a surface of 54 Al ₂ O ₃ film 44 and a platinum film of about 200nm film thickness of the heating pattern 46 composed of And temperature measurement patterns 48; electrode portions 50a, 50b formed at both ends of the heating pattern 46; and electrode portions 52a, 52b formed at both ends of the temperature measurement pattern 48. The resistance value of the titanium / platinum film resistor for the heating pattern 46 is set to less than 40Ω (<40Ω), and the resistance value of the titanium / platinum film resistor for the temperature measurement pattern 48 is set to about 50 to 80Ω.

Each of the electrode portions 50a and 50b of the heating pattern 46 and each of the electrode portions 52a and 52b of the temperature measurement pattern 48 are provided with a copper film 56 having a thickness of 1 μm or more via a chromium film 55 having a thickness of about 30 nm, and A gold film 58 having a thickness of about 200 nm is formed on the copper film 56 through a chromium film 57 having a thickness of about 30 nm. In this way, resistance can be reduced, and oxidation at high temperatures can be suppressed.

The back side of the pseudo heating wafer 40 is provided with a silver film 60 having a thickness of about 2 μm via a titanium film 59 having a thickness of about 30 μm below the insulating substrate 42.

The heating pattern 46 is formed in a predetermined shape and size optimized from the viewpoint of thermal resistance measurement as shown in FIGS. 7 (a) and (b) to heat the insulating substrate 42 as uniformly as possible.

That is, the simulated heating chip 40 according to the embodiment is designed to control the steady-state power Q applied to the heating pattern 46 with high accuracy to achieve as high-precision and uniform heating as possible. Curvature, etc.

In particular, when mass production of the evaluation sample 20 is carried out, it is important for the reproducibility of the thermal characteristics that the conditions for film formation of the simulated heat generating wafer 40 be consistent.

On the other hand, the pattern 48 for temperature measurement has a size and shape as shown in Figs. 7 (a) and (b), and is arranged near the center of the simulated heating chip 40, so that the pattern for heating can be measured more accurately. A typical surface temperature of the simulated heat-generating wafer 40 is increased by the heat of 46. Although the measurement is performed indirectly, by accurately measuring the representative surface temperature of the simulated heating chip 40, the rising temperature ΔT (temperature difference) of the insulating substrate 42 can be measured with high accuracy.

In addition, the temperature of the insulating substrate 42 is transmitted to the ceramic wiring substrate 30 and the temperature of the ceramic wiring substrate 30 is increased. Therefore, although the evaluation is performed analogously, since the rising temperature ΔT of the insulating substrate 42 can be measured with high accuracy, it is possible to quantitatively determine the amount of heat and the rising temperature ΔT conducted from the simulated heating wafer 40 to the ceramic wiring substrate 30 due to heat generation The thermal resistance characteristics (steady-state thermal resistance value Rth = ΔT / Q) of the ceramic wiring substrate 30 were evaluated with high accuracy.

The unit of each dimension in Figs. 7 (a) and (b) is mm.

Here, the results obtained by performing a simulation of the temperature distribution and thermal measurement of the Finite Element Method (FEM) on the heating pattern 46 will be described. For example, assuming that the thermal resistance of the ceramic wiring board 30 is 0.615K / W, and the 100W current is applied to the analog heating chip 40, the maximum temperature of the heating pattern 46 is 110 ° C, and the average temperature of the temperature measurement pattern 48 is about 87 ° C. . Based on the average temperature of the temperature measurement pattern 48, the thermal resistance of the ceramic wiring board 30 was 0.67 K / W, and a value close to the assumed thermal resistance value was obtained.

In the embodiment, the silver film 60 on the back side of the simulated heating wafer 40 is bonded to the wafer bonding pattern 34dp of the front-side electrode pattern 34 of the ceramic wiring substrate 30 by the bonding silver paste 22, and each electrode portion 50a, 50b, The gold films 58 of 52a and 52b are connected to each of the electrode pad bonding patterns 34ep of the surface-side electrode pattern 34 of the ceramic wiring board 30 by a gold wire BW. Thereby, the evaluation sample 20 comprised by mounting the pseudo heat generating wafer 40 on the surface of the ceramic wiring board 30 is comprised.

The two electrode rods 130 connected to the heating power source 14 are in contact with the electrode pad bonding patterns 34ep and 34ep connected to the electrode portions 50a and 50b of the heating pattern 46, respectively. The two electrode rods 130 connected to the temperature measurement sensor 16 are in contact with the electrode pad bonding patterns 34ep and 34ep connected to the electrode portions 52a and 52b of the temperature measurement pattern 48, respectively.

During the test, the evaluation sample 20 was placed on the upper surface of the heat sink 100 with the heat dissipation paste 24 interposed therebetween, but the thermal resistance characteristics depended on the interface thermal resistance (Rth) between the evaluation sample 20 and the heat sink 100, so The application state of the thermal paste 24 becomes a factor that causes the thermal resistance characteristics to fluctuate.

In this regard, for example, an appropriate load (up to about 70 N) is applied to the evaluation sample 20 using four electrode rods 130 to stabilize the interface thermal resistance (Rth) with the heat sink 100.

That is, the interface thermal resistance (Rth) is affected by the magnitude of the load when the evaluation sample 20 is pressed against the heat sink 100.

In this regard, an experiment (preliminary test) is performed on the evaluation sample 20 for the embodiment. For example, when the steady-state power Q is fixed at 127 W, and the load is cyclically changed from 5N to 30N, the test is performed. When the load is 25 to 30N The interface thermal resistance (Rth) with the heat sink 100 is the most stable (about 0.61 ~ 0.63K / W).

In addition, by repeating the above-mentioned experiments, it was found that there is a cyclic dependency between the load and the thermal resistance, and that the thermal resistance is more stable when the load is reduced than when the load is increased.

On the other hand, according to experiments, when the load is constant (for example, 30 N) and the steady-state power Q is changed, the interface thermal resistance (Rth) of the evaluation sample 20 and the heat sink 100 increases with the steady-state power Q. And the tendency to converge.

In addition, by repeating the above experiments, it was found that there is a cyclic dependency between steady-state power and thermal resistance.

Furthermore, the test sample 20 for evaluation, in which the load (for example, 30 N) and the voltage value of the steady-state power Q (for example, 80 V) are kept constant, can be repeated, and the measurement temperature of the temperature sensor 16 (for example, T_Pt ℃) has a decisive influence on the interface thermal resistance (Rth) with the heat sink 100.

From the above results, it is inferred that, when the load is large, the influence of the thermal paste 24 on the interface thermal resistance becomes smaller, and the test accuracy is higher.

Further, in the embodiment, for example, if the temperature characteristics of the temperature measurement pattern 48 of the analog heating wafer 40 can be corrected in accordance with the temperature during the evaluation, a more accurate evaluation can be achieved.

(Characteristics of a simulated heating chip)

Here, the characteristics of the simulated heat generating wafer 40 in the evaluation sample 20 of the embodiment will be described.

FIG. 8 is a schematic perspective view showing a configuration example of an analog heating chip 40A for comparison with the evaluation sample 20 of the embodiment.

The shape of the heating pattern 46A of the simulation heating wafer 40A of the comparative example shown in FIG. 8 is different from the shape of the heating pattern 46 of the simulation heating wafer 40 of the embodiment shown in FIG. , So its detailed description is omitted.

That is, the simulated heating wafer 40 according to the embodiment is formed by forming the heating pattern 46 into a predetermined shape that uniformly heats the insulating substrate 42 as much as possible. In contrast, the simulated heating wafer 40A of the comparative example is slightly inferior at this point.

Fig. 9 (a) is a graph showing a simulation result of the relationship between the thermal resistance Rth (K / W) and the probe temperature (° C) of the simulated heating chip 40 of the embodiment, and Fig. 9 (b) is a graph showing a comparative example. A graph of the simulation results of the relationship between the thermal resistance Rth (K / W) of the heating wafer 40A and the probe temperature (° C).

As can be seen from Figs. 9 (a) and (b), the temperature distribution of the simulated heating chip 40 according to the embodiment can be improved compared with the simulated heating chip 40A of the comparative example.

Fig. 10 shows the characteristics of the simulated heating chip 40 of the embodiment and the simulated heating chip 40A of the comparative example. The thermal resistance Rth (K / W) and the calculated thermal resistance (calculated value) Rcalc are calculated as a result of the simulation. (K / W).

It can be seen from FIG. 10 that, compared with the analog heating chip 40A of the comparative example, the simulated heating chip 40 according to the embodiment can more faithfully reproduce a preset exemplary thermal resistance (the one shown by the dotted line in the figure).

That is, the heating pattern 46 of the simulated heating wafer 40 of the embodiment and the heating pattern 46A of the simulated heating wafer 40A of the comparative example are subjected to a simulation of the temperature distribution and thermal measurement by the above-mentioned finite element method (FEM), for example, The heating pattern 46 of the simulation heating chip 40 of the embodiment and the heating pattern 46A of the simulation heating chip 40A of the comparative example were energized at 100 W, so that the thermal resistance of the ceramic wiring board 30 was changed from 0.6 K / W to 2.0 K / W. It can be seen that the simulated heating chip 40 of the embodiment is closer to the original thermal resistance of the ceramic wiring board 30.

In addition, the pattern for heating the simulated heating wafer can be designed in various shapes. FIG. 11 shows an example of a finned heating pattern 46B obtained by adding a plurality of fins 47 to the heating pattern 46A of the analog heating wafer 40A of the comparative example. Adding a plurality of fins 47 allows the heat on the simulated heating wafer to be spread more uniformly.

Figures 12 (a) and (b) show a comparison between the heating pattern 46 (see Figure 7 (b), etc.) of the simulated heating chip 40 of the embodiment and the heating pattern 46B with fins shown in Figure 11 Diagram of the case of uniform heating (for example, steady-state power Q = 200W). Fig. 12 (a) shows the temperature distribution on the upper surface side and the lower surface side of the simulated heating wafer 40 in which the heating pattern 46 of the embodiment is arranged. FIG. 12 (b) shows the temperature distribution on the upper and lower surfaces of the simulated heat-generating wafer in which the finned heating pattern 46B of FIG. 11 is arranged.

It can be seen from FIG. 12 (b) that, compared with the heating pattern 46 of the embodiment without fins, the heating pattern 46B with fins with a plurality of fins 47 can heat the simulated heating chip as a whole. In particular, the entire upper surface side can be heated more uniformly.

Here, a plurality of fins 47 may be added to the heating pattern 46 of the embodiment to form a heating pattern with fins.

(Test for evaluation)

From the above, it can be understood that the test sample 20 for evaluating the thermal characteristics of the ceramic wiring substrate 30 is performed by the substrate evaluation device 1 using the evaluation sample 20 on which the simulated heating chip 40 of the embodiment is mounted, and the stability of the ceramic wiring substrate 30 can be accurately evaluated State thermal resistance.

That is, in the substrate evaluation device 1 according to the embodiment, first, the evaluation sample 20 is placed on the surface of the heat sink 100, and then the operator operates the handle 154. During operation, the load displayed by the load sensor indicator 18 is adjusted by monitoring the load detected by the load sensor element 18a, and a predetermined load (for example, 30 N) is applied to the support rigid body 140. Corresponding to this load, the sample 20 for evaluation is pressed against the heat sink 100 whose constant temperature is controlled to a predetermined temperature (for example, 25 ° C.) by the electrode rod 130.

In this state, the evaluation sample 20 is energized by the heating power source 14 through the two electrode rods 130 connected thereto, with the steady-state power Q (for example, about 200 W) for heating. In response to the energization of the steady-state power Q, for example, the simulated heating chip 40 of the evaluation sample 20 is heated by Joule heat, thereby heating the insulating substrate 42 as the heating pattern 46 generates heat.

Then, when a predetermined time elapses from the start of energization and becomes stable, two electrode rods 130 connected to the pattern 48 for temperature measurement and the temperature sensor 16 are used to measure the temperature in the evaluation sample 20 with the temperature sensor 16. The surface temperature of the simulated heat-generating wafer 40. Thereby, the rising temperature ΔT of the insulating substrate 42 can be measured indirectly.

Here, assuming that the temperature slope (rise temperature) of the ceramic wiring board 30 in the thickness direction in a steady state is ΔT ° C, the thermal resistance Rth (K / W) of the ceramic wiring board 30 can be obtained from the following formula (1) .

Rth = △ T / Q. ． ． (1)

Among them, Q is the amount of heat generated by the simulated heating chip 40, that is, the steady-state power (W) at the time of energization.

As described above, by measuring the rising temperature ΔT of the insulating substrate 42, the steady-state thermal resistance value Rth of the ceramic wiring substrate 30 can be obtained from the rising temperature ΔT and the steady-state power Q.

If the steady-state thermal resistance value Rth is automatically calculated by, for example, a computer (not shown) of the control board evaluation device 1, the ceramic wiring board 30 can be simulated in a state approximately the same as that in the case of actually driving an actual power module. Evaluation of thermal characteristics. As a result, highly accurate evaluation of the thermal characteristics of the ceramic wiring board 30 and establishment of a standard method for the evaluation can be easily achieved.

According to the evaluation sample 20 and the substrate evaluation device 1 according to the embodiment, it is possible to more accurately measure the ceramic wiring substrate by measuring the representative temperature of the surface of the simulated heating wafer 40 while uniformly heating the evaluation sample 20 as much as possible. 30 rising temperature. Therefore, the steady-state thermal resistance characteristics of the ceramic wiring substrate 30 can be accurately evaluated, and the evaluation can be easily standardized.

In particular, in the embodiment, since the load is applied to the evaluation sample 20 via the electrode rod 130 for supplying power and measuring the thermal resistance, the configuration can be simplified and the test for evaluation can be performed with high accuracy.

In addition, the electrical and thermal contact area of the contact portion 132 of each electrode rod 130 with each electrode pad bonding pattern 34ep is minimized. Therefore, a decrease in the accuracy of the temperature measurement can be suppressed, and the accuracy of the evaluation can be improved.

In addition, according to the embodiment, since the load at the time of pressing against the evaluation sample 20 can be accurately detected, the interface thermal resistance Rth of the heat sink 100 and the ceramic wiring substrate 30 can be controlled with high accuracy.

The evaluation sample 20 and the substrate evaluation device 1 according to the embodiment can be applied to tests such as heat dissipation characteristics and thermal shock characteristics of the ceramic wiring substrate 30, and are not limited to tests of steady-state thermal resistance characteristics.

In addition, when it is not necessary to measure the surface temperature of the simulated heating wafer 40 with the temperature measurement pattern 48, the temperature measurement pattern 48 and the electrode portions formed at both ends of the temperature measurement pattern 48 can be omitted from the configuration of the simulated heating wafer 40. 52a, 52b.

Further, in order not to be affected by convection, the periphery may be covered with a cover member (not shown).

The present invention has been described with reference to the embodiments, but the embodiment is only an example. The scope of the invention described in the scope of patent application can be changed in various ways without departing from the spirit of the invention.

Claims (8)

    A wafer for substrate evaluation is used for a test for evaluating thermal characteristics of a mounting substrate on which a power semiconductor can be mounted. The wafer for substrate evaluation includes an insulating substrate that is bonded to the mounting substrate and a pattern for heating that uses a metal. The film is formed on the surface of the insulating substrate, and is arranged to have a predetermined shape optimized to heat the insulating substrate more uniformly.         The wafer for substrate evaluation described in item 1 of the patent application scope further includes a pattern for temperature measurement, which is formed on the surface of the insulating substrate by a metal film, and is used to measure the temperature of the insulating substrate heated by the heating pattern. .         The wafer for substrate evaluation according to item 1 or 2 of the scope of patent application, wherein the insulating substrate has a thermal conductivity of 250 W / mK or more.         The substrate evaluation wafer according to any one of claims 1 to 3, wherein the insulating substrate is a substrate having an insulating film formed on a surface of a SiC single crystal substrate.         The wafer for substrate evaluation according to any one of claims 1 to 4, wherein the mounting substrate is a ceramic wiring substrate.         A substrate evaluation device for conducting a test for evaluating the thermal characteristics of the mounting substrate in a state in which the substrate evaluation wafer is mounted on a surface of a mounting substrate on which a power semiconductor can be mounted. The substrate evaluation device includes: the substrate evaluation. The wafer is provided with an insulating substrate bonded to the mounting substrate, a heating film formed on a surface of the insulating substrate by a metal film, and formed into a predetermined shape optimized to uniformly heat the insulating substrate. A pattern and a temperature measurement pattern formed on the surface of the insulating substrate by a metal film and used to measure the temperature of the insulating substrate heated by the heating pattern; the mounting substrate includes: A pattern for bonding wafers, and a plurality of patterns for bonding electrode pads to which each of the electrode pads for the heating pattern and the temperature measurement pattern are connected; a cooling section for cooling the mounting substrate; and a load applying section for Pressing the mounting substrate through the plurality of electrode pad bonding patterns The plurality of terminal electrodes abutting the cooling section; and the heating section is used to heat the heating pattern of the substrate evaluation wafer through any one of the plurality of terminal electrodes, thereby insulating the insulation of the substrate evaluation wafer. The temperature of the substrate is increased; and the measurement unit is configured to measure the temperature of the insulating substrate by using the temperature measurement pattern of the substrate evaluation wafer through any one of the plurality of terminal electrodes, and to evaluate the temperature based on the measurement result of the measurement unit. Thermal characteristics of the aforementioned mounting substrate.         The substrate evaluation device according to item 6 of the scope of patent application, wherein, in each of the plurality of terminal electrodes, the contact portion that abuts the plurality of electrode pad bonding patterns of the mounting substrate has a hemispherical shape.         The substrate evaluation device according to item 6 or 7 of the scope of patent application, wherein the plurality of terminal electrodes are commonly supported by an insulating support member, and the support member includes a load detection section, and the load detection section is used for The load applied when the load is applied by the load applying section to press the mounting substrate against the cooling section is detected.