TW201933537A - Semiconductor on insulator substrate and method for manufacturing the same - Google Patents

Abstract

Some embodiments of the invention relate to methods of forming a semiconductor substrate on an insulating layer. The method can include epitaxially forming a germanium layer on the sacrificial substrate, and epitaxially forming the first active layer on the germanium layer. The composition of the first active layer is different from the composition of the germanium layer. The sacrificial substrate is flipped over and the first active layer is bonded to the upper surface of the dielectric layer on the first substrate. The sacrificial substrate and the germanium layer are removed and the first active layer is etched to define the outer sidewalls and expose the outer edges of the upper surface of the dielectric layer. Epitaxy forms a second active layer on the first active layer to form a connected active layer. The first active layer and the second active layer have substantially the same composition.

Description

Semiconductor substrate on insulating layer and forming method thereof

Embodiments of the present invention relate to a semiconductor substrate on an insulating layer and a method of forming the same, and more particularly to a single crystal active layer having substantially no misalignment defects in a semiconductor substrate on an insulating layer and a method of forming the same.

The integrated circuit is formed on the semiconductor substrate and is packaged to form a wafer or a microchip. A conventional integrated circuit is formed on a base semiconductor substrate, and the substrate is composed of a semiconductor material such as germanium. In recent years, semiconductor substrates on insulating layers have been chosen as an alternative. The semiconductor substrate on the insulating layer has a thin layer of active semiconductor material (such as germanium) interposed between the underlying processing substrate and an insulating material layer. The layer of insulating material electrically isolates the thin layer of active semiconductor material from the processing substrate to reduce device leakage currents in the active semiconductor material formed in the thin layer. Thin layers of active semiconductor materials can also provide other advantages such as faster switching times, lower operating voltages, and smaller packages.

A method for forming a semiconductor substrate on an insulating layer according to an embodiment of the invention includes: epitaxial forming a germanium layer on a sacrificial substrate; epitaxial forming a first active layer on the germanium layer, and the composition of the first active layer is different a composition of the germanium layer; bonding the first active layer to the dielectric layer on the first substrate; removing the sacrificial substrate and the germanium layer; etching the first active layer to expose the outer side of the upper surface of the dielectric layer And arranging the second active layer on the first active layer to form a connected active layer, wherein the first active layer and the second active layer have substantially the same composition.

A method for forming a semiconductor substrate on an insulating layer according to an embodiment of the invention includes: epitaxially forming a germanium layer on the sacrificial substrate. The epitaxial layer forms a first active layer of the first thickness on the upper surface of the germanium layer, and the first active layer comprises a semiconductor material. The sacrificial substrate is flipped over and the first active layer is bonded to the dielectric layer on the first substrate. The sacrificial substrate and the portion of the germanium layer are removed, and the remaining portion of the germanium layer is left to cover the upper surface of the first active layer. The residual portion of the ruthenium layer and the upper portion of the first active layer are removed. Forming a second active layer on the first active layer, the first active layer and the second active layer have a combined second thickness, and the second thickness is greater than the first thickness.

A semiconductor substrate on an insulating layer according to an embodiment of the invention includes a dielectric layer on a first substrate, wherein an outer edge of the dielectric layer is aligned with an outer edge of the first substrate. The active layer covers the first annular portion of the dielectric layer. And a second annular portion of the upper surface of the dielectric layer surrounding the first annular portion and extending to the outer edge of the dielectric layer. The active layer does not cover the second annular portion.

Thickness of thk, thk ₁ , thk ₂ , 206, 302‧‧

100‧‧‧Semiconductor substrate on insulation

102‧‧‧First substrate

104‧‧‧ dielectric layer

104s, 106s, 108s, 202s, 204s‧‧‧ upper surface

106‧‧‧Active layer

108‧‧‧First active layer

110‧‧‧Second active layer

114‧‧‧Maximum width

116‧‧‧Outer edge width

118‧‧‧First ring section

120‧‧‧second ring part

122‧‧‧lower part

124‧‧‧Upper part

126‧‧‧ crystal face shape

Cutaway view of 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100‧‧

202‧‧‧矽锗

204‧‧‧ Sacrifice substrate

304‧‧‧ Chart

602‧‧‧ upper part

604‧‧‧Remaining layers

702‧‧‧ Thin layer

802‧‧‧ mask layer

1002‧‧‧ semiconductor devices

1004‧‧‧Inline structure

1006‧‧‧Metal interconnect layer

1008‧‧‧Interlayer dielectric structure

1102‧‧‧ grain

1104‧‧‧ cutting line

1200‧‧‧ method

1202, 1204, 1206, 1208, 1210, 1212, 1214, 1216‧ ‧ steps

1A to 1C are cross-sectional views of a semiconductor substrate on an insulating layer in some embodiments of the present invention.

2, 3A-3B, 4-11 are cross-sectional views showing a method of forming a semiconductor substrate on an insulating layer in some embodiments of the present invention.

Figure 12 is a view showing a semiconductor substrate on an insulating layer in some embodiments of the present invention Flow chart of the method.

Different embodiments or examples provided by embodiments of the invention may implement different structures of the invention. The specific components and arrangements of the embodiments are intended to simplify the invention and not to limit the invention. For example, the description of forming the first member on the second member includes direct contact between the two, or the other is spaced apart from other direct members rather than in direct contact. In addition, the various embodiments of the disclosure may be repeated, and the description is only for the sake of simplicity and clarity, and does not represent the same correspondence between units having the same reference numerals between different embodiments and/or arrangements.

In addition, spatial relative terms such as "below", "below", "lower", "above", "upper", or similar terms may be used to simplify the description of the relative orientation of one element to another. relationship. Spatial relative terms may be extended to elements used in other directions, and are not limited to the illustrated orientation. The component can also be rotated by 90° or other angles, so the directional terminology is only used to illustrate the orientation in the illustration. In addition, the terms "first", "second", "third", "fourth", and the like are used only for distinguishing, and the above terms are interchangeable in various embodiments. For example, when a certain unit (such as an opening) in some embodiments is referred to as a "first unit," it may be referred to as a "second unit" in other embodiments.

The semiconductor substrate on the insulating layer is used in many modern RF devices, such as germanium-based photons and highly accurate microelectromechanical systems. The device formed in the semiconductor substrate on the insulating layer can have improved performance and a smaller package than the device formed in the base substrate. The active semiconductor material in the semiconductor substrate on the insulating layer may ideally have a relaxed single crystal lattice without defects and misalignment. This structure in active semiconductor materials promotes more efficient current for embedding Semiconductor device.

One of the methods for forming a semiconductor substrate on an insulating layer comprises epitaxially growing a single crystal germanium layer on a germanium layer on a sacrificial substrate. The tantalum layer is then bonded to the oxide layer, and the oxide layer is originally bonded to the handle substrate. Then, the sacrificial substrate and the germanium layer are removed by an etching process to retain the semiconductor substrate on the insulating layer, the etching process has etching selectivity to the single crystal germanium layer, and the semiconductor substrate on the insulating layer has a single crystal germanium layer, an oxide layer, and Process the substrate.

However, it is currently known that it is difficult to form a single crystal germanium layer on a germanium layer of a desired thickness (such as a thickness required for radio frequency applications, between approximately 75 nm and approximately 150 nm) due to lattice mismatch of the germanium layer. Stress. For example, using a germanium layer with a low germanium concentration, a thick single crystal layer can be formed on the sacrificial substrate. However, this method has poor control over the thickness of the single crystal germanium layer because the etching selectivity of the single crystal germanium layer is low. On the other hand, the use of a high concentration of ruthenium layer controls the variation of the total thickness of the single crystal ruthenium layer because the ruthenium layer with a high ruthenium concentration has a higher etch selectivity than ruthenium. However, this practice also makes it easier for the single crystal germanium layer to produce misalignment defects along the upper surface of the layer because of the high stress caused by the lattice mismatch of the germanium layer. For example, epitaxial growth of a single crystal germanium layer having a thickness between 70 nm and 150 nm may cause misalignment along the upper surface of the single crystal germanium layer. The etch rate of the misalignment is higher than the etch rate of the remaining single crystal germanium layer, and a divot may be formed along the upper surface of the single crystal germanium layer. The recess will negatively impact device performance in the semiconductor substrate on the insulating layer.

In some embodiments of the invention, a semiconductor substrate on an insulating layer having a single crystal active layer substantially free of misalignment defects can be fabricated using a low cost method. The above method includes epitaxially forming a germanium layer on the sacrificial substrate. Epitaxial formation of the active layer on the germanium layer, and the composition of the active layer is different from the composition of the germanium layer. Flip The substrate is sacrificed and the active layer is bonded to the upper surface of the dielectric layer on the first substrate. The sacrificial substrate and the germanium layer are removed, followed by selective epitaxial growth to increase the active layer thickness. After the germanium layer is removed, the selective epitaxial growth is used to increase the active layer thickness, and when the active layer thickness is increased, no misalignment defects are generated in the active layer. In addition, the tantalum layer having a high germanium concentration has good etching selectivity and can improve the overall thickness variation of the active layer.

Figure 1A is a cross-sectional view of a substrate on an insulating layer of a single crystal active layer having substantially no misalignment defects in some embodiments.

The semiconductor substrate 100 on the insulating layer includes a first substrate 102 covering the dielectric layer 104. For example, the first substrate 102 can be a base germanium substrate in the form of a dish substrate. In some embodiments, the thickness of the first substrate 102 is between approximately 200 μm and approximately 1000 μm. For example, dielectric layer 104 can be or can include yttria, tantalum carbide, tantalum nitride, cerium-rich oxide, or the like.

The active layer 106 is directly on the dielectric layer 104. The active layer 106 is disposed on the dielectric layer 104. In some embodiments, the active layer 106 has a thickness thk. In some embodiments, the active layer 106 has a thickness thk between approximately 70 nm and approximately 150 nm. In some embodiments, the active layer 106 may have a thickness thk of up to about 2000 nm. The active layer 106 has a relaxed single crystal lattice and has substantially no misalignment defects. In some embodiments, the active layer 106 can comprise a single crystal germanium. In other embodiments, the active layer 106 can comprise a different semiconductor material. In some embodiments, active layer 106 can also be a semiconductor compound that is composed of two or more different elements. For example, these elements can form binary alloys (such as gallium arsenide), ternary alloys (such as indium gallium arsenide or aluminum gallium arsenide), or quaternary alloys (such as aluminum indium gallium phosphide).

The active layer 106 has a maximum width 114 defined by the sidewalls and the sidewalls are spaced from the outer edges of the dielectric layer 104 by a lateral outer edge width 116. Since the dielectric layer 104 is laterally spaced from the active layer 106, the upper surface of the dielectric layer 104 is exposed. In some embodiments, the outer edge width 116 can be between approximately 1 mm and approximately 2 mm.

Fig. 1B is a top view showing the semiconductor substrate 100 on the insulating layer of Fig. 1A. As shown in FIG. 1B, the active layer 106 covers the first annular portion 118 of the upper surface 104s of the dielectric layer 104. The outermost edge of the sidewall of the active layer 106 defines the inner boundary of the second annular portion of the upper surface of the dielectric layer 104. The second annular portion 120 surrounds the first annular portion 118 and extends laterally across the outer edge width 116 to the dielectric layer 104 and the outermost edge of the first substrate 102. The active layer 106 does not cover the second annular portion 120, and the second annular portion 120 is exposed on the upper surface 104s of the dielectric layer 104.

As shown in FIG. 1C, the side wall (in cross-sectional view) of the active layer 106 includes a lower side portion 122 and an upper side portion 124. The lower side portion 122 has a substantially linear profile extending vertically upward from the dielectric layer 104. The upper portion 124 has an oblique profile with its face shape 126 sloped inward toward the upper surface 106s of the active layer 106. The width of the upper surface 106s of the active layer 106 is less than the maximum width 114 of the active layer 106. In some embodiments, the epitaxial growth of the active layer 106 may have the sidewall portion 124 of the active layer 106 having a facet shape 126. In some embodiments, the crystal structure of the crystal face shape 126 can be the Miller index (1, 1, 1). In other embodiments, the crystallographic structure of the facet shape 126 can be a different Miller index (such as (1, 1, 0), (0, 0, 1), or other value).

In this way, the semiconductor substrate on the insulating layer of the embodiment of the invention 100 has an active layer 106, which is a connected active layer of a semiconductor material, has a substantially relaxed lattice structure and is substantially free of defects, and has a thickness of up to 150 nm or more.

2 through 11 are cross-sectional views of a method corresponding to forming a semiconductor structure on an insulating layer in some embodiments, and the semiconductor structure on the insulating layer has a single crystal active layer substantially free of dislocation defects. This method allows the final active layer to have good overall thickness variation. For example, the total thickness variation of the final active layer can be less than about 4 nm. Although Figures 2 through 11 are used to illustrate the method, it should be understood that the structures of Figures 2 through 11 are not limited to being formed by the method described, but may be independent of the method.

As shown in the cross-sectional view 200 of FIG. 2, the germanium layer 202 is epitaxially formed on the upper surface 204s of the sacrificial substrate 204. For example, the sacrificial substrate 204 can be a base germanium structure in the form of a dish substrate. For example, the diameter of the substrate can be 1 吋 (25 mm), 2 吋 (51 mm), 3 吋 (76 mm), 4 吋 (100 mm), 5 吋 (130 nm), 125 mm (4.9 吋), 150 mm (5.9 吋). , commonly referred to as 6吋), 200mm (7.9吋, commonly referred to as 8吋), 300mm (11.8吋, commonly referred to as 12吋), or 450mm (17.7吋, commonly referred to as 18吋). In some embodiments, the sacrificial substrate 204 can have a p-type doping (eg, p+ doping). In other embodiments, the sacrificial substrate 204 can have n-type doping. In some embodiments, the thickness of the sacrificial substrate 204 is between approximately 200 [mu]m and approximately 1000 [mu]m.

In some embodiments, the germanium layer 202 can be formed directly on the sacrificial substrate 204, and the forming method can be an epitaxial growth process. In other embodiments, an additional semiconductor layer (not shown) having the same composition (eg, germanium) as the sacrificial substrate 204 may be formed on the sacrificial substrate 204 prior to forming the germanium layer 202. In these embodiments, the additional semiconductor layer is doped (eg, p-type doped) compared to the sacrificial substrate 204. The concentration is lower.

In various embodiments, the germanium layer 202 can be formed by an epitaxial growth process such as molecular beam epitaxy, chemical vapor deposition, or low pressure chemical vapor deposition. In a chemical vapor deposition process, the sacrificial substrate 204 may be exposed to one or more volatile gas precursors that may decompose and react on the upper surface 204s of the sacrificial substrate 204 to create a germanium layer 202 of a desired thickness 206. . In some embodiments, the thickness 206 of the tantalum layer 202 can be between approximately 20 nm and approximately 200 nm.

In some embodiments, the entire thickness 206 of the tantalum layer 202 can contain substantially fixed % of germanium atoms. In some embodiments, the substantially fixed amount of germanium atoms described above may be between approximately 10 atomic percent to approximately 100 atomic percent. In some embodiments, the substantially fixed amount of germanium atoms described above can be between approximately 25 atomic percent to approximately 35 atomic percent. In other embodiments, the germanium atomic % of germanium layer 202 may vary with thickness 206, which may be achieved by changing the precursor gas in the deposition process of germanium layer 202. For example, the initially selected gas precursors and process conditions facilitate the formation of high concentrations of germanium and low concentrations of germanium, which facilitates the formation of a lattice between the germanium layer 202 and the upper surface of the sacrificial substrate 204 below. The degree of matching is lowered and the adhesion to the sacrificial substrate 204 is improved. When depositing the tantalum layer, the gas precursor and process conditions can be gradually changed to increase the germanium concentration (e.g., atomic %) near the upper surface 202s of the tantalum layer 202. The higher germanium concentration along the upper surface 202s of the germanium layer 202 facilitates improved etch selectivity in subsequent etching processes. In some embodiments, the germanium concentration (relative to germanium concentration) of the sacrificial substrate 204 can be between about 0 and 20 atomic percent. In some embodiments, the germanium concentration (relative to the germanium concentration) of the upper surface 202s of the germanium layer 202 can be between approximately 10 atomic percent and 100 atomic percent.

As shown in the cross-sectional view 300 of FIG. 3A, the first active layer is epitaxially grown. 108 is on the layer 202. The material composition of the first active layer 108 is different from the material composition of the tantalum layer 202. For example, the first active layer 108 can comprise a semiconductor material such as germanium. In some embodiments, the first active layer 108 can comprise a single crystal germanium layer. The first active layer 108 can also be a semiconductor compound that is composed of two or more different elements. For example, these elements can form binary alloys (such as gallium arsenide), ternary alloys (such as indium gallium arsenide or aluminum gallium arsenide), or quaternary alloys (such as aluminum indium gallium phosphide).

In various embodiments, the epitaxial growth method of the first active layer 108 may employ vapor phase epitaxy, molecular beam epitaxy, liquid phase epitaxy, or the like. In some embodiments, the vapor phase epitaxial process can react tetrachloromethane with hydrogen at an elevated temperature (eg, about 1200 ° C) to deposit ruthenium. In other embodiments, vapor phase epitaxy can deposit ruthenium with decane, methylene chloride, and/or trichloromethane at a lower temperature (eg, about 650 °C). This process does not produce by-products such as hydrogen chloride which may etch ruthenium. Control the growth rate of the crucible to a single crystal or polycrystalline crucible structure.

The first active layer 108 can grow to a desired thickness 302. In some embodiments, the thickness 302 of the first active layer 108 can be between approximately 20 nm and approximately 50 nm. The thickness 302 of the first active layer 108 can be adjusted according to the % of germanium in the germanium layer 202, so the first active layer 108 can have the stress applied by the germanium layer 202 without creating misalignment defects.

For example, the graph 304 shown in FIG. 3B is the critical thickness of the erbium content function (ie, exceeding this thickness, ie forming a defect in the first active layer of the epitaxial germanium). As shown in FIG. 3B, as the germanium content increases, the thickness of the first active layer 108 can be reduced. For example, when the germanium concentration is 0.3, the thickness of the first active layer 108 is still not defective when it is approximately 20 nm. At a germanium concentration of 0.2, the thickness of the first active layer 108 can be as high as approximately 200 μm without defects.

As shown in the cross-sectional view 400 of FIG. 4, the sacrificial substrate 204 is flipped and the first active layer 108 is bonded to the upper surface 104s of the dielectric layer 104 of the first substrate 102. In some embodiments, a direct bonding process or a fusion bonding process can be employed. The direct bonding process depends on intermolecular forces such as van der Waals forces, hydrogen bonds, or covalent bonds to form bonds between the two mating surfaces. The bonding process does not require additional or intermediate layers between the surfaces to be joined. In some embodiments, to increase the bonding strength, an oxide layer (not shown) may be formed on the upper surface of the dielectric layer 104 prior to bonding, and then the oxide layer is bonded to the mating surface of the first active layer 108. . Direct bonding can be carried out at room temperature followed by elevated temperature to temper the bonded structure.

In some embodiments, the first substrate 102 is used to provide the support required for the structure and thus does not need to be present in the device structure or interconnect structure. In many examples, the first substrate 102 is in the form of a dish substrate. In some embodiments, the first substrate 102 and the sacrificial substrate 204 may have the same diameter. The first substrate 102 may comprise a base germanium substrate and may have a thickness between approximately 300 nm and approximately 1000 nm.

As shown in the cross-sectional view 500 of FIG. 5, the sacrificial substrate 204 is removed after bonding to the first substrate 102. In some embodiments, the method of removing the sacrificial substrate 204 can be an etching, mechanical grinding, and/or chemical mechanical planarization process. The etching process can include wet etching or dry etching. In some embodiments, the etching process may employ a wet etchant containing tetramethylammonium hydroxide. In other embodiments, the wet etchant can comprise a mixture of hydrofluoric acid, nitric acid, and acetic acid; potassium hydroxide; and/or a buffered oxide etchant. In some embodiments, the wet etching step includes thinning the sacrificial substrate 204, followed by complete removal of the sacrificial substrate 204 by chemical mechanical polishing. In some embodiments, the thinning step comprises a dry etch process.

Partially removing the layer of tantalum as shown in the cross-sectional view 600 of FIG. 202. In some embodiments, the ruthenium layer 202 can be partially removed to retain the remaining ruthenium layer 604 to cover the upper surface 108s of the first active layer 108. In some embodiments, the wet etch process employs tetramethylammonium hydroxide or potassium hydroxide, which selectively removes the upper portion 602 of the ruthenium layer 202. When the etch rate of the etchant such as tetramethylammonium hydroxide to the underlying epitaxial material such as germanium is greater than the etching rate of the germanium material, the wet etching process is terminated before reaching the upper surface 108s of the first active layer 108. Otherwise, it will cause unwanted high total thickness variations in the epitaxial material.

In some embodiments, the wet etch process used to remove the ruthenium layer 202 may also remove additional semiconductor layers (not shown), and the doping concentration of the additional semiconductor layers is lower than the doping concentration of the sacrificial substrate 204. Since tetramethylammonium hydroxide has high etch selectivity to ruthenium and osmium, for example, the etch rate of ruthenium is 20 times higher than that of ruthenium, which provides good total thickness variation when removing additional semiconductor layers. .

As shown in the cross-sectional view 700 of Figure 7, the residual ruthenium layer 604 is completely removed. In some embodiments, dry etching or wet etching may be employed to remove residual germanium layers. A wet or dry etch may be selected to preferably etch the remaining germanium layer 604 without etching the first active layer 108. In some embodiments, the dry etching process may employ a hydrogen chloride etchant. In some embodiments, the temperature of the etching process is between 500 ° C and 700 ° C, preferably near 500 ° C. The low temperature process can reduce crystallization variations or defect formation in the first active layer 108. In other embodiments, a hydrogen chloride-containing wet etch process can be used to completely remove the residual ruthenium layer 604.

In some embodiments, the dry or wet etch may continue until the residual germanium layer 604 is completely removed to remove the strained thin layer 702 from the upper surface 108s of the first active layer 108 (eg, etch removal first Strain portion of active layer 108 Share). By removing the thin layer 702, the crystalline structure of the first active 108 transitions to substantially relax. In some embodiments, the removed thin layer 702 can have a thickness between approximately 5 nm and approximately 10 nm. In some embodiments, the thickness of the first active layer 108 reduced by the removal of the thin layer 702 may be between approximately 10 nm and approximately 40 nm.

In some embodiments, an initial cleaning process is performed prior to removing the residual ruthenium layer 604. The initial cleaning process removes the native oxide in the remaining layer 604 from the partial removal of the layer 202. In some embodiments, the cleaning process can include a plasma assisted dry etch process to simultaneously expose residual germanium layer 604 to hydrogen, nitrogen trifluoride, plasma and by-products with ammonia. In some embodiments, the temperature of the cleaning process can be less than 400 ° C to reduce crystallization variations and defect formation in the first active layer 108.

As shown in the cross-sectional view 800 of FIG. 8, the first active layer 108 is selectively etched to define the outermost sidewalls and exposes the outer side edge width 116 of the upper surface 104s of the dielectric layer 104. In some embodiments, a mask layer 802 can be formed over the first annular portion 118 of the upper surface 108s of the first active layer 108. The mask layer 802 can extend radially from the upper surface 108s of the first active layer 108 to cover the outer radius of the first annular portion 118 to expose the outer edge of the first active layer 108 to be etched. In some embodiments, the mask layer 802 may comprise an organic material (such as photoresist, amorphous carbon, a siloxane-based material, or the like), or an inorganic material (such as yttrium oxide, tantalum nitride, or nitridation). Titanium, or the like). In some embodiments, the outer edge width 116 of the dielectric layer can be between 1 mm and about 2 mm. In some embodiments, the first active layer 108 is selectively etched to expose the outer edge width 116, and the etchant employed may comprise hydrogen chloride or tetramethylammonium hydroxide.

Selectively etching the first active layer 108 to expose the outer edge width The practice of 116 can effectively reduce the total thickness variation of the first active layer 108. The etching process for removing the thin layer 702 of the tantalum layer 202 and the first active layer 108 may result in more erosion, thus causing more thickness variations at the outer edge of the first active layer 108. Etching the outer edge of the first active layer 108 removes the locally high thickness variation material, resulting in a lower overall thickness variation of the first active layer 108. The above steps also remove wafer defects along the edges of the first active layer 108 from the step of bonding the first active layer 108 to the dielectric layer 104.

As shown in the cross-sectional view 900 of FIG. 9, the second active layer 110 is epitaxially grown on the first active layer 108. The crystalline structure (e.g., crystal lattice) of the second active layer substantially repeats the crystalline structure of the first active layer 108. Since the first active layer 108 is a relaxed layer having substantially no misalignment defects, the second active layer 110 can be formed to a desired thickness without a misalignment defect. In some embodiments, the second active layer 110 and the first active layer 108 together form an active layer 106. In some embodiments, the active layer 106 comprises germanium. In some embodiments, the active layer 106 has a total thickness of between about 70 nm and 150 nm. In other embodiments, the active layer 106 has a total thickness greater than 150 nm.

The first active layer 108 or the second active layer 110 does not cover the outer side edge of the upper surface 104s of the dielectric layer 104. After stripping the mask layer 802, the first active layer 108 (shown in phantom) has a flat upper surface and a substantially vertical sidewall on the substrate, and the exposed outer edge width 116 of the upper surface 104s of the dielectric layer 104 will Around the first active layer 108. The outer edge width 116 extends laterally from the outermost edge of the sidewall of the first active layer 108 to the outer edge of the dielectric layer 104.

The method for forming the second active layer 110 may be a selective epitaxial growth process using the first active layer 108 as a seed for growing the second active layer 110. In some embodiments, the first active layer 108 can include germanium, and the selective epitaxial growth process can epitaxially grow on the exposed surface of the first active layer 108. In some embodiments, the selective epitaxial growth process can include a precursor gas comprising dichloromethane with (or without) hydrogen chloride; or decane, dioxane, or trioxane with (or without) hydrogen chloride. In some embodiments, a cyclic deposition-etching approach can be employed to achieve selective epitaxial growth. This process can use a precursor gas of decane main, and the process temperature can be lower than 550 °C.

In some embodiments, the epitaxially grown second active layer 110 can have a facet shape 126 of the sidewall portion 124 above the sidewall of the active layer 106. In some embodiments, the crystallographic orientation of the crystal face shape 126 can be a value defined by the Miller index, such as (1, 1, 1). In other embodiments, the crystallographic orientation of the facet shape 126 can be other values defined by the Miller index, such as (1, 1, 0), (0, 0, 1), or other values. The selective epitaxy of the second active layer 110 is generally an anisotropic pattern, i.e., the ratio between the extension in the vertical direction and the extension in the lateral direction is about 1:1. In some embodiments, the selective epitaxial growth process produces a single crystal layer of germanium, such as a known epitaxial lateral overgrowth layer.

The lateral growth of the second active layer 110 causes the second active layer 110 to grow on the sidewalls of the first active layer 108 and abut the exposed outer edge width 116 of the upper surface 104s of the dielectric layer 104. Although the exposed outer edge width 116 produces some small reduction, these are reduced to the nanometer scale, which is approximately equal to the growth thickness of the second active layer 110 (e.g., the thickness thk ₂ minus the thickness thk ₁ ). The exposed outer edge width 116 is substantially between about 1 mm and 2 mm.

In some embodiments, the cross-sectional profile sidewall of the active layer 106 has a lower side portion 122 and an upper side portion 124. The lower side lower portion 122 has a self-dielectric layer 104 A substantially linear profile extending vertically upwards. The upper side portion 124 has an oblique profile with a crystal face or tapered shape that slopes inwardly toward the upper surface 106s of the active layer 106. The width of the upper surface 106s of the active layer 106 is less than the maximum width 114 of the active layer 106. In some embodiments, the sidewall portion 124 of the active layer 106 has an orientation and cross-sectional profile that varies depending on the particular material of the first active layer and the second active layer. In some embodiments, the crystalline structure of the active layer 106 can be represented by the Miller index, which has various values including (1, 1, 1).

As shown in the cross-sectional view 1000 of FIG. 10, a plurality of semiconductor devices 1002 are formed in the active layer 106. In various embodiments, the plurality of semiconductor devices 1002 can comprise gold oxide half field effect transistors and/or other field effect transistors. Although not shown, the transistor can be in other forms, such as a fin field effect transistor device, a bipolar junction transistor, or other transistor.

An interconnect structure 1004 can then be fabricated over the upper surface 106s of the active layer 106. The interconnect structure includes a plurality of metal interconnect layers 1006 (eg, metal lines, vias, and contacts) coupled to the plurality of semiconductor devices 1002, and the interlayer dielectric structure 1008 surrounds the metal interconnect layer 1006. In some embodiments, the metal interconnect layer 1006 can comprise copper, tungsten, aluminum, gold, titanium, or titanium nitride. In some embodiments, the interlayer dielectric structure 1008 can comprise hafnium oxide, tantalum nitride, hafnium oxynitride, a low dielectric constant dielectric material, a very low dielectric constant dielectric material, some other dielectric materials, or Any combination of the above.

As shown in the cross-sectional view 1100 of FIG. 11, the substrate is diced from the first substrate 102 to form a plurality of individual dies 1102. In some embodiments, the method of cutting individual dies from the first substrate 102 can be cut or broken along the cutting line 1104, such as mechanical cutting with a dicing saw, laser cutting, or other feasible cutting side. law.

Figure 12 is a flow diagram of some embodiments of a method of forming a semiconductor substrate on an insulating layer.

The method 1200 described herein is described in a series of steps or events, but it should be understood that the order of the steps or events is merely illustrative and not limiting of the embodiments of the invention. For example, some steps may be performed in a different order, and/or some steps and other steps may be performed simultaneously, but in a different order than described herein. Moreover, one or more embodiments described herein do not require all steps. Furthermore, one or more of the steps described herein can be performed by one or more separate steps and/or aspects.

In step 1202, epitaxial formation of the germanium layer on the sacrificial substrate. The cross-sectional view 200 shown in FIG. 2 corresponds to some embodiments of step 1202.

In step 1204, epitaxial formation of the first active layer on the germanium layer, and the composition of the first active layer is different from the composition of the germanium layer. The cross-sectional view 300 shown in FIG. 3 corresponds to some embodiments of step 1204.

In step 1206, the sacrificial substrate is flipped and the first active layer is bonded to the upper surface of the dielectric layer on the first substrate. The cross-sectional view 400 shown in FIG. 4 corresponds to some embodiments of step 1206.

In step 1208, the sacrificial substrate and the germanium layer are removed. Sections 500, 600, and 700 correspond to some embodiments of step 1208.

In step 1210, the first active layer is etched to define the outermost sidewalls and expose the outer side edges of the upper surface of the dielectric layer. The cross-sectional view 800 shown in FIG. 8 corresponds to some embodiments of step 1210.

In step 1212, epitaxial formation of the second active layer on the first active layer, and the first active layer or the second active layer does not cover the upper surface of the dielectric layer Side edge width. The first active layer and the second active layer together form an active layer. The cross-sectional view 900 shown in FIG. 9 corresponds to some embodiments of step 1212.

In step 1214, a plurality of semiconductor devices are formed in the first active layer and the second active layer, and an interconnect structure is formed on the semiconductor device. The cross-sectional view 1000 shown in FIG. 10 corresponds to some embodiments of step 1214.

In step 1216, a dicing process is performed to form a plurality of separate dies. The cross-sectional view 1100 shown in FIG. 11 corresponds to some embodiments of step 1216.

In summary, some embodiments of the present invention are directed to a method of forming a semiconductor substrate on an insulating layer having a thicker (greater than 75 nm) single crystal active layer having substantially no misalignment defects. The active layer provided by the above method has a good thickness variation (such as less than 4 nm).

As previously mentioned, some embodiments of the present invention provide a method of fabricating a semiconductor substrate on an insulating layer comprising epitaxially forming a germanium layer on the sacrificial substrate. Epitaxial formation of the first active layer on the germanium layer, and the composition of the first active layer is different from the composition of the germanium layer. Bonding the first active layer to the dielectric layer on the first substrate. The sacrificial substrate and the germanium layer are removed. The first active layer is etched to expose an outer side edge of the upper surface of the dielectric layer. The epitaxial layer forms a second active layer on the first active layer to form a connected active layer, wherein the first active layer and the second active layer have substantially the same composition.

In some embodiments, the first active layer or the second active layer in the above method does not cover the outer side edge width of the upper surface of the dielectric layer.

In some embodiments, the active layers connected in the above method comprise germanium.

In some embodiments, the thickness of the active layer connected in the above method The degree is between approximately 70 nm and approximately 150 nm.

In some embodiments, the active layer connected in the above method includes a lower side portion having a side wall extending vertically, and an upper side portion having a crystal face shape inclined inward toward the upper surface of the connected active layer.

In some embodiments, the crystalline structure of the active layers connected in the above method includes a Miller index of (1, 1, 1).

In some embodiments, the tantalum layer in the above method comprises a germanium concentration of between 10 atomic percent and 100 atomic percent.

In some embodiments, the ruthenium layer in the above method comprises a ruthenium concentration of between about 25 atomic percent and about 35 atomic percent.

In some embodiments, the step of removing the germanium layer in the above method comprises partially removing the germanium layer, leaving a residual portion to cover the first active layer, and exposing the residual portion to hydrogen, three at the same time. Nitrogen fluoride, with ammonia plasma and by-products to clean the remaining parts.

In some embodiments, the above method includes removing a residual portion of the tantalum layer by a hydrogen chloride etching process.

In some embodiments, the above method includes removing a portion of the first active layer after removing the germanium layer and before epitaxially forming the second active layer.

In some embodiments, the thickness of the first active layer in the above method is increased to between about 20 nm and 50 nm, and the thickness of the germanium layer is grown to between about 20 nm and about 200 nm.

In addition, the method provided by other embodiments of the present invention includes epitaxially forming a germanium layer on the sacrificial substrate. The epitaxial layer forms a first active layer of the first thickness on the upper surface of the germanium layer, and the first active layer comprises a semiconductor material. Flip sacrificial base A plate and bonding the first active layer to the dielectric layer on the first substrate. The sacrificial substrate and the portion of the germanium layer are removed, and the remaining portion of the germanium layer is left to cover the upper surface of the first active layer. The residual portion of the ruthenium layer and the upper portion of the first active layer are removed. Forming a second active layer on the first active layer, the first active layer and the second active layer have a combined second thickness, and the second thickness is greater than the first thickness.

In some embodiments, the step of removing the portion of the ruthenium layer by the above method comprises etching with tetramethylammonium hydroxide or potassium hydroxide.

In some embodiments, the method includes etching the first active layer to define an outermost sidewall and exposing a lateral surface of the surface of the first active layer facing the dielectric layer.

In some embodiments, the step of removing the residual portion of the tantalum layer by the above method comprises etching with hydrogen chloride.

In some embodiments, the second active layer of the above method has a lower total side width along a lowermost side surface of the second active layer, an upper side total width along an uppermost side surface of the second active layer, and a lower total side width. Greater than the total width of the upper side.

In addition, other embodiments of the present invention provide a semiconductor substrate on an insulating layer, including a dielectric layer, on the first substrate, wherein an outer edge of the dielectric layer is aligned with an outer edge of the first substrate. The active layer covers the first annular portion of the dielectric layer. And a second annular portion of the upper surface of the dielectric layer surrounding the first annular portion and extending to the outer edge of the dielectric layer. The active layer does not cover the second annular portion.

In some embodiments, the active layer height of the semiconductor substrate on the insulating layer is between about 70 nm and about 150 nm.

In some embodiments, the active layer of the semiconductor substrate on the insulating layer includes a lower side portion having a sidewall extending vertically, and having a crystal face shape toward The upper portion of the upper surface of the active layer that is inclined inward.

The features of the above-described embodiments are advantageous to those of ordinary skill in the art in understanding the embodiments of the invention. Those having ordinary skill in the art should understand that the embodiments of the present invention can be used to design and change other processes and structures to achieve the same objectives and/or advantages of the above embodiments. It is to be understood by those of ordinary skill in the art that the present invention is not limited to the spirit and scope of the invention, and may be changed, substituted, or modified without departing from the spirit and scope of the invention.

Claims (20)

A method for forming a semiconductor substrate on an insulating layer, comprising: epitaxially forming a germanium layer on a sacrificial substrate; epitaxially forming a first active layer on the germanium layer, and the composition of the first active layer is different from a layer of the germanium layer; bonding the first active layer to a dielectric layer on a first substrate; removing the sacrificial substrate and the germanium layer; etching the first active layer to expose the dielectric layer An outer side edge of the upper surface; and epitaxially forming a second active layer on the first active layer to form a continuous active layer, wherein the first active layer and the second active layer have substantially the same composition . The method of forming a semiconductor substrate on an insulating layer according to claim 1, wherein the first active layer or the second active layer does not cover an outer side edge width of the upper surface of the dielectric layer. The method of forming a semiconductor substrate on an insulating layer according to claim 1, wherein the connected active layer comprises germanium. The method for forming a semiconductor substrate on an insulating layer according to claim 1, wherein the thickness of the connected active layer is between approximately 70 nm and approximately 150 nm. The method for forming a semiconductor substrate on an insulating layer according to claim 1, wherein the connected active layer comprises a lower portion having a sidewall extending vertically, and having a crystal face shape inwardly facing the upper surface of the active layer The upper part of the slope. The method for forming a semiconductor substrate on an insulating layer according to claim 5, wherein the crystal structure of the connected active layer comprises a Miller index of (1, 1, 1). The method for forming a semiconductor substrate on an insulating layer according to claim 1, wherein the germanium layer comprises a germanium concentration of between 10 atom% and 100 atom%. The method for forming a semiconductor substrate on an insulating layer according to claim 1, wherein the germanium layer comprises a germanium concentration of between about 25 atom% and about 35 atom%. The method for forming a semiconductor substrate on an insulating layer according to claim 1, wherein the step of removing the germanium layer comprises partially removing the germanium layer and leaving a residual portion to cover the An active layer is exposed to hydrogen, nitrogen trifluoride, and ammonia plasma and by-products simultaneously to clean the residual portion. The method for forming a semiconductor substrate on an insulating layer according to claim 9, further comprising removing the residual portion of the germanium layer by a hydrogen chloride etching process. The method for forming a semiconductor substrate on an insulating layer according to claim 10, further comprising removing a portion of the first active layer after removing the germanium layer and epitaxially forming the second active layer Share. The method for forming a semiconductor substrate on an insulating layer according to claim 1, wherein the thickness of the first active layer is increased to between about 20 nm and 50 nm, and the thickness of the germanium layer is grown to be about Between 20 nm and about 200 nm. A method for forming a semiconductor substrate on an insulating layer, comprising: epitaxially forming a germanium layer on a sacrificial substrate; and epitaxially forming a first active layer on the upper surface of the germanium layer, and The first active layer includes a semiconductor material; the sacrificial substrate is flipped, and the first active layer is bonded to a dielectric layer on a first substrate; the sacrificial substrate and the portion of the germanium layer are removed, and Leaving a residual portion of the germanium layer to cover an upper surface of the first active layer; removing the residual portion of the germanium layer and an upper portion of the first active layer; and forming a second active The layer is on the first active layer, the first active layer and the second active layer have a combined second thickness, and the second thickness is greater than the first thickness. The method of forming a semiconductor substrate on an insulating layer according to claim 13, wherein the step of removing the portion of the germanium layer comprises etching with tetramethylammonium hydroxide or potassium hydroxide. The method for forming a semiconductor substrate on an insulating layer according to claim 13 , further comprising: etching the first active layer to define an outermost sidewall, and exposing the dielectric layer facing the first active layer; An outer edge of the surface. The method of forming a semiconductor substrate on an insulating layer according to claim 13, wherein the step of removing the residual portion of the germanium layer comprises etching with hydrogen chloride. Formation of a semiconductor substrate on an insulating layer as described in claim 13 The method, wherein the second active layer has a lower side total width along a lowermost side surface of the second active layer, an upper side total width along the uppermost side surface of the second active layer, and the lower side total width is greater than The total width of the upper side. A semiconductor substrate on an insulating layer, comprising: a dielectric layer on a first substrate, wherein an outer edge of the dielectric layer is aligned with an outer edge of the first substrate; and an active layer covering the dielectric layer An annular portion; and a second annular portion of the upper surface of the dielectric layer surrounding the first annular portion and extending to an outer edge of the dielectric layer, wherein the active layer does not cover the second annular portion Part. The semiconductor substrate on an insulating layer according to claim 18, wherein the active layer has a height of between about 70 nm and about 150 nm. The semiconductor substrate on an insulating layer according to claim 19, wherein the active layer comprises a lower side portion having a side wall extending vertically, and an upper side portion having a crystal face shape inclined inward toward the upper surface of the active layer.