TW201939697A - Semiconductor package structure - Google Patents

Abstract

A semiconductor packaging structure includes a flexible substrate, a plurality of first test pads, a plurality of second test pads, a plurality of first conductive circuits, a plurality of second conductive circuits, and a wafer. The flexible substrate has a first surface and a second surface opposite to each other, wherein the first conductive circuits are disposed on the first surface and are electrically connected to each other through a plurality of first conductive through holes penetrating the flexible substrate. These first test pads on the second surface. Each second conductive line includes a second pin provided on the first surface and a connection line provided on the second surface, and each second pin is connected to a corresponding one through a second conductive through hole penetrating the flexible substrate. Connection line. These second test pads are disposed on the second surface, and each connection line is connected to the corresponding second test pad. The chip is disposed on the first surface and is electrically connected to the first pins and the second pins.

Description

Semiconductor packaging structure

The present invention relates to a packaging structure, and more particularly, to a semiconductor packaging structure.

The current chip on film (COF) package structure has limited wiring area. In order to meet the design requirements of high pin count and fine pitch, the width of each pin can only be between any two adjacent pins. The distance between the leads is further narrowed, and the area of the test pads corresponding to the pins is reduced accordingly. When the area of the test pad is reduced, the pin diameter of the test probe used to touch the test pad is reduced accordingly, which not only improves the difficulty of the test probe to touch the test pad, but also the refined test probe may The structure is not strong enough to be easily worn, bent or shifted, which leads to problems such as poor test reliability and increased test costs. In addition, even if the area of the test pad continues to shrink, it still has to face the limitation of the minimum setting size. This limitation also makes it impossible to reduce the pitch of the pins, which further limits the development of high pin count and micro-pitch design.

The invention provides a semiconductor package structure with excellent wiring flexibility.

The semiconductor package structure of the present invention includes a flexible substrate, a plurality of first test pads, a plurality of second test pads, a plurality of first conductive circuits, a plurality of second conductive circuits, and a wafer. The flexible substrate has a first surface and a second surface opposite to each other. The first surface has a wafer setting region, an extension region, and an intermediate region between the wafer setting region and the extension region. The second surface has a test area, wherein the test area pair is located in the extension area, and the test area has a first test pad area and a second test pad area. The first test pad area is farther from the wafer setting area than the second test pad area. The first test pads are disposed in the first test pad region, and the second test pads are disposed in the second test pad region. Each first conductive circuit includes a first pin and a first pad, and is disposed on the first surface. These first pads are located in the extension area, and each first pin extends outward from the chip setting area through the middle area and terminates in the extension area, and is connected to the corresponding first pad. The first pads are respectively aligned with and overlap the first test pads, and are electrically connected through a plurality of first conductive vias penetrating the extension area and the test area. Each second conductive line includes a second pin and a connection line. The second pins are disposed on the first surface and are staggered with the first pins. Each second pin extends outward from the chip setting region and terminates in the middle region. These connecting lines are disposed on the second surface. A first end of each connection line is connected to a corresponding second pin through a second conductive through hole penetrating the flexible substrate, and a second end of each connection line is connected to a corresponding second test pad. The chip is disposed in the chip setting area and is electrically connected to the first pins and the second pins.

Based on the above, in the semiconductor package structure of the present invention, since the first pins and the second pins are arranged in a staggered manner, any two adjacent first pins or any two adjacent pins are increased. The distance between the second pins makes the first test pads corresponding to the first pins and the second test pads corresponding to the second pins have a larger space for layout, so these first test pads The area or size of the second test pads is not reduced by the micro-pitch layout of the first pins and the second pins. In contrast, since the test area is set on the second surface of the flexible substrate, and the test area is divided into a first test pad area and a second test pad area, the first test pad in the first test pad area corresponds to Connected to the first pins, and the second test pads in the second test pad area are correspondingly connected to the second pins, and the first pins and the second pins do not need to cooperate with the first test pads and The minimum setting size of these second test pads increases the pitch, so it can meet the design requirements of high pin count and micro pitch. In addition, the first test pads and the second test pads are disposed on the same side of the flexible substrate, which can not only improve the accuracy and reliability of the test probe to detect the touch, but also save the test time.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

FIG. 1A is a schematic partial plan view of a semiconductor package structure according to an embodiment of the present invention. FIG. 1B is a partial bottom view of the semiconductor package structure of FIG. 1A. Fig. 1C is a schematic partial cross-sectional view taken along the line I-I 'of Fig. 1A. Fig. 1D is a schematic partial cross-sectional view of Fig. 1A along a line II-II '. It is particularly noted that part of the circuits (such as pins, pads, test pads, or other traces) laid on the flexible substrate 110 are omitted and not shown one by one. Please refer to FIGS. 1A to 1D. In this embodiment, the semiconductor package structure 100 is, for example, a thin-film flip-chip package structure, which includes a flexible substrate 110, a plurality of first test pads 120, and a plurality of second test pads 130. , A plurality of first conductive lines 140, a plurality of second conductive lines 150, and a chip 160.

The material of the flexible substrate 110 is, for example, polyimide (PI), polyester resin (PET), or other flexible insulating materials. The flexible substrate 110 has a first surface 112 and a second surface opposite to each other. The surface 114 and the wafer 160 are disposed on the first surface 112, and the first test pads 120 and the second test pads 130 are disposed on the second surface 114. The first surface 112 has a wafer setting region 112a, an extension region 112c, and an intermediate region 112b located between the wafer setting region 112a and the extension region 112c. The wafer 160 is disposed in the wafer setting region 112a. Each of the first conductive lines 140 and each of the second conductive lines 140 and The conductive lines 150 are electrically connected to the chip 160, respectively, and extend outward from the chip setting area 112a. Further, each first conductive line 140 is disposed on the first surface 112, and extends outward from the wafer setting region 112 a through the intermediate region 112 b and terminates in the extended region 112 c. A portion of each of the second conductive lines 150 is disposed on the first surface 112, and extends outward from the wafer setting region 112 a and terminates in the intermediate region 112 b.

The second surface 114 has a test region 114a, and the test region 114a is aligned with the extension region 112c. The first test pads 120 and the second test pads 130 are both disposed in the test area 114a. Further, the test area 114a can be divided into a first test pad area 114a1 and a second test pad area 114a2, of which the first test pad The region 114a1 is disposed corresponding to the first conductive lines 140, and the second test pad region 114a2 is disposed corresponding to the second conductive lines 150. As shown in FIG. 1B, the first test pad region 114a1 is farther from the wafer setting region 112a than the second test pad region 114a2, that is, the shortest distance between the first test pad region 114a1 and the wafer setting region 112a is greater than the second test pad The shortest distance between the region 114a2 and the wafer setting region 112a. On the other hand, the first test pads 120 are located in the first test pad area 114a1, and the second test pads 130 are located in the second test pad area 114a2. That is, the shortest distance between any one of the first test pads 120 and the wafer setting area 112a is greater than the shortest distance between any one of the second test pads 130 and the wafer setting area 112a.

Please continue to refer to FIGS. 1A to 1D. In this embodiment, each of the first conductive lines 140 includes a first pin 141 and a first pad 142, wherein the first pads 142 are located in the extension region 112c, and the first A pin 141 extends outward from the wafer setting region 112a through the intermediate region 112b and terminates in the extended region 112c. In addition, each first pin 141 is connected to a corresponding first pad 142. On the other hand, the first pads 142 on the first surface 112 are respectively aligned with the first test pads 120 overlapping the second surface 114, and each of the first pads 142 in the flexible substrate 110 is aligned. A first conductive through hole 143 is provided at an overlap with a corresponding first test pad 120, and each of the first conductive through holes 143 penetrates the extension region 112c and the first test pad region 114a1 of the test region 114a for electrical connection. A corresponding set of the first connection pad 142 and the first test pad 120. Therefore, each first test pad 120 can be electrically connected to the corresponding first pin 141 through the corresponding first conductive through hole 143 and the corresponding first pad 142.

Each of the second conductive lines 150 includes a second pin 151 provided on the first surface 112, a second pad 152 provided on the first surface 112, a third pad 154 provided on the second surface 114, and The connecting lines 155 on the second surface 114, wherein the second pins 151 and the first pins 141 are arranged in a staggered manner along a direction parallel to the long side 112a1 of the wafer setting area 112a, that is, any two phases A second pin 151 is disposed between the adjacent first pins 141. Further, the second pads 152 are located in the middle region 112b, and the second pins 151 extend outward from the wafer setting region 112a and terminate in the middle region 112b. In addition, each second pin 151 is connected to a corresponding second pad 152. On the other hand, the second pads 152 on the first surface 112 are respectively aligned with the third pads 154 on the second surface 114, and each of the second pads 152 in the flexible substrate 110 is aligned. A second conductive through hole 153 is provided at an overlap with a corresponding third pad 154, and each of the second conductive through holes 153 penetrates the flexible substrate 110 in the middle region 112b for electrically connecting the corresponding group The second pad 152 and the third pad 154.

In this embodiment, each connection line 155 has a first end 155a and a second end 155b opposite to each other, wherein each first end 155a is located directly below the middle region 112b and is electrically connected to the corresponding third pad 154. Therefore, each connection line 155 can be electrically connected to the corresponding second pin 151 through the corresponding third pad 154, the second conductive through hole 153, and the second pad 152. Each connection line 155 extends from directly below the middle region 112b to the second test pad region 114a2 of the test region 114a, and is electrically connected to the corresponding second test pad 130 through the second end 155b. Therefore, each of the second test pads 130 can be electrically connected to the corresponding second pin 151 through the corresponding connection line 155, the third connection pad 154, the second conductive through hole 153, and the second connection pad 152. However, in other embodiments, the second conductive through hole 153 may be directly disposed at the overlapping position of the second pin 151 and the corresponding connection line 155, so that each of the second test pads 130 only passes through the corresponding connection line 155 and the second The conductive via 153 is electrically connected to the corresponding second pin 151, that is, the arrangement of the second pad 152 and the third pad 154 is omitted.

Please continue to refer to FIG. 1A to FIG. 1D. The first test pads 120 may be divided into a plurality of first groups 122, and the first groups 122 are successively arranged along a direction parallel to the long side 112 a 1 of the wafer setting area 112 a. Each first group 122 includes a plurality of first test pads 120, and the first test pads 120 in each first group 122 are arranged in at least two rows along a direction perpendicular to the long side 112a1 of the wafer setting area 112a. Each first test pad 120 has a width parallel to the long side 112a1 of the wafer setting area 112a, and the total width of the first test pads 120 in each row of these first groups 122 is set from the closest to the wafer setting area 112a to be far away from the wafer The region 112a gradually increases. That is, the total width of the first test pads 120 in the first groups 122 that are farther from the wafer setting region 112a is larger than the total width of the first test pads 120 that are closer to the wafer setting region 112a.

On the other hand, the second test pads 130 can be divided into a plurality of second groups 132, and the second groups 132 are successively arranged along a direction parallel to the long side 112a1 of the wafer setting area 112a. Each second group 132 includes a plurality of second test pads 130, and the second test pads 130 in each second group 132 are arranged in at least two rows along a direction perpendicular to the long side 112a1 of the wafer setting area 112a. Each second test pad 130 has a width parallel to the long side 112a1 of the wafer setting area 112a, and the total width of the second test pads 130 in each row of these second groups 132 is set from the closest to the wafer setting area 112a to be far away from the wafer The region 112a gradually increases. That is, the total width of the second test pads 130 in the second group 132 that is farther from the wafer setting area 112a is larger than the total width of the second test pads 130 that are closer to the wafer setting area 112a.

In this embodiment, each first group 122 is disposed corresponding to a second group 132 in a direction perpendicular to the long side 112a1 of the wafer setting area 112a, and these first tests in each first group 122 The number of pads 120 is equal to the number of these second test pads 130 in the corresponding second group 132.

The chip 160 is disposed in the chip setting area 112 a and is electrically connected to the first pins 141, the second pins 151, and a plurality of third pins 170. In this embodiment, the third pins 170 may be input pins, and the first pins 141 and the second pins 151 may be output pins. Specifically, the wafer 160 includes a plurality of first bumps 161 and a plurality of second bumps 162. The first bumps 161 are adjacently arranged along the long side 112a1 of the wafer setting area 112a, and the second bumps 162 are along the wafer. The long sides 112a2 of the installation area 112a are arranged next to each other. The wafer 160 is disposed on the flexible substrate 110 in a flip-chip manner, so that each first bump 161 is bonded to the corresponding first pin 141 or the corresponding second pin 151, and each second bump 162 Bonded to the corresponding third pin 170.

Please refer to FIG. 1A again, the first surface 112 of the flexible substrate 110 further includes a test region 112d, wherein the test region 112d and the extension region 112c are located on opposite sides of the wafer 160, respectively. These third pins 170 extend outward from the chip setting area 112a and terminate at the test area 112d, and are electrically connected to a plurality of third test pads 180 located in the test area 112d, respectively. When testing electrical properties, the electrical signals are input from the third test pads 180, and then the probes are used to probe the first test pads 120 and the second test pads 130 to test whether the output electrical signals are normal.

On the other hand, the flexible substrate 110 also has two transmission regions 115 and 116 and a plurality of transmission holes 117 opposite to each other. The transmission holes 117 are respectively located in the transmission regions 115 and 116 and penetrate the flexible substrate 110. The transmission holes 117 are arranged along a direction perpendicular to the long side 112a1 of the wafer setting area 112a, and the transmission holes 117 are configured to cooperate with the transmission mechanism to drive the flexible substrate 110 to move. However, the two transmission regions 115 and 116 of the flexible substrate 110 are mechanisms used to facilitate the transmission of the flexible substrate 110 during the process of forming the semiconductor package structure 100. After the semiconductor package structure 100 is manufactured, the flexible substrate 110 of the semiconductor package structure 100 can be separated from the two transmission regions 115 and 116.

In addition, please refer to FIG. 1C and FIG. 1D. The semiconductor package structure 100 further includes a plurality of solder resist layers 190 respectively disposed on the first surface 112 and the second surface 114 of the flexible substrate 110. Specifically, these solder mask layers 190 respectively cover a portion of the first pin 141, a portion of the second pin 150, a portion of the third pin 170, a second pad 152, a third pad 154, and a portion of the connection. Line 155 to protect these electrical transmission lines from electrical shorts and disconnections caused by scratches, foreign matter attachment, or other factors. In particular, in order to clearly describe the technical content of the present invention, the solder mask 190 is omitted in FIGS. 1A and 1B.

As in the above wiring arrangement, since the first pins 141 and the second pins 151 are arranged in a staggered manner, any two adjacent first pins 141 or any two adjacent second pins are increased. The distance between the pins 151 allows the first test pads 120 corresponding to the first pins 141 and the second test pads 130 corresponding to the second pins 151 to have a larger space for layout. The area or size of a test pad 120 and the second test pads 130 will not be reduced by the micro-pitch layout of the first pins 141 and the second pins 151. In contrast, the test area 114a is disposed on the second surface 114 of the flexible substrate 110, and the test area 114a is divided into a first test pad area 114a1 and a second test pad area 114a2, so that the first test pad area 114a1 The first test pad 120 is connected to the first pins 141, and the second test pad 130 in the second test pad region 114a2 is connected to the second pins 151. The first pins 141 and the first pins 141 are connected to the first pins 141. The two pins 151 do not need to increase the pitch in order to meet the minimum setting size limitation of the first test pads 120 and the second test pads 130, so it can meet the design requirements of high pin counts and fine pitches. In addition, the first test pads 120 and the second test pads 130 are disposed on the same side of the flexible substrate 110, which can not only improve the accuracy and reliability of the test probe detection, but also save test time.

Other embodiments will be listed below for illustration. It must be noted here that the following embodiments use the component numbers and parts of the foregoing embodiments, in which the same reference numerals are used to indicate the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

FIG. 2 is a schematic partial plan view of a semiconductor package structure according to another embodiment of the present invention. Please refer to FIG. 2. The main difference between the semiconductor package structure 100a of FIG. 2 and the semiconductor package structure 100 of FIG. 1A is that each second pin 151a extends to the boundary between the intermediate region 112b and the extended region 112c and terminates at this boundary . Further, after the second pins 151a extend outward from the wafer setting region 112a and are connected to the corresponding second pads 152 located in the intermediate region 112b, the second pins 151a continue to extend toward the intermediate region 112b and extend. The boundary of the zone 112c extends and ends at this boundary. Therefore, after the test is completed and the test area 114a is cut out, the ends of the first pins 141 and the second pins 151a are terminated at the same position. For the subsequent external pin bonding process, that is, the terminals connecting external components with the ends of the first pins 141 and the second pins 151a, the configuration of this embodiment can simplify the bonding process and reduce the design complexity of the external component terminals. degree.

3 is a schematic bottom view of a semiconductor package structure according to another embodiment of the present invention. Please refer to FIG. 3. The main difference between the semiconductor package structure 100b of FIG. 3 and the semiconductor package structure 100 of FIG. 1B is that at least one row of each first group 122 has two first test pads 120b arranged symmetrically, and At least one row in the second group 132 has two second test pads 130b arranged symmetrically. Further, the two first test pads 120b arranged symmetrically and in a row in each of the first groups 122 are farther away from the wafer setting area 112a than the other first test pads 120b, and are symmetrically arranged and formed in each of the second groups 132. The two second test pads 130b in the row are farther from the wafer setting area 112a than the other second test pads 130b. Based on the circuit layout method described above, the space of the second surface 114 can be used to set the first test pads 120b and the second test pads 130b. In particular, this embodiment does not limit the number of rows of symmetrically arranged test pads. In other embodiments, the number of rows of symmetrically arranged test pads may be multiple.

In summary, in the semiconductor package structure of the present invention, since the first pins and the second pins are arranged in a staggered manner, any two adjacent first pins or any two phases are increased. The distance between adjacent second pins makes the first test pads corresponding to the first pins and the second test pads corresponding to the second pins have a larger space for layout, so these first The area or size of the test pads and the second test pads will not be reduced by the micro-pitch layout of the first pins and the second pins. In contrast, since the test area is set on the second surface of the flexible substrate, and the test area is divided into a first test pad area and a second test pad area, the first test pad in the first test pad area corresponds to Connected to the first pins, and the second test pads in the second test pad area are correspondingly connected to the second pins, and the first pins and the second pins do not need to cooperate with the first test pads and The minimum setting size of these second test pads increases the pitch, so it can meet the design requirements of high pin count and micro pitch. In addition, the first test pads and the second test pads are disposed on the same side of the flexible substrate, which can not only improve the accuracy and reliability of the test probe to detect the touch, but also save the test time.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

100, 100a, 100b ‧‧‧ semiconductor package structure

110‧‧‧ flexible substrate

112‧‧‧first surface

112a‧‧‧ Wafer Setting Area

112a1, 112a2 ‧‧‧ long side

112b‧‧‧Middle

112c‧‧‧Extension

112d‧‧‧Test Area

114‧‧‧Second surface

114a‧‧‧Test Area

114a1‧‧‧The first test pad area

114a2‧‧‧Second Test Pad Area

115, 116‧‧‧ transmission area

117‧‧‧ transmission hole

120, 120b‧‧‧first test pad

122‧‧‧The first group

130, 130b‧‧‧Second Test Pad

132‧‧‧Second Group

140‧‧‧The first conductive line

141‧‧‧first pin

142‧‧‧The first pad

143‧‧‧first conductive via

150‧‧‧ the second conductive line

151, 151a‧‧‧Second pin

152‧‧‧Second pad

153‧‧‧Second conductive via

154‧‧‧The third pad

155‧‧‧Connecting cable

155a‧‧‧ the first end

155b‧‧‧ second end

160‧‧‧Chip

161‧‧‧The first bump

162‧‧‧Second bump

170‧‧‧ third pin

180‧‧‧Third test pad

190‧‧‧solder mask

FIG. 1A is a schematic partial plan view of a semiconductor package structure according to an embodiment of the present invention. FIG. 1B is a partial bottom view of the semiconductor package structure of FIG. 1A. Fig. 1C is a schematic partial cross-sectional view taken along the line I-I 'of Fig. 1A. Fig. 1D is a schematic partial cross-sectional view of Fig. 1A along a line II-II '. FIG. 2 is a schematic partial plan view of a semiconductor package structure according to another embodiment of the present invention. 3 is a schematic bottom view of a semiconductor package structure according to another embodiment of the present invention.

Claims (10)

A semiconductor package structure includes: a flexible substrate having a first surface and a second surface opposite to each other, the first surface having a wafer setting area, an extension area, and the wafer setting area and the extension area; A middle area between the second surface has a test area, wherein the test area pair is located in the extension area, and the test area has a first test pad area and a second test pad area, the first test pad A plurality of first test pads are provided in the first test pad area; a plurality of second test pads are provided in the second test pad area; a plurality of A first conductive circuit, each of which includes a first pin and a first pad, and is disposed on the first surface; the first pads are located in the extension area; The feet extend outward from the chip setting area through the intermediate area and terminate in the extended area, and are connected to the corresponding first pads, and the first pads are respectively aligned and overlap the first test pads, and are respectively Through a plurality of through the extension area and the test area A plurality of second conductive lines, each of which includes a second pin and a connecting line, and the second pins are disposed on the first surface and are connected to the first conductive via; The first pins are staggered, each of the second pins extends outward from the chip setting region and terminates in the middle region, the connection lines are disposed on the second surface, and a first of each of the connection lines The end is connected to the corresponding second pin through a second conductive through hole penetrating the flexible substrate, and a second end of each of the connection lines is connected to the corresponding second test pad; and a chip is disposed on the The chip is disposed in the area, and the first pins and the second pins are electrically connected. The semiconductor package structure according to item 1 of the scope of patent application, wherein the chip setting area has two opposite long sides, and the first pins and the second pins are parallel to each other in a staggered manner. The long sides are aligned. According to the semiconductor package structure described in item 2 of the patent application scope, the first test pads are divided into a plurality of first groups, and the first groups are successively arranged along a direction parallel to the long sides, each The first test pads in the first group are arranged in at least two rows along a direction perpendicular to each of the long sides. The semiconductor package structure according to item 3 of the scope of patent application, wherein each of the first test pads has a width parallel to each of the long sides, and the total of the first test pads of each row in the first group The width gradually increases from the closest to the wafer setting area to the distance away from the wafer setting area. The semiconductor package structure according to item 3 of the scope of patent application, wherein at least one row of each of the first groups farthest from the chip setting area has two first test pads arranged symmetrically. The semiconductor package structure according to item 3 of the scope of patent application, wherein the second test pads are divided into a plurality of second groups, and the second groups are successively arranged along a direction parallel to the long sides, each The second test pads in the second group are arranged in at least two rows along a direction perpendicular to each of the long sides. The semiconductor package structure according to item 6 of the scope of patent application, wherein each of the second test pads has a width parallel to each of the long sides, and a total of the second test pads of each row in the second group. The width gradually increases from the closest to the wafer setting area to the distance away from the wafer setting area. The semiconductor package structure according to item 6 of the scope of patent application, wherein at least one row of each of the second groups farthest from the chip setting area has two second test pads arranged symmetrically. The semiconductor package structure according to item 6 of the scope of patent application, wherein the first groups are set corresponding to the second groups, and the number and correspondence of the first test pads in each of the first groups are corresponding. The number of the second test pads in the second group is equal. According to the semiconductor package structure described in item 1 of the scope of patent application, wherein each of the second pins is connected to a second pad located in the middle area, and the first end of each of the connection lines is connected to a third pad, the The second pads are respectively aligned with the third pads, and each of the second pads and the corresponding third pads are connected through the corresponding second conductive vias.