TW201939688A - Semiconductor package - Google Patents

Abstract

A semiconductor package includes a connection structure including a first insulation layer, a second insulation layer, first and second wiring layers, and first and second connection vias. A core structure including a core member is on the first insulation layer. A first through-hole passes through the core member. Passive components are on the first insulation layer in the first through-hole and connected to the first wiring layer through the first connection via. A first encapsulant covers at least a portion of the passive components. A second through-hole passes through the core structure and the first insulation layer. A semiconductor chip is on the second insulation layer in the second through-hole and is connected to the second wiring layer through the second connection via. A second encapsulant covers at least a portion of the semiconductor chip.

Description

Semiconductor package

This disclosure relates to a semiconductor package that is modularized by mounting a semiconductor chip together with multiple passive components in a single package.

As the size of mobile device displays increases, it has become necessary to increase battery capacity. As the battery capacity increases, the area occupied by the battery increases. Therefore, the size of a printed circuit board (PCB) must be reduced, so that the mounting area for components is reduced and the interest in modularization is increasing.

Traditional technologies for mounting multiple components include chip-on-board (COB) technology. The chip on board may involve a method of mounting individual passive components and semiconductor packages on a printed circuit board (such as a motherboard) using surface mount technology (SMT). This may be cost-effective, but there may be problems with the large mounting area due to the minimum spacing between components, relatively high electromagnetic interference (EMI) between components, and semiconductor wafers and passive components The relatively large distance between them can increase electrical noise.

The aspect of the present disclosure is to provide a semiconductor package with a novel structure, which significantly reduces the mounting area of a semiconductor wafer and a passive component, significantly shortens the electrical path between the semiconductor wafer and the passive component, and significantly reduces Process defects such as undulations and cracks are reduced, and electrodes of passive components are easily connected to the connection vias by a laser-through-hole process.

An aspect of the present disclosure is to provide a semiconductor package with a novel structure in which a passive component and a semiconductor chip are mounted together in a single package and modularized. In the packaging process, passive components and semiconductor wafers are encapsulated in two separate stages. The through hole of a semiconductor wafer is deeper than that of a passive component. Therefore, a step is formed between the bottom surfaces of the through holes including the semiconductor wafer and the passive component.

According to an aspect of the present disclosure, a semiconductor package includes: a connection structure including a first insulating layer, a second insulating layer lower in thickness direction than the first insulating layer, and respectively located in the first insulating layer and the substrate. The first wiring layer and the second wiring layer on the lower surface of the second insulation layer, and the first connection through-hole and the second connection through-hole passing through the first insulation layer and the second insulation layer, respectively . A core member is located on the first insulating layer. A first through-hole passes through the core member, wherein one or more passive components are located on the first insulating layer, are located in the first through-hole, and are connected to the first through-hole through the first connection through-hole. A wiring layer. The first encapsulation body covers at least part of the passive component and fills at least part of the first through hole. A second through hole passes through the core member and the first insulating layer. The semiconductor wafer is located on the second insulating layer, is located in the second through hole, and is connected to the second wiring layer via the second connection via. A second encapsulation body covers at least a portion of the semiconductor wafer and fills at least a portion of the second through hole.

According to another aspect of the present disclosure, a semiconductor package includes a core member having a first through hole and a second through hole. One or more passive components are located in the first through hole, and a semiconductor wafer is located in the second through hole. The semiconductor wafer has an active surface including a connection pad and a non-active surface opposite to the active surface. The encapsulation body covers at least part of the passive component and at least part of the non-active surface of the semiconductor wafer, and fills at least part of the first through hole and at least part of the second through hole. The connection structure is located on the active surface of the passive component and the semiconductor wafer, and includes at least one wiring layer electrically connected to the passive component and the connection pad of the semiconductor wafer. The bottom surface of the second through-hole has a step with respect to the bottom surface of the first through-hole.

Hereinafter, embodiments of the present disclosure will be explained with reference to the drawings as follows. For clarity, the shapes and sizes of elements in the drawings may be exaggerated or reduced. Electronic device

FIG. 1 is a block diagram schematically illustrating an exemplary embodiment of an electronic device system.

Referring to the drawings, the electronic device 1000 may include a motherboard 1010. The motherboard 1010 may be physically connected to and / or electrically connected to the chip-related component 1020, the network-related component 1030, and other components 1040. These components can also be combined with other components to be described later to form various signal lines 1090.

The chip-related component 1020 may include a memory chip, such as a volatile memory (for example, dynamic random access memory (DRAM)), a non-volatile memory (for example, read only memory memory (ROM)), flash memory, etc .; application processor chips, such as a central processing unit (eg, a central processing unit (CPU)), a graphics processor (eg, a graphic processing unit, GPU)), digital signal processor, cryptographic processor, microprocessor, microcontroller, etc .; logic chips, such as analog-to-digital converters, application-specific integrated circuits (ASICs) Etc .; etc., but not limited to this, and may include other types of wafer related components. The components 1020 may be combined with each other.

The network related components 1030 may include: wireless fidelity (Wi-Fi) (Institute of Electrical And Electronics Engineers (IEEE) 802.11 family, etc.), worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high speed packet access + (high speed packet access + , HSPA +), high speed downlink packet access + (HSDPA +), high speed uplink packet access + (HSUPA +), enhanced data GSM environment (EDGE ), Global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiple access , CDMA), time-division multiple access (Time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G, 4G, 5G, and any other wireless and wireline protocol designated as a later agreement, but It is not limited thereto, and may include any of various other wireless standards or protocols or wired standards or protocols. The network related component 1030 may also be combined with the chip related component 1020.

Other components 1040 may include a high frequency inductor, a ferrite inductor, a power inductor, a ferrite bead, and a low temperature co-firing ceramic. LTCC), electromagnetic interference (EMI) filters, and multilayer ceramic capacitors (MLCC), but not limited to this, and may include other passive components for various other purposes. In addition to the chip-related component 1020 and / or the network-related component 1030, other components 1040 may be combined with each other.

Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may be physically connected to and / or electrically connected to the motherboard 1010 or may not be physically connected to and / or electrically connected to the motherboard 1010. Other components may include, for example, camera 1050, antenna 1060, display 1070, battery 1080, audio codec (not shown), video codec (not shown), power amplifier (not shown) , Compass (not shown), accelerometer (not shown), gyroscope (not shown), speaker (not shown), mass storage unit (for example, hard drive) ) (Not shown), compact disk (CD) (not shown), and digital versatile disk (DVD) (not shown), etc., but not limited to this, And depending on the type of the electronic device 1000, other components for various purposes may be included.

The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet computer, a notebook computer, a portable easy net machine, a television, a video game , Smart watches, cars, etc., but is not limited to this and can be any other electronic device that processes data.

FIG. 2 is a perspective view schematically illustrating an exemplary embodiment of an electronic device.

Referring to the drawings, a semiconductor package can be applied to various electronic devices for various purposes as described above. For example, the body 1101 of the smart phone 1100 may include a printed circuit board 1110 such as a motherboard. In addition, various components 1120 may be physically connected to and / or electrically connected to the printed circuit board 1110. In addition, other components (such as the camera 1130) that can be physically connected to and / or electrically connected to the printed circuit board 1110 or can not be physically connected and / or electrically connected to the printed circuit board 1110 can be housed in the body 1101. A portion of the component 1120 may be a wafer-related component such as, but not limited to, a semiconductor package 1121. The electronic device need not be limited to the smart phone 1100, but may be other electronic devices as described above. Semiconductor package

In general, many microelectronic circuits can be integrated into a semiconductor wafer, but the semiconductor wafer itself does not necessarily serve as a finished product of the semiconductor, and the semiconductor wafer may be damaged due to external physical or chemical influences. Therefore, the semiconductor wafer itself may not be used as it is, but may be packaged and used as an electronic device in such a packaged state.

Since there may be a difference in circuit width in terms of electrical connection between the semiconductor chip and the motherboard of the electronic device, a semiconductor package may be required. Specifically, for semiconductor wafers, the size of the connection pads and the spacing between the connection pads are very small and narrow, while the size of the component mounting pads and the spacing between the component mounting pads are respectively much larger than the specifications of the semiconductor wafers and Much wider. Therefore, since it is difficult to directly mount a semiconductor wafer on such a motherboard, a packaging technology that can buffer the difference in circuit width between the two is needed.

A semiconductor package manufactured by such a packaging technology can be classified into a fan-in type semiconductor package or a fan-out type semiconductor package depending on the structure and use of the semiconductor package.

Hereinafter, the fan-in type semiconductor package and the fan-out type semiconductor package will be explained in more detail with reference to the drawings. Fan-in semiconductor package

3A and 3B are cross-sectional views schematically showing states of the fan-in semiconductor package before and after the package.

FIG. 4 is a cross-sectional view schematically showing a packaging process of a fan-in semiconductor package.

Referring to the drawings, the semiconductor wafer 2220 may be an integrated circuit IC in a bare state. The body 2221 may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), and the like. The connection pad 2222 may include a conductive material such as aluminum (Al) formed on one surface of the body 2221. A passivation film 2223 such as an oxide film or a nitride film may be formed on one surface of the body 2221, and the passivation film 2223 covers at least a part of the connection pad 2222. At this time, since the connection pad 2222 is very small, it may be difficult to mount the integrated circuit IC even on the intermediate printed circuit board PCB and on the motherboard of the electronic device.

The connection structure 2240 can be formed on the semiconductor wafer 2220 according to the size of the semiconductor wafer 2220 to rewire the connection pads 2222. The connection structure 2240 can be prepared by the following steps: forming an insulating layer 2241 on the semiconductor wafer 2220 with an insulating material such as photo-imageable dielectric resin PID, forming a through hole 2243h to expose the connection pad 2222, A wiring pattern 2242 and a through hole 2243 are formed. Then, a passivation layer 2250 for protecting the connection structure 2240 may be formed, an opening 2251 may be formed, and a metal layer 2260 under the bump may be formed. For example, a fan-in semiconductor package 2200 including, for example, a semiconductor wafer 2220, a connection structure 2240, a passivation layer 2250, and a under bump metal layer 2260 can be formed through a series of processes.

As described above, a fan-in type semiconductor package may be a package type in which all connection pads (for example, input / output (I / O) terminals) of a semiconductor wafer are arranged within the element. Fan-in semiconductor packages can have good electrical characteristics and can be produced at relatively low cost. As a result, many components in smart phones have been manufactured in the form of fan-in semiconductor packages. Specifically, it is moving toward a form of miniaturization and at the same time a rapid signal transmission.

Since all input / output terminals should be located in a semiconductor chip in a fan-in semiconductor package, there may be many space constraints. Therefore, such a structure may be difficult to apply to a semiconductor wafer having a large number of input / output terminals or a semiconductor wafer having a small size. In addition, due to such problems, a fan-in semiconductor package may not be directly mounted and used on a motherboard of an electronic device. Even when the size and spacing of the input / output terminals of the semiconductor wafer are expanded by a rewiring process, it does not have a size and spacing sufficient to be directly mounted on a motherboard of an electronic device.

5 is a cross-sectional view schematically showing a fan-in semiconductor package mounted on a printed circuit board and finally mounted on a main board of an electronic device.

6 is a cross-sectional view schematically showing a fan-in semiconductor package embedded in a printed circuit board and finally mounted on a main board of an electronic device.

Referring to the drawings, the fan-in type semiconductor package 2200 may be configured to rewire the connection pads 2222 (ie, input / output terminals) of the semiconductor wafer 2220 through the printed circuit board 2301, and mount the printed circuit board 2301 on The fan-in semiconductor package 2200 is mounted on a motherboard 2500 of an electronic device. At this time, the resin 2280 may be underfilled to fix the solder balls 2270 and the like, and the outside thereof may be covered with a molding material 2290 and the like. Alternatively, the fan-in type semiconductor package 2200 may be embedded in a separate printed circuit board 2302, and the connection pads 2222 (ie, input / output terminals) of the semiconductor wafer 2220 may be rewired in an embedded form, and finally mounted on the motherboard of the electronic device 2500 on.

As described above, it may be difficult to directly mount a fan-in type semiconductor package on a motherboard of an electronic device. Therefore, the fan-in type semiconductor package may be mounted on a separate printed circuit board, and then may be mounted on the main board of the electronic device through a packaging process, or may be mounted on the main board of the electronic device in a form embedded in the printed circuit board. Fan-out semiconductor package

FIG. 7 is a cross-sectional view schematically showing a fan-out type semiconductor package.

Referring to the drawing, in the fan-out semiconductor package 2100, for example, the outside of the semiconductor wafer 2120 may be protected by the encapsulation body 2130, and the connection pad 2122 of the semiconductor wafer 2120 may be re-routed to the semiconductor wafer 2120 by the connection structure 2140. Outside. A passivation layer 2150 may be further formed on the connection structure 2140. An under bump metal layer 2160 may be further formed on the opening of the passivation layer 2150. A solder ball 2170 may be further formed on the under bump metal layer 2160. The semiconductor wafer 2120 may be an integrated circuit IC including a body 2121, a connection pad 2122, and the like. The connection structure 2140 may include an insulating layer 2141, a wiring layer 2142 formed on the insulating layer 2241, and a through hole 2143 for electrically connecting the connection pad 2122 and the wiring layer 2142.

The fan-out type semiconductor package can be formed by rewiring the input / output terminals to the outside of the semiconductor wafer by a connection structure formed on the semiconductor wafer. As described above, in a fan-in type semiconductor package, all input / output terminals of a semiconductor wafer should be provided in the semiconductor wafer. When the size of the component is reduced, the size and pitch of the ball should be reduced. Therefore, it may not be possible to use standardized ball layouts. On the other hand, in a fan-out type semiconductor package, the input / output terminals can be rewired outward from the semiconductor wafer through a connection structure formed on the semiconductor wafer. Despite the reduced size of semiconductor wafers, standardized ball layouts can still be used. Therefore, the fan-out type semiconductor package can be mounted on a main board of an electronic device without a separate printed circuit board, as described later.

FIG. 8 is a cross-sectional view schematically showing a fan-out type semiconductor package mounted on a main board of an electronic device.

Referring to the drawings, the fan-out type semiconductor package 2100 can be mounted on the motherboard 2500 of the electronic device via a solder ball 2170 or the like. For example, as described above, the fan-out semiconductor package 2100 may include the connection structure 2120 on the semiconductor wafer 2120, and the connection structure 2120 may re-route the connection pad 2122 to a fan-out area outside the size of the semiconductor wafer 2120. The standardized ball layout can be used as it is, and therefore it can be mounted on the main board 2500 of the electronic device without a separate printed circuit board or the like.

Since the fan-out type semiconductor package can be mounted on a main board of an electronic device without a separate printed circuit board as described above, the fan-out type semiconductor package can be made thinner than a fan-in type semiconductor package using a printed circuit board. Therefore, reduction in size and thickness of the fan-out semiconductor package can be achieved. Fan-out semiconductor packages are also suitable for mobile products due to their excellent thermal and electrical properties. In addition, the fan-out type semiconductor package can be implemented to be more compact than a general package-on-package (POP) type using a printed circuit board PCB, and can prevent problems caused by a bending phenomenon.

A fan-out type semiconductor package may refer to a packaging technology for mounting a semiconductor wafer on a motherboard or the like of an electronic device and for protecting the semiconductor wafer from external influences, and may have a connection with a printed circuit board PCB such as a fan-in type semiconductor package embedded therein Different concepts of the printed circuit board), the fan-out semiconductor package and the printed circuit board differ from each other in terms of specifications, uses, and the like.

In the following, a semiconductor package with a novel structure can be explained with reference to the drawings. The semiconductor package with the novel structure significantly reduces the mounting area of the semiconductor wafer and the passive component, significantly shortens the electrical path between the semiconductor wafer and the passive component, and significantly reduces Process defects such as undulations and cracks, and in addition, it is easy to connect the electrodes of the passive components to the connection vias by a laser-through-hole process.

FIG. 9 is a cross-sectional view schematically showing an exemplary embodiment of a semiconductor package.

FIG. 10A is a schematic top view of the semiconductor package shown in FIG. 9, taken along a line II ′.

FIG. 10B is a schematic top view of the semiconductor package shown in FIG. 9, taken along the line II-II ′.

The drawing shows a semiconductor package 100A according to an exemplary embodiment. The connection structure 140 includes: a first insulating layer 141a; a second insulating layer 141b, which is lower than the first insulating layer 141a; a first wiring layer 142a and a second wiring layer 142b, which are respectively located on the first insulating layer 141a and the second insulating layer On the lower surface of 141b; and the first connection through hole 143a and the second connection through hole 143b pass through the first insulation layer 141a and the second insulation layer 141b, respectively. The core structure 105 includes a core member 110 on the first insulating layer 141a, wherein the first through hole 110HA1 and the first through hole 110HA2 pass through the core member 110. The one or more passive components 125A1 and 125A2 are located in the first through hole 110HA1 and the first through hole 110HA2 on the first insulating layer 141a, and are connected to the first wiring layer 142a through the first connection through hole 143a. The first encapsulation body 131 covers at least part of the passive component 125A1 and the passive component 125A2, and fills at least part of the first through-hole 110HA1 and the first through-hole 110HA2. The second through hole 110HB passes through the core structure 105 and the first insulating layer 141a. The semiconductor wafer 120 is located on the second insulating layer 141b of the second through hole 110H2, and is connected to the second wiring layer 142b via the second connection via 143b. The second encapsulation body 132 encapsulates the semiconductor wafer 120 and fills at least a portion of the second through hole 110HB.

The depth "db" of the second through hole 110HB may be deeper than the depth "da1" and the depth "da2" of the first through hole 110HA1 and the first through hole 110HA2. The bottom surface of the second through hole 110HB may therefore be lower than the bottom surfaces of the first through hole 110HA1 and the first through hole 110HA2. The bottom surfaces may have step differences. The bottom surface of the second through hole 110HB may be the upper surface of the second insulating layer 141b, and the bottom surfaces of the first through hole 110HA1 and the first through hole 110HA2 may be the upper surface of the first insulating layer 141a. For example, the semiconductor wafer 120 may have an active surface and a non-active surface opposite to the active surface, and the active surface has a connection pad 122 connected to the second connection through-hole 143b. The semiconductor wafer 120 may be positioned such that the lower surface thereof is lower than the lower surfaces of the passive components 125A1 and 125A2. For example, the active surface of the semiconductor wafer 120 may be substantially coplanar with the lower surface of the first wiring layer 143a.

Recently, as the size of mobile displays has increased, battery capacity needs to be increased. As the battery capacity increases, the area occupied by the battery increases. For this reason, it may be necessary to reduce the size of the printed circuit board PCB. Therefore, the installation area of the component can be reduced. In addition, there is a growing interest in modularity. As a conventional technology for mounting multiple components, a chip-on-board (COB) technology can be exemplified. Chip-on-board can be a method of mounting individual passive components and semiconductor packages on a printed circuit board using surface mount technology (SMT). This method may be cost-effective, but there may be problems with large mounting areas due to the minimum spacing between components, relatively high electromagnetic interference (EMI) between components, and semiconductor wafers and passive components The relatively long distance between them can increase electrical noise.

On the other hand, in the semiconductor package 100A according to the exemplary embodiment, the plurality of passive components 125A1 and 125A2 may be arranged together with the semiconductor wafer 120 and modularized in a single package. As a result, the mounting area on a printed circuit board such as a motherboard can be significantly reduced, which can significantly reduce the spacing between components. In addition, the circuit path between the semiconductor chip 120 and the passive components 125A1 and 125A2 can be significantly shortened, thereby reducing noise problems. In addition, since there are two or more encapsulation operations 131 and 132 instead of a single encapsulation operation, it is possible to significantly reduce the number of passive components 125A1 and 125A2 caused by foreign matter when the passive components 125A1 and 125A2 are installed. Problems such as low yield caused by bad installation effects.

The connection pads of a semiconductor wafer may be generally made of aluminum (Al), and may be easily damaged during the laser-via process. Therefore, it may be common to expose the connection pads by a light-through-hole process rather than a laser-through-hole process. To this end, a photosensitive imaging dielectric material PID may be used as the insulating layer provided to form the redistribution layer RDL. When the photosensitive imaging dielectric material PID is stacked in a similar manner to form a redistribution layer RDL on the lower surface of the passive component, undulations may occur due to protrusion of electrodes in the passive component. Therefore, the flatness of the photosensitive imaging dielectric material PID can be reduced. Therefore, there may be inconvenience that a relatively thick photosensitive imaging dielectric material PID should be used to improve the flatness. In this case, cracks may occur due to the thickness of the photosensitive imaging dielectric material PID.

In addition, when the encapsulation body is used to encapsulate the passive component, a problem may occur in which the encapsulation body forming material can penetrate the electrodes of the passive component. In this case, when the redistribution layer RDL is formed using the photosensitive imaging dielectric material PID, a photo-via process may be used as described above. In such a case, it may be difficult to use a light-through-hole process to expose the encapsulation body forming material. Therefore, defects of the exposed electrode may occur due to the exuded encapsulant-forming material, resulting in deterioration of electrical characteristics.

On the other hand, in the semiconductor package 100A according to an exemplary embodiment, a first through-hole 110HA1 and a first through-hole 110HA2 in which the passive component 125A1 and the passive component 125A2 are arranged may be initially formed, and then the passive component 125A1 and the passive The component 125A2, and the first insulating layer 141a and the first wiring layer 142a may be formed to rewire the passive component 125A1 and the passive component 125A2 once. Then, a second through hole 110HB passing through the first insulating layer 141a may be formed, a semiconductor wafer 120 may be provided, and a second insulating layer 142b and a second wiring layer 142b for rewiring the semiconductor wafer 120 may be formed. . For example, the second through hole 110HB provided with the semiconductor wafer 120 may pass through not only the core member 110 but also the first insulating layer 141 a of the connection structure 140. Therefore, the active surface of the semiconductor wafer 120 can be positioned in a position lower than the position of the lower surface of each of the passive element 125A1 and the passive element 125A2. In this case, the material of the first insulating layer 141 a may be selected regardless of the semiconductor wafer 120. For example, a non-photosensitive imaging dielectric material containing an inorganic filler 141af may be used instead of the photosensitive imaging dielectric material PID, such as jinomoto build-up film (ABF). Such a film-type non-photosensitive imaging dielectric material can have excellent flatness, and thus can solve the above-mentioned problems regarding undulations and cracks more effectively.

Such a non-photosensitive imaging dielectric material can be opened by a laser-via process. Even when the material of the first encapsulation body 131 penetrates the electrodes of the passive component 125A1 and the passive component 125A2, the electrodes can be effectively exposed by the laser-through hole process. Therefore, problems caused by defects of the exposed electrodes can be prevented.

As in the conventional case, the semiconductor package 100A according to an exemplary embodiment may use a photosensitive imaging dielectric material PID as the second insulating layer 141b. In this case, fine pitch can be introduced by the light-through-hole process. As in the conventional case, tens to millions of connection pads 122 in the semiconductor wafer 120 can be rewired very efficiently. For example, in the structure of the semiconductor package 100A according to the exemplary embodiment, the following materials can be selectively controlled to have excellent synergistic effects: the passive wiring for the passive component 125A1 and the passive component 125A2 The first wiring layer 142a, the first insulating layer 141a formed with the first connection via 143a, the second wiring layer 142b for rewiring the connection pad 122 of the semiconductor wafer 120, and the second connection via 143b Of the second insulating layer 141b.

The semiconductor package 100A according to an exemplary embodiment may further include: a passivation layer 150 located below the connection structure 140 and having an opening 150v that exposes at least a portion of the second wiring layer 142b; a metal layer 160 under the bump disposed on the passivation layer 150 An exposed at least part of the opening and connected to the second wiring layer 142b; and an electrical connection structure 170, located below the passivation layer 150 and connected to the second wiring layer 142b exposed through the under bump metal layer 160, And therefore, the semiconductor package 100A can be connected to a motherboard or the like.

The semiconductor package 100A according to the exemplary embodiment may further include a wall surface and an upper surface of the core insulation layer 111 formed in the core member 110 in which the first through-hole 110HA1, the first through-hole 110HA2, and the second through-hole 110HB are formed, and The metal layer 115a, the metal layer 115b, the metal layer 115c, and the metal layer 115d on the lower surface, and thus can effectively shield the semiconductor wafer 120 and the passive component 125A1 and the passive component 125A2 from being introduced or discharged into the semiconductor wafer 120 and the passive component 125A1 And the electromagnetic interference EMI in the passive component 125A2, and in addition, a heat radiation effect can be achieved. In addition, the back side metal layer 135 provided on the first encapsulation body 131 and / or the second encapsulation body 132 and the back side of the first encapsulation body 131 and / or the second encapsulation body 132 may be passed through. The metal through hole 133 further improves the EMI shielding and heat radiation effects of the semiconductor wafer 120 and the passive components 125A1 and 125A2. A cover layer 180 covering the back-side metal layer 135 may be further disposed on the first encapsulation body 131 and / or the second encapsulation body 132 to protect the back-side metal layer 135.

Hereinafter, each configuration included in the semiconductor package 100A according to an example will be explained in more detail.

The core member 110 can further increase the rigidity of the packaging module 100A according to a specific material, and can play a role of ensuring thickness uniformity of the first and second encapsulation bodies 131 and 132. The core member 110 may have a plurality of first through holes 110HA1 and first through holes 110HA2. The plurality of first through holes 110HA1 and 110HA2 may be physically spaced from each other. The passive component 125A1 and the passive component 125A2 may be disposed in the first through hole 110HA1 and the first through hole 110HA2, respectively. Each of the passive component 125A1 and the passive component 125A2 may be surrounded by a wall surface of each of the first through-hole 110HA1 and the first through-hole 110HA2 and be in contact with a wall of the first through-hole 110HA1 and the first through-hole 110HA2 The surfaces are spaced a predetermined distance apart, but various modifications can be made as needed.

The core member 110 may include a core insulating layer 111. The material of the core insulating layer 111 is not particularly limited. For example, an insulating material may be used. As the insulating material, a thermosetting resin such as epoxy resin; a thermoplastic resin such as polyimide; or a resin in which the above-mentioned resin is immersed in a core material such as glass fiber, glass cloth, glass fiber cloth, such as prepreg Body, Ajinomoto constituting film (ABF), etc.

The core member 110 may include a first metal layer 115a and a second metal layer 115b, which are disposed on a wall surface of the core insulating layer 111 formed with the first through-holes 110HA1, the first through-holes 110HA2, and the second through-holes 110HB and respectively surround The passive components 125A1 and 125A2 and the semiconductor wafer 120; and the third metal layer 115c and the fourth metal layer 115d are respectively disposed on the lower surface and the upper surface of the core insulating layer 111. The first metal layer 115a, the second metal layer 115b, the third metal layer 115c, and the fourth metal layer 115d may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), Nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof, but is not limited thereto. The electromagnetic wave shielding and heat dissipation of the semiconductor wafer 120 and the passive components 125A1 and 125A2 can be achieved by the first metal layer 115a, the second metal layer 115b, the third metal layer 115c, and the fourth metal layer 115d. The metal layer 115a, the metal layer 115b, the metal layer 115c, and the metal layer 115d may be connected to each other and may also be used as a ground. In this case, the metal layer 115a, the metal layer 115b, the metal layer 115c, and the metal layer 115d may be electrically connected to the ground of the wiring layer 142a and the wiring layer 142b of the connection structure 140.

Each of the passive components 125A1 and 125A2 may be a capacitor, such as a multilayer ceramic capacitor MLCC or a low inductance chip capacitor (LICC), an inductor (such as a power inductor and beads), and the like. The passive components 125A1 and 125A2 may have different thicknesses from each other. In addition, the passive components 125A1 and 125A2 may have a thickness different from that of the semiconductor wafer 120. The semiconductor package 100A according to an exemplary embodiment may encapsulate the passive component 125A1 and the passive component 125A2 in two or more operations, which may significantly reduce the problem of defects due to such a thickness variation. The number of the passive components 125A1 and 125A2 is not particularly limited, and may be relatively more or less than the figure.

The first encapsulation body 131 may respectively enclose the passive component 125A1 and the passive component 125A2, and may also fill at least a part of each of the first through-hole 110HA1 and the first through-hole 110HA2. In addition, in one example, the core component 110 may be encapsulated. The first encapsulation body 131 may include an insulating material, and examples of the insulating material may include a material including an inorganic filler and an insulating resin, such as a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), Resins (specifically, Ajinomoto constituting films, FR-4, bismaleimide triazine (BT), resins, etc.) and reinforcing materials (such as inorganic fillers). In addition, a molding material such as an epoxy molding compound (EMC) can be used. In addition, a photosensitive imaging material such as a photo-imageable encapsulant (PIE) can be used as needed. For example, an insulating resin such as a thermosetting resin or a thermoplastic resin may be a material impregnated with an inorganic filler and / or a core material such as glass fiber, glass cloth, and glass fiber cloth.

The semiconductor wafer 120 may be disposed in the second through hole 110HB. The semiconductor wafer 120 may be spaced apart from the wall surface of the second through hole 110HB by a predetermined distance, and may be surrounded by the wall surface of the second through hole 110HB, but may be modified as required. The semiconductor wafer 120 may be an integrated circuit IC in which hundreds to millions of components are integrated into one wafer. The integrated circuit may be a power management integrated circuit (PMIC), but is not limited thereto, and may be a volatile memory (for example, dynamic random access memory), a non-volatile memory (for example, Read-only memory), memory chips (such as flash memory); application processor chips, such as a central processing unit (such as a central processing unit), a graphics processor (such as a graphics processing unit), a digital signal processor, Cryptographic processors, microprocessors, etc .; analog-to-digital converters, logic chips (such as application-specific integrated circuits (ASICs)), etc.

The semiconductor wafer 120 may be an integrated circuit in an exposed state, in which a separate bump or a wiring layer is not formed. Integrated circuits can be formed on the basis of active wafers. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like can be used as a base material of the body 121 of the semiconductor wafer 120. Various circuits can be formed in the body 121. The connection pad 122 may be used to electrically connect the semiconductor wafer 120 to other components, and a conductive material such as aluminum (Al) may be used as a forming material thereof without any particular limitation. A passivation film 123 may be formed on the body 121 to expose the connection pad 122. The passivation film 123 may be an oxide film or a nitride film, or may be a double layer composed of an oxide film and a nitride film. An insulating film (not shown in the figure) and the like may be further provided in other required positions. At the same time, in the semiconductor wafer 120, the surface on which the connection pad 122 is disposed may become an active surface, and the surface opposite to the active surface may become an inactive surface. At this time, when the passivation film 123 is formed on the active surface of the semiconductor wafer 120, the active surface of the semiconductor wafer 120 may determine the positional relationship based on the lowermost surface of the passivation film 123.

The second encapsulation body 132 may encapsulate the semiconductor wafer 120 and may also fill at least a portion of the through hole 110HA. In one example, the first encapsulation body 131 can also be encapsulated. The second encapsulation body 132 may also include an insulating material. Examples of the insulating material may include a material including an inorganic filler and an insulating resin, such as a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a resin including the above materials and a reinforcing material (such as an inorganic filler). (Specifically, Ajinomoto constitutes a film, FR-4, bismaleimide triazine, a photosensitive imaging dielectric resin, etc.). In addition, known molding materials such as EMC can be used. For example, an insulating resin such as a thermosetting resin or a thermoplastic resin may be a material impregnated with an inorganic filler and / or a core material such as glass fiber, glass cloth, and glass fiber cloth.

The first encapsulation body 131 and the second encapsulation body 132 may be the same material, and may also be different materials. Even when the first encapsulation body 131 and the second encapsulation body 132 include the same material, the boundary between the two can be confirmed. The first encapsulation body 131 and the second encapsulation body 132 may include similar materials, but may have different colors. For example, the first encapsulation body 131 may be more transparent than the second encapsulation body 132, so the boundary between the two may be clear. The first encapsulation body 131 may be formed of an insulating material, and the second encapsulation body 132 may be formed of a magnetic material as required. In this case, the second encapsulation body 132 may have an EMI absorption effect. In the case of the semiconductor wafer 120, the electrodes may not be exposed via the body 121. Therefore, even when the second encapsulation body 132 is formed of a magnetic material, there is no specific problem.

The back metal layer 135 may be disposed on the second encapsulation body 132 to cover the semiconductor wafer 120 and the passive components 125A1 and 125A2. The back-side metal layer 135 may be connected to the fourth metal layer 115 d of the core member 110 through the back-side metal through holes 133 passing through the first encapsulation body 131 and the second encapsulation body 132. The semiconductor wafer 120 and the passive components 125A1 and 125A2 may be surrounded by a metal material through the back metal layer 135 and the back metal through hole 133 to further improve the EMI shielding effect and the heat radiation effect. The back-side metal layer 135 and the back-side metal through hole 133 may also include conductive materials, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and lead (Pb), titanium (Ti), or an alloy thereof. The back-side metal layer 135 and the back-side metal through hole 133 can also be used as ground. In this case, the metal layer 115a, the metal layer 115b, the metal layer 115c, and the metal layer 115d may be electrically connected to the ground of the wiring layer 142a and the wiring layer 142b of the connection structure 140. The back-side metal layer 135 may be in the form of a plate covering most of the upper surface of the second encapsulation body 132, as shown in FIG. 10B. The back-side metal layer 133 may be in the form of a trench via having a predetermined length, as shown in FIG. 10B. In this case, the moving path of the electromagnetic wave can be substantially cut off and thus has a better electromagnetic shielding effect, but it is not limited to this. The back-side metal layer 135 may have a plurality of plate forms in a range of shielding electromagnetic waves. An opening may be formed in the middle of the back-side metal through hole 133 to provide a gas moving path.

The connection structure 140 may rewire the connection pads 122 of the semiconductor wafer 120. In addition, the semiconductor chip 120 and the passive components 125A1 and 125A2 can be electrically connected. The connection pads 122 having various functions of hundreds of semiconductor wafers 120 may be re-wired through the connection structures 140, respectively. The connection pad 122 may be physically and / or electrically connected to the outside through the electrical connection structure 170 depending on its function. The connection structure 140 may include a first insulating layer 141a disposed at a position lower than the positions of the core member 110 and the passive components 125A1 and 125A2; the first wiring layer 142a disposed on a lower surface of the first insulating layer 141a A first connection through-hole 143a passing through the first insulating layer 141a and electrically connecting the passive component 125A1 and the passive component 125A2; a second insulating layer 141b provided on the lower surface of the first insulating layer 141a and the semiconductor wafer The active surface of 120 covers at least part of the first wiring layer 142a; the second wiring layer 142b is disposed on the lower surface of the second insulating layer 141b; and the second connection through-hole 143b passes through the second insulating layer 141b The first wiring layer 142a and the second wiring layer 142b, and the connection pad 122 of the semiconductor wafer 120 and the second wiring layer 142b are electrically connected. The connection structure 140 may include more insulation layers, wiring layers, and connection via layers than those shown in the figure.

An insulating material may be used as a material of the first insulating layer 141a. At this time, as the insulating material, for example, a non-photosensitive imaging dielectric material including an inorganic filler 141af (for example, silicon dioxide or aluminum oxide), such as Ajinomoto, can be used to form a film. This can prevent undulations and defects caused by cracks more effectively. In addition, this can effectively solve the open electrode defects of the passive component 125A1 and the passive component 125A2 that may be caused by the leakage of the material forming the first encapsulation body 131. For example, when a non-photosensitive imaging dielectric material containing an inorganic filler 141af is used as the first insulating layer 141a, the problem of simply using the photosensitive imaging dielectric material PID can be more effectively solved.

As the second insulating layer 141b, a photosensitive imaging dielectric material PID may be used. In this case, a fine pitch can also be introduced by a light-through-hole process, so that tens to millions of connection pads 122 of the semiconductor wafer 120 can be rewired very efficiently as in a normal situation. The photosensitive imaging dielectric material PID may or may not include a small amount of an inorganic filler. For example, the following can be selectively controlled to have a superior synergy effect: the first wiring layer 142a for rewiring the passive component 125A1 and the passive component 125A2, and the first connection layer may be formed thereon The first insulating layer 141a of the hole 143a and the connection pad 122 of the semiconductor wafer 120, the second wiring layer 142b for rewiring the first connection via 143a, and the second insulation for forming the second connection via 143b. Layer 141b.

The first insulating layer 141a formed of a non-photosensitive imaging dielectric material including an inorganic filler 141af may be a plurality of layers, and the second insulating layer 141b formed of a photosensitive imaging dielectric material PID may be a plurality of layers. Can be multiple layers. The second through hole 110HB may pass through the first insulating layer 141a formed of a non-photosensitive imaging dielectric material, and when the first insulating layer 141a has a plurality of layers, it may pass through all of the plurality of layers.

The first insulating layer 141a may have a lower thermal expansion coefficient than a coefficient of thermal expansion (CTE) of the second insulating layer 141b. This is because the first insulating layer 141a may include an inorganic filler 141af. In this case, the weight percentage of the inorganic filler 141af included in the first insulating layer 141a may be greater than the weight percentage of the inorganic filler of the second insulating layer 141b, but the second insulating layer 141b may include a small amount of inorganic filler (see FIG. Not shown). Therefore, the thermal expansion coefficient CTE of the first insulating layer 141a may be lower than the thermal expansion coefficient CTE of the second insulating layer 141b. Since the inorganic filler 141af has a relatively large amount, the first insulating layer 141a having a relatively low thermal expansion coefficient CTE may facilitate warping, such as a relatively low thermal shrinkage. As described above, the problem of occurrence of undulations or cracks can be overcome more effectively, and the problem of electrode exposure defects of the passive components 125A1 and 125A2 can be improved more effectively.

The first wiring layer 142a can be electrically connected to the connection pad 122 of the semiconductor wafer 120 by rewiring the electrodes of the passive device 125A1 and the passive device 125A2. For example, it can be used as a redistribution layer RDL. As a material for forming the first wiring layer 142a, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead ( Pb), titanium (Ti), or an alloy thereof. The first wiring layer 142a may perform various functions depending on a desired design. For example, the first wiring layer 142a may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. In this case, the signal pattern may include various signals other than a ground pattern, a power pattern, and the like, such as a data signal. In addition, through-hole pads and the like may be included. The second through hole 110HB provided with the semiconductor wafer 120 may also pass through the first insulating layer 141a. The lower surface of the first wiring layer 142 a may be substantially the same level as the active surface of the semiconductor wafer 120. For example, the lower surface of the first wiring layer 142 a may be coplanar with the active surface of the semiconductor wafer 120.

The second wiring layer 142 b can be electrically connected to the electrical connection structure 170 by rewiring the connection pads 122 of the semiconductor wafer 120. For example, it can be used as a redistribution layer RDL. As a material for forming the second wiring layer 142b, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead ( Pb), titanium (Ti), or an alloy thereof. The second wiring layer 142b may also perform various functions depending on a desired design. For example, the second wiring layer 142b may include a ground pattern, a power pattern, a signal pattern, and the like. In this case, the signal pattern may include various signals other than a ground pattern, a power pattern, and the like, such as a data signal. In addition, through-hole pads and the like may be included. In addition, it may include through-hole pads, electrical connection structure pads, and the like.

The first connection via 143a can be electrically connected to the passive component 125A1 and the passive component 125A2 and the first wiring layer 142a. The first connection through hole 143a may physically contact an electrode of each of the passive component 125A1 and the passive component 125A2. For example, the passive component 125A1 and the passive component 125A2 can directly contact the first connection through-hole 143a in an embedded type instead of a surface mount type using solder bumps or the like. As a material for forming the first connection via 143a, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), Lead (Pb), titanium (Ti), or an alloy thereof. The first connection through-hole 143a may be completely filled with a conductive material, or may be a conductive material formed along a wall of the through-hole. In addition, the shape of the first connection through hole 143a may be tapered.

The second connection via 143b can be electrically connected to the first wiring layer 142a and the second wiring layer 142b formed on different layers from each other, and can be electrically connected to the connection pad 122 and the second wiring layer 142b of the semiconductor wafer 120. . The second connection via 143b may physically contact the connection pad 122 of the semiconductor wafer 120. For example, the semiconductor wafer 120 may be directly connected to the second connection through-hole 143b of the connection structure 140 in the form of an exposed die without bumps or the like. As a material for forming the second connection via 143b, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and lead can be used. (Pb), titanium (Ti), or an alloy thereof. The second connection through-hole 143b may also be completely filled with a conductive material, or may be a conductive material formed along the wall of the through-hole. In addition, the shape of the second connection through hole 143b may be tapered.

The passivation layer 150 can protect the connection structure 140 from external physical and chemical damage. The passivation layer 150 may have an opening exposing at least a portion of the second wiring layer 142 b of the connection structure 140. Such openings may be formed in the passivation layer 150 in the range of tens to thousands. The passivation layer 150 may include an insulating resin and an inorganic filler 150f, but may not include glass fibers. For example, the passivation layer 150 may be an Ajinomoto film, but it is not limited thereto.

The under-bump metal layer 160 can improve the connection reliability of the electrical connection structure 170, and thus improve the board-level reliability of the packaging module 100A. The under bump metal layer 160 may be connected to the second wiring layer 142 b of the connection structure 140 exposed through the opening of the passivation layer 150. The under bump metal layer 160 may be formed at the opening of the passivation layer 150 by using a known metallization method using a known conductive material (such as metal), but it is not limited thereto.

The electrical connection structure 170 may be a structure for externally physically connecting and / or electrically connecting the semiconductor package module 100A. For example, the semiconductor package module 100A can be mounted on a motherboard of an electronic device through the electrical connection structure 170. The electrical connection structure 170 may be composed of a low melting point metal such as tin (Sn) or an alloy containing tin (Sn). More specifically, the electrical connection structure may be formed of solder or the like, but this may be only an exemplary embodiment, and the material is not particularly limited thereto. The electrical connection structure 170 may be a pin, a ball, a pin, or the like. The electrical connection structure 170 may be formed of multiple layers or a single layer. In the case of being formed of multiple layers, the electrical connection structure 170 may include copper pillars and solder. In the case of being formed of a single layer, tin-silver solder or copper may be included, but this may be merely an example, but is not limited thereto. The number, interval, and arrangement type of the electrical connection structures 170 are not particularly limited, and can be fully modified by general engineers depending on the design specifications. For example, the number of the electrical connection structures 170 may be in the range of several tens to several thousands depending on the number of the connection pads 122, and may be more or less than the above range.

At least one of the electrical connection structures 170 may be disposed in the fan-out area. The fan-out area may be an area other than an area where the semiconductor wafer 120 is provided. A fan-out package can be more reliable than a fan-in package, can have many input / output terminals, and can facilitate 3D interconnection. In addition, thinner packages such as ball grid array BGA packages and land grid array LGA packages can be manufactured, and the packages can be excellent in price competitiveness.

Meanwhile, a cover layer 180 covering the back-side metal layer 135 may be further provided on the first encapsulation body 131 and / or the second encapsulation body 132 to protect the back-side metal layer 135. The cover layer 180 may include an insulating resin and an inorganic filler 150f, but may not include glass fibers. For example, the cover layer 180 may be, but is not limited to, Ajinomoto's film. Due to the symmetry effect, the passivation layers 150 and 180 stacked on / under the layers may include the same material to control the coefficient of thermal expansion CTE.

FIG. 11 is a cross-sectional view schematically showing an exemplary embodiment of a panel used in the semiconductor package shown in FIG. 9.

Referring to the drawings, a semiconductor package 100A according to an exemplary embodiment may be manufactured using a panel 500 having a relatively large size. The size of the panel 500 can be 2 to 4 times larger than that of a conventional wafer, and thus a larger number of semiconductor packages 100A can be manufactured by a single process. For example, productivity can increase significantly. Specifically, relative to the case of using a wafer, the larger the size of each package module 100A, the higher the productivity. Each unit portion of the panel 500 may be a core member 110 first prepared in a manufacturing method described below. After the panel 500 is used to simultaneously manufacture a plurality of semiconductor packages 100A in a single process, they can be cut by known cutting processes such as a singulation process to obtain individual semiconductor packages 100A.

12A to 12E are schematic flowcharts illustrating an exemplary method of manufacturing the semiconductor package shown in FIG. 9.

Referring to FIG. 12A, a core member 110 may be first prepared. The core member 110 may be formed by the following steps: preparing a copper clad laminate CCL using the panel 500 described above and by, for example, a semi-additive process (SAP) or a modified semi-additive process (modified) A known plating process such as a semi-additive process (MSAP) uses a copper foil of a copper-clad laminate CCL to form a metal layer 115a, a metal layer 115b, a metal layer 115c, and a metal layer 115d. For example, the metal layer 115a, the metal layer 115b, the metal layer 115c, and the metal layer 115d may be respectively composed of a seed layer and a conductor layer thicker than the seed layer. Depending on the material of the core insulating layer 111, a first through hole 110HA1 and a first through hole 110HA2 and a preliminary second through hole 110HB 'can be formed in the core member 110 using laser drilling and / or mechanical drilling or sand blasting, etc. . The first adhesive film 210 may be attached to a position lower than the position of the core member 110, and the passive components 125A1 and 125A2 may be disposed in the first through-holes 110HA1 and 110HA2, respectively. The first adhesive film 210 may be a known adhesive tape, but is not limited thereto.

Referring to FIG. 12B, the first encapsulation body 131 may be used to encapsulate the core member 110 and the passive components 125A1 and 125A2. The first encapsulation body 131 may be formed by laminating a film in an uncured state and then curing the laminated film, or may be formed by applying a liquid material and then curing the liquid material. The first adhesive film 210 can be removed. As a method of peeling the first adhesive film 210, a mechanical method can be used. Then, on the removed portion of the first adhesive film 210, a first insulating layer 141a may be formed by using Ajinomoto to form a film lamination method or the like, and a via hole may be formed by a laser-via process, and then may be borrowed The first wiring layer 142a and the first connection via 143a are formed by a known plating process such as SAP or MSAP. For example, the first wiring layer 142a and the first connection via 143a may be respectively composed of a seed layer and a conductor layer thicker than the seed layer. Next, laser drilling and / or mechanical drilling or sand blasting may be used to form the second through hole 110HB passing through the first encapsulation body 131 and the first insulating layer 141a. At this time, the side surface of the second metal layer 115b may be substantially coplanar with the wall surface of the second through hole 110HB where the first encapsulation body 131 is formed.

Referring to FIG. 12C, the second adhesive film 220 may be attached to a position lower than the position of the first insulating layer 141a, and the semiconductor wafer 120 may be attached face down to the second exposed through the second through hole 110HB. On the adhesive film 220. The second encapsulation body 132 may be used to encapsulate the first encapsulation body 131 and the semiconductor wafer 120. Similarly, the second encapsulant 132 may be formed by laminating a film in an uncured state and then curing the laminated film, or may be formed by applying a liquid material and then curing the liquid material. A carrier film 230 may be attached on the second encapsulation body 132. In some cases, the second encapsulation body 132 may be formed and then laminated on the carrier film 230. The unfinished module manufactured in an upside-down form may be reversed, and the second adhesive film 220 may be separated and removed by a mechanical method or the like.

Referring to FIG. 12D, a second insulating layer 141b can be formed on the active surface of the first insulating layer 141a and the semiconductor wafer 120 by laminating a photosensitive imaging dielectric material PID, and a via hole can be formed by a photo-via process. Similarly, the second wiring layer 142b and the second connection via 143b can be formed by a known plating process to form the connection structure 140. The second wiring layer 142b and the second connection via 143b may also be composed of a seed layer and a conductor layer. The passivation layer 150 may be formed on the connection structure 140 by a known lamination method or a coating method. The carrier film 230 may be separated and removed.

Referring to FIG. 12E, a through hole 133v passing through the first encapsulation body 131 and the second encapsulation body 132 may be formed using laser drilling or the like. Laser drilling or the like may be used to form an opening 150v in the passivation layer 150 that exposes at least a portion of the second wiring layer 142b of the connection structure 140. The backside metal through hole 133 and the backside metal layer 135 can be formed by a known plating process. These may be composed of a seed layer and a conductor layer. In addition, the under bump metal layer 160 may be formed by a plating process. The under bump metal layer 160 may also be composed of a seed layer and a conductor layer. When the cover layer 180 is formed on the second encapsulation body 132 and the electrical connection structure 170 is formed on the under bump metal layer 160, the semiconductor package 100A according to the above-described exemplary embodiment may be prepared.

When the panel 500 or the like shown in FIG. 11 is used, a plurality of semiconductor packages 100A can be manufactured by a single process including a series of operations. After that, each semiconductor package 100A can be obtained by a singulation process or the like.

FIG. 13 is a cross-sectional view schematically showing another example of a semiconductor package.

Referring to the drawings, in a semiconductor package 100B according to another exemplary embodiment, a surround may be further provided on a side surface of the second metal layer 115b and a wall surface of the second through hole 110HB where the first encapsulation body 131 is formed. The fifth metal layer 115e of the semiconductor wafer 120. Therefore, a plurality of metal layers 115b and 115e are disposed on the inner wall of the second through hole 110HB. The fifth metal layer 115e may be introduced for the EMI shielding effect and heat dissipation effect of the semiconductor wafer 120. The fifth metal layer 115e may also include a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti ), Or its alloy. The fifth metal layer 115e can be formed using a known plating process, and can be composed of a seed layer and a conductor layer. The fifth metal layer 115e can also be used as a ground. In this case, the fifth metal layer 115e may be electrically connected to the ground in the wiring layer 142a and the wiring layer 142b of the connection structure 140. Other configurations and manufacturing methods are substantially the same as those described above, and detailed descriptions thereof will be omitted.

FIG. 14 is a cross-sectional view schematically showing another example of a semiconductor package.

Referring to the drawings, in a semiconductor package 100C according to another exemplary embodiment, a surround may be further provided on a side surface of the second metal layer 115b and a wall surface of the second through hole 110HB where the first encapsulation body 131 is formed. The fifth metal layer 115e of the semiconductor wafer 120 may further include a first backside metal layer 135a on the first encapsulation body 131 to cover the passive components 125A1 and 125A2, and the first backside metal layer 135a may pass through The first backside metal through hole 133a of the first encapsulation body 131 is connected to the fourth metal layer 115d. A second back-side metal layer 135 b may be provided on the second encapsulation body 132 to cover at least the semiconductor wafer 120, and the second back-side metal layer 135 b may pass through the second back-side metal through hole passing through the second encapsulation body 132. 133b is connected to the first back-side metal layer 135a. The semiconductor wafer 120 and / or the passive component 125A1 and the passive component can be achieved by the first backside metal layer 135a and the second backside metal layer 135b, and the first backside metal through hole 133a and the second backside metal through hole 133b. 125A2 EMI shielding and heat dissipation. It may also include conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or the like alloy. These can also be formed by a known plating process, and each can be composed of a seed layer and a conductor layer. It can also be used as ground, or it can be electrically connected to the wiring layer of the connection structure 140 via the first metal layer 115a, the second metal layer 115b, the third metal layer 115c, the fourth metal layer 115d, and the fifth metal layer 115e. Ground in 142a and wiring layer 142b. Other configurations and manufacturing methods are substantially the same as those described above.

FIG. 15 is a cross-sectional view schematically showing another example of a semiconductor package.

Referring to the drawings, in a semiconductor package 100D according to another exemplary embodiment, a surface mount component 155 may be further disposed on a lower surface of the passivation layer 150. The surface mount component 155 may be a capacitor, an inductor, a bead, or the like. For example, the surface-mount component 155 may be a land side capacitor LSC, but it is not limited thereto, and may be an active component, such as a die in the form of an integrated circuit IC. The surface mount component 155 may be electrically connected to the connection pad 122 and / or the passive component 125A1 and the passive component 125A2 of the semiconductor chip 120 via the wiring layer 142a and the wiring layer 142b of the connection structure 140 and the connection vias 143a and 143b. Other configurations and manufacturing methods are substantially the same as those described above, and detailed descriptions thereof will be omitted.

FIG. 16 is a cross-sectional view schematically showing another example of a semiconductor package.

Referring to the drawings, a semiconductor package 100E according to another exemplary embodiment may further include a wiring through hole 113 in which the core member 110 passes through the first and second wiring layers 112 a and 112 b and the core insulating layer 111, and the wiring through hole 113. The first and second wiring layers 112a and 112b are respectively arranged on the lower surface and the upper surface of the core insulation layer 111 and are electrically connected. The first wiring layer 112a and the second wiring layer 112b may be electrically connected to the connection pad 122 and / or the passive component of the semiconductor wafer 120 via the wiring layer 142a and the wiring layer 142b of the connection structure 140 and the connection vias 143a and 143b. 122a. The semiconductor package 100E may have a vertical electrical connection path through the core member 110 and may be introduced into a stacked package structure.

The wiring layer 112 a and the wiring layer 112 b can be used for rewiring the connection pads 122 of the semiconductor wafer 120. As a material for forming the wiring layer 112a and the wiring layer 112b, a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), Lead (Pb), titanium (Ti), or an alloy thereof. The wiring layers 112a and 112b may perform various functions depending on the desired design of the layer of interest. For example, it may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. In this case, the signal pattern may include various signals other than a ground pattern, a power pattern, and the like, such as a data signal. In addition, it may include through-hole pads, wire bonding pads, electrical connection structure pads, and the like. The wiring layer 112a and the wiring layer 112b may be formed by a known plating process, and may be composed of a seed layer and a conductor layer, respectively. The thicknesses of the wiring layers 112a and 112b may be thicker than the thicknesses of the wiring layers 142a and 142b.

The material of the core insulating layer 111 is not particularly limited. For example, an insulating material may be used. As the insulating material, a thermosetting resin such as epoxy resin; a thermoplastic resin such as polyimide; or a mixture of these resins and an inorganic filler; or the above resin is dipped into, for example, glass together with an inorganic filler such as silicon dioxide. Resins in core materials such as fiber, glass cloth, or glass fiber cloth, such as prepregs.

The wiring vias 113 may electrically connect the wiring layer 112 a and the wiring layer 112 b formed in different layers to each other to form an electrical path in the core member 110. The wiring vias 113 may also be formed of a conductive material. The wiring through-hole 113 may be completely filled with a conductive material, or the conductive material may be formed along a wall surface of the hole of the through-hole. The wiring through hole 113 may have an hourglass shape. The wiring vias 113 may also be formed by a known plating process, and may be composed of a seed layer and a conductor layer, respectively.

In the semiconductor package 100E according to another exemplary embodiment, a back-side wiring layer 135s other than the back-side metal layer 135 may be further provided on the second encapsulation body 132. The back-side wiring layer 135s may be connected to the second wiring layer 112b of the core member 110 through the back-side wiring through-holes 133s passing through the first and second encapsulation bodies 131 and 132. An opening 180v1 and an opening 180v2 for exposing at least a part of each of the back-side metal layer 135 and the back-side wiring layer 135s may be formed in the cover layer 180. The electrical connection structure 190A and the electrical connection structure 190B may be disposed on the opening 180v1 and the opening 180v2, and may be connected to the back-side metal layer 135 and the back-side wiring layer 135s respectively exposed through the above.

The back-side metal layer 135 and the back-side metal via 133 may be formed as described above for EMI shielding and heat dissipation purposes. In this case, when the back-side metal layer 135 and the back-side metal through-hole 133 are connected to a printed circuit board such as a motherboard through the electrical connection structure 190A, the EMI shielding and heat dissipation effects can be further improved. The back-side metal layer 135 and the back-side metal through hole 133 can be used as the ground as described above, and can be electrically connected to the connection structure 140 via the metal layer 115a, the metal layer 115b, the metal layer 115c, and the metal layer 115d of the core member 110. The wiring layers 142a and 142b are grounded.

The back-side wiring layer 135s and the back-side metal through-hole 133s can pass through the wiring layer 112a and the wiring layer 112b of the core member 110, the wiring through-hole 113, the wiring layer 142a and the wiring layer 142b of the connection structure 140, and the connection via 143a and the connection via The hole 143b is electrically connected to the semiconductor wafer 120 and / or the passive component 125A1 and the passive component 125A2. For example, the main purpose of the back-side wiring layer 135s and the back-side wiring vias 133s is for signal connection. The back-side wiring layer 135s may be connected to a printed circuit board such as a motherboard via an electrical connection structure 190B to provide an electrical path between the semiconductor package 100E and the printed circuit board. In this case, in the semiconductor package 100E, the back side thereof may be mounted on a printed circuit board, and the front side thereof may be connected to the antenna substrate or the like in a stacked package manner via the electrical connection structure 170. For example, the semiconductor package 100B according to another exemplary embodiment can be easily applied to various types of module structures in a stacked package manner. The back-side wiring layer 135s and the back-side wiring vias 133s may also include conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and lead (Pb), titanium (Ti), or an alloy thereof.

The back-side metal layer 135 may cover most of the upper surface of the second encapsulation body 132 and may not cover a space where the back-side wiring layer 135s is formed. At this time, the back-side metal layer 135 and the back-side wiring layer 135s may be physically separated from each other by a predetermined distance. For example, the back-side wiring layer 135s may be provided in an island form with respect to the back-side metal layer 135.

Each of the electrical connection structure 190A and the electrical connection structure 190B may be made of a low melting point metal (for example, tin (Sn) or an alloy containing tin (Sn)). More specifically, it may be formed of solder or the like, but this may be merely an example, and its material is not particularly limited thereto. The electrical connection structure 190A and the electrical connection structure 190B may be pins, balls, pins, and so on. The electrical connection structure 190A and the electrical connection structure 190B may be formed of multiple layers or a single layer, respectively. In the case of being formed of multiple layers, the electrical connection structure 190A and the electrical connection structure 190B may include copper pillars and solder. In the case of being formed of a single layer, tin-silver solder or copper may be included, but this may be merely an example and is not limited thereto. The electrical connection structure 190A may be connected to the back-side metal layer 135, and the electrical connection structure 190B may be connected to the back-side wiring layer 135s.

FIG. 17 is a cross-sectional view schematically showing another example of a semiconductor package.

Referring to the drawings, in the semiconductor package 100E according to another example described above, the semiconductor package 100F according to another exemplary embodiment may include a first core insulating layer 111a, in which the core member 110 contacts the connection structure 140; the first wiring layer 112a Contacting the connection structure 140 and embedded in the first core insulating layer 111a; the second wiring layer 112b is disposed opposite to the side where the first wiring layer 112a of the first core insulating layer 111a is embedded; the second core insulating layer 111b, The third wiring layer 112c is disposed on the first core insulating layer 111a and covers at least a portion of the second wiring layer 112b; and the third wiring layer 112c is disposed on the second core insulating layer 111b. The first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c may be electrically connected to the connection pad 122. The first wiring layer 112a and the second wiring layer 112b, and the second wiring layer 112b and the third wiring layer 112c may be electrically connected to the first wiring through holes passing through the first core insulation layer 111a and the second core insulation layer 111b, respectively. 113a and the second wiring via 113b.

The first wiring layer 112a may be recessed in the first core insulating layer 111a. In this way, when the first wiring layer 112a is recessed in the first core insulating layer 111a and there is a step difference between the lower surface of the first core insulating layer 111a and the lower surface of the first wiring layer 112a, it is possible to prevent the The material forming the encapsulation body 131 leaks and contaminates the first wiring layer 112a. The wiring layer 112 a, the wiring layer 112 b, and the wiring layer 112 c of the core member 110 may be thicker than the wiring layer 142 a and the wiring layer 142 b of the connection structure 140.

The materials of the core insulating layer 111a and the core insulating layer 111b are not particularly limited. For example, an insulating material may be used. As the insulating material, a thermosetting resin such as an epoxy resin; a thermoplastic resin such as polyimide; or a resin in which the above resin and an inorganic filler are mixed, such as Ajinomoto constituting a film (ABF). A photosensitive imaging dielectric resin such as a photosensitive imaging dielectric PID resin may be used.

When the hole of the first wiring via 113a is formed, a part of the pad of the first wiring layer 112a may serve as a termination element. The width of the upper surface of the first wiring through-hole 113a may have a tapered shape that is wider than the width of the lower surface thereof according to the manufacturing process. In this case, the first wiring through hole 113a may be integrated with the pad pattern of the second wiring layer 112b. When the hole of the second wiring via 113b is formed, a part of the pad of the second wiring layer 112b may serve as a termination element. The width of the upper surface of the second wiring through hole 113b may have a tapered shape that is wider than the width of the lower surface thereof according to the manufacturing process. In this case, the second wiring via 113b may be integrated with the pad pattern of the third wiring layer 112c.

Meanwhile, the core component 110 of the semiconductor package 100E can be applied to the above-mentioned various semiconductor packages 100A, semiconductor packages 100B, semiconductor packages 100C, and 100D. The other configurations are substantially the same as those described above, and detailed descriptions thereof will be omitted.

FIG. 18 is a cross-sectional view schematically showing another example of a semiconductor package.

Referring to the drawings, based on the semiconductor package 100E according to another exemplary embodiment described above, in the semiconductor package 100G according to another exemplary embodiment, the core member 110 may include a first core insulating layer 111a; a first wiring layer 112a and The second wiring layer 112b is disposed on the lower surface and the upper surface of the first core insulation layer 111a, respectively; the second core insulation layer 111b is disposed on the lower surface of the first core insulation layer 112a and covers the first wiring layer 112a. At least a part; a wiring layer 111c provided on a lower surface of the second core insulating layer 111b; a third core insulating layer 111c provided on an upper surface of the first core insulating layer 111a and covering at least a part of the second wiring layer 112b; And the fourth wiring layer 112d is provided on the upper surface of the third core insulating layer 111c. The first wiring layer 112a, the second wiring layer 112b, the third wiring layer 112c, and the fourth wiring layer 112d may be electrically connected to the connection pad 122. Since the core member 110 includes a larger number of wiring layers 112a, 112b, 112c, and 112d, the connection structure 140 can be further simplified. Therefore, the decrease in yield due to defects generated in the process of forming the connection structure 140 can be improved. The first wiring layer 112a, the second wiring layer 112b, the third wiring layer 112c, and the fourth wiring layer 112d may be electrically connected to the first core insulation layer 111a, the second core insulation layer 111b, and the third core insulation layer, respectively. The first wiring via 113a, the second wiring via 113b, and the third wiring via 113c of 111c.

The first core insulation layer 111a may be thicker than the second core insulation layer 111b and the third core insulation layer 111c. The first core insulation layer 111a may be relatively thick to maintain rigidity, and the second core insulation layer 111b and the third core insulation layer 111c may be introduced to form a larger number of wiring layers 112c and 112d. The first core insulating layer 111a may include an insulating material different from the second core insulating layer 111b and the third core insulating layer 111c. For example, the first core insulating layer 111a may be, for example, a prepreg including a core material, a filler, and an insulating resin, and the second core insulating layer 111c and the third core insulating layer 111c may be a flavor including a filler and an insulating resin. The element constitutes a film or a PID, but is not limited thereto. From a similar perspective, the diameter of the first wiring via 113a passing through the first core insulating layer 111a may be longer than the second wiring via 113b and the third wiring passing through the second core insulating layer 111b and the third core insulating layer 111c.通 孔 113c. Similarly, the wiring layer 112a, the wiring layer 112b, the wiring layer 112c, and the wiring layer 112d of the core member 110 may be thicker than the wiring layer 142a and the wiring layer 142b of the connection structure 140.

At the same time, the core component 110 of the semiconductor package 100F can be applied to the above-mentioned various semiconductor packages 100A, 100B, 100C, and 100D. The other configurations are substantially the same as those described above, and detailed descriptions thereof will be omitted.

FIG. 19 is a plan view schematically showing an effect of implementing a semiconductor package according to the present disclosure in an electronic device.

Referring to the drawings, as the sizes of the mobile device display 1100A and the mobile device display 1100B increase, it is necessary to increase the battery capacity. As the battery capacity increases, the area occupied by the battery 1180 increases. Therefore, it may be necessary to reduce the size of the printed circuit board 1101 such as a motherboard. Therefore, the area occupied by the module 1150 including the PMIC and its accompanying passive components is continuously reduced. In this case, when the semiconductor package 100A, semiconductor package 100B, semiconductor package 100C, semiconductor package 100D, semiconductor package 100E, semiconductor package 100F, and semiconductor package 100G are applied to the module 1150 according to the present disclosure, the size can be significantly reduced. , And therefore narrowed areas can be effectively used.

In this disclosure, for convenience, the terms lower part, lower part, lower surface, etc. are used to refer to the downward direction of the cross section of the drawing (in the vertical direction of the drawing, this is also referred to as the thickness direction) ), And use the words upper part, upper part, upper surface, etc. to refer to directions opposite to the above. It should be understood that the directions referred to by the definition are for ease of explanation, the scope of the patent application scope of the present invention is not particularly limited by the description of such directions, and the concept of the up / down direction may be changed at any time.

The term "connect or connection" in this disclosure may not only be a direct connection, but also a concept including an indirect connection by an adhesive layer or the like. In addition, the term "electrically connected or electrically connected" means a concept including both physical connection and physical disconnection. In addition, the expressions "first", "second", and the like are used to distinguish each component and do not limit the order and / or importance of the components. In some cases, the first component may be referred to as a second component without departing from the spirit of the present invention, and similarly, the second component may also be referred to as a first component.

The use of the expression "exemplary embodiment" used in this disclosure does not all refer to the same embodiment, but can be provided to emphasize and explain different unique features. However, the above exemplary embodiments do not exclude that they are implemented in combination with the features of the other exemplary embodiments. For example, although a description in a particular exemplary embodiment may not be described in another exemplary embodiment, the description may be understood unless otherwise illustrated or contradicted by another exemplary embodiment. This is an explanation related to another exemplary embodiment.

The terminology used in this disclosure is only for illustrating exemplary embodiments and is not intended to limit the disclosure. At this time, unless clearly indicated otherwise in the context, singular expressions include plural expressions.

As one of the effects of a semiconductor package with a novel structure according to an exemplary embodiment of the present disclosure, a mounting area of a semiconductor wafer and a passive component can be significantly reduced, and an electrical path between the semiconductor wafer and the passive component can be significantly shortened, such as Process defects such as undulations and cracks can be significantly reduced, and in addition, the electrodes of the passive component can be easily connected to the connection vias by a laser-via-hole process or the like.

Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications may be made without departing from the scope of this disclosure as defined by the scope of the accompanying patent application. And variants.

100A‧‧‧semiconductor package / package module / semiconductor package module

100B, 100C, 100D, 100E, 100F, 100G, 1121‧‧‧ semiconductor package

105‧‧‧Core Structure

110‧‧‧Core components

110HA‧‧‧through hole

110HA1, 110HA2‧‧‧First through hole

110HB‧‧‧Second Through Hole

110HB'‧‧‧ preliminary second through hole

111‧‧‧core insulation

111a‧‧‧first core insulation layer / core insulation layer

111b‧‧‧Second core insulation layer / core insulation layer

111c‧‧‧third core insulation

112a, 142a‧‧‧First wiring layer / wiring layer

112b, 142b‧‧‧Second wiring layer / wiring layer

112c‧‧‧Third wiring layer / wiring layer

112d‧‧‧Fourth wiring layer

113‧‧‧Wiring Vias

113a‧‧‧First wiring through hole

113b‧‧‧Second wiring through hole

113c‧‧‧Third wiring through hole

115a‧‧‧metal layer / first metal layer

115b‧‧‧metal layer / second metal layer

115c‧‧‧metal layer / third metal layer

115d‧‧‧metal layer / fourth metal layer

115e‧‧‧Fifth metal layer

120, 2120, 2220‧‧‧ semiconductor wafer

121, 2121, 2221‧‧‧ Ontology

122, 2122, 2222‧‧‧ connecting pad

123, 2223‧‧‧ passivation film

125A1, 125A2‧‧‧Passive components

131‧‧‧The first encapsulation body / encapsulation body / encapsulation operation

132‧‧‧Second Encapsulation Body / Encapsulation Operation

133‧‧‧Back side metal through hole

133a‧‧‧First backside metal through hole

133b‧‧‧Second back side metal through hole

133s‧‧‧Back side wiring through hole

133v, 2243h‧‧‧ through hole

135‧‧‧Back side metal layer

135a‧‧‧first backside metal layer

135b‧‧‧Second back side metal layer

135s‧‧‧Back side wiring layer

140, 2140, 2240‧‧‧ connection structure

141a‧‧‧First insulation layer

141af, 150f‧‧‧ inorganic filler

141b‧‧‧Second insulation layer

143a‧‧‧First connection via / connection via

143b‧‧‧Second connection via / connection via

150, 2150, 2250 ‧‧‧ passivation layer

150v, 180v1, 180v2, 2251‧‧‧ opening

155‧‧‧Surface Mount Components

160, 2160, 2260‧‧‧ metal layer under bump

170, 190A, 190B‧‧‧ Electrical connection structure

180‧‧‧ Overlay

210‧‧‧The first adhesive film

220‧‧‧Second adhesive film

230‧‧‧ carrier film

500‧‧‧ panel

1000‧‧‧ electronic device

1010, 2500‧‧‧ Motherboard

1020‧‧‧Chip-related components

1030‧‧‧Network related components

1040, 1120‧‧‧ components

1050, 1130‧‧‧ Camera

1060‧‧‧antenna

1070‧‧‧Display

1080, 1180‧‧‧ battery

1090‧‧‧Signal line

1100‧‧‧Smartphone

1100A, 1100B‧‧‧ mobile device display

1101‧‧‧Body / Printed Circuit Board

1110, 2301, 2302‧‧‧ printed circuit boards

1150‧‧‧Module

2100‧‧‧fan-out semiconductor package

2130‧‧‧Encapsulation body

2141, 2241‧‧‧ Insulation

2142‧‧‧Wiring layer

2143, 2243‧‧‧through hole

2170, 2270‧‧‧ solder balls

2200‧‧‧fan-in semiconductor package

2242‧‧‧Wiring pattern

2280‧‧‧ underfill resin

2290‧‧‧Molding material

db, da1, da2‧‧‧ depth

s‧‧‧step difference

I-I ', II-II'‧‧‧ lines

Reading the following detailed description in conjunction with the drawings, the above and other aspects, features, and advantages of the present disclosure will be more clearly understood, in the drawings: FIG. 1 is a block diagram schematically illustrating an exemplary embodiment of an electronic device system . FIG. 2 is a perspective view schematically illustrating an exemplary embodiment of an electronic device. 3A and 3B are cross-sectional views schematically showing states of the fan-in semiconductor package before and after the package. FIG. 4 is a cross-sectional view schematically showing a packaging process of a fan-in semiconductor package. 5 is a cross-sectional view schematically showing a fan-in semiconductor package mounted on a printed circuit board and finally mounted on a main board of an electronic device. 6 is a cross-sectional view schematically showing a fan-in semiconductor package embedded in a printed circuit board and finally mounted on a main board of an electronic device. FIG. 7 is a cross-sectional view schematically showing a fan-out type semiconductor package. FIG. 8 is a cross-sectional view schematically showing a fan-out type semiconductor package mounted on a main board of an electronic device. FIG. 9 is a cross-sectional view schematically showing an exemplary embodiment of a semiconductor package. FIG. 10A is a schematic top view of the semiconductor package shown in FIG. 9, taken along a line II ′. FIG. 10B is a schematic top view of the semiconductor package shown in FIG. 9, taken along the line II-II ′. FIG. 11 is a cross-sectional view schematically showing an exemplary embodiment of a panel used in the semiconductor package shown in FIG. 9. 12A to 12E are schematic flowcharts illustrating an exemplary method of manufacturing the semiconductor package shown in FIG. 9. FIG. 13 is a cross-sectional view schematically showing another example of a semiconductor package. FIG. 14 is a cross-sectional view schematically showing another example of a semiconductor package. FIG. 15 is a cross-sectional view schematically showing another example of a semiconductor package. FIG. 16 is a cross-sectional view schematically showing another example of a semiconductor package. FIG. 17 is a cross-sectional view schematically showing another example of a semiconductor package. FIG. 18 is a cross-sectional view schematically showing another example of a semiconductor package. FIG. 19 is a plan view schematically showing an effect of implementing a semiconductor package according to the present disclosure in an electronic device.

Claims (32)

A semiconductor package includes: a connection structure including a first insulating layer, a second insulating layer that is lower than the first insulating layer in a thickness direction, and a second insulating layer located on the first insulating layer and the second insulating layer, respectively; A first wiring layer and a second wiring layer on the lower surface, and a first connection through-hole and a second connection through-hole passing through the first insulation layer and the second insulation layer, respectively; Said first insulating layer; a first through-hole passing through said core member; one or more passive components located in said first through-hole on said first insulating layer and communicating through said first connection One or more of the holes are connected to the first wiring layer; a first encapsulation body covering at least a portion of the passive component and filling at least a portion of the first through-hole; a second through-hole passing through the The core member and the first insulating layer; a semiconductor wafer located in the second through hole on the second insulating layer, and connected to the first through one or more of the second connection vias. Two wiring layers; and a second encapsulation body covering the half At least a portion of the wafer, and at least partially filling the second through-hole. The semiconductor package according to item 1 of the patent application scope, wherein a first depth of the second through hole in the thickness direction is greater than a second depth of the first through hole in the thickness direction. The semiconductor package according to item 1 of the patent application scope, wherein a second bottom surface of the second through-hole is lower than a first bottom surface of the first through-hole in the thickness direction. The semiconductor package according to item 3 of the scope of patent application, wherein the first bottom surface of the first through-hole is located at a first upper surface of the first insulating layer, and a location of the second through-hole is The second bottom surface is located at a second upper surface of the second insulating layer. The semiconductor package according to item 1 of the scope of patent application, wherein the semiconductor wafer has an active surface on which a connection pad connected to the second connection through-hole is disposed and a non-active surface opposite to the active surface, and The lower surface of the first wiring layer is substantially coplanar with the active surface of the semiconductor wafer. The semiconductor package according to item 1 of the scope of patent application, wherein the first insulating layer and the second insulating layer include materials different from each other. The semiconductor package according to item 6 of the scope of patent application, wherein the first insulating layer and the second insulating layer respectively include an inorganic filler and an insulating resin, and the inorganic filler included in the first insulating layer The first weight percentage of is greater than the second weight percentage of the inorganic filler contained in the second insulating layer. The semiconductor package according to item 6 of the scope of patent application, wherein the first insulating layer has a smaller coefficient of thermal expansion (CTE) than the second insulating layer. The semiconductor package according to item 6 of the scope of patent application, wherein the first insulating layer includes a non-photosensitive imaging dielectric material, and the second insulating layer includes a photosensitive imaging dielectric material. The semiconductor package according to item 1 of the scope of patent application, further comprising: a passivation layer located on a lower surface of the connection structure and having at least a portion of an opening exposing the second wiring layer; and a first electrical connection structure Is located on the opening of the passivation layer and is connected to the exposed portion of the second wiring layer. The semiconductor package according to item 10 of the scope of patent application, further comprising: one or more surface mount components located on the lower surface of the passivation layer and electrically connected to the semiconductor wafer via the connection structure. The semiconductor package according to item 1 of the scope of patent application, wherein the first encapsulation body covers an upper portion of the core member, and the second encapsulation body covers an upper portion of the first encapsulation body. The semiconductor package according to item 12 of the scope of patent application, wherein the core component includes a core insulation layer, is located on the first wall surface of the core insulation layer on which the first through hole is formed, and surrounds the passive component. A first metal layer of the component, a second metal layer on the second wall surface on which the second through hole is formed above the core insulating layer and surrounding the semiconductor wafer, and The third metal layer and the fourth metal layer on the lower surface and the upper surface; and wherein the first metal layer and the second metal layer are connected to the fourth metal layer. The semiconductor package according to item 13 of the scope of patent application, further comprising: a back-side metal layer on the second encapsulation body and covering the passive component and the inactive surface of the semiconductor wafer; and The side metal through hole passes through the first encapsulation body and the second encapsulation body, and connects the back metal layer to the fourth metal layer. The semiconductor package according to item 14 of the scope of patent application, wherein the backside metal via is a trench via having a predetermined length. The semiconductor package according to item 14 of the scope of patent application, further comprising a cover layer located on the second encapsulation body and covering the backside metal layer. The semiconductor package according to item 14 of the scope of patent application, further comprising: a cover layer on the second encapsulation body and having at least a portion of the opening exposing the back-side metal layer; and a second electrical connection structure Is located on the opening of the cover layer and is connected to the back-side metal layer that is exposed. The semiconductor package according to item 13 of the patent application scope, wherein a side surface of the second metal layer is substantially coplanar with a wall surface of the first encapsulation body at the second through hole and surrounds the The fifth metal layer of the semiconductor wafer is located on the side surface of the second metal layer and on the wall surface of the first encapsulation body at the second through hole. The semiconductor package according to item 18 of the scope of patent application, further comprising: a first backside metal layer located on the first encapsulation body, covering the passive component, and connected to the fifth metal layer; A backside metal through hole passes through the first encapsulation body and connects the first backside metal layer to the fourth metal layer. A second backside metal layer is located in the second encapsulation. And covers at least the semiconductor wafer; and a second back-side metal through hole passes through the second encapsulation body and connects the second back-side metal layer to the first back-side metal layer . The semiconductor package according to item 1 of the scope of patent application, wherein the core component includes a first core insulation layer, a first wiring layer and a second wiring located on a lower surface and an upper surface of the first core insulation layer, respectively. Layer, and a first wiring via that passes through the first core insulation layer and electrically connects the first wiring layer and the second wiring layer; and wherein the first wiring layer and the first wiring layer The two wiring layers are electrically connected to the connection pads of the semiconductor wafer. According to the semiconductor package of claim 20, wherein the core component further includes the lower surface and the upper surface of the first core insulation layer and covers the first wiring layer and the substrate, respectively. A second core insulation layer and a third core insulation layer of at least a part of the second wiring layer, a third wiring layer located on a lower surface of the second core insulation layer, and an upper surface of the third core insulation layer A fourth wiring layer thereon, a second wiring via that passes through the second core insulation layer and electrically connects the first wiring layer and the third wiring layer, and passes through the third core A third wiring via that is an insulating layer and electrically connects the second wiring layer and the fourth wiring layer; and wherein the third wiring layer and the fourth wiring layer are electrically connected to the semiconductor The connection pad of the wafer. The semiconductor package according to item 1 of the scope of patent application, wherein the core component includes a first core insulation layer contacting the connection structure, and a first wiring contacting the connection structure and embedded in the first core insulation layer. Layer, a second wiring layer opposite to a side on which the first wiring layer of the first core insulation layer is embedded, passing through the first core insulation layer and facing the first wiring layer and the first wiring layer A first wiring through-hole electrically connected by the two wiring layers, a second core insulating layer located on the first core insulating layer and covering at least part of the second wiring layer, located on the second core insulating layer A third wiring layer that passes through, and a second wiring via that passes through the second core insulation layer and electrically connects the second wiring layer and the third wiring layer; and the first wiring layer is up to The third wiring layer is electrically connected to a connection pad of the semiconductor wafer. A semiconductor package includes: a core member; a first through hole passing through the core member; a second through hole passing through the core member and spaced from the first through hole; one or more passive components, Located in the first through-hole; a semiconductor wafer located in the second through-hole, and having an active surface including a connection pad and a non-active surface opposite to the active surface; an encapsulation body covering the passive component And at least a part of each of the non-active surfaces of the semiconductor wafer, and filling at least a part of each of the first through-hole and the second through-hole; and a connection structure located in the The passive component and the active surface of the semiconductor wafer include at least one wiring layer electrically connected to the passive component and the connection pad of the semiconductor wafer, and wherein the The first bottom surface has a step with respect to the second bottom surface of the first through hole. The semiconductor package according to item 23 of the scope of patent application, wherein the passive components and the connection pads of the semiconductor wafer are respectively connected to different levels in the wiring layer of the connection structure via connection vias. Wiring layer. A semiconductor package includes: a core member having one or more first through holes and at least one second through hole; a first insulating layer located under the one or more first through holes; one or more passive components Is located in the one or more first through holes on the first insulation layer; a second insulation layer is located under the first insulation layer and under the second through holes; a semiconductor wafer is located in the In the at least one second through hole on the second insulating layer. The semiconductor package according to item 25 of the scope of patent application, further comprising: a first encapsulation body contacting the first insulating layer, covering at least a part of the one or more passive components, and covering the core component. At least a portion of the upper surface; and a second encapsulation body, which contacts the second insulating layer, covers at least a portion of the semiconductor wafer, and covers at least a portion of the first encapsulation body. The semiconductor package according to claim 25, wherein: the first insulating layer includes a non-photosensitive imaging dielectric material; and the second insulating layer includes a photosensitive imaging dielectric material. The semiconductor package according to item 25 of the scope of patent application, further comprising: a side metal layer on a side surface of the at least one second through hole containing the semiconductor wafer, and between the semiconductor wafer and the semiconductor wafer Between at least one of the one or more passive components; and an upper metal layer connected to the side metal layer, located on at least a portion of the core member, and located in the one or more passive components On at least part of said at least one. A method for manufacturing a semiconductor package includes: obtaining a core member having a first through-hole and a second through-hole; providing one or more passive components in the first through-hole; and on the one or more passive components And forming a first insulating layer on at least a portion of the core member; providing a semiconductor wafer in the second through hole; and forming a second insulating layer on the semiconductor wafer and on the first insulating layer. The method according to item 29 of the patent application scope, further comprising: after forming the first insulating layer and before forming the second insulating layer, forming a through-the first insulating layer and connecting to the first insulating layer One or more first conductive vias of the one or more passive components and one or more first conductive layers on the first insulation and connected to the one or more first conductive vias; and After the second insulating layer, one or more second conductive vias passing through the second insulating layer are formed, and the second insulating layer is located on the second insulating layer and is connected to the one or more second conductive vias. One or more second conductive layers, the one or more second conductive vias include one or more second conductive vias connected to the one or more first conductive layers, and are connected to the semiconductor One or more second conductive vias of the wafer. The method of claim 30, further comprising: before forming the first insulating layer, covering the one or more passive components and at least a portion of the core component with a first encapsulation body; and Before forming the second insulating layer, at least a part of the semiconductor wafer and the first encapsulation body are covered with a second encapsulation body. The method according to item 31 of the scope of patent application, further comprising: forming one or more third portions that pass through the first encapsulation body and the second encapsulation body and are connected to corresponding portions of the core member. A conductive via and one or more third conductive layers on the second encapsulation body, wherein the core member includes a conductively connecting the first conductive via to the third conductive via Or multiple metal layers.