TW201939679A - Wiring board having component integrated with leadframe and method of making the same - Google Patents

Abstract

The circuit board of the present invention includes an electrical component, a lead frame, a first build-up circuit and a second build-up circuit, wherein the lead frame surrounds the electrical component laterally, and the first and second build-up circuits are provided on the lead frame. The space surrounds the side and extends to the lead frame. The electrical component includes a semiconductor component, a first routing circuit, and a sealing material integrated into a whole, and may optionally further include a series of vertical connectors and a second routing circuit. The first routing circuit can provide primary routing for the semiconductor elements, and the first and second build-up circuits not only provide further routing, it can also mechanically bond the electrical components with the lead frame. The lead frame provides electrical connection between the first build-up circuit and the second build-up circuit.

Description

Circuit board with integrated components and lead frame and manufacturing method thereof

The invention relates to a circuit board, in particular to a circuit board integrating components and a lead frame, and a manufacturing method thereof.

In order to integrate mobile, communication and computing functions, the semiconductor packaging industry is facing great challenges in terms of bulk performance and size. Various packaging technologies have been widely developed, such as ball grid array packages (BGA), quad flat no-lead packages (QFN), and wafer-level packages (WLP), but no technology has been developed to meet the high-performance requirements at cost . For example, the design concept of a micro ball grid array package (microBGA) or a quad flat no-lead package (QFN) uses a rugged metal frame combined with conventional wire bonding technology to reduce size and cost. Due to the limited winding capabilities of etched metal leads, QFN or microBGA packages are not suitable for high-performance, high-input / output (I / O) components.

Integrating electrical components (such as resistors, capacitors, inductors, memory chips or logic chips) into circuit boards can greatly improve the electrical performance of semiconductor assemblies and reduce their size. US Patent Nos. 8,453,323, 8,525,337, 8,618,652, and 8,836,114 disclose various circuit boards based on this purpose. However, due to the lack of strong support of resin-based circuit boards, embedded components with mismatched thermal expansion coefficients will instead lead to poor results and cause serious problems on warpage control and misalignment issues. In addition, since the vertical connection pieces of these circuit boards are usually conductive vias or staggered metallized blind holes, major problems such as signal transmission interruption and poor reliability may occur.

For the above reasons and other reasons described below, there is an urgent need to develop a new type of circuit board with embedded components that integrates the embedded components with the surrounding lead frame to ensure ultra-high package density and high signal integrity And low warpage requirements.

The main object of the present invention is to provide a core substrate of a circuit board, which is provided with a lead frame surrounding the electrical components, and the electrical components include a first routing circuit, an embedded component and a sealing material, and can be selectively It also includes a series of vertical connectors and a second routing circuit. Since the metal leads of the surrounding lead frame can increase the rigidity of the core substrate, the problem of board warpage can be reduced, thereby improving the production yield and device-level reliability.

The circuit board of the present invention further includes a first layer-increasing circuit and a second layer-increasing circuit, which are respectively disposed on two sides of the core substrate. The first routing circuit and the first build-up circuit can provide two-level horizontal routing for embedded components, and the metal lead of the lead frame can provide vertical connection channels for the first and second build-up circuits, thereby improving the semiconductor assembly. Design flexibility, signal integrity and electrical characteristics.

According to the above and other objectives, the present invention provides a circuit board, which includes a first routing circuit, a semiconductor element, a sealing material, a series of optional vertical connectors, a second routing circuit of optional, and a lead frame. A first layer-increasing circuit and a second layer-increasing circuit. Here, the first routing circuit, the semiconductor element, the sealing material, the optional vertical connection member and the optional second routing circuit are integrated into an electrical component, and the lead frame surrounds the electrical component. In a preferred embodiment, the lead frame located around the peripheral edge of the electrical component can provide metal leads as a vertical connection channel between the first build-up circuit and the second build-up circuit; The semiconductor components on the routing circuit are buried in the sealing material; the first routing circuit adjacent to one side of the sealing material can provide primary routing / interconnection to the semiconductor components; the optional second routing circuit adjacent to the other side of the sealing material can provide Further routing / interconnection; the selective vertical connection between the first routing circuit and the second routing circuit can provide the electrical connection between the first routing circuit and the second routing circuit; the electrical components and the lead frame are opposite to each other The first build-up circuit and the second build-up circuit on both sides can be electrically connected to each other through the lead wires of the lead frame, and the electrical components can be mechanically bonded to the lead frame and provide further fan-out routing.

In another aspect, the present invention provides a circuit board including: an electrical component including a semiconductor component, a first routing circuit, and a sealing material, wherein the semiconductor component is electrically coupled to the first The routing circuit is covered laterally by a sealing material, and the sealing material has a first surface facing the first routing circuit and a second surface opposite to the first surface; a lead frame which surrounds the electrical component laterally and includes A plurality of metal leads and a bonding resin, wherein the bonding resin fills the space between the metal leads; a first build-up circuit, which is arranged on the first routing circuit and extends laterally on the lead frame, wherein the first build-up layer The circuit includes at least one dielectric layer and at least one circuit layer that are alternately formed, and the circuit layer of the first build-up circuit is electrically coupled to the first routing circuit and the metal lead; and a second build-up circuit that is disposed on the seal The second build-up circuit includes at least one dielectric layer and at least one circuit layer that are alternately formed, and the circuit layer of the second build-up circuit is electrically coupled to It is a lead.

In yet another aspect, the present invention provides a method for manufacturing a circuit board, which includes the following steps: providing an electrical component including a semiconductor component, a first routing circuit, and a sealing material, wherein the semiconductor component is electrically conductive Is coupled to the first routing circuit and is covered laterally by a sealing material, and the sealing material has a first surface facing the first routing circuit and a second surface opposite to the first surface; a lead frame is provided, the side frame surrounds The electrical component includes a plurality of metal leads and a bonding resin, wherein the bonding resin fills a space between the metal leads; a first build-up circuit is formed on the first routing circuit and extends laterally on the lead frame Wherein the first build-up circuit includes at least one dielectric layer and at least one circuit layer that are alternately formed, and the line layer of the first build-up circuit is electrically coupled to the first routing circuit and the metal lead; and forming a second The build-up circuit is disposed on the second surface of the sealing material and extends laterally on the lead frame. The second build-up circuit includes at least one dielectric layer and at least one circuit layer that are alternately formed. A second wiring layer of the build-up circuits coupled to the metal leads.

The order of the above steps is not limited to those listed above, and can be changed or re-arranged according to the required design, unless the word "next" is specifically described or used between steps, or the steps must occur sequentially.

The method for manufacturing a circuit board of the present invention has many advantages. For example, it is particularly advantageous to form a lead frame that surrounds electrical components because the metal leads of the lead frame can provide horizontal routing and a vertical connection path between the first build-up circuit and the second build-up circuit. The combination of the electrical component and the lead frame can provide a stable platform for the first layer-increasing circuit and the second layer-increasing circuit to be formed thereon. The method of forming a sealing material on the first routing circuit can provide a high-modulus bending-resistant platform for the circuit board, so that the mechanical strength of the sealing material and the lead frame can avoid warping after removing the sacrificial carrier board. In addition, when it is necessary to form a multilayer routing circuit, the method of forming a circuit board through multiple stages can avoid serious bending problems.

The above and other features and advantages of the present invention can be made clearer by the following detailed description of the preferred embodiments.

In the following, an embodiment will be provided to explain the implementation of the present invention in detail. The advantages and effects of the present invention will be more significant by the content disclosed by the present invention. The attached drawings are simplified and used for illustration. The number, shape and size of the components shown in the drawings can be modified according to the actual situation, and the configuration of the components may be more complicated. The present invention can also be practiced or applied in other aspects, and various changes and adjustments can be made without departing from the spirit and scope defined by the present invention.

[Example 1]

1-25 is a diagram of a method for manufacturing an uncut circuit board in a first embodiment of the present invention, which includes an electrical component, a lead frame, a first layer-increasing circuit and a second layer-increasing circuit.

1 and 2 are a cross-sectional view and a top perspective view of a routing layer 211 formed on the sacrificial carrier 10, respectively. The routing layer 211 is formed by a metal deposition and metal patterning process. The sacrificial carrier plate 10 is generally made of copper, aluminum, iron, nickel, tin, stainless steel, silicon, or other metals or alloys, but any other conductive or non-conductive material may be used. The thickness of the sacrificial carrier plate 10 is preferably in the range of 0.1 to 2.0 mm. In this embodiment, the sacrificial carrier plate 10 is made of an iron-containing material and has a thickness of 1.0 mm. The routing layer 211 is usually made of copper and can be patterned and deposited by various techniques, such as electroplating, electroless plating, evaporation, sputtering, or a combination thereof, or formed by thin film deposition followed by a metal patterning step. . As for the sacrificial carrier 10 having conductivity, it is generally deposited by metal plating to form the routing line layer 211. The metal patterning technology includes wet etching, electrochemical etching, laser-assisted etching, and combinations thereof, and uses an etching mask (not shown) to define the routing layer 211.

3 and 4 are a cross-sectional view and a top perspective view of the multilayer dielectric layer 214 and the multilayer wire layer 216 formed alternately, respectively. The dielectric layer 214 can be generally deposited by lamination or coating, and can be made of epoxy resin, glass epoxy resin, polyimide, or the like. The wire layer 216 extends laterally on the dielectric layer 214 and includes a metallized blind hole 218 in the dielectric layer 214. Therefore, the conductive layers 216 can be electrically coupled to each other through the metallized blind holes 218. Similarly, the innermost wire layer 216 may be electrically coupled to the routing layer 211 through the metallized blind hole 218.

Each wire layer 216 may be deposited as a single layer or multiple layers by various techniques, such as electroplating, electroless plating, evaporation, sputtering, or a combination thereof. For example, the wiring layer 216 may be deposited in the following manner. First, the structure is immersed in an activator solution to cause a dielectric reaction between the dielectric layer 214 and electroless copper, and then a thin copper layer is coated by electroless plating as a seed layer, and then the required thickness of the layer is electroplated. A second copper layer is formed on the seed layer. Alternatively, before depositing the electroplated copper layer on the seed layer, the seed layer may be formed as a titanium / copper seed layer film by sputtering. Once the desired thickness is achieved, the coating layer can be patterned using various techniques to form the wire layer 216, which includes wet etching, electrochemical etching, laser-assisted etching, and combinations thereof, and uses an etching mask (not shown) To define the wire layer 216.

This stage has completed the fabrication of the first routing circuit 21 on the sacrificial carrier board 10. In this figure, the first routing circuit 21 includes a routing layer 211, a dielectric layer 214, and a wire layer 216.

FIG. 5 is a cross-sectional view of an array-type vertical connection member 23 formed on the first routing circuit 21. In this figure, the vertical connecting members 23 are shown as metal pillars, and are electrically connected to the outermost conductive layer 216 of the first routing circuit 21 and are in contact with the outermost conductive layer 216.

FIG. 6 is a cross-sectional view of the semiconductor device 25 electrically coupled to the first routing circuit 21. The semiconductor element 25 (shown as a bare chip) can be electrically coupled to the outermost wire layer 216 of the first routing circuit 21 through a bump 253 by thermal compression, reflow, or thermal ultrasonic bonding technology.

FIG. 7 is a cross-sectional view of the sealing material 27 formed on the vertical connection member 23, the semiconductor element 25, and the first routing circuit 21. The sealing material 27 can be formed by, for example, resin-glass lamination, resin-glass coating or molding ( forming). The sealing material 27 covers the vertical connecting member 23, the semiconductor element 25, and the first routing circuit 21 from above, and surrounds and uniformly covers and covers the sidewalls of the vertical connecting member 23 and the semiconductor element 25.

FIG. 8 is a cross-sectional view of the vertical connecting member 23 exposed from above. The upper region of the sealing material 27 can be removed by grinding. In this figure, the exposed surfaces of the vertical connectors 23 are substantially coplanar with the outer surface of the sealing material 27 above.

FIG. 9 is a cross-sectional view of a routing layer 291 formed on the sealing material 27 and electrically coupled to the vertical connection member 23, wherein the routing layer 291 is made by a metal pattern deposition method as described below. First, the top surface of the structure can be metallized by various techniques (such as electroplating, electroless plating, evaporation, sputtering, or a combination thereof) to form a single-layer or multi-layer conductive layer (usually a copper layer). The conductive layer may be made of Cu, Ni, Ti, Au, Ag, Al, a combination thereof, or other suitable conductive materials. Generally, a seed layer is formed on the topmost surface of the structure before the conductive layer is plated to a desired thickness. The seed layer can be formed by a diffusion resistance layer and a plating bus layer. The diffusion resistance layer is used to offset oxidation or erosion of the conductive layer (such as copper). In most examples, the diffusion barrier layer can also be used as an adhesion enhancement layer for the underlying material, and can be formed by physical vapor deposition (PVD). For example, Ti can be formed by sputtering to a thickness of about 0.01 μm to 0.1 μm Or TiW layer. However, the diffusion barrier layer can also be made of other materials, such as TaN or other suitable materials, and its thickness is not limited to the above range. The plating carrier layer is usually made of the same material as the conductive layer and has a thickness ranging from about 0.1 μm to 1 μm. For example, when the conductive layer is copper, the plating carrier layer is preferably a copper thin film made by physical vapor deposition or electroless plating. However, the electroplated support layer can also be made of other suitable materials, such as silver, gold, chromium, nickel, tungsten, or a combination thereof, and its thickness is not limited to the above range.

After the seed layer is deposited, a photoresist layer (not shown) is formed on the seed layer. The photoresist layer can be formed by a wet process (such as a spin coating process) or a dry process (such as a lamination dry film). After the photoresist layer is formed, the photoresist layer is patterned to form openings, and then the openings are filled with a covering metal (such as copper) to form a routing layer 291. After the metal is plated, the exposed seed layer is removed through an etching process to form conductive wires that are electrically isolated from each other.

FIG. 10 is a cross-sectional view in which the dielectric layers 294 and the wire layers 296 are alternately formed. The dielectric layer 294 contacts the sealing material 27 and the routing layer 219, is covered from above and extends laterally on the sealing material 27 and the routing layer 219. The wire layer 296 extends laterally on the dielectric layer 294 and includes a metallized blind hole 298 in the dielectric layer 294. Therefore, the wire layer 296 can be electrically coupled to the routing layer 291 through the metallized blind hole 298.

At this stage, the production of the second routing circuit 29 has been completed, and it is electrically connected to the first routing circuit 21 through the vertical connection member 23. In this figure, the second routing circuit 29 includes a routing layer 291, a dielectric layer 294, and a wire layer 296.

FIG. 11 is a sectional view with the sacrificial carrier 10 removed. The sacrificial carrier 10 can be removed in various ways to reveal the first routing circuit 21 from below, which includes wet etching using an acidic solution (such as ferric chloride, copper sulfate solution) or an alkaline solution (such as an ammonia solution), Electrochemical etching, or chemical etching after mechanical means (such as drilling or end milling). In this embodiment, the sacrificial carrier 10 made of an iron-containing material can be removed by a chemical etching solution, wherein the chemical etching solution is selective between copper and iron to avoid removing the sacrificial carrier 10 As a result, the copper routing layer 211 is etched.

FIG. 12 is a cross-sectional view of the panel size structure of FIG. 11 cut into individual pieces. As shown in the figure, the panel size structure is separated into individual electrical components 20 along the cutting line “L”.

FIG. 13 is a cross-sectional view of an individual electrical component 20, which includes a first routing circuit 21, a vertical connection 23, a semiconductor element 25, a sealing material 27, and a second routing circuit 29. In this figure, the first routing circuit 21 and the second routing circuit 29 are multilayer build-up routing circuits, which are respectively located on opposite sides of the sealing material 27 and are electrically connected to each other through a vertical connection member 23. The first routing circuit 21 is located on the first surface 271 of the sealing material 27, and the second routing circuit 29 is located on the second surface 272 of the sealing material 27. The semiconductor element 25 is embedded in the sealing material 27 and is electrically coupled to the first routing circuit 21. The vertical connectors 23 are buried in the sealing material 27 and surround the semiconductor element 25, and extend from the first routing circuit 21 to the second surface 272 of the sealing material 27. The second routing circuit 29 is electrically coupled to the vertical connection member 23, and therefore can be electrically connected to the first routing circuit 21 through the vertical connection member 23.

14 and 15 are a sectional view and a top perspective view of the patterned metal plate 31, respectively. The patterned metal plate 31 is generally made of a copper alloy, steel, or alloy 42, which can be formed by a wet etching or stamping / punching process on a rolled metal strip. Wherein the rolled metal strip has a thickness ranging from about 0.15 mm to about 1.0 mm. Here, an etching process may be performed on one or both sides to etch through the metal strip, and the metal strip is made into a patterned metal plate 31 having a predetermined entire pattern, which includes a metal frame 32, a plurality of metal leads 33, and a metal block. 35 and plural coupling rods 36. The metal leads 33 extend laterally from the metal frame 32 toward a central region in the metal frame 32. Therefore, each metal lead 33 has an outer end 331 and an inner end 333. The outer end 331 of the metal lead 33 is integrally connected to the inner side wall of the metal frame 32, and the inner end 333 of the metal lead 33 faces away from the inside. Metal frame 32. The metal block 35 is located in a central region within the metal frame 32 and is connected to the metal frame 32 by a connecting rod 36. In addition, the specific embodiment further performs a selective half-etching process from the bottom side of the patterned metal plate 31. Accordingly, the metal leads 33 have a stepped peripheral edge, and each metal lead 33 has a horizontally extending portion 336 and a vertically protruding portion 337. The vertical protruding portion 337 is directed downward and protrudes from the lower surface of the horizontally extending portion 336.

16 and 17 are a cross-sectional view and a top perspective view of the bonding resin 38, respectively. The bonding resin 38 can be formed by applying a resin material to the remaining space in the metal frame 32 and filling the space between the metal leads 33 and the space between the metal block 35 and the metal leads 33. The resin material can be applied by paste printing, compressive molding, transfer molding, liquid injection molding, spin coating, or other suitable methods. Formed by cloth. Next, a heat treatment (or a thermosetting process) is performed to harden the resin material to convert the resin material into a solid molding compound. Accordingly, the bonding resin 38 covers the lower surface of the horizontally extending portion 336, the side wall of the vertical protruding portion 337, and the side wall of the metal block 35. Since the metal lead 33 has a stepped cross-sectional profile, the bonding resin 38 can be firmly bonded to the metal lead 133 to prevent the metal lead 33 from detaching from the bonding resin 38 in a vertical direction, and to prevent a vertical crack at the interface. . In this figure, through the planarization step, the top surface of the bonding resin 38 is substantially coplanar with the top sides of the metal leads 33 and the metal blocks 35, and the bottom surface of the bonding resin 38 is the metal leads 33 and the metal blocks 35. The bottom sides are substantially coplanar.

The bonding resin 38 generally includes a bonding resin, a filler, a hardener, a diluent, and an additive. The bonding resin used in the present invention is not particularly limited. For example, the adhesive resin can be selected from epoxy resin, phenol resin, polyimide resin, polyurethane resin, silicone resin, polyester resin, acrylic resin, and bismaleimide. , BMI) at least one of the groups of resins and their equivalents. Adhesive resin can provide close adhesion between the adhesive and the filler. The adhesive resin can also be linked by a chain of fillers to provide thermal conductivity. In addition, the binding resin can also improve the physical and chemical stability of the molding compound.

In addition, the filler used in the present invention is not particularly limited. For example, a thermally conductive filler can be used, which is selected from the group consisting of alumina, aluminum nitride, silicon carbide, tungsten carbide, boron carbide, silicon dioxide, and their equivalents. More specifically, if an appropriate filler is dispersed therein, the bonding resin 38 can become thermally conductive or have a low coefficient of thermal expansion (CTE). For example, aluminum nitride (AlN) or silicon carbide (SiC) has a relatively high thermal conductivity, a relatively high electrical resistance, and a relatively low thermal expansion coefficient. Accordingly, when such a material is used as a filler in the bonding resin 38, the bonding resin 38 can exhibit better heat dissipation efficiency and electrical insulation performance, and its low CTE characteristic can prevent peeling or cracking of the circuit or interface. The maximum particle diameter of the thermally conductive filler can be 25 μm or less. The content of the filler can be in the range of 10 to 90 weight percent. If the content of the thermally conductive filler is less than 10% by weight, the thermal conductivity may be insufficient and the viscosity may be too low. Low viscosity means that during coating or molding, the resin is too easy to flow out of the tool, making the process difficult to operate and control. On the other hand, if the content of the filler is more than 90% by weight, the adhesive strength of the molding material may be reduced, and the viscosity may be too high. High-viscosity molding materials have poor workability because the resin cannot flow out of the tool during coating or molding. In addition, the bonding resin 38 may include more than one filler. For example, polytetrafluoroethylene (PTFE) can be used as the second filler to further improve the electrical insulation characteristics of the bonding resin 38. In short, the bonding resin 38 preferably has an elastic modulus of more than 1.0 GPa and a linear thermal expansion coefficient in a range of about 5 x 10 ^-6 K ^-1 to 15 x 10 ^-6 K ^-1 .

18 and 19 are a cross-sectional view and a top perspective view after the metal block 35 is removed, respectively. Various techniques can be used to remove the entire metal block 35, such as wet etching, electrochemical etching, or laser, thereby forming a through opening 305, wherein the through opening 305 extends from the top surface to the bottom surface of the bonding resin 38. Accordingly, the uncut lead frame 30 has been completed at this stage, and includes a metal frame 32, metal leads 33, a connecting rod 36, and a bonding resin 38.

FIG. 20 is a cross-sectional view of the electrical component 20 inserted into the lead frame 30 through the opening 305. Here, the inner side wall surface 309 of the bonding resin 38 is adjacent to the peripheral edge of the electrical component 20, but keeps a distance from the peripheral edge of the electrical component 20. Therefore, there is a gap 307 in the through opening 305 between the electrical component 20 and the lead frame 30. The lead frame 30 surrounds the gap 307 laterally, and the gap 307 surrounds the electrical component 20 laterally.

FIG. 21 is a cross-sectional view of the first dielectric layer 411 and the second dielectric layer 511 laminated or coated on the electrical component 20 and the lead frame 30 from above and below, respectively. The first dielectric layer 411 is covered from above and contacts the first routing circuit 21 and the lead frame 30, and the second dielectric layer 511 is covered from below and contacts the second routing circuit 29 and the lead frame 30. In addition, the first dielectric layer 411 and the second dielectric layer 511 further extend into the gap 307 between the electrical component 20 and the lead frame 30. Therefore, the inner sidewall surface 309 of the bonding resin 38 can be bonded to the peripheral edge of the electrical component 20 through the first dielectric layer 411 and the second dielectric layer 511. The first dielectric layer 411 and the second dielectric layer 511 may be made of epoxy resin, glass epoxy resin, polyimide, or the like, and generally have a thickness of 50 micrometers.

22 is a cross-sectional view of a first blind hole 413 formed in the first dielectric layer 411 and a second blind hole 513 formed in the second dielectric layer 511. The first blind hole 413 extends through the first dielectric layer 411 and is aligned with a selected portion of the routing layer 211 and the metal lead 33 of the first routing circuit 21. The second blind hole 513 extends through the second dielectric layer 511 and is aligned with the selected portion of the wire layer 296 and the metal lead 33 of the second routing circuit 29. The first blind hole 413 and the second blind hole 513 can be formed by various technologies, including laser drilling, plasma etching, and lithography, and usually have a diameter of 50 microns. Pulse lasers can be used to improve laser drilling performance. Alternatively, a scanning laser beam can be used with a metal mask.

Referring to FIG. 23, a first circuit layer 415 and a second circuit layer 515 are formed on the first dielectric layer 411 and the second dielectric layer 511 by a metal deposition and metal patterning process, respectively. The first circuit layer 415 extends upward from the routing layer 211 of the first routing circuit 21 and the horizontal extension portion 336 of the metal lead 33 and fills the first blind hole 413 to form a direct contact with the first routing circuit 21 and the metal lead 33. The first metallized blind hole 417 also extends laterally on the first dielectric layer 411. The second circuit layer 515 extends downward from the wire layer 296 of the second routing circuit 29 and the vertical protruding portion 337 of the metal lead 33 and fills the second blind hole 513 to form direct contact with the second routing circuit 29 and the metal lead. The second metallized blind hole 517 of 33 also extends laterally on the second dielectric layer 511.

FIG. 24 is a cross-sectional view of forming the third dielectric layer 431, the fourth dielectric layer 531, the third blind hole 433, and the fourth blind hole 533, in which the third dielectric layer 431 and the fourth dielectric layer 531 are laminated or Coated on the first dielectric layer 411 / first circuit layer 415 and the second dielectric layer 511 / second circuit layer 515, and the third blind hole 433 and the fourth blind hole 533 are formed on the third dielectric layer, respectively. 431 and the fourth dielectric layer 531. The third dielectric layer 431 contacts and covers the first dielectric layer 411 / the first wiring layer 415. The fourth dielectric layer 531 contacts and covers the second dielectric layer 511 / the second wiring layer 515. The third dielectric layer 431 and the fourth dielectric layer 531 may be made of epoxy resin, glass epoxy resin, polyimide, or the like, and generally have a thickness of 50 micrometers. After the third dielectric layer 431 and the fourth dielectric layer 531 are deposited, a third blind hole 433 and a fourth blind hole 533 are formed to expose the selection of the first wiring layer 415 and the second wiring layer 515 from above and below, respectively. section. The third blind hole 433 extends through the third dielectric layer 431 and is aligned with a selected portion of the first circuit layer 415. The fourth blind hole 533 extends through the fourth dielectric layer 531 and is aligned with a selected portion of the second circuit layer 515. As described in the first blind hole 413 and the second blind hole 513, the third blind hole 433 and the fourth blind hole 533 can also be formed by various technologies, including laser drilling, plasma etching, and lithography, and It usually has a diameter of 50 microns.

FIG. 25 is a cross-sectional view of forming the third wiring layer 435 and the fourth wiring layer 535, wherein the third wiring layer 435 and the fourth wiring layer 535 can be formed on the third dielectric layer 431 and the metal patterning process, respectively. On the fourth dielectric layer 531. The third circuit layer 435 extends upward from the first circuit layer 415 and fills the third blind hole 433 to form a third metallized blind hole 437 directly contacting the first circuit layer 415, and at the same time extends laterally on the third intermediary. Electrical layer 431. The fourth circuit layer 535 extends downward from the second circuit layer 515 and fills the fourth blind hole 533 to form a fourth metallized blind hole 537 directly contacting the second circuit layer 515, and at the same time extends laterally on the fourth interface. On the electrical layer 531. Therefore, the first build-up circuit 40 and the second build-up circuit 50 are formed on opposite sides of the electrical component 20 and the lead frame 30, respectively. In this figure, the first build-up circuit 40 includes a first dielectric layer 411, a first circuit layer 415, a third dielectric layer 431, and a third circuit layer 435, and the second build-up circuit 50 includes a second dielectric Layer 511, second circuit layer 515, fourth dielectric layer 531, and fourth circuit layer 535. At this stage, the production of the uncut circuit board 100 has been completed, which includes the electrical component 20, the lead frame 30, the first layer-increasing circuit 40 and the second layer-increasing circuit 50.

26 is a cross-sectional view of the printed circuit board 100 after the metal frame 32, part of the first build-up circuit 40 and part of the second build-up circuit 50 are removed. After the metal frame 32 is separated from the metal lead 33, the outer end 331 of the metal lead 33 is located at the peripheral edge of the circuit board 100 after cutting, and the side of the outer end 331 of the metal lead 33 is flush with the peripheral edge of the bonding resin 38.

FIG. 27 is a cross-sectional view of the semiconductor group body 110. The top semiconductor element 61 is electrically coupled to the circuit board 100 shown in FIG. The top semiconductor element 61 (illustrated as a wafer) is connected to the first build-up circuit 40 through the conductive bump 613 and is electrically coupled to the third circuit layer 435.

FIG. 28 is a cross-sectional view of another semiconductor group 120. The top semiconductor element 61 is electrically coupled to the circuit board 100 shown in FIG. 26, and is thermally conducted to the heat sink 81. The top semiconductor elements 61 are connected to the first build-up circuit 40 through conductive bumps 613. The heat sink 81 can be made of any material with high thermal conductivity, such as metal, alloy, silicon, ceramic or graphite, and is attached to the top semiconductor element 61 for heat dissipation.

FIG. 29 is a cross-sectional view of still another semiconductor group 130. The top semiconductor element 61, the passive element 63, the bottom semiconductor element 62, and the solder ball 75 are electrically coupled to the circuit board 100 shown in FIG. The top semiconductor element 61 is electrically coupled to the first build-up circuit 40, and the bottom semiconductor element 65 is electrically coupled to the second build-up circuit 50. Therefore, the top semiconductor element 61 and the bottom semiconductor element 65 can be electrically connected to each other through the electrical element 20, the lead frame 30, the first build-up circuit 40 and the second build-up circuit 50. To achieve heat dissipation, a heat sink 81 can be attached to the top semiconductor element 61. In addition, the passive element 63 is connected to the third circuit layer 435 of the first build-up circuit 40 to improve electrical performance, and the solder ball 75 is connected to the fourth circuit layer 535 of the second build-up circuit 50. Connect with the following level.

[Example 2]

FIG. 30 is a cross-sectional view of another circuit board in a second embodiment of the present invention.

For the purpose of brief description, any description that can be used for the same application in the above embodiment 1 is incorporated herein, and it is not necessary to repeat the same description.

The electrical component 20 of the circuit board 200 is similar to the structure shown in FIG. 13. The difference is that the sealing material 27 is not provided with a vertical connector, and does not have a second routing line electrically coupled to the second build-up circuit 50. Therefore, the first build-up circuit 40 and the second build-up circuit 50 are electrically connected to each other through the metal leads 33 of the lead frame 30.

FIG. 31 is a cross-sectional view of the semiconductor group 210, and the top semiconductor element 61 is electrically coupled to the circuit board 200 shown in FIG. 30. The top semiconductor element 61 is connected to the first build-up circuit 40 through the conductive bump 613, so as to be electrically connected to the embedding material 27 through the first build-up circuit 40 and the first routing circuit 21. Of semiconductor element 25.

[Example 3]

32 is a cross-sectional view of another circuit board in a third embodiment of the present invention.

For the purpose of brief description, any description that can be used for the same application in the above embodiments is incorporated herein, and it is not necessary to repeat the same description.

The electrical component 20 of the circuit board 300 is similar to the structure shown in FIG. 13. The difference is that a second routing circuit is not provided between the sealing material 27 and the second build-up circuit 20. Therefore, the second build-up circuit 50 is directly and electrically coupled to the vertical connection member 23 through the second metallization blind hole 517 in contact with the vertical connection member 23.

[Example 4]

33 is a cross-sectional view of another circuit board in a fourth embodiment of the present invention.

For the purpose of brief description, any description that can be used for the same application in the above embodiments is incorporated herein, and it is not necessary to repeat the same description.

The circuit board 400 is similar to the structure shown in FIG. 32. The difference is that the electrical component 20 further includes a heat sink 26 attached to the non-active surface of the semiconductor component 25. The heat sink 26 is in thermal contact with the second build-up circuit 50 through an additional second metallized blind hole 518 that is in contact with the heat sink 26 and serves as a heat pipe. Accordingly, the heat generated by the semiconductor element 25 can be dissipated through the heat sink 26 and the second build-up circuit 50.

The above-mentioned circuit boards and assemblies are merely illustrative examples, and the present invention can be implemented through various other embodiments. In addition, the above embodiments may be mixed and used with each other or with other embodiments based on design and reliability considerations. For example, the circuit board may include a plurality of electrical components arranged in an array shape. In addition, the first build-up circuit and the second build-up circuit may also include additional wires to receive and connect additional electrical components.

As shown in the above embodiment, the present invention constructs a unique circuit board that can exhibit better reliability, which includes an electrical component, a lead frame, a first build-up circuit and a second build-up circuit. In a preferred embodiment, the electrical component includes a first routing circuit, a semiconductor component and a sealing material, and optionally further includes a vertical connection member and a second routing circuit. The first routing circuit and the optional second routing circuit are disposed in the space surrounded by the lead frame, and the first layer-increasing circuit and the second layer-increasing circuit are disposed outside the space surrounded by the lead frame and extend laterally respectively. To the opposite sides of the lead frame. For the convenience of the following description, the direction facing the first surface of the sealing material is defined as the first direction, and the direction facing the second surface of the sealing material is defined as the second direction. The first routing circuit is disposed adjacent to the first surface of the sealing material, and the second routing circuit is disposed adjacent to the second surface of the sealing material.

The semiconductor device may be a packaged or unpackaged wafer. For example, the semiconductor device may be a bare wafer, or a wafer-level package die. Alternatively, the semiconductor element may be a stacked wafer. In a preferred embodiment, the semiconductor device is electrically coupled to the first routing circuit (the first routing circuit is detachably connected to a sacrificial carrier board), and is selectively connected by a vertical connector. The side is surrounded, then a sealing material is provided on the first routing circuit, and a second routing circuit is selectively formed on the sealing material, and then the sacrificial carrier is removed to form an electrical component. In this aspect, the semiconductor element may be electrically coupled to the first routing circuit through a bump, and an active surface thereof faces the first routing circuit. Preferably, the electrical components are prepared together in a panel size and then cut into individual pieces. In addition, a heat sink can be attached to the semiconductor device before the sealing material is provided. Accordingly, the heat generated by the semiconductor element can be dissipated outward through the heat sink.

The optional vertical connection members can be covered laterally by the sealing material to provide electrical contacts for lower-level circuit connections, and the thickness of the vertical connection members can be substantially equal to or less than the thickness of the sealing material. In a preferred embodiment, the selective vertical connections are located between the first routing circuit and the second routing circuit, and the opposite sides of the vertical connection are electrically coupled to the first routing circuit and the second routing circuit. Routing circuit. Or, in another preferred embodiment, the second routing circuit is not formed on the second surface of the sealing material, and the vertical connection member is located between the first routing circuit and the second build-up circuit and is electrically coupled. Connected to the first routing circuit and the second build-up circuit.

The first routing circuit may be a multilayer build-up circuit without a core layer, which includes at least one dielectric layer and at least one wire layer, wherein the wire layer includes a metallized blind hole in the dielectric layer and extends laterally in the dielectric On the electrical layer. The dielectric layer and the wire layer are continuously formed alternately, and can be formed repeatedly if necessary. For example, the first routing circuit may include a routing layer, a dielectric layer, and a wire layer. The routing layer is located on the sacrificial carrier board, the dielectric layer is located on the routing layer and the sacrificial carrier board, and the wire layer is formed by the routing layer. A selected portion extends through the dielectric layer to form a metallized blind hole, while extending laterally on the dielectric layer. If more signal routing is needed, the first routing circuit may further include an additional dielectric layer and an additional wire layer. In the present invention, the first routing circuit may be formed directly on the sacrificial carrier board, or the first routing circuit may be separately formed, and then the first routing circuit may be detachably attached to the sacrificial carrier board to complete the sacrificial carrier board. The step of forming a first routing circuit on the board. In a preferred embodiment, the flat top surface of the first routing circuit may be substantially coplanar with the flat top side of the lead frame, and the flat top surface of the first routing circuit is in contact with the first build-up circuit.

The optionally included second routing circuit is disposed on the second surface of the sealing material, and the second routing circuit may include a routing layer extending laterally on the second surface of the sealing material and electrically coupled to the vertical connection member. In addition, the second routing circuit may be a multilayer build-up circuit without a core layer, which may further include at least one dielectric layer and at least one wire layer, wherein the wire layer includes a metallized blind hole in the dielectric layer, and Extends over the dielectric layer. The dielectric layer and the wire layer are continuously formed alternately, and can be formed repeatedly if necessary. The innermost wire layer adjacent to the routing layer in the second routing circuit can be electrically coupled to the routing layer through a metalized blind hole in contact with the routing layer, and the outermost layer adjacent to the second layer-increasing circuit in the second routing circuit. The wire layer can provide electrical contacts for the next level of circuit connection. Therefore, the second routing circuit can provide an electrical connection between the vertical connector and the second build-up circuit.

The lead frame includes a plurality of metal leads and a bonding resin, and is located around the peripheral edges of the first routing circuit, the sealing material, and the selective second routing circuit. In a preferred embodiment, the lead frame can be made by the following steps: providing a metal frame and metal leads, wherein the metal leads are integrally connected to the metal frame, and each metal lead has an inwardly facing away from the metal frame. The inner end; and forming a bonding resin which fills the remaining space in the metal frame. After the bonding resin is formed, the metal frame can be separated from the metal lead. Therefore, the outer side surface of the metal lead is flush with the peripheral edge of the bonding resin. In addition, before forming the bonding resin, a metal block may be provided in the metal frame. According to this, a through opening can be formed in the lead frame by removing the metal block after forming the bonding resin. Specifically, the through opening of the lead frame is laterally surrounded by the bonding resin, and extends from the top surface of the bonding resin to the bottom surface of the bonding resin. In a preferred embodiment, the inner wall surface of the lead frame through-opening laterally surrounds the peripheral edge of the electrical component, keeps a distance from the peripheral edge of the electrical component, and is bonded to the peripheral edge of the electrical component. .

These metal leads can provide horizontal and vertical signal transmission paths, or provide ground / power planes for energy transfer and return. These metal leads are preferably integrated leads, and the top and bottom sides of the metal leads are not covered by the bonding resin. In a preferred embodiment, the thickness of the metal lead ranges from about 0.15 mm to 1.0 mm, and the perimeter of the metal lead preferably extends at least laterally to coincide with the peripheral edge of the bonding resin. In order to securely bond the metal lead and the bonding resin, the metal lead may have a stepped peripheral edge bonded to the bonding resin. Therefore, the bonding resin also has a stepped cross-sectional profile at the point of contact with the metal lead to prevent the metal lead from detaching from the bonding resin in the vertical direction and to prevent the formation of cracks at the interface in the vertical direction.

The bonding resin can provide mechanical bonding force between the metal leads, and the top surface of the bonding resin can be substantially coplanar with the top side of the metal lead, and the bottom surface of the bonding resin can be substantially coplanar with the bottom side of the metal lead. When the second routing circuit is not provided in the electrical component, the bottom surface of the bonding resin and the bottom side of the metal lead are preferably substantially coplanar with the second surface of the sealing material. Alternatively, when the electrical component is provided with the second routing circuit on the second surface of the sealing material, the bottom surface of the bonding resin and the bottom side of the metal lead are preferably substantially coplanar with the outer surface of the second routing circuit. That is, it is preferable that the lead frame has a flat bottom side that is substantially coplanar with the bottom surface of the electrical component. In addition, the bonding resin may have an elastic modulus greater than 1.0 GPa and a linear thermal expansion coefficient ranging from about 5 x 10 ^-6 K ^-1 to 15 x 10 ^-6 K ^-1 . In addition, in order to have sufficient thermal conductivity and appropriate viscosity, the bonding resin may include 10 to 90 weight percent of a thermally conductive filler. For example, the thermally conductive filler can be made of aluminum nitride (AlN), aluminum oxide, silicon carbide (SiC), tungsten carbide, boron carbide, silicon dioxide, or the like, and preferably has a relatively high thermal conductivity and a relatively high resistance Rate and relatively low thermal expansion coefficient. According to this, the bonding resin can exhibit better heat dissipation efficiency and electrical insulation performance, and its low CTE characteristic can avoid peeling or cracking of the first build-up circuit and the second build-up circuit or interface deposited thereon. In addition, the maximum particle diameter of the thermally conductive filler can be 25 μm or less.

The first build-up circuit and the second build-up circuit may include at least one dielectric layer and at least one circuit layer, respectively. The dielectric layer and the circuit layer are continuously formed alternately, and can be formed repeatedly if necessary. The dielectric layers of the first build-up circuit and the second build-up circuit cover the opposite sides of the electrical component and the lead frame in the first direction and the second direction, respectively. In addition, the dielectric layers of the first build-up circuit and the second build-up circuit can further extend into the space between the peripheral edge of the electrical component and the surface of the inner side wall of the lead frame to provide the mechanical bonding force between the electrical component and the lead frame. . The circuit layer extends through the dielectric layer to form a metallized blind hole, and extends laterally on the dielectric layer. Accordingly, the first build-up circuit can be electrically coupled to the metal lead and the first routing circuit through a metallized blind hole in contact with the first routing circuit and the top side of the metal lead. Similarly, the second build-up circuit may be electrically coupled to the metal lead through a metallized blind hole in contact with the bottom side of the metal lead. When the electrical component includes a vertical connection, the second build-up circuit can be electrically coupled to the vertical connection through an additional metallized blind hole in contact with the vertical connection. Alternatively, when the electrical component includes a second routing circuit electrically connected to the vertical connecting member, the second layer-increasing circuit may further include an additional metallized blind hole in contact with the second routing circuit, whereby the second layer-increasing The circuit can be electrically connected to the vertical connector through the second routing circuit. The outermost circuit layer of the first build-up circuit and the second build-up circuit can contain conductive contacts, such as bumps, solder balls, for electrical transmission and mechanical connection with the next-level assembly or another electronic component.

The term "coverage" means incomplete and complete coverage in vertical and / or lateral directions. For example, in a preferred embodiment, the second build-up circuit covers the sealing material, regardless of whether another component such as the second routing circuit is located between the seal material and the second build-up circuit.

The terms "connected to" and "attached to" include contact and non-contact with a single or multiple components. For example, in a preferred embodiment, the heat sink can be attached to the semiconductor element, whether the heat sink contacts the semiconductor element or is separated from the semiconductor element by a thermally conductive adhesive.

The terms "electrically connected" and "electrically coupled" mean directly or indirectly electrically connected. For example, in a preferred embodiment, the vertical connection member is directly in contact with and electrically connected to the first routing circuit, and the second routing circuit is kept at a distance from the first routing circuit, and is electrically connected to the first routing circuit through the vertical connection member. First routing circuit.

The "first direction" and "second direction" do not depend on the orientation of the circuit board, and anyone who is familiar with this technique can easily understand the actual direction it refers to. For example, the first surface of the sealing material faces the first direction, and the second surface of the sealing material faces the second direction, which has nothing to do with whether the circuit board is inverted. Therefore, the first and second directions are opposite to each other and perpendicular to the side direction. Furthermore, in a state where the outer surface of the first build-up circuit faces upward, the first direction is an upward direction, and a second direction is a downward direction; in a state where the outer surface of the first build-up circuit is downward, the first direction is Is the downward direction, and the second direction is the upward direction.

The circuit board of the present invention has many advantages. For example, the semiconductor device is electrically coupled to the first routing circuit through a conventional flip-chip bonding process such as hot pressing or reflow, which can avoid the use of an adhesive carrier as a temporary bonding in a stackable system, You will run into position accuracy issues. The first routing circuit can provide a first-level fan-out / interconnection to the semiconductor element, and the second routing circuit on the sealing material can provide a second-level fan-out / interconnection. The first build-up circuit and the second build-up circuit on the opposite sides of the electrical component and the lead frame, respectively, can provide a third-level fan-out / interconnection, and provide electrical contacts for the next-level board assembly. The lead frame can provide the electrical connection between the first build-up circuit and the second build-up circuit, and provide a bending-resistant platform for the double-build-up circuit to be formed thereon to avoid warping of the circuit board. The circuit board prepared by this method has high reliability, low price, and is very suitable for mass production.

The manufacturing method of the present invention has high applicability, and uses various mature electrical and mechanical connection technologies in a unique and progressive way. In addition, the manufacturing method of the present invention can be implemented without expensive tools. Therefore, compared with the traditional technology, this production method can greatly improve the yield, yield, efficiency and cost effectiveness.

The embodiments described herein are for illustrative purposes, and the embodiments may simplify or omit elements or steps that are well known in the technical field, so as not to obscure the features of the present invention. Similarly, to make the drawings clear, the drawings may omit repeated or unnecessary components and component symbols.

100, 200, 300, 400‧‧‧ circuit boards

110, 120, 130, 210‧‧‧ semiconductor assembly

10‧‧‧ sacrificial carrier board

20‧‧‧ Electrical components

21‧‧‧First routing circuit

211, 291‧‧‧ routing layer

214, 294‧‧‧ dielectric layer

216, 296‧‧‧ Conductor layer

218, 298‧‧‧‧ metallized blind hole

23‧‧‧Vertical Connector

25‧‧‧Semiconductor

253‧‧‧ bump

26, 81‧‧‧ Radiator

27‧‧‧sealing material

271‧‧‧First surface

272‧‧‧Second Surface

29‧‧‧Second routing circuit

30‧‧‧ lead frame

305‧‧‧ through opening

307‧‧‧Gap

309‧‧‧ inside wall surface

31‧‧‧ patterned metal plate

32‧‧‧ metal frame

33‧‧‧metal lead

331‧‧‧outer end

333‧‧‧Inner end

336‧‧‧Horizontal extension

337‧‧‧Vertical protrusion

35‧‧‧ metal block

36‧‧‧Connecting rod

38‧‧‧Joint resin

40‧‧‧First layer increase circuit

41‧‧‧first dielectric layer

413‧‧‧First blind hole

415‧‧‧First line layer

417‧‧‧The first metallized blind hole

431‧‧‧Third dielectric layer

433‧‧‧The third blind hole

435‧‧‧Third circuit layer

437‧‧‧ Third metallized blind hole

50‧‧‧Second layer increase circuit

511‧‧‧second dielectric layer

513‧‧‧second blind hole

515‧‧‧Second circuit layer

517‧‧‧second metallized blind hole

531‧‧‧ fourth dielectric layer

533‧‧‧The fourth blind hole

535‧‧‧Fourth circuit layer

537‧‧‧Fourth metallized blind hole

61‧‧‧Top semiconductor component

62‧‧‧Bottom semiconductor element

613‧‧‧Conductive bump

63‧‧‧Passive components

75‧‧‧solder ball

L‧‧‧ cutting line

With reference to the accompanying drawings, the present invention can be more clearly understood through the detailed description of the following preferred embodiments, in which:

1 and 2 are respectively a cross-sectional view and a top perspective view of a routing layer formed on a sacrificial carrier board in a first embodiment of the present invention;

3 and 4 are a cross-sectional view and a top perspective view of the first embodiment of the present invention, wherein a multilayer dielectric layer and a multilayer wire layer are formed on the structure of FIGS.

5 is a cross-sectional view of a vertical connecting member formed on the structure of FIG. 3 in a first embodiment of the present invention;

FIG. 6 is a cross-sectional view of a semiconductor element provided in the structure of FIG. 5 in a first embodiment of the present invention; FIG.

7 is a cross-sectional view of a sealing material provided in the structure of FIG. 6 in a first embodiment of the present invention;

8 is a cross-sectional view of a top region of the sealing material removed from the structure of FIG. 7 in a first embodiment of the present invention;

9 is a cross-sectional view of a routing layer provided in the structure of FIG. 8 in a first embodiment of the present invention;

10 is a cross-sectional view of a first embodiment of the present invention, in which a dielectric layer and a wire layer are provided on the structure of FIG. 9 to complete a second routing circuit on the sealing material;

11 is a cross-sectional view of the first embodiment of the present invention, with the sacrificial carrier removed from the structure of FIG. 10;

FIG. 12 is a cross-sectional view of the panel dimensional structure of FIG. 11 after cutting in the first embodiment of the present invention; FIG.

13 is a cross-sectional view of an electrical component corresponding to the cut-off unit of FIG. 12 in a first embodiment of the present invention;

14 and 15 are a cross-sectional view and a top perspective view of a patterned metal plate in a first embodiment of the present invention, respectively;

16 and 17 are respectively a cross-sectional view and a top perspective view of the bonding resin provided on the structure of FIGS. 14 and 15 in the first embodiment of the present invention;

18 and 19 are a cross-sectional view and a top perspective view of the first embodiment of the present invention, the through-openings are formed on the structure of FIGS. 16 and 17 to complete the production of the lead frame;

FIG. 20 is a cross-sectional view of the electrical component shown in FIG. 13 on the structure of FIG. 18 in the first embodiment of the present invention; FIG.

21 is a cross-sectional view of a first dielectric layer and a second dielectric layer provided on the structure of FIG. 20 in a first embodiment of the present invention;

22 is a cross-sectional view of a first blind hole and a second blind hole provided on the structure of FIG. 21 in the first embodiment of the present invention;

FIG. 23 is a cross-sectional view of a first circuit layer and a second circuit layer provided on the structure of FIG. 22 in a first embodiment of the present invention; FIG.

24 is a cross-sectional view of a third dielectric layer, a fourth dielectric layer, a third blind hole, and a fourth blind hole provided in the structure of FIG. 23 in the first embodiment of the present invention;

25 is a cross-sectional view of a first embodiment of the present invention, in which a third circuit layer and a fourth circuit layer are provided on the structure to complete the production of an uncut circuit board;

26 is a cross-sectional view of a circuit board cut from the structure of FIG. 25 in a first embodiment of the present invention;

27 is a cross-sectional view of a top semiconductor element provided on the structure of FIG. 26 in a first embodiment of the present invention;

28 is a cross-sectional view of a top semiconductor element and a heat sink provided on the structure of FIG. 26 in a first embodiment of the present invention;

FIG. 29 is a cross-sectional view of a top semiconductor element, a passive element, a heat sink, a bottom semiconductor element, and a solder ball provided in the structure of FIG. 26 in the first embodiment of the present invention; FIG.

30 is a cross-sectional view of a circuit board in a second embodiment of the present invention;

FIG. 31 is a cross-sectional view of a top semiconductor element provided on the structure of FIG. 30 in a second embodiment of the present invention; FIG.

32 is a cross-sectional view of a circuit board in a third embodiment of the present invention;

33 is a cross-sectional view of a circuit board in a fourth embodiment of the present invention.

Claims (14)

A circuit board includes: An electrical element includes a semiconductor element, a first routing circuit, and a sealing material, wherein the semiconductor element is electrically coupled to the first routing circuit and is covered laterally by the sealing material, and the sealing material has Facing a first surface of the first routing circuit and a second surface opposite to the first surface; A lead frame that surrounds the electrical component laterally and includes a plurality of metal leads and a bonding resin, wherein the bonding resin fills a space between the metal leads; A first layer-increasing circuit is disposed on the first routing circuit and extends laterally on the lead frame, wherein the first layer-increasing circuit includes at least one dielectric layer and at least one circuit layer that are alternately formed, and The line layer of the first build-up circuit is electrically coupled to the first routing circuit and the metal leads; and A second build-up circuit is disposed on the second surface of the sealing material and extends laterally on the lead frame, wherein the second build-up circuit includes at least one dielectric layer and at least one line formed alternately Layer, and the circuit layer of the second build-up circuit is electrically coupled to the metal leads. The circuit board according to item 1 of the scope of patent application, wherein the dielectric layers of the first build-up circuit and the second build-up circuit further extend into the space between the electrical component and the lead frame to The lead frame is bonded to a peripheral edge of the electrical component. The circuit board according to item 2 of the scope of patent application, wherein the inner side wall surface of the bonding resin is kept at a distance from the peripheral edges of the electrical component, and the first layer increasing circuit and the second layer increasing The dielectric layers of the multilayer circuit are bonded to the peripheral edges of the electrical component. The circuit board according to item 1 of the scope of patent application, wherein the electrical component further includes a series of vertical connectors electrically coupled to the first routing circuit and covered laterally by the sealing material, and the The circuit layer of the second build-up circuit is electrically connected to the vertical connectors. The circuit board according to item 4 of the scope of patent application, wherein the electrical component further includes a second routing circuit disposed on the second surface of the sealing material, and the circuit of the second build-up circuit The layer is electrically connected to the vertical connectors through the second routing circuit. The circuit board according to item 1 of the scope of patent application, wherein each of the metal leads has a stepped peripheral edge bonded to the bonding resin. A method for manufacturing a circuit board includes: An electrical component is provided, which includes a semiconductor component, a first routing circuit and a sealing material, wherein the semiconductor component is electrically coupled to the first routing circuit and is covered laterally by the sealing material, and the sealing material Having a first surface facing the first routing circuit and a second surface opposite to the first surface; Provide a lead frame that surrounds the electrical component laterally and includes a plurality of metal leads and a bonding resin, wherein the bonding resin fills a space between the metal leads; Forming a first build-up circuit that is disposed on the first routing circuit and extends laterally on the lead frame, wherein the first build-up circuit includes at least one dielectric layer and at least one circuit layer that are alternately formed, And the line layer of the first build-up circuit is electrically coupled to the first routing circuit and the metal leads; and Forming a second build-up circuit, which is disposed on the second surface of the sealing material and extends laterally on the lead frame, wherein the second build-up circuit includes at least one dielectric layer and at least one alternately formed A circuit layer, and the circuit layer of the second build-up circuit is electrically coupled to the metal leads. The manufacturing method according to item 7 of the scope of patent application, wherein the step of providing the lead frame includes: Providing a metal frame and the metal leads, wherein the metal leads are integrally connected to the metal frame, and each of the metal leads has an inner end facing away from the metal frame inward; and The bonding resin is formed and fills the remaining space in the metal frame. The manufacturing method according to item 8 of the scope of patent application, wherein the step of providing the lead frame further comprises: after forming the bonding resin, separating the metal frame from the metal leads. The manufacturing method according to item 8 of the scope of patent application, wherein the step of providing the lead frame further comprises: forming a through opening extending from a top surface of the bonding resin to a bottom surface of the bonding resin, and the The inner sidewall surface of the through opening surrounds the electrical component laterally and is bonded to the peripheral edge of the electrical component. The manufacturing method according to item 10 of the scope of patent application, wherein the dielectric layers of the first build-up circuit and the second build-up circuit further extend into the space between the electrical component and the lead frame to The inner sidewall surface of the through opening is bonded to the peripheral edges of the electrical component. The manufacturing method according to item 10 of the patent application scope, wherein the step of providing the lead frame further comprises: before forming the bonding resin, providing a metal block in the metal frame, and the through opening is formed to form the It is formed by removing the metal block after bonding the resin. The manufacturing method according to item 7 of the scope of patent application, wherein the electrical component further includes a series of vertical connectors electrically coupled to the first routing circuit and covered laterally by the sealing material, and the The circuit layer of the second build-up circuit is electrically connected to the vertical connectors. The manufacturing method according to item 13 of the scope of patent application, wherein the electrical component further includes a second routing circuit disposed on the second surface of the sealing material, and the circuit of the second build-up circuit The layer is electrically connected to the vertical connectors through the second routing circuit.