TW201935541A - Method for forming semiconductor structure - Google Patents

Abstract

A method for forming a semiconductor structure includes the following steps. A conductive element is formed in an opening of a dielectric layer. The dielectric layer is etched back so as to transferring down a top dielectric surface of the dielectric layer from at least a height position as a top conductive surface of the conductive element to form a recess. An etching stop layer is formed to fill the recess and on the top conductive surface of the conductive element. A chemical mechanical polish process is performed to remove a portion of the etching stop layer so as to make the etching stop layer coplanar with the top conductive surface of the conductive element.

Description

Method for forming semiconductor structure

The invention relates to a method for forming a semiconductor structure.

In recent years, due to the continuous change of the semiconductor structure, the process steps of the semiconductor structure have increased correspondingly, and it is easy to reduce the process yield of the semiconductor structure. Especially when the component has defects, it is easy to cause the yield of subsequent processes to decrease.

Therefore, designers are all committed to reducing defects in the semiconductor process to improve the yield of the product.

The invention relates to a method for forming a semiconductor structure.

According to a concept of the present disclosure, a method for forming a semiconductor structure is proposed, which includes the following steps. A conductive element is formed in the opening of the dielectric layer. The dielectric layer is etched back so that the top dielectric surface of the dielectric layer is transferred downward from at least the height of the top conductive surface of the conductive element to form a notch. An etch stop layer is formed to fill the recess and is positioned on the top conductive surface of the conductive element. Chemical mechanical polishing is performed to remove part of the etch stop layer, so that the etch stop layer is flush with the top conductive surface of the conductive element.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are described in detail below in conjunction with the accompanying drawings:

In the following, some examples are used for illustration. It should be noted that this disclosure does not show all possible embodiments, and other implementations not proposed in this disclosure may also be applicable. Moreover, the dimensional proportions in the drawings are not drawn according to the actual products. Therefore, the contents of the description and the drawings are only used to describe the embodiments, and not used to limit the scope of the disclosure. In addition, the descriptions in the embodiments, such as the detailed structure, process steps, and application of materials, are for illustration purposes only, and are not intended to limit the scope of the disclosure to be protected. The details of the steps and structures of the embodiments can be changed and modified according to the needs of the actual application process without departing from the spirit and scope of the present disclosure. The following uses the same / similar symbols to indicate the same / similar components for explanation.

1A to 1H illustrate a method for forming a semiconductor structure according to the concept of the first embodiment.

Referring to FIG. 1A, the gate structure G may be formed on the semiconductor substrate 102. In one embodiment, the semiconductor substrate 102 includes a silicon substrate, but is not limited thereto, and other semiconductor materials may also be used. The gate structure G may include, for example, a gate dielectric layer 104 formed on the semiconductor substrate 102, a gate dielectric element 106 formed on the gate dielectric layer 104, a gate dielectric element 108 formed on the gate dielectric element 106, A gate electrode 110 on the gate dielectric element 108, a cap layer 112 formed on the gate electrode 110, and a gap 114 formed on sidewalls of the gate dielectric element 106 and the cap layer 112. The material of the gate structure G may include a metal such as tungsten, but is not limited thereto, and other suitable conductive materials may also be used. The capping layer 112 may be an insulating material. The dielectric layer 116 may fill a gap between the gate structures G. A dielectric layer 118 may be formed on the dielectric layer 116. In one embodiment, the dielectric layer D1 may include a dielectric layer 116 and a dielectric layer 118. In one embodiment, the dielectric layer 116 and the dielectric layer 118 include an oxide, such as silicon oxide, but are not limited thereto. Other dielectric materials such as nitride, such as silicon nitride, and the like can also be used. An opening 120 is formed in the dielectric layer D1.

Referring to FIG. 1B, a conductive element C1 is formed in the opening 120. In one embodiment, the conductive element C1 can also be formed on the upper surface of the dielectric layer D1. The material of the conductive element C1 may include metal, such as tungsten or other suitable conductive materials. In one embodiment, the conductive element C1 may be formed by a chemical vapor deposition method, but is not limited thereto, and may be formed using other suitable methods. Chemical mechanical polishing may be performed so that the dielectric layer D1 and the conductive element C1 have flush upper surfaces, for example, the top dielectric surface DS forming the dielectric layer D1 and the top conductive surface CS of the conductive element C1 are aligned flat surfaces. The conductive element C1 may be a 0th layer contact element.

Referring to FIG. 1C, an etching process is performed on the dielectric layer D1, so that the top dielectric surface DS of the dielectric layer D1 is transferred downward from the height position of the top conductive surface CS of the conductive element C1 to the top dielectric surface DS '. , Thereby forming a notch 122. The notch 122 may be defined by a top dielectric surface DS ′ of the dielectric layer D1 and a side conductive surface CW of the conductive element C1. In one embodiment, the etch-back process may include a dry etching step and a wet etching step. For example, the dry etching step may use a reactive gas containing fluorine element to remove the dielectric layer D1. The wet etch step can be used to remove unwanted residues.

Referring to FIG. 1D, an etch stop layer 124 is formed to fill the recess 122 and cover the top conductive surface CS of the conductive element C1. In one embodiment, the material of the etch stop layer 124 includes silicide, such as silicon nitride, but is not limited thereto. The etch stop layer 124 can be formed by an appropriate method, such as a chemical vapor deposition method, a physical vapor deposition method, and the like.

Referring to FIG. 1E, chemical mechanical polishing may be performed to remove part of the etch stop layer 124, so that the etch stop layer 124 is flush with the top conductive surface CS of the conductive element C1. In one embodiment, the etch stop layer 124 removes about half of the original thickness. For example, the thickness of the etch stop layer 124 shown in FIG. 1E is about 100 Å to 200 Å.

Referring to FIG. 1F, a dielectric film D2 can be formed on the etch stop layer 124 and the conductive element C1. In one embodiment, the dielectric film D2 includes silicon oxycarbide (SiOC), but is not limited thereto, and other dielectric materials may also be used. A thin film structure 126 may be formed on the dielectric film D2. The thin film structure 126 may include a film layer 128, a film layer 130, and a film layer 132. The thin film structure 126 may be patterned. In one embodiment, the film layer 128 and the film layer 132 may be anti-reflection layers, such as a nitrogen-free anti-reflection layer (NFARL). The film layer 130 may be a hard mask layer, and may include titanium nitride, or other suitable materials. The thin film structure 126 can be patterned using a yellow light lithography process.

Referring to FIG. 1G, an etching step may be performed, using the thin film structure 126 as an etching mask, and transferring the opening pattern of the thin film structure 126 downward to the dielectric film D2 and the etching stop layer 124 to form a hole 134. In this embodiment, the etching step also removes part of the conductive element C1, so that the top conductive surface CS thereof is transferred downward to the top conductive surface CS ′. The depth of the formed hole 134 is controlled so as not to reach the bottom surface of the etch stop layer 124. In one embodiment, the etching step includes wet etching or dry etching, or other suitable methods. For example, dry etching may be performed to form the outline of the holes 134, and then wet etching may be performed to remove undesired residues.

Referring to FIG. 1H, the hole 134 is filled with the conductive layer C2. In one embodiment, the conductive layer C2 may be formed after the thin film structure 126 is removed, and then the conductive layer C2 above the dielectric film D2 may be removed by a chemical mechanical polishing method. In another embodiment, the conductive layer C2 may be formed over the thin film structure 126, and then the conductive layer C2 and the thin film structure 126 are removed by a chemical mechanical polishing method. In one embodiment, the material of the conductive layer C2 may include metal, such as tungsten or other suitable conductive materials. In one embodiment, the conductive layer C2 shown in FIG. 1H is a first metal layer (M1).

2A to 2B illustrate a method for forming a semiconductor structure according to the concept of the second embodiment. The second embodiment is similar to the first embodiment except that the steps shown in Fig. 1G of the first embodiment are changed to Fig. 2A. As shown in FIG. 2A, the etching step for forming the hole 134 is automatically stopped on the top conductive surface CS and the etching stop layer 124 of the conductive element C1, so the bottom of the formed hole 134 can be substantially aligned with the top of the conductive element C1 CS position on the conductive surface. For example, the etching process can determine the etching depth by detecting whether element gas related to the conductive element C1 and / or the etching stop layer 124 is present. In one embodiment, once the signal of the conductive element C1 and / or the etching stop layer 124 is detected, the etching step is automatically stopped. Therefore, the depth of the hole 134 can be accurately controlled. In one embodiment, the process steps shown in FIG. 1G may also be holes 134 formed by controlling the etching depth based on the process steps shown in FIG. 2A to form a desired contour. Among them, the hole 134 does not reach the bottom of the etch stop layer 124 (ie, does not reach the dielectric layer D1), so the depth of the conductive layer C2 can be controlled as close to the gate structure G as possible, thereby reducing the distance between the conductive layer C2 and the semiconductor substrate 102 In addition, the resistance can also ensure that the conductive layer C2 is not short-circuited to the gate structure G due to excessive etching, so the yield and efficiency of the device can be improved.

3A to 3B illustrate a method for forming a semiconductor structure according to the concept of the third embodiment. The third embodiment is similar to the first and second embodiments, except that the steps shown in FIG. 1G / 2A of the first embodiment are changed to FIG. 3A. As shown in FIG. 3A, the etching step used to form the holes 134 has a larger etch rate for the etch stop layer 124 and a smaller etch rate for the dielectric film D2. In one embodiment, for example, the material density of the etch stop layer 124 is greater than that of the dielectric film D2. The etching step may not substantially remove the conductive element C1, so the conductive element C1 may substantially maintain the top conductive surface CS with a constant height. The etching step removes the etch stop layer 124 exposed by the holes 134, so the upper surface position of the etch stop layer 124 moves downward and is lower than the top conductive surface CS. Therefore, the formed hole 134 not only exposes the top conductive surface CS of the conductive element C1, but also exposes the side conductive surface CW of the conductive element C1. In an embodiment, the process steps shown in FIG. 3A may also be holes 134 formed with a desired profile based on the process steps shown in FIG. 2A to further control the etching depth of the etching stop layer 124. Among them, the hole 134 does not reach the bottom of the etch stop layer 124 (that is, does not reach the dielectric layer D1). Therefore, the depth of the conductive layer C2 formed in FIG. In addition, the resistance between the substrates 102 can also ensure that the conductive layer C2 is not short-circuited to the gate structure G due to excessive etching, so the yield and efficiency of the device can be improved.

4A to 4H illustrate a method for forming a semiconductor structure according to the concept of the fourth embodiment.

Referring to FIG. 4A, an opening 120 is formed in the dielectric layer D1. A conductive element C1 is formed in the opening 120. In one embodiment, the conductive element C1 can also be formed on the upper surface of the dielectric layer D1. Chemical mechanical polishing can be performed so that the dielectric layer D1 and the conductive element C1 have a flush upper surface, for example, the top dielectric surface DS of the dielectric layer D1 and the top conductive surface CS of the conductive element C1 are aligned flat surfaces.

Referring to FIG. 4B, an etching process is performed on the dielectric layer D1, so that the top dielectric surface DS of the dielectric layer D1 is shifted downward from the height position of the top conductive surface CS of the conductive element C1, thereby forming the notch 122. The notch 122 may be defined by a top dielectric surface DS ′ of the dielectric layer D1 and a side conductive surface CW of the conductive element C1.

Referring to FIG. 4C, an etch stop layer 224 is formed in the recess 122 and covers the conductive element C1. In one embodiment, the etch stop layer 224 is a conformal film, and the thickness may be about 100 Å. The etch stop layer 224 can be formed by a suitable method such as chemical vapor deposition or physical vapor deposition. In one embodiment, the etch stop layer 224 includes Nitrogen-Doped silicon Carbide (NDC), but the disclosure is not limited thereto.

Referring to FIG. 4D, a dielectric film D2 can be formed on the etch stop layer 224. In one embodiment, the dielectric film D2 may include, for example, tetraethoxysilane (TEOS), an ultra-low-k (ULK) dielectric material, and the like. A thin film structure 126 may be formed on the dielectric film D2. In one embodiment, the film layer 128 and the film layer 132 may be anti-reflection layers, and the material may include silicon carbon oxide (SiOC), or other suitable materials. The film layer 130 may be a hard mask layer, and may include titanium nitride, or other suitable materials.

Referring to FIG. 4E, the thin film structure 126 can be patterned by a yellow light lithography process.

Referring to FIG. 4F, an etching step may be performed. The thin film structure 126 is used as an etching mask, and the opening pattern of the thin film structure 126 is transferred downward to the dielectric film D2 to form a hole 234.

Referring to FIG. 4G, different etching steps may be performed to transfer the depth of the hole 234 downward to the etching stop layer 224 to expose the conductive element C1. Removable film structure 126. In one embodiment, the etch stop layer 224 on the sidewall of the conductive element C1 has a large thickness, so that the problem of undesired contours caused by over-etching may occur when the holes 234 are etched and shifted, which may cause the conductive layer C2 (Figure 4H) is shorted to the gate structure G, so it can increase the margin of the etching offset and improve the yield of the product.

Referring to FIG. 4H, the hole 234 is filled with the conductive layer C2. In one embodiment, a barrier layer may be formed first, and then a metal such as copper is used to fill the holes 234 to form a conductive layer C2. In one embodiment, the conductive layer C2 can also be formed on the dielectric film D2 and then planarized by a chemical mechanical polishing method.

In summary, although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

102‧‧‧ semiconductor substrate

104‧‧‧Gate dielectric layer

106, 108‧‧‧ Gate dielectric components

110‧‧‧Gate electrode

112‧‧‧ cap

114‧‧‧ bulkhead

116, 118, D1‧‧‧ dielectric layer

120‧‧‧ opening

122‧‧‧ Notch

124, 224‧‧‧ etch stop layer

126‧‧‧ thin film structure

128, 130, 132‧‧‧ film

134, 234‧‧‧holes

C1‧‧‧ conductive element

C2‧‧‧ conductive layer

CS, CS'‧‧‧ top conductive surface

CW‧‧‧ side conductive surface

D2‧‧‧ Dielectric film

DS, DS'‧‧‧ top dielectric surface

G‧‧‧Gate structure

1A to 1H illustrate a method for forming a semiconductor structure according to the concept of the first embodiment. 2A to 2B illustrate a method for forming a semiconductor structure according to the concept of the second embodiment. 3A to 3B illustrate a method for forming a semiconductor structure according to the concept of the fourth embodiment. 4A to 4H illustrate a method for forming a semiconductor structure according to the concept of the fifth embodiment.

Claims (10)

A method for forming a semiconductor structure includes: forming a conductive element in an opening of a dielectric layer; performing an etch back process on the dielectric layer so that a top dielectric surface of the dielectric layer is at least from the conductive element. The height of the top conductive surface is shifted downward to form a notch; an etch stop layer is formed to fill the notch and be positioned on the top conductive surface of the conductive element; and a chemical mechanical polishing is performed to remove part of the etching The stop layer, so that the etch stop layer is flush with the top conductive surface of the conductive element. The method for forming a semiconductor structure according to item 1 of the application, wherein the recess exposes a conductive surface on one side of the conductive element. The method for forming a semiconductor structure according to item 1 of the patent application scope further includes forming a dielectric film on the etch stop layer and the conductive element. According to the method for forming a semiconductor structure described in item 3 of the patent application scope, the method further includes an etching step, which removes part of the dielectric film to form a hole, and the hole exposes the top conductive surface of the conductive element. The method for forming a semiconductor structure according to item 4 of the scope of patent application, wherein the hole further exposes a conductive surface on one side of the conductive element. The method for forming a semiconductor structure according to item 4 of the application, wherein the etching step is stopped on the top conductive surface of the conductive element. The method for forming a semiconductor structure according to item 6 of the application, wherein the etching step further removes part of the etching stop layer. The method for forming a semiconductor structure according to item 4 of the application, wherein the bottom of the hole does not reach the bottom surface of the etch stop layer. The method for forming a semiconductor structure according to item 4 of the patent application scope further includes filling the hole with a conductive layer. The method for forming a semiconductor structure according to item 4 of the scope of patent application, further comprising: forming a thin film structure on the dielectric film; and patterning the thin film structure; wherein the etching step includes patterning the thin film structure downward Transfer to the dielectric film.