TW201923999A - Semiconductor packages relating to thermal transfer plate and methods of manufacturing the same - Google Patents

Abstract

The present application can provide a semiconductor package element and a method for manufacturing the semiconductor package element. The semiconductor package element may include a first semiconductor wafer disposed on a first surface of the interconnection layer, a second semiconductor wafer and a third semiconductor wafer disposed on a second surface of the interconnection layer. The semiconductor package element may include a heat transfer plate disposed between the second semiconductor wafer and the third semiconductor wafer, in contact with the second surface of the interconnection layer, and overlapping the first semiconductor wafer. The heat transfer plate may be configured to provide a heat radiation path.

Description

Semiconductor package element related to heat transfer plate and manufacturing method thereof

The present disclosure relates generally to a semiconductor package element technology, and more particularly, to a semiconductor package element related to a heat transfer plate and a method of manufacturing the same.

Semiconductor packaging components have been used in electronic systems such as mobile phones or computers. Much effort has been focused on integrating multiple semiconductor wafers into a single packaged component, enabling a single packaged component to perform multiple operations while also being able to process large amounts of data at high speed. For example, 2.5-dimensional (2.5D) system-in-package (SIP) technology has been proposed to place a processor chip and a memory chip side by side on a carrier board. Since various types of semiconductor wafers are embedded in a single packaged component, a cooling structure for radiating heat generated by a specific semiconductor wafer in a single packaged component may be required to prevent performance degradation of the single packaged component.

This application claims priority from Korean Patent Application No. 10-2017-0153368, filed on November 16, 2017, which is incorporated herein by reference in its entirety.

According to one embodiment, a semiconductor package element may include a first semiconductor wafer disposed on a first surface of an interconnection layer. The semiconductor package element may include a second semiconductor wafer and a third semiconductor wafer spaced apart from each other and disposed on a second surface of the interconnection layer. The semiconductor package element may include a heat transfer plate disposed between the second semiconductor wafer and the third semiconductor wafer, in contact with a second surface of the interconnection layer, and in contact with the first A semiconductor wafer overlaps. The heat transfer plate may provide a heat radiation path.

According to one embodiment, a semiconductor package element may include a first semiconductor wafer disposed on a first surface of an interconnection layer. The semiconductor package element may include a second semiconductor wafer disposed on a second surface of the interconnection layer, so that four corner regions of the first semiconductor wafer are respectively different from those of the second semiconductor wafer. The edge regions overlap. The semiconductor package element may include a heat transfer plate disposed between the second semiconductor wafers to be in contact with a second surface of the interconnection layer and overlap the first semiconductor wafer. The heat transfer plate may provide a heat radiation path.

According to one embodiment, a method of manufacturing a semiconductor package element is provided. The method may include disposing a heat transfer plate between the second semiconductor wafer and the third semiconductor wafer. The method may include forming a sealant layer for fixing the second and third semiconductor wafers and the heat transfer plate. The method may include forming an interconnect layer on the second semiconductor wafer and the heat transfer plate such that a second surface of the interconnect layer is in contact with the second semiconductor wafer and the heat transfer plate. The method may include disposing a first semiconductor wafer on a first surface of the interconnect layer to overlap the heat transfer plate.

The terms used herein may correspond to words selected in consideration of their function in the embodiment, and the meanings of these terms may be interpreted as being different according to common techniques in the field to which the embodiments belong. If defined in detail, these terms can be interpreted according to their definition. Unless otherwise defined, the terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong.

It should be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another, but are not used to define the element itself or to indicate a particular order.

It should also be understood that when an element or layer is referred to as being "on," "above," "below," "below" or "outside" another element or layer, The elements or layers are in direct contact, or intervening elements or layers may be present. Other words used to describe the relationship between elements or layers should be interpreted in a similar fashion (for example, "between" versus "directly between" or "adjacent" versus "directly related" adjacent").

For example, as shown in the diagram, spatially relative terms such as "below", "below", "below", "above", "above", "top", "bottom", etc. can be used to describe an element And / or feature in relation to another element and / or feature. It should be understood that in addition to the orientation shown in the drawings, spatially relative terms are intended to include different orientations of the device in use and / or operation. For example, when the device in the figures is turned over, elements described as “under and / or under” other elements or features would then be oriented “above” the other elements or features. The device can be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein interpreted accordingly.

The semiconductor package element may include an electronic device such as a semiconductor wafer or a semiconductor die. A semiconductor wafer or a semiconductor die can be obtained by separating a semiconductor substrate such as a wafer into a plurality of pieces using a die cutting process. A semiconductor wafer may correspond to a memory chip, a logic chip (including an application specific integrated circuit (ASIC) chip), or a system on chip (SoC). The memory chip may include a dynamic random access memory (DRAM) circuit, a static random access memory (SRAM) circuit, a NAND type flash memory circuit, a NOR type flash memory circuit, a magnetic random access integrated on a semiconductor substrate Access Memory (MRAM) circuit, Resistive Random Access Memory (ReRAM) circuit, Ferroelectric Random Access Memory (FeRAM) circuit or Phase Change Random Access Memory (PcRAM) circuit. The logic chip may include a logic circuit integrated on a semiconductor substrate. Semiconductor package components can be used in communication systems such as mobile phones, electronic systems related to biotechnology or healthcare, or wearable electronic systems.

Throughout the description, the same drawing reference numerals refer to the same elements. Although a drawing mark is mentioned or described without referring to the drawing, the drawing mark may be mentioned or described with reference to another drawing. In addition, even if a drawing mark is not shown in a drawing, it may be mentioned or described with reference to another drawing.

The present disclosure may provide a semiconductor package element, each of which may be configured to include a plurality of semiconductor wafers and a heat transfer plate three-dimensionally stacked above and below an interconnect layer, and the heat transfer plate It may be provided to vertically overlap with any one of the plurality of semiconductor wafers and to be in contact with the interconnection layer.

FIG. 1 is a plan view illustrating a semiconductor package element 100 according to an embodiment. FIG. 2 is a cross-sectional view taken along a line AA ′ of FIG. 1.

Referring to FIGS. 1 and 2, the semiconductor package element 100 may include a first semiconductor wafer 120, a second semiconductor wafer 130, and an interconnection layer 110 disposed between the first semiconductor wafer 120 and the second semiconductor wafer 130. The interconnection layer 110 may have a first surface 111 and a second surface 112 opposite to each other. The first semiconductor wafer 120 may be disposed on a first surface 111 (corresponding to a bottom surface in FIG. 2) of the interconnection layer 110. The first semiconductor wafer 120 may be connected to the first surface 111 of the interconnection layer 110 through an internal connector 121. The internal connector 121 may be a micro bump having a relatively small size. The second semiconductor wafer 130 may be disposed on the second surface 112 (corresponding to the top surface in FIG. 2) of the interconnection layer 110.

The third semiconductor wafer 130A may be additionally disposed on the second surface 112 of the interconnection layer 110 to be laterally spaced from the second semiconductor wafer 130. The fourth semiconductor wafer 130B and the fifth semiconductor wafer 130C may also be disposed on the second surface 112 of the interconnection layer 110 to be laterally spaced from the second semiconductor wafer 130. The heat transfer plate 140 may be disposed on the second surface 112 of the interconnection layer 110 opposite to the first semiconductor wafer 120 so as to vertically overlap the first semiconductor wafer 120. All of the second to fifth semiconductor wafers 130, 130A, 130B, and 130C and the heat transfer plate 140 may be disposed in contact with the second surface 112 of the interconnection layer 110. The heat transfer plate 140 may have a bottom surface 142 that is in contact with the second surface 112 of the interconnection layer 110.

The heat transfer plate 140 may be disposed between the second semiconductor wafer 130 and the third semiconductor wafer 130A. When viewed from the plan view of FIG. 1, the first distance D1 between the second semiconductor wafer 130 and the third semiconductor wafer 130A in the X-axis direction may be set to be second than in the Y-axis direction perpendicular to the X-axis direction. The second distance D2 between the semiconductor wafer 130 and the fourth semiconductor wafer 130B is large. The heat transfer plate 140 may be disposed between the second semiconductor wafer 130 and the third semiconductor wafer 130A spaced apart from each other by the first distance D1, and may extend to the fourth semiconductor wafer 130B and the fifth semiconductor spaced apart from the first distance D1. Between wafers 130C. Therefore, the heat transfer plate 140 may be substantially positioned to vertically overlap with most of the first semiconductor wafer 120. As a result, each of the second to fifth semiconductor wafers 130, 130A, 130B, and 130C may have an edge region 130E overlapping with any one of the four corner regions 120C of the first semiconductor wafer 120 or with the first semiconductor Any one of the four corner regions 120C of the wafer 120 is adjacent.

Referring again to FIG. 2, the semiconductor package component 100 may further include a sealant layer 150 covering the second surface 112 of the interconnection layer 110. The sealant layer 150 may not be disposed on the first surface 111 of the interconnection layer 110. An external connector 160 may be provided on the first surface 111 of the interconnection layer 110 instead of the sealant layer 150 to connect the semiconductor package element 100 to an external device. The external connector 160 may include solder balls larger in size than the internal connector 121. The sealant layer 150 may include a sealant such as an epoxy encapsulant (EMC) material.

The second to fifth semiconductor wafers 130, 130A, 130B, and 130C and the heat transfer plate 140 may be disposed in the sealant layer 150. In this case, the sealant layer 150 may be formed to have a top surface 151 provided at the same horizontal plane as the top surface 131 of the second semiconductor wafer 130. That is, the top surface 131 of the second semiconductor wafer 130 may be exposed at the same horizontal plane as the top surface 151 of the sealant layer 150. In addition, the top surface 141 of the heat transfer plate 140 may be exposed at the same horizontal plane as the top surface 151 of the sealant layer 150. The sealant layer 150 may be formed to cover and protect the side surfaces of the second semiconductor wafer 130 and the third semiconductor wafer 130A, and fill a gap between the second semiconductor wafer 130 and the heat transfer plate 140 and the third semiconductor wafer 130A and the heat transfer plate. A gap between the hot plates 140. Therefore, the heat transfer plate 140 may be disposed to substantially penetrate a portion of the sealant layer 150 between the second semiconductor wafer 130 and the third semiconductor wafer 130A. That is, the heat transfer plate 140 may provide a heat radiation path (ie, a heat conduction path) extending from the second surface 112 of the interconnection layer 110 to reach a horizontal plane of the top surface 151 of the sealant layer 150.

FIG. 3 is a cross-sectional view showing a heat conduction path of the semiconductor package element 100 shown in FIG. 2.

Referring to FIG. 3, the semiconductor package element 100 may be mounted on a circuit substrate 170. The circuit substrate 170 may be a printed circuit board (PCB) or a motherboard including a circuit pattern. For example, the semiconductor package element 100 may be connected to the circuit substrate 170 through an external connector 160. The first semiconductor wafer 120 may be disposed between the circuit substrate 170 located below the first semiconductor wafer 120 and the interconnection layer 110 located above the first semiconductor wafer 120. In addition, in a plan view, the first semiconductor wafer 120 may be surrounded by the external connector 160. That is, the first semiconductor wafer 120 may be disposed in the internal space 171 surrounded by the interconnection layer 110, the circuit substrate 170, and the external connector 160.

The heat may be generated by the operation of the first semiconductor wafer 120 located in the internal space 171, and the heat generated by the operation of the first semiconductor wafer 120 may be maintained in the internal space 171. However, according to one embodiment, the heat generated by the operation of the first semiconductor wafer 120 may be transferred into the outer region of the semiconductor package element 100 through the heat transfer plate 140. The heat transfer plate 140 may include a thermally conductive material, which has a higher thermal conductivity than that of the sealant layer 150. Therefore, the heat generated by the operation of the first semiconductor wafer 120 can be quickly transferred into the outer region of the semiconductor package element 100. Therefore, since the heat transfer plate 140 prevents heat generated by the operation of the first semiconductor wafer 120 from being accumulated in the internal space 171, the temperature of the first semiconductor wafer 120 may not be excessively increased. That is, the heat transfer plate 140 may be used as a heat conduction path for quickly transferring heat generated by the first semiconductor wafer 120 to an outer region of the semiconductor package element 100. The heat transfer plate 140 may be formed to include a thermally conductive material, such as a copper material or an aluminum material, which has a higher thermal conductivity than the EMC material used to form the sealant layer 150.

Since the first semiconductor wafer 120 is disposed in the inner space 171, the first height H1 from the first surface 111 of the interconnection layer 110 to the surface of the first semiconductor wafer 120 opposite to the interconnection layer 110 may be greater than that of the interconnection layer The second height H2 corresponding to the distance between 110 and the circuit board 170 is small. In order to make the first height H1 smaller than the second height H2, the first semiconductor wafer 120 may have a thickness T smaller than the second height H2 corresponding to the height of each external connector 160.

FIG. 4 is a sectional view showing a semiconductor package element 100S according to an embodiment.

Referring to FIG. 4, the semiconductor package element 100S may provide a structure in which a heat sink 180 is additionally attached to a top surface 151 of the sealant layer 150 included in the semiconductor package element 100 of FIG. 3. The heat sink 180 may also be attached to the top surface 141 of the heat transfer plate 140. The heat sink 180 may radiate heat transferred from the heat transfer plate 140. Therefore, the heat generated by the first semiconductor wafer 120 can be more efficiently radiated through the heat sink 180. In this case, the thermal interface material layer 181 may be located at an interface between the heat sink 180 and the heat transfer plate 140. The thermal interface material layer 181 can improve the heat exchange between the heat transfer plate 140 and the heat sink 180.

The heat sink 180 may extend to be attached to the top surface 131 of the second semiconductor wafer 130 and the top surface 151 of the sealant layer 150. Since the top surface 131 of the second semiconductor wafer 130 is exposed by the sealant layer 150, the heat exchange between the second semiconductor wafer 130 and the heat sink 180 can occur more easily through the thermal interface material layer 181. The heat sink 180 and the thermal interface material layer 181 may extend onto the second semiconductor wafer 130 and the third semiconductor wafer 130A. Therefore, the heat generated by the second semiconductor wafer 130 and the third semiconductor wafer 130A can also be radiated by the heat sink 180.

The heat transfer plate 140 may be disposed such that the side surface 143 of the heat transfer plate 140 faces the side surface 133 of the second semiconductor wafer 130. The side surface 143A of the heat transfer plate 140 opposite to the second semiconductor wafer 130 may face the side surface 133A of the third semiconductor wafer 130A. The heat transfer plate 140 may be disposed such that the side surface 143 of the heat transfer plate 140 is adjacent to the side surface 133 of the second semiconductor wafer 130. Therefore, the heat generated by the operation of the second semiconductor wafer 130 may be transferred to the heat transfer plate 140 through the side surface 133 of the second semiconductor wafer 130, and the heat transferred to the heat transfer plate 140 may be transferred to the heat sink 180 and may be radiated. Into the outer region of the semiconductor package element 100. Therefore, the heat generated by the operation of the third semiconductor wafer 130A may be transferred to the heat transfer plate 140 through the side surface 133A of the third semiconductor wafer 130A, and the heat transferred to the heat transfer plate 140 may be transferred to the heat sink 180 and may be radiated. Into the outer region of the semiconductor package element 100. In this way, the heat sink 180 can more effectively improve the cooling efficiency of the semiconductor package element 100S.

Referring again to FIG. 2, since the first semiconductor wafer 120 of the semiconductor package element 100 can be cooled by the heat transfer plate 140, the first semiconductor wafer 120 can be disposed on the first surface 111 of the interconnection layer 110. In addition, since the second semiconductor wafer 130 is disposed on the second surface 112 of the interconnection layer 110 that is opposite to the first semiconductor wafer 120, at least a part of the second semiconductor wafer 130 may be at least a part of the first semiconductor wafer 120 in a plan view. Some overlap. That is, since at least a part of the second semiconductor wafer 130 may be stacked on at least a part of the first semiconductor wafer 120, when viewed from a plan view, compared with a case where the first semiconductor wafer 120 and the second semiconductor wafer 130 are arranged side by side, , The total width of the semiconductor package element 100 can be reduced.

Since the second semiconductor wafer 130 is stacked on the first semiconductor wafer 120 in a plan view so that at least a part of the second semiconductor wafer 130 overlaps with at least a part of the first semiconductor wafer 120, the arrangement on the first semiconductor wafer 120 can be reduced The length of a signal routing path with the second semiconductor wafer 130. The interconnection layer 110 may include a redistribution pattern 114 and a dielectric layer 115 covering the redistribution pattern 114 to insulate the redistribution pattern 114 from each other. In this case, at least a part of the second semiconductor wafer 130 may overlap at least a part of the first semiconductor wafer 120 in a plan view. Therefore, the length of the redistribution pattern 114 for connecting the first semiconductor wafer 120 and the second semiconductor wafer 130 to each other can be reduced.

5 to 7 are sectional views showing examples of the interconnection layer 110 included in any one of the semiconductor package elements 100 and 100S shown in FIGS. 1 to 4. 5 to 7 are enlarged views showing portions of the semiconductor package element 100 shown in FIG. 2, respectively.

FIG. 5 is an enlarged cross-sectional view showing a region “E1” of FIG. 2. The interconnection layer 110 may include a first dielectric layer 115A that electrically insulates the redistribution pattern 114 from the heat transfer plate 140. The interconnection layer 110 may further include a second dielectric layer 115B that electrically insulates the redistribution patterns 114 from each other. The first dielectric layer 115A and the second dielectric layer 115B may be laminated to contact each other and provide a dielectric layer (115 in FIG. 2). Since the interconnection layer 110 is configured to include a dielectric layer (115 of FIG. 2) and the redistribution pattern 114, the interconnection layer 110 may have a thickness smaller than that of a general PCB. Therefore, the total thickness of the semiconductor package element (100 in FIG. 2) can be reduced.

An edge region (essentially, one of the corner regions 120C) of the first semiconductor wafer 120 may vertically overlap the edge region 130E of the second semiconductor wafer 130. A solid layer having an interface structure for signal transmission between the first semiconductor wafer 120 and the second semiconductor wafer 130 may be provided in the corner region 120C of the first semiconductor wafer 120, and may have a layer for the first semiconductor wafer 120. Another physical layer of the interface structure for signal transmission with the second semiconductor wafer 130 may also be disposed in the edge region 130E of the second semiconductor wafer 130.

In one embodiment, the first wafer pad 135A may be disposed on an edge region 130E of the second semiconductor wafer 130 to electrically connect the second semiconductor wafer 130 to the first semiconductor wafer 120. In addition, the first internal connector 121A may be disposed on a corner region 120C of the first semiconductor wafer 120 to electrically connect the first semiconductor wafer 120 to the second semiconductor wafer 130. The first internal connectors 121A may correspond to some of the internal connectors 121.

The first redistribution pattern 114A may be disposed in the interconnect layer 110 such that a first end portion of the first redistribution pattern 114A is electrically connected to the first wafer pad 135A of the second semiconductor wafer 130, and the The second end portion is electrically connected to the first internal connector 121A. The first redistribution pattern 114A may correspond to some of the redistribution patterns 114 and may be disposed between an edge region 130E of the second semiconductor wafer 130 and a corner region 120C of the first semiconductor wafer 120.

The first redistribution pattern 114A may be used as a vertical signal path that substantially connects an edge region 130E of the second semiconductor wafer 130 to a corner region 120C of the first semiconductor wafer 120. In a plan view, the first redistribution pattern 114A may be disposed to overlap an edge region 130E of the second semiconductor wafer 130 and a corner region 120C of the first semiconductor wafer 120. Therefore, according to one embodiment, the length of the first redistribution pattern 114A can be reduced, and the routing length of the signal path between the first semiconductor wafer 120 and the second semiconductor wafer 130 can also be reduced.

The first dielectric layer 115A may be formed to have a first opening 116A for exposing the first wafer pad 135A so as to connect the first end portion of the first redistribution pattern 114A to the first wafer pad 135A. The first end portion of the first redistribution pattern 114A may fill the first opening 116A to be connected to the first wafer pad 135A. The second dielectric layer 115B may be formed to have a second opening 116B for exposing the second end portion of the first redistribution pattern 114A so as to connect the second end portion of the first redistribution pattern 114A to the first internal connection.器 121A. The first internal connector 121A may extend to fill the second opening 116B to connect to the first redistribution pattern 114A.

FIG. 6 is an enlarged cross-sectional view showing a region “E2” of FIG. 2. In a plan view, the second redistribution pattern 114B corresponding to one of the redistribution patterns 114 may extend from a region overlapping the second semiconductor wafer 130 into an outer region of the second semiconductor wafer 130. In a plan view, the second redistribution pattern 114B may extend into a region overlapping the sealant layer 150. Therefore, in a plan view, the first external connector 160A corresponding to one of the external connectors 160 may be connected to the second redistribution pattern 114B, and may be provided to the second semiconductor wafer 130 on the sealant layer 150. Part of the outer area overlaps. As a result, the first external connector 160A may be a connector that electrically connects the second semiconductor wafer 130 to an external device.

The second redistribution pattern 114B may extend into an outer region of the second semiconductor wafer 130 to connect the first external connector 160A to the second wafer pad 135B corresponding to one of the wafer pads of the second semiconductor wafer 130. Since the second redistribution pattern 114B extends into an outer region of the second semiconductor wafer 130, the first dielectric layer 115A may also extend to contact the bottom surface 152 of the sealant layer 150.

The second redistribution pattern 114B may be disposed in the interconnection layer 110 such that a first end portion of the second redistribution pattern 114B is electrically connected to the second wafer pad 135B of the second semiconductor wafer 130, and the second redistribution pattern 114B The second end portion is electrically connected to the first external connector 160A. The first dielectric layer 115A may be formed to have a third opening 116C for exposing the second wafer pad 135B to connect the first end portion of the second redistribution pattern 114B to the second wafer pad 135B. The first end portion of the second redistribution pattern 114B may fill the third opening 116C to be connected to the second wafer pad 135B. The second dielectric layer 115B may be formed to have a fourth opening 116D for exposing the second end portion of the second redistribution pattern 114B so as to connect the second end portion of the second redistribution pattern 114B to the first external connection.器 160A. The first external connector 160A may extend to fill the fourth opening 116D to connect to the second redistribution pattern 114B.

FIG. 7 is an enlarged cross-sectional view showing a region “E3” of FIG. 2. In a plan view, the third redistribution pattern 114C corresponding to one of the redistribution patterns 114 may extend from a region overlapping the third semiconductor wafer 130A into an outer region of the third semiconductor wafer 130A. Therefore, the second external connector 160B corresponding to one of the external connectors 160 may be connected to the third redistribution pattern 114C, and may be disposed to overlap the third semiconductor wafer 130A. In one embodiment, as shown in FIG. 2, another external connector 160 connected to the third redistribution pattern 114C may be disposed to overlap the sealant layer 150. The second external connector 160B may be a connector that electrically connects the first semiconductor wafer 120 to an external device.

The third redistribution pattern 114C may extend into an outer region of the first semiconductor wafer 120 to connect the second external connector 160B to the second internal connector 121B, and the second internal connector 121B is connected to the first semiconductor wafer One of the internal connectors 121 of 120 corresponds. Since the third redistribution pattern 114C extends into an outer region of the first semiconductor wafer 120, the first dielectric layer 115A may also extend to overlap the third semiconductor wafer 130A.

The third redistribution pattern 114C may be disposed in the interconnection layer 110 such that a first end portion of the third redistribution pattern 114C is electrically connected to the second internal connector 121B, and a second end portion of the third redistribution pattern 114C It is electrically connected to the second external connector 160B. The second dielectric layer 115B may be formed to have a fifth opening 116E for exposing the first end portion of the third redistribution pattern 114C so as to connect the first end portion of the third redistribution pattern 114C to the second internal connection.器 121B. The second internal connector 121B may extend to fill the fifth opening 116E to connect to the first end portion of the third redistribution pattern 114C. The second dielectric layer 115B may be formed to have a sixth opening 116F for exposing the second end portion of the third redistribution pattern 114C so as to connect the second end portion of the third redistribution pattern 114C to the second external connection器 160B. The second external connector 160B may extend to fill the sixth opening 116F to connect to the second end portion of the third redistribution pattern 114C.

As such, the redistribution pattern 114 may include first to third redistribution patterns 114A, 114B, and 114C having different shapes.

FIG. 8 is a cross-sectional view showing the second semiconductor wafer 130 in FIG. 2.

Referring to FIGS. 2 and 8, the second semiconductor wafer 130 may include a plurality of semiconductor dies that are vertically stacked. For example, the second semiconductor wafer 130 may include a base logic semiconductor die 136 and first to fourth core semiconductor die 137A, 137B, 137C, and 137D sequentially stacked on the base logic semiconductor die 136. The second semiconductor wafer 130 including the base logic semiconductor die 136 and the first core semiconductor die to the fourth core semiconductor die 137A, 137B, 137C, and 137D can be used as a high-performance memory such as a high-bandwidth memory memory (HBM) device Body. Each of the third to fifth semiconductor wafers (130A, 130B, and 130C in FIG. 1) may be provided to have substantially the same configuration and function as the second semiconductor wafer 130.

The base logic semiconductor die 136 and the first to fourth core semiconductor die 137A, 137B, 137C, and 137D may be electrically connected to each other through an inter-die connector 138B. The inter-die connector 138B may include micro-bumps. Each of the first core semiconductor die to the third core semiconductor die 137A, 137B, and 137C may include a first through silicon via (TSV) 138A penetrating its body, and the first core semiconductor die to the third core The first through-silicon vias (TSV) 138A of the semiconductor die 137A, 137B, and 137C may be vertically connected through the die-to-die connector 138B to form an input / output (I / O) path. The fourth core semiconductor die 137D corresponding to the topmost semiconductor die among the first core semiconductor die to the fourth core semiconductor die 137A, 137B, 137C, and 137D may not include a TSV (TSV) ). However, in some other embodiments, the fourth core semiconductor die 137D may also include a through silicon via (TSV).

The first to fourth core semiconductor die 137A, 137B, 137C, and 137D may include substantially the same integrated circuits to perform the same operation. The first core semiconductor die to the fourth core semiconductor die 137A, 137B, 137C, and 137D may include a DRAM unit to provide a data bank. The base logic semiconductor die 136 can control operations of the first core semiconductor die to the fourth core semiconductor die 137A, 137B, 137C, and 137D.

The base logic semiconductor die 136 may include a second through silicon via (TSV) 136A, and the second TSV 136A is coupled to the first TSV 138A of the first core semiconductor die 137A through an inter-die connector 138B. The base logic semiconductor die 136 may include a wafer pad 135 that electrically connects the second semiconductor wafer 130 to the interconnect layer (110 of FIG. 2). The wafer pad 135 may include a first wafer pad 135A shown in FIG. 5 and a second wafer pad 135B shown in FIG. 6. The base logic semiconductor die 136 may further include an internal interconnection line 136B connecting the second TSV 136A to the wafer pad 135.

The second semiconductor wafer 130 and the third to fifth semiconductor wafers (130A, 130B, and 130C of FIG. 1) may provide a memory piece, and the first semiconductor wafer (120 of FIG. 2) may be, for example, a central processing unit (CPU) ) Or graphics processing unit (GPU) processor. In this case, the semiconductor package element 100 of FIG. 1 or the semiconductor package element 100S of FIG. 4 may correspond to a system on a chip (SoC). Therefore, the first semiconductor wafer 120 and the second semiconductor wafer 130 can transmit data to each other at high speed and wide bandwidth.

The second semiconductor wafer 130 may further include an internal protection layer 139 that covers and protects the base logic semiconductor die 136 and the first to fourth core semiconductor die 137A, 137B, 137C, and 137D. The inner protective layer 139 may be formed to include a sealant such as an EMC material or an underfill material. The internal protection layer 139 may be formed to expose the side surfaces 136S of the base logic semiconductor die 136 and cover the side surfaces of the first core semiconductor die to the fourth core semiconductor die 137A, 137B, 137C, and 137D. The internal protective layer 139 may be formed to expose the top surface of the fourth core semiconductor die 137D (ie, the top surface 131 of the second semiconductor wafer 130).

9 to 14 are cross-sectional views illustrating a method of manufacturing a semiconductor package element according to an embodiment.

Referring to FIG. 9, the second semiconductor wafer 130, the heat transfer plate 140, and the third semiconductor wafer 130A may be disposed on a first carrier 191. The heat transfer plate 140 may be disposed between the second semiconductor wafer 130 and the third semiconductor wafer 130A spaced apart from each other. In this case, as shown in FIG. 1, the fourth semiconductor wafer and the fifth semiconductor wafer (130B and 130C of FIG. 1) may also be disposed to be spaced apart from the second semiconductor wafer 130 and the third semiconductor wafer 130A. The second semiconductor wafer 130 may be mounted on the first carrier 191 such that the wafer pad 135 on the bottom surface 132 of the second semiconductor wafer 130 faces the surface of the first carrier 191. Therefore, the top surface 131 of the second semiconductor wafer 130 may be located on the opposite side of the first carrier 191.

The second semiconductor wafer 130, the heat transfer plate 140, and the third semiconductor wafer 130A may be temporarily attached to the surface of the first carrier 191 using an adhesive layer. In subsequent processes, the first carrier 191 may be used as a support for supporting the second semiconductor wafer 130, the heat transfer plate 140, and the third semiconductor wafer 130A. The first carrier 191 may have a wafer form, so that wafer-level packaging technology is applied to the first carrier 191.

Referring to FIG. 10, an initial sealant layer 159 may be formed on the first carrier 191 to cover the second semiconductor wafer 130, the heat transfer plate 140, and the third semiconductor wafer 130A. The initial sealant layer 159 can fix the relative positions of the second semiconductor wafer 130, the heat transfer plate 140, and the third semiconductor wafer 130A. The initial sealant layer 159 may be formed of a sealing layer to protect the second semiconductor wafer 130, the heat transfer plate 140, and the third semiconductor wafer 130A.

The planarization process may be applied to the top surface of the initial sealant layer 159 to remove the upper portion of the initial sealant layer 159. The planarization process may be performed using a removal process such as a grinding process. An upper portion of the initial sealant layer 159 may be selectively removed through a planarization process to provide a sealant layer 150 having a reduced thickness and a planarized surface. A planarization process may be performed to expose the top surface 141 of the heat transfer plate 140. In addition, after the planarization process is performed, the top surface 131 of the second semiconductor wafer 130 may be exposed, and the top surface 131A of the third semiconductor wafer 130A may also be exposed.

The sealant layer 150 may fix the second semiconductor wafer 130, the heat transfer plate 140, and the third semiconductor wafer 130A to the first carrier 191 to form a reconstruction wafer 100W. The reconstructed wafer 100W may be configured to include a sealant layer 150 filling a gap between the second semiconductor wafer 130, the heat transfer plate 140, and the third semiconductor wafer 130A. The reconstructed wafer 100W may have a wafer shape to be processed by a device that processes a semiconductor wafer. That is, the reconstructed wafer 100W may be a wafer-shaped layer having a first surface 101W and a second surface 102W opposed to each other. Therefore, redistribution layers and bumps can be formed on the reconstructed wafer 100W using various semiconductor processes.

After the reconstruction wafer 100W is formed, the first carrier 191 may be detached from the reconstruction wafer 100W.

Referring to FIG. 11, the reconstructed wafer 100W may be flipped so that the first surface 101W of the reconstructed wafer 100W is located at a higher level than the second surface 102W of the reconstructed wafer 100W. A second carrier 193 may then be attached to the second surface 102W of the reconstructed wafer 100W to support the reconstructed wafer 100W. In some other embodiments, the process for attaching the second carrier 193 to the reconstructed wafer 100W may be omitted. The bottom surface 152 of the sealant layer 150 opposite to the second carrier 193 may be exposed at the first surface 101W of the reconstruction wafer 100W. In addition, the bottom surface 132 of the second semiconductor wafer 130 opposite to the second carrier 193 may be exposed at the first surface 101W of the reconstruction wafer 100W. In addition, the bottom surface 142 of the heat transfer plate 140 opposite to the second carrier 193 may also be exposed at the first surface 101W of the reconstruction wafer 100W. Also, the bottom surface 132A of the third semiconductor wafer 130A opposite to the second carrier 193 may be exposed at the first surface 101W of the reconstruction wafer 100W.

Referring to FIG. 12, the interconnection layer 110 may be formed on the first surface 101W of the reconstruction wafer 100W. The interconnection layer 110 may be provided to include a dielectric layer 115 and a redistribution pattern 114 embedded in the dielectric layer 115. The interconnection layer 110 may be formed on the reconstruction wafer 100W such that the second surface 112 of the interconnection layer 110 is in contact with the first surface 101W of the reconstruction wafer 100W, and the first surface 111 of the interconnection layer 110 is exposed. Some of the redistribution patterns 114 in the dielectric layer 115 may be formed to be electrically connected to the second semiconductor wafer 130.

Referring to FIG. 13, the first semiconductor wafer 120 may be mounted on the first surface 111 of the interconnection layer 110 using an internal connector 121. In this case, the internal connector 121 may be in contact with the interconnection layer 110 to be electrically connected to some of the redistribution patterns 114. The external connector 160 may be attached to the first surface 111 of the interconnection layer 110. The external connector 160 may be attached to the interconnection layer 110 to be electrically connected to some of the redistribution patterns 114 in the interconnection layer 110.

In the case where the second carrier 193 is attached to the reconstructed wafer 100W in the previous process, the second carrier 193 may be detached from the reconstructed wafer 100W after the external connector 160 is attached to the interconnection layer 110.

Referring to FIG. 14, a die separation process may be used to perform a separation process to separate the semiconductor package elements 100 from each other. As shown in FIG. 4, the heat sink (180 of FIG. 4) may be additionally attached to each semiconductor package element 100 using a thermal interface material layer (181 of FIG. 4).

According to the above-described embodiment, a semiconductor package element is provided, each semiconductor package element being configured to include a plurality of semiconductor wafers three-dimensionally stacked above and below an interconnect layer. In a plan view, the interconnection layer may be configured to include a redistribution pattern extending into an outer region of the semiconductor wafer. Since one of the semiconductor wafers is disposed to overlap vertically and partially with the remaining semiconductor wafers, the length of the routing path between the physical layers included in the semiconductor wafer can be reduced, and each semiconductor package can also be reduced The planar area of the component.

Each semiconductor package element may further include a heat transfer plate overlapping with any one of the plurality of semiconductor wafers. The heat transfer plate may penetrate the sealant layer of the semiconductor package element to provide a heat conduction path extending from the interconnect layer to reach the top surface of the semiconductor package element. Therefore, the heat transfer plate can improve the cooling efficiency of the semiconductor package element.

FIG. 15 is a block diagram showing an electronic system including a memory card 7800 employing at least one semiconductor package element according to an embodiment. The memory card 7800 may include a memory 7810 and a memory controller 7820 such as non-volatile memory pieces. The memory 7810 and the memory controller 7820 can store data or read out the stored data. At least one of the memory 7810 and the memory controller 7820 may include at least one semiconductor package element according to an embodiment.

The memory 7810 may include a non-volatile memory piece to which the technology of the embodiment of the present disclosure is applied. The memory controller 7820 may control the memory 7810 so that it reads out the stored data or stores the data in response to a read / write request from the host 7830.

FIG. 16 is a block diagram illustrating an electronic system 8710 including at least one semiconductor package element according to an embodiment. The electronic system 8710 may include a controller 8711, an input / output unit 8712, and a memory 8713. The controller 8711, the input / output unit 8712, and the memory 8713 may be coupled to each other through a bus 8715, which provides a path for moving data through it.

In one embodiment, the controller 8711 may include one or more of a microprocessor, a digital signal processor, a microcontroller, and / or a logic device capable of performing the same functions as these elements. The controller 8711 or the memory 8713 may include at least one semiconductor package element according to an embodiment of the present disclosure. The input / output unit 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, and the like. Memory 8713 is a device for storing data. The memory 8713 may store data and / or commands and the like to be executed by the controller 8711.

The memory 8713 may include a volatile memory device such as a DRAM and / or a non-volatile memory device such as a flash memory. For example, flash memory can be installed in an information processing system such as a mobile terminal or a desktop computer. Flash memory can form a solid state disk (SSD). In this case, the electronic system 8710 can stably store a large amount of data in the flash memory storage system.

The electronic system 8710 may further include an interface 8714 configured to transmit and receive data to and from the communication network. The interface 8714 may be a wired type or a wireless type. For example, the interface 8714 may include an antenna or a wired or wireless transceiver.

The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, mobile systems can be in personal digital assistants (PDAs), portable computers, tablets, mobile phones, smart phones, wireless phones, laptops, memory cards, digital music systems, and information transmission / reception systems. Either.

If the electronic system 8710 is a device capable of performing wireless communication, the electronic system 8710 can be used in a communication system having the following technologies: CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (Digital cellular North America), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution) or Wibro (Wireless Broadband Internet).

Embodiments of the present disclosure have been disclosed for illustrative purposes. Those skilled in the art will understand that various modifications, additions and substitutions may be made without departing from the scope and spirit of the disclosure and the appended claims.

100, 100S‧‧‧ semiconductor package components

100W‧‧‧Reconstruction chip

101W, 102W‧‧‧ first surface, second surface

110‧‧‧interconnect layer

111, 112‧‧‧ first surface, second surface

114, 114A, 114B, 114C ‧‧‧ redistribution pattern

115, 115A, 115B‧‧‧Dielectric layers

116A, 116B, 116C, 116D, 116E, 116F‧‧‧ opening

120‧‧‧Semiconductor wafer

120C‧‧‧ Corner Area

121, 121A, 121B‧‧‧ Internal connectors

130, 130A, 130B, 130C‧‧‧ semiconductor wafer

130E‧‧‧Marginal area

131, 131A‧‧‧Top surface

132, 132A‧‧‧ bottom surface

133, 133A‧‧‧ side surface

135, 135A, 135B‧‧‧ Wafer Mat

136‧‧‧Base Logic Semiconductor Die

136A‧‧‧Silicon Via

136B‧‧‧Interconnect

136S‧‧‧side surface

137A, 137B, 137C, 137D‧‧‧Core semiconductor bare die

138A, 138B ‧‧‧Silicon Via

139‧‧‧Inner protective layer

140‧‧‧heat transfer plate

141‧‧‧Top surface

142‧‧‧ bottom surface

143, 143A‧‧‧ side surface

150‧‧‧sealing layer

151‧‧‧Top surface

152‧‧‧ bottom surface

159‧‧‧ initial sealing layer

160, 160A, 160B‧‧‧External connectors

170‧‧‧circuit board

171‧‧‧Internal interval

180‧‧‧ Radiator

181‧‧‧ thermal interface material layer

191, 193‧‧‧ first carrier, second carrier

7800‧‧‧Memory Card

7810‧‧‧Memory

7820‧‧‧Memory Controller

7830‧‧‧Host

8710‧‧‧Electronic System

8711‧‧‧Controller

8712‧‧‧Input / Output Unit

8713‧‧‧Memory

8714‧‧‧Interface

8715‧‧‧Bus

A-A'‧‧‧ hatching

D1, D2‧‧‧ first distance, second distance

E1, E2, E3‧‧‧ Zone

H1, H2‧‧‧ first height, second height

T‧‧‧thickness

[Fig. 1] A plan view showing a semiconductor package element according to an embodiment. [Fig. 2] A sectional view taken along line AA 'of Fig. 1. [Fig. [FIG. 3] A cross-sectional view showing a heat conduction path of the semiconductor package element shown in FIG. 2. [FIG. 4] A cross-sectional view showing a semiconductor package element according to an embodiment. 5 to 7 are sectional views showing a configuration of an interconnection layer included in a semiconductor package element according to an embodiment. [FIG. 8] A sectional view showing a semiconductor wafer included in a semiconductor package element according to an embodiment. 9 to 14 are cross-sectional views illustrating a method of manufacturing a semiconductor package element according to an embodiment. [FIG. 15] A block diagram showing an electronic system employing a memory card including a semiconductor package element according to an embodiment. [FIG. 16] A block diagram showing an electronic system including a semiconductor package element according to an embodiment.

no.

Claims (20)

A semiconductor package element includes: a first semiconductor wafer provided on a first surface of an interconnection layer; a second semiconductor wafer and a third semiconductor wafer, the second semiconductor wafer and the third semiconductor wafer being spaced apart from each other And disposed on the second surface of the interconnection layer; and a heat transfer plate disposed between the second semiconductor wafer and the third semiconductor wafer, in contact with the second surface of the interconnection layer, and Overlapping with the first semiconductor wafer; wherein the heat transfer plate provides a heat radiation path. The semiconductor package element according to claim 1, wherein the heat transfer plate has a bottom surface that is in contact with a second surface of the interconnect layer; and wherein the heat transfer plate has One side surface of the side surface of the second semiconductor wafer and the other side surface of the side surface facing the third semiconductor wafer. The semiconductor package element according to claim 1, further comprising a sealant layer covering a second surface of the interconnect layer and side surfaces of the second semiconductor wafer and the third semiconductor wafer, And a gap between the second semiconductor wafer and the heat transfer plate is filled. The semiconductor package element according to claim 3, wherein the heat transfer plate is provided to penetrate the sealant layer; and wherein the sealant layer exposes a top surface of the heat transfer plate. The semiconductor package element according to claim 4, wherein the sealant layer is provided to expose a top surface of the second semiconductor wafer. The semiconductor package element according to claim 1, further comprising a heat sink attached to the heat transfer plate. The semiconductor package element according to claim 6, wherein the heat sink extends to contact a top surface of the second semiconductor wafer. The semiconductor package element according to claim 6, further comprising a thermal interface material layer provided between the heat sink and the heat transfer plate. The semiconductor package element according to claim 3, wherein the interconnection layer comprises: a redistribution pattern extending from a portion of the interconnection layer overlapping with the second semiconductor wafer to Another portion overlapping the sealant layer; and a dielectric layer that insulates the redistribution patterns from each other. The semiconductor package element according to claim 1, wherein the second semiconductor wafer has an edge region overlapping a corner region of the first semiconductor wafer. The semiconductor package element according to claim 10, wherein the interconnection layer includes a first redistribution pattern, the first redistribution pattern, the corner region of the first semiconductor wafer, and the second semiconductor Both of the edge regions of the wafer overlap, and the first redistribution pattern electrically connects the first semiconductor wafer to the second semiconductor wafer vertically. The semiconductor package element according to claim 10, wherein a solid layer having an interface structure for signal transmission between the first semiconductor wafer and the second semiconductor wafer is provided on the first semiconductor wafer. In the corner region, another physical layer having an interface structure for signal transmission between the first semiconductor wafer and the second semiconductor wafer is disposed in an edge region of the second semiconductor wafer. The semiconductor package element according to claim 1, further comprising an external connector attached to the first surface of the interconnection layer. The semiconductor package element according to claim 13, wherein the interconnection layer includes a second redistribution pattern that electrically connects one of the external connectors to the first redistribution pattern. Two semiconductor wafers. The semiconductor package element according to claim 14, wherein the second redistribution pattern is extended such that a first end portion of the second redistribution pattern is connected to a wafer pad of the second semiconductor wafer, and the first A second end portion of the dual redistribution pattern is connected to one of the external connectors. The semiconductor package component according to claim 14, wherein the interconnection layer includes a dielectric layer having a first opening and a second opening, the first opening exposes a wafer pad of the second semiconductor wafer, and The second opening exposes a second end portion of the second redistribution pattern; and wherein the first opening is filled with the first end portion of the second redistribution pattern, and the second opening is filled with The one external connector is filled. The semiconductor package element according to claim 12, wherein the interconnection layer further includes a third redistribution pattern that electrically connects the second semiconductor wafer to one of the external connectors Connector. The semiconductor package element according to claim 12, wherein an external connector is provided to surround a side surface of the first semiconductor wafer. The semiconductor package element according to claim 12, wherein a height ratio from a first surface of the interconnection layer to a surface of the first semiconductor wafer opposite to the interconnection layer is attached to the interconnection layer The height of the external connector on the first surface is small. A semiconductor package element includes: a first semiconductor wafer provided on a first surface of an interconnection layer; a second semiconductor wafer provided on a second surface of the interconnection layer such that the first semiconductor wafer Four corner regions of each overlap with an edge region of the second semiconductor wafer; and a heat transfer plate disposed between the second semiconductor wafers to contact the second surface of the interconnect layer and to the second surface of the interconnect layer The first semiconductor wafer overlaps; wherein the heat transfer plate provides a heat radiation path.