TW201929013A - Method for forming capacitor structure - Google Patents
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- TW201929013A TW201929013A TW106144978A TW106144978A TW201929013A TW 201929013 A TW201929013 A TW 201929013A TW 106144978 A TW106144978 A TW 106144978A TW 106144978 A TW106144978 A TW 106144978A TW 201929013 A TW201929013 A TW 201929013A
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- 239000003990 capacitor Substances 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 21
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 14
- 239000000463 material Substances 0.000 claims description 11
- 230000003746 surface roughness Effects 0.000 claims description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims 2
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 15
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000000059 patterning Methods 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- -1 HfZrO 4 ) Chemical compound 0.000 description 2
- 229910052454 barium strontium titanate Inorganic materials 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- SIOXCQVDGDVRSM-UHFFFAOYSA-B [Hf+4].[Hf+4].[Hf+4].OC(CC([O-])=O)(CC([O-])=O)C([O-])=O.OC(CC([O-])=O)(CC([O-])=O)C([O-])=O.OC(CC([O-])=O)(CC([O-])=O)C([O-])=O.OC(CC([O-])=O)(CC([O-])=O)C([O-])=O Chemical compound [Hf+4].[Hf+4].[Hf+4].OC(CC([O-])=O)(CC([O-])=O)C([O-])=O.OC(CC([O-])=O)(CC([O-])=O)C([O-])=O.OC(CC([O-])=O)(CC([O-])=O)C([O-])=O.OC(CC([O-])=O)(CC([O-])=O)C([O-])=O SIOXCQVDGDVRSM-UHFFFAOYSA-B 0.000 description 1
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- VNSWULZVUKFJHK-UHFFFAOYSA-N [Sr].[Bi] Chemical compound [Sr].[Bi] VNSWULZVUKFJHK-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
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- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
本發明係有關於半導體製程領域，尤其是關於一種改善電容結構良率與品質的方法。The present invention relates to the field of semiconductor fabrication, and more particularly to a method of improving the yield and quality of a capacitor structure.
電容結構是半導體技術領域中重要的元件之一，尤其是針對記憶體元件製作，電容結構更是不可或缺的元件。電容結構的品質，也將會直接影響到後續完成的記憶體元件之品質。Capacitor structure is one of the important components in the field of semiconductor technology, especially for memory device fabrication, capacitor structure is an indispensable component. The quality of the capacitor structure will also directly affect the quality of the subsequently completed memory components.
電容結構一般由上電極、下電極，以及位於上下電極中間的介電層所組成。在製作電容結構的過程中，由於電極常會採用物理氣相沉積的方式形成，所製作成的電極表面較為粗糙，如此將會影響到電容以及記憶體的品質與良率。因此如何解決上述問題並提高電容的品質與良率，為半導體製程領域的研究目標之一。The capacitor structure generally consists of an upper electrode, a lower electrode, and a dielectric layer located between the upper and lower electrodes. In the process of fabricating the capacitor structure, since the electrode is often formed by physical vapor deposition, the surface of the electrode is rough, which will affect the capacitance and the quality and yield of the memory. Therefore, how to solve the above problems and improve the quality and yield of capacitors is one of the research goals in the field of semiconductor manufacturing.
本發明提供一種電容結構的製作方法，首先，提供一基底，基底上形成有一下電極，該下電極具有一粗糙頂面，接著對該下電極進行一平坦化步驟，以將該下電極的該粗糙頂面全部轉換為一平坦頂面，且形成一氮氧化物層於該平坦頂面上，然後對該氮氧化物層進行一氮氣處理，以移除該氮氧化物層，以及依序形成一介電層以及一上電極於該下電極的該平坦頂面上。The present invention provides a method for fabricating a capacitor structure. First, a substrate is provided. A bottom electrode is formed on the substrate, the lower electrode has a rough top surface, and then a planarization step is performed on the lower electrode to The rough top surface is all converted into a flat top surface, and an oxynitride layer is formed on the flat top surface, and then the nitrogen oxide layer is subjected to a nitrogen treatment to remove the oxynitride layer and sequentially form A dielectric layer and an upper electrode are on the flat top surface of the lower electrode.
本發明所述的電容結構，其包含有下電極、介電層以及上電極，此外由於下電極的表面依序經過平坦化處理以及氮氣處理，因此不但可以降低下電極的表面粗糙度，更可以同時避免由水氣所產生的氮氧化物層影響電容結構的品質。總而言之，本發明提供一種提高電容結構製程良率與品質的方法。The capacitor structure of the present invention comprises a lower electrode, a dielectric layer and an upper electrode. In addition, since the surface of the lower electrode is sequentially subjected to planarization treatment and nitrogen treatment, the surface roughness of the lower electrode can be reduced, and At the same time, the NOx layer generated by moisture is prevented from affecting the quality of the capacitor structure. In summary, the present invention provides a method of improving the yield and quality of a capacitor structure process.
為使熟習本發明所屬技術領域之一般技藝者能更進一步了解本發明，下文特列舉本發明之較佳實施例，並配合所附圖式，詳細說明本發明的構成內容及所欲達成之功效。The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .
為了方便說明，本發明之各圖式僅為示意以更容易了解本發明，其詳細的比例可依照設計的需求進行調整。在文中所描述對於圖形中相對元件之上下關係，在本領域之人皆應能理解其係指物件之相對位置而言，因此皆可以翻轉而呈現相同之構件，此皆應同屬本說明書所揭露之範圍，在此容先敘明。For the convenience of description, the drawings of the present invention are only for the purpose of understanding the present invention, and the detailed proportions thereof can be adjusted according to the design requirements. As described in the text for the relative relationship between the relative elements in the figure, it should be understood by those skilled in the art that it refers to the relative position of the object, and therefore can be flipped to present the same member, which should belong to the same specification. The scope of the disclosure is hereby stated.
請參考第1圖至第4圖，其繪示本發明製作電容結構的方法的結構示意圖。首先，如第1圖所示，提供一基底100，例如為一矽基底。接下來，預定在基底100上形成一電容結構，其中電容結構一般係由導電層-介電層-導電層所堆疊形成的結構。上下兩層導電層分別作為上下電極使用，而兩電極之間夾有一介電材質層。首先，形成一下電極102於基底100上，其中值得注意的是，下電極102可能已經經過圖案化步驟，形成所需的圖案於基底100上，材質例如為氮化鈦(TiN)或氮化鉭(TaN)，但不限於此。形成下電極102的方法例如為物理氣相沉積(Physical Vapor Deposition，PVD)。申請人發現，當使用物理氣相沉積形成下電極102時，仔細觀察可發現所形成的下電極102表面具有一粗糙頂面104。當粗糙頂面104接觸到後續的介電層時，粗糙頂面104容易影響後續電容結構的品質，例如會在特定區域產生較大的電流，不利於電容結構用於儲存電荷所需的穩定度。Please refer to FIG. 1 to FIG. 4 , which are schematic structural diagrams of a method for fabricating a capacitor structure according to the present invention. First, as shown in Fig. 1, a substrate 100 is provided, such as a substrate. Next, a capacitor structure is predetermined to be formed on the substrate 100, wherein the capacitor structure is generally a structure formed by stacking a conductive layer-dielectric layer-conductive layer. The upper and lower conductive layers are respectively used as upper and lower electrodes, and a dielectric material layer is sandwiched between the two electrodes. First, the lower electrode 102 is formed on the substrate 100. It is noted that the lower electrode 102 may have undergone a patterning step to form a desired pattern on the substrate 100, such as titanium nitride (TiN) or tantalum nitride. (TaN), but not limited to this. The method of forming the lower electrode 102 is, for example, Physical Vapor Deposition (PVD). Applicant has found that when the lower electrode 102 is formed using physical vapor deposition, it can be observed that the surface of the lower electrode 102 formed has a rough top surface 104. When the rough top surface 104 contacts the subsequent dielectric layer, the rough top surface 104 easily affects the quality of the subsequent capacitor structure, such as generating a large current in a specific area, which is disadvantageous for the stability required for the capacitor structure to store the charge. .
因此，如第2圖所示，本發明在形成下電極102後，於後續繼續形成介電層之前，先對下電極102的粗糙頂面104進行一平坦化步驟P1，例如為化學機械研磨(Chemical-Mechanical Planarization)製程。由於下電極102位於平坦的基底100上，從剖面圖來看也具有一平坦結構，因此平坦化步驟P1之後，所有下電極102的粗糙頂面104被完全移除，進而磨平取代成為一平坦頂面106。此時，對於上述下電極102頂面粗糙的問題已經解決。根據申請人的實驗，未進行平坦化步驟P1之前，粗糙頂面104的表面粗糙度(Ra)大於1.9奈米，而進行平坦化步驟P1之後，平坦頂面106的表面粗糙度(Ra) 小於0.39奈米。其中此處所述的表面粗糙度之計算方法為整個樣本上取多個計算點(例如n個計算點)，中心線距離外形偏差值的算術平均數，換句話說，Ra=(|Y1|+|Y2|+.....+|Yn|)/n。其中|Y1|為第一個計算點與中心線的垂直距離之絕對值，|Y2|為第二個計算點與中心線的垂直距離之絕對值，以此類推。其他關於表面粗糙度的取點或計算方式屬於本領域的已知技術，在此不多加贅述。Therefore, as shown in FIG. 2, after forming the lower electrode 102, the present invention performs a planarization step P1 on the rough top surface 104 of the lower electrode 102, for example, chemical mechanical polishing (before continuing to form the dielectric layer). Chemical-Mechanical Planarization) Process. Since the lower electrode 102 is located on the flat substrate 100, it also has a flat structure from the cross-sectional view. Therefore, after the planarization step P1, the rough top surfaces 104 of all the lower electrodes 102 are completely removed, and the flattening is replaced by a flattening. Top surface 106. At this time, the problem of the top surface roughness of the lower electrode 102 described above has been solved. According to the applicant's experiment, the surface roughness (Ra) of the rough top surface 104 is greater than 1.9 nm before the planarization step P1 is performed, and the surface roughness (Ra) of the flat top surface 106 is less than after the planarization step P1 is performed. 0.39 nm. The method for calculating the surface roughness described herein is to take a plurality of calculation points (for example, n calculation points) on the entire sample, and the arithmetic mean of the center line distance shape deviation value, in other words, Ra=(|Y1| +|Y2|+.....+|Yn|)/n. Where |Y1| is the absolute value of the vertical distance between the first calculated point and the centerline, |Y2| is the absolute value of the vertical distance between the second calculated point and the centerline, and so on. Other ways of taking or calculating the surface roughness are known in the art and will not be described here.
然而，如第2圖所示，根據申請人的實驗，當平坦化步驟P1之後，下電極102的粗糙表面雖然被移除，並且產生一平坦頂面106。然而，平坦頂面106的親水性較原先的粗糙頂面更好，且由於平坦化步驟P1的過程中含有研磨液等水氣，因此水氣會與裸露的下電極102材質(例如為氮化鈦)產生反應而形成氧化物。舉例來說，在平坦頂面106頂面將會額外形成一氮氧化物層108，本實施例中氮氧化物層為氮氧化鈦(TiON)，但不限於此。根據不同的下電極材質，氮氧化物層108的材質也會隨之改變。申請人發現，若在執行平坦化步驟P1之後，直接繼續形成介電層以及上電極而堆疊於下電極102表面的氮氧化物層108上，對於電容結構的良率改善效果有限。原因在於氮氧化物將會隔絕下電極102與介電層直接接觸。However, as shown in FIG. 2, according to the applicant's experiment, after the planarization step P1, the rough surface of the lower electrode 102 is removed, and a flat top surface 106 is produced. However, the flat top surface 106 is more hydrophilic than the original rough top surface, and since the flattening step P1 contains water vapor such as a polishing liquid, the moisture and the bare lower electrode 102 material (for example, nitriding) Titanium) reacts to form an oxide. For example, an oxynitride layer 108 is additionally formed on the top surface of the flat top surface 106. In this embodiment, the oxynitride layer is titanium oxynitride (TiON), but is not limited thereto. The material of the oxynitride layer 108 also changes depending on the material of the lower electrode. The Applicant has found that if the dielectric layer and the upper electrode are directly formed and stacked on the oxynitride layer 108 on the surface of the lower electrode 102 after the planarization step P1 is performed, the effect of improving the yield of the capacitor structure is limited. The reason is that the nitrogen oxides will insulate the lower electrode 102 from direct contact with the dielectric layer.
為了解決氮氧化物所產生的問題，本發明中如第3圖所示，在形成氮氧化物層108之後，繼續進行一氮氣處理P2，其中氮氣處理P2包含通入氮氣並且加熱至攝氏300度至500度。經過氮氣處理P2之後，可以有效地移除殘留於下電極表面的水氣，並且將已形成的氮氧化物層108還原，舉例來說，以本實施例來說，以形成的氮氧化鈦將會被還原成為氮化鈦，也就是還原成為下電極的材質。因此經過氮氣處理P2之後，氮氧化物層將不復存在於下電極102上，並且留下具有平坦頂面106的下電極102於基底100上。至此步驟為止，已經藉由平坦化步驟P1以及氮氣處理P2依序解決下電極表面粗糙，以及表面將會產生氮氧化物層的問題。In order to solve the problem caused by nitrogen oxides, in the present invention, as shown in FIG. 3, after the formation of the oxynitride layer 108, a nitrogen treatment P2 is continued, wherein the nitrogen treatment P2 contains nitrogen gas and is heated to 300 degrees Celsius. Up to 500 degrees. After the P2 treatment with nitrogen, the moisture remaining on the surface of the lower electrode can be effectively removed, and the formed nitrogen oxide layer 108 is reduced, for example, in the present embodiment, the titanium oxynitride formed will It will be reduced to titanium nitride, which is the material that is reduced to the lower electrode. Thus, after nitrogen treatment of P2, the oxynitride layer will no longer be present on the lower electrode 102 and leave the lower electrode 102 having a flat top surface 106 on the substrate 100. Up to this point, the surface roughness of the lower electrode has been solved in order by the planarization step P1 and the nitrogen treatment P2, and the surface will generate a problem of the oxynitride layer.
後續，如第4圖所示，在下電極102上依序形成介電層110以及上電極112。其中上電極112的材質可以與下電極102材質相同或是不同，例如為氮化鈦、氮化鉭等材質，但本發明不限於此。至於介電層110則可能包含例如介電常數大於4的介電材料，例如係選自氧化鉿(hafnium oxide，HfO2 )、矽酸鉿氧化合物(hafnium silicon oxide，HfSiO4 )、矽酸鉿氮氧化合物(hafnium silicon oxynitride，HfSiON)、氧化鋁(aluminum oxide，Al2 O3 )、氧化鑭(lanthanum oxide，La2 O3 )、氧化鉭(tantalum oxide，Ta2 O5 )、氧化釔(yttrium oxide，Y2 O3 )、氧化鋯(zirconium oxide，ZrO2 )、鈦酸鍶（strontium titanate oxide， SrTiO3 ）、矽酸鋯氧化合物(zirconium silicon oxide，ZrSiO4 )、鋯酸鉿(hafnium zirconium oxide，HfZrO4 )、鍶鉍鉭氧化物(strontium bismuth tantalate, SrBi2 Ta2 O9 , SBT)、鋯鈦酸鉛(lead zirconate titanate , PbZrxTi1 -xO3 , PZT)、鈦酸鋇鍶(barium strontium titanate, BaxSr1 -xTiO3 , BST)、或其組合所組成之群組，但不限於此，上述材質仍可依照實際需求而調整。此外關於此處所述介電層110與上電極112的材質與製作方法，屬於本領域的已知技術，在此不多加贅述。Subsequently, as shown in FIG. 4, the dielectric layer 110 and the upper electrode 112 are sequentially formed on the lower electrode 102. The material of the upper electrode 112 may be the same as or different from the material of the lower electrode 102, and is, for example, a material such as titanium nitride or tantalum nitride. However, the present invention is not limited thereto. The dielectric layer 110 may include, for example, a dielectric material having a dielectric constant greater than 4, for example, selected from hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), and hafnium citrate. Hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (Ta 2 O 5 ), cerium oxide ( Yttrium oxide, Y 2 O 3 ), zirconium oxide (ZrO 2 ), strontium titanate oxide (SrTiO 3 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconate Zirconium oxide, HfZrO 4 ), strontium bismuth tantalate (SrBi 2 Ta 2 O 9 , SBT), lead zirconate titanate (PbZrxTi 1 -xO 3 , PZT), barium titanate ( The group consisting of barium strontium titanate, BaxSr 1 -xTiO 3 , BST), or a combination thereof is not limited thereto, and the above materials can be adjusted according to actual needs. In addition, the materials and manufacturing methods of the dielectric layer 110 and the upper electrode 112 described herein are known in the art, and will not be further described herein.
此外，在上述的實施例中，先對下電極102進行圖案化步驟，形成所需的電極圖案之後才進行平坦化步驟以及氮氣處理。然而在本發明的其他實施例中，圖案化步驟的時間點或是順序可以調整。舉例來說，可以先形成一下電極材料層(圖未示)，覆蓋整個基底100，此時先不進行圖案化步驟，直接進行平坦化步驟P1與氮氣處理P2，並且形成介電層110與上電極材料層之後，再進行圖案化的步驟，以形成所需的電容圖案。該實施順序也屬於本發明的涵蓋範圍內。Further, in the above embodiment, the lower electrode 102 is first subjected to a patterning step to form a desired electrode pattern before the planarization step and the nitrogen treatment are performed. However, in other embodiments of the invention, the timing or order of the patterning steps can be adjusted. For example, a layer of electrode material (not shown) may be formed to cover the entire substrate 100. At this time, the patterning step is not performed, and the planarization step P1 and the nitrogen treatment P2 are directly performed, and the dielectric layer 110 and the upper layer are formed. After the electrode material layer, a patterning step is performed to form a desired capacitance pattern. This order of implementation is also within the scope of the invention.
至此步驟為止，已經完成本發明所述的電容結構114，其包含有下電極102、介電層110以及上電極112，此外由於下電極102的表面依序經過平坦化處理P1以及氮氣處理P2，因此不但可以降低下電極102的表面粗糙度，更可以同時避免由水氣所產生的氮氧化物層108影響電容結構的品質。總而言之，本發明提供一種提高電容結構製程良率與品質的方法。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。Up to this step, the capacitor structure 114 of the present invention has been completed, which includes the lower electrode 102, the dielectric layer 110 and the upper electrode 112, and further, since the surface of the lower electrode 102 is sequentially subjected to the planarization treatment P1 and the nitrogen treatment P2, Therefore, not only the surface roughness of the lower electrode 102 can be reduced, but also the oxynitride layer 108 generated by moisture can be prevented from affecting the quality of the capacitor structure. In summary, the present invention provides a method of improving the yield and quality of a capacitor structure process. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
100‧‧‧基底100‧‧‧Base
102‧‧‧下電極102‧‧‧ lower electrode
104‧‧‧粗糙頂面104‧‧‧Rough top
106‧‧‧平坦頂面106‧‧‧flat top surface
108‧‧‧氮氧化物層108‧‧‧Nitrogen oxide layer
110‧‧‧介電層110‧‧‧ dielectric layer
112‧‧‧上電極112‧‧‧Upper electrode
114‧‧‧電容結構114‧‧‧Capacitor structure
P1‧‧‧平坦化步驟P1‧‧‧ flattening steps
P2‧‧‧氮氣處理P2‧‧‧Nitrogen treatment
第1圖繪示本發明製作電容結構的方法的結構示意圖。 第2圖繪示本發明製作電容結構的方法的結構示意圖。 第3圖繪示本發明製作電容結構的方法的結構示意圖。 第4圖繪示本發明製作電容結構的方法的結構示意圖。FIG. 1 is a schematic structural view of a method of fabricating a capacitor structure according to the present invention. FIG. 2 is a schematic structural view of a method of fabricating a capacitor structure according to the present invention. FIG. 3 is a schematic structural view of a method of fabricating a capacitor structure according to the present invention. FIG. 4 is a schematic structural view of a method of fabricating a capacitor structure according to the present invention.
Claims (8)
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