TW201928074A - Wiring structure and target material - Google Patents

Abstract

The wiring structure (10) of the present invention includes a glass substrate (11), an intermediate layer (12) provided on the glass substrate (11), and a wiring layer (13) provided on the intermediate layer (12). The wiring layer (13) contains copper. The intermediate layer (12) contains zirconium and the remainder contains copper and unavoidable impurities. The ratio of the molar number of zirconium contained in the intermediate layer (12) to the total molar number of copper and zirconium is 5 mol% or more and 33 mol% or less. The intermediate layer (12) preferably further contains silicon. It is also preferable to include an insulating layer (15) on the wiring layer (13).

Description

Wiring structure and target

The present invention relates to a wiring structure. The present invention also relates to a target for manufacturing the wiring structure.

As the wiring film of a circuit substrate used for a touch panel of a liquid crystal display, a plasma display, or an organic EL (Electroluminescence) display device, an aluminum alloy is mostly used. Recently, along with the high definition and high speed of devices, the miniaturization and thinning of wiring films have been demanded, so that wiring films with lower resistivity than aluminum alloys are required. Therefore, copper with low resistance and high melting point has attracted attention. However, since the adhesion between copper and glass or silicon is poor, it is necessary to arrange an adhesion layer between a copper wiring film and a substrate containing glass or the like to improve the adhesion between the two.

Patent Document 1 describes a technique for providing a barrier layer containing titanium between a glass substrate and a copper thin film as a main conductive film. This barrier layer is considered to have the effect | action which improves the adhesiveness of a glass substrate and a copper thin film.

Patent Document 2 describes that a conductive film is provided on a SiO ₂ substrate by using a sputtering target containing copper as a main component and added with zirconium, thereby improving the adhesion between the SiO ₂ substrate and the conductive film. Prior art literature patent literature

Patent Document 1: US Patent Application Publication No. 2012/0315757 Patent Document 2: Japanese Patent Laid-Open No. 3-196619

The technology described in Patent Document 1 is a separate titanium-containing layer from a copper thin film as a main conductive film. Due to the high performance of thin-film transistors in recent years, the tendency to increase the process temperature has gradually increased. Therefore, the diffusion of elements is likely to occur between copper and titanium. As a result, there is a possibility that the conductivity of the copper thin film is reduced.

The technology described in Patent Document 2 relates to a method in which a conductive film is directly provided on a substrate and the adhesion between the conductive film and the substrate is improved. This conductive film contains zirconium in addition to copper as a main conductive material. Since the volume resistance value of zirconium is one bit higher than the volume resistance value of copper, it is difficult to express sufficient conductivity if the conductive film is used directly.

Therefore, an object of the present invention is to provide a technology for improving the adhesion between a wiring layer and a substrate without impairing the conductivity of the wiring layer in a wiring structure including a wiring layer containing copper.

As a result of diligent research, the inventors have found that the above-mentioned problem is solved by forming an intermediate layer containing a specific alloy between the substrate and the wiring layer containing copper.

The present invention is based on the above findings and solves the above problems by providing a wiring structure including a glass substrate, an intermediate layer provided on the glass substrate, and a wiring layer provided on the intermediate layer. The wiring layer contains copper, the intermediate layer contains zirconium and the remainder contains copper and unavoidable impurities, and the ratio of the molar number of zirconium contained in the intermediate layer to the total molar number of copper and zirconium is 5 More than Molar% and less than 33 Molar%.

In addition, the present invention provides a target material for use in manufacturing the above-mentioned wiring structure. The target material contains zirconium and the remaining portion contains copper and unavoidable impurities, or the target material contains zirconium and silicon and the remaining portion contains copper and unavoidable Impurities.

Hereinafter, the present invention will be described based on its preferred embodiments with reference to the drawings. An embodiment of the wiring structure of the present invention is shown in FIG. 1. The wiring structure 10 shown in the figure is used for, for example, various semiconductor devices such as a thin film transistor. The wiring structure 10 includes a glass substrate 11.

A copper-containing wiring layer 13 is provided on the glass substrate 11. The so-called copper-containing wiring layer refers to the wiring of a circuit containing pure copper or a copper alloy, and is generally composed of a thin film layer formed on the glass substrate 11 by various thin film forming methods. The thickness of the wiring layer 13 can be arbitrarily set according to the specific application of the wiring structure 10, and can be set to, for example, 100 nm or more and 2000 nm or less.

When the wiring layer 13 contains a copper alloy, examples of the copper alloy include copper-based alloys containing one or two or more elements selected from the group consisting of manganese, magnesium, bismuth, and indium as alloying components. These alloy components may be contained in the copper alloy at a ratio of 0.01 mol% to 25 mol%. When the wiring layer 13 contains a copper alloy, the copper alloy is different from or the same as the alloy constituting the metal layer 14 described below.

When the wiring layer 13 contains copper, as long as the wiring layer 13 has the original conductivity of copper, it is allowed to contain trace elements other than copper. From the viewpoint of ensuring conductivity and being easily etched together with the intermediate layer 12 described below, an alloy containing copper and unavoidable impurities is preferred, and the purity after removing gas components such as oxygen is more preferred 3 N or higher purity.

The thickness of the wiring layer 13 is preferably 100 nm to 2000 nm. By setting the thickness of the wiring layer 13 to 100 nm or more, the conductivity required as a wiring structure is ensured. In addition, by setting the thickness of the wiring layer 13 to 2000 nm or less, the wiring layer 13 does not become an obstacle when used in a multilayer build-up substrate, and does not become excessively thick with respect to the width direction, so that it can cope with high definition. Furthermore, it is not easy to impair mass productivity at the time of manufacture of a circuit board. From such a viewpoint, the thickness of the wiring layer 13 is more preferably 150 nm to 1200 nm, and more preferably 200 nm to 800 nm.

An intermediate layer 12 is formed between the wiring layer 13 and the glass substrate 11 to improve the adhesion between the two. The intermediate layer 12 is directly connected to the glass substrate 11 and is also directly connected to the wiring layer 13. In other words, no layer is initially interposed between the intermediate layer 12 and the glass substrate 11 in the film formation step. Similarly, no layer is initially interposed between the intermediate layer 12 and the wiring layer 13 in the film formation step.

From the viewpoint of improving the adhesion between the wiring layer 13 and the glass substrate 11, the intermediate layer 12 is made of a material containing zirconium and the remainder containing copper and unavoidable impurities. That is, the intermediate layer 12 contains a copper-zirconium (Cu-Zr) alloy (hereinafter, "an alloy containing zirconium and the remainder containing copper and unavoidable impurities" is also referred to as "copper-zirconium alloy"). As a result of a study by the present inventors, it was found that by providing the intermediate layer 12 having the alloy composition between the glass substrate 11 and the wiring layer 13, the adhesion between the glass substrate 11 and the wiring layer 13 is effectively improved. In addition, since zirconium is an element having low diffusibility with copper, there is an advantage that the conductivity of the wiring layer 13 is not easily reduced even when the wiring structure 10 is used in a high-temperature environment. In this way, by using a copper-zirconium alloy as the intermediate layer 12, it is possible to improve the adhesion between the wiring layer 13 and the glass substrate 11 without impairing the conductivity of the wiring layer 13. These advantages can also be said when using the copper-zirconium-silicon alloy described below as the intermediate layer 12.

The copper-zirconium alloy can be easily etched by a known etching solution such as copper chloride or a sulfuric acid hydrogen peroxide mixture. Therefore, by using the intermediate layer 12 containing a copper-zirconium alloy, there is also an advantage that short-circuit failure caused by a wiring circuit that is left undissolved during etching is not easily generated. This advantage can also be said when using the copper-zirconium-silicon alloy described below as the intermediate layer 12.

From the viewpoint of making the improvement in the adhesion between the wiring layer 13 and the glass substrate 11 described above obvious, the glass substrate 11 is preferably a glass substrate containing SiO _2. Examples include alkali-free glass and soda lime glass. , Borosilicate glass, aluminosilicate glass, etc., it is particularly preferred to use an alkali-free glass substrate for liquid crystal displays.

Similarly, from the viewpoint of improving the adhesion between the intermediate layer 12 and the glass substrate 11, the copper-zirconium alloy constituting the intermediate layer 12 preferably has a molar number of zirconium relative to that of copper and zirconium. The ratio of the total number of ears is 5 mol% or more and 33 mol% or less, more preferably 10 mol% or more and 25 mol% or less, and still more preferably 12 mol% or more and 20 mol% or less. .

The intermediate layer 12 is preferable from the viewpoint of ensuring the adhesion between the wiring layer 13 and the glass substrate 11 obtained by the zirconium contained in the intermediate layer 12 and facilitating the etching properties during the manufacture of the wiring structure 10. To further contain silicon. That is, the intermediate layer 12 preferably contains a material containing zirconium and silicon, and the remaining portion contains copper and unavoidable impurities, in other words, a copper-zirconium-silicon (Cu-Zr-Si) alloy (hereinafter, " The "alloy containing copper and unavoidable impurities" is called "copper-zirconium-silicon alloy").

When the intermediate layer 12 contains a copper-zirconium-silicon alloy, the copper-zirconium-silicon alloy preferably has a molar ratio of zirconium to a total molar number of copper, zirconium, and silicon of 5 mole% or more. And less than 33 mol%. From the viewpoint of further improving the adhesion between the wiring layer 13 and the glass substrate 11, it is preferably 5 mol% or more. Moreover, from the viewpoint of improving the etchability in the formation step of the wiring structure and ensuring the ease of film formation in the manufacturing process at the time of forming the intermediate layer, it is preferably 33 mol% or less. From this viewpoint, the ratio of the molar number of zirconium to the total molar number of copper, zirconium, and silicon is further preferably 6 mol% or more and 25 mol% or less, and still more preferably 7 mol%. Above 20 mol%. Regarding silicon, also from the same viewpoint, the ratio of the molar number of silicon to the total molar number of copper, zirconium, and silicon is preferably 5 mol% or more and 33 mols. % Or less, more preferably 6 mol% or more and 25 mol% or less, and still more preferably 7 mol% or more and 20 mol% or less.

The copper-zirconium-silicon alloy constituting the intermediate layer 12 of the wiring layer 13 and the glass substrate 11 is preferably a ratio of the sum of the moles of zirconium and silicon to the sum of the moles of copper, zirconium, and silicon is 10 moles % Or more and 40 mol% or less. From the viewpoint of further improving the adhesion, it is preferably 10 mol% or more. From the viewpoint of suppressing the zirconium concentration to be low and ensuring the ease of etching in the formation step of the wiring structure, it is preferably 40 mol% or less. From this point of view, the ratio of the total number of moles of zirconium and silicon to the total number of moles of copper, zirconium, and silicon is preferably 11 mol% or more and 33 mol% or less, and more preferably 12 More than Molar% and less than 25 Molar%.

When the intermediate layer 12 contains a copper-zirconium alloy, as described above, the copper-zirconium alloy is preferably an alloy containing zirconium and the remainder containing copper and unavoidable impurities. When the intermediate layer 12 contains a copper-zirconium-silicon alloy, as described above, the copper-zirconium-silicon alloy is preferably an alloy containing zirconium and silicon and the remainder containing copper and unavoidable impurities. When the intermediate layer contains any alloy, these alloys are allowed to contain trace elements other than copper, zirconium, and silicon to the extent that the effects of the present invention are exerted.

Regardless of whether the copper-zirconium alloy and the copper-zirconium-silicon alloy contain other elements, the ratio of unavoidable impurities is preferably relative to the total number of moles of copper and zirconium or the total number of moles of copper, zirconium, and silicon 2 mol% or less, more preferably 1 mol% or less. The smaller the ratio of inevitable impurities, the better.

The intermediate layer 12 can be formed by various thin film forming methods, for example. As a method for forming a thin film, a conventionally known method such as sputtering or vacuum deposition can be used. For example, when sputtering is performed as a method for forming a thin film, it is preferable to use a target material containing zirconium and the remaining portion containing copper and unavoidable impurities, or containing zirconium and silicon and the remaining portion containing copper and unavoidable impurities as the copper-zirconium alloy source. Or copper-zirconium-silicon alloy source. The alloy composition in the target is the same as that of the alloy constituting the intermediate layer 12, and may also be the same composition. That is, the target is a copper-zirconium alloy or a copper-zirconium-silicon alloy, and in the wiring structure 10, it is used to form an intermediate layer 12 for improving the adhesion between the glass substrate 11 and the wiring layer 13. . In addition, for this target, for the same reason as the intermediate layer 12, a trace amount of elements other than copper, zirconium, and silicon, such as oxygen, is allowed, but the smaller the content of the element, the better.

In the case where the target is a sputtering target containing a copper-zirconium-silicon alloy, the copper-zirconium in the target is more obvious from the viewpoint of improving the adhesion between the intermediate layer 12 and the glass substrate 11 more clearly. -The ratio of the silicon alloy is preferably 6% or more and 40% or less, further preferably 9% or more and 40% or less, and most preferably 15% or more and 35% or less. The above ratio is calculated by the method described in [the ratio of copper-zirconium-silicon alloy in the sputtering target] in the following examples.

In addition, the above-mentioned target is naturally used for sputtering, and can also be favorably used as a target for various physical vapor deposition (PVD) methods such as vacuum evaporation such as arc ion plating.

The target material can be produced by various methods known in the technical field. For example, copper and zirconium, which have been melted in a vacuum, and silicon, if necessary, are used as raw materials for casting and alloying. Next, a target is manufactured using the obtained ingot. The processing method of processing into the target is not particularly limited. For example, it can be hot forging, cold forging, or hot rolling. Moreover, it can also be cut out by a wire saw and formed into a plate material. In the case where the above target is used as a sputtering target, it is sufficient to use a bonding material such as indium to attach the obtained plate to a backing plate as a sputtering fixture. Furthermore, in the present invention, the so-called target material also includes a state before the final processing step of the target material such as plane grinding or bonding. The shape of the target is not limited to a flat plate, and includes a cylindrical shape. In the present invention, the sputtering target refers to a person who sputters such an singular or plural target material by bonding it to a backing plate or the like.

The thickness of the intermediate layer 12 formed by the above method is preferably 10 nm or more and 100 nm or less. By setting the thickness of the intermediate layer 12 to 10 nm or more, the intermediate layer 12 can be formed on the glass substrate 11 without leaving a dead angle, and the adhesion between the glass substrate 11 and the wiring layer 13 can be reliably improved. In addition, by setting the thickness of the intermediate layer 12 to 100 nm or less, the volume resistivity of the wiring structure is not unnecessarily increased, and productivity at the time of manufacturing is not impaired. The thickness of the intermediate layer 12 can be arbitrarily set within the above range within the range of improving the adhesion between the glass substrate 11 and the wiring layer 13, and is more preferably 15 nm or more and 80 nm or less, and further preferably 20 nm. Above and below 50 nm.

The wiring layer 13 has a first surface 13 a which is a surface facing the glass substrate 11. In addition, the wiring layer 13 has a second surface 13b that is a surface located on the side opposite to the first surface 13a. The first surface 13a is in contact with the intermediate layer 12. A metal layer 14 is provided on the second surface 13b. The wiring layer 13 is directly connected to the metal layer 14, and no other layer is interposed between the two layers 13 and 14. The metal layer 14 is formed so as to cover the entire area of the second surface 13 b of the wiring layer 13. Therefore, there is no exposed area on the second surface 13b of the wiring layer 13.

In the present invention, the adhesion between the substrate 11 and the intermediate layer 12 is important, and the adhesion between the intermediate layer 12 and the wiring layer 13 via the first surface 13 a is further important. In order to improve the adhesiveness, it is preferable to perform an annealing treatment (heat treatment). The temperature of the annealing treatment is generally 100 ° C or higher, more preferably 300 ° C or higher, and even more preferably 500 ° C or higher. The annealing time is generally 15 minutes or more and 120 minutes or less. If the annealing process is performed after the wiring layer 13 is formed, the annealing process may be performed after the metal layer 14 or the insulating layer 15 described below is formed or the resist is patterned. Moreover, you may perform simultaneously with a film-forming process in the range which satisfy | fills the said annealing conditions.

As shown in FIG. 1, an insulating layer 15 is provided on the wiring layer 13. The insulating layer 15 is additionally provided in order to prevent oxidation of the wiring layer 13 and to prevent a short circuit due to a foreign substance or the like. For this purpose, the insulating layer 15 contains a material having high oxidation resistance. Examples of materials having high oxidation resistance include nitrides, carbides, and oxides. Among these materials, the insulating layer 15 is preferably made of a material containing a non-oxide in terms of exhibiting oxidation resistance. Examples of the non-oxide include nitrides and carbides. In terms of the ability to maximize the oxidation resistance, nitrides are particularly preferably used. As the nitride, for example, a metal or semi-metal nitride is favorably used. Examples thereof include silicon nitride, which is a material that can be formed in a reducing atmosphere to suppress oxidation of the wiring layer 13. As the oxide, in terms of the stability of the thin film transistor, an oxide containing silicon such as SiO ₂ and an oxide containing rare earths such as Y ₂ O ₃ are preferred.

From the viewpoint of maximizing the oxidation resistance, the insulating layer 15 is provided so as to cover the entirety including the side surfaces of the wiring layer 13 and the intermediate layer 12. Instead, an insulating layer may be provided only in the entire area on the second surface 13b side of the wiring layer 13.

FIG. 2 shows another embodiment of the present invention. Furthermore, regarding aspects not specifically described in this embodiment in FIG. 2, descriptions related to the embodiment shown in FIG. 1 described above are appropriately applied. In FIG. 2, the same components as those in FIG. 1 are denoted by the same reference numerals. The wiring structure 10 according to this embodiment is provided with an insulating layer 15 on the wiring layer 13. A metal layer 14 is disposed between the wiring layer 13 and the insulating layer 15. The metal layer 14 is directly connected to the wiring layer 13 and is also directly connected to the insulating layer 15 at the beginning of the film formation step.

Like the insulating layer 15, the metal layer 14 is a layer used additionally. By providing the metal layer 14 on the wiring layer 13 and under the insulating layer 15 as shown in FIG. 2, the oxidation of the wiring layer 13 is further effectively prevented. The metal layer 14 and the insulating layer 15 may be used in order to prevent oxidation of the wiring layer 13. That is, only the metal layer 14 may be provided on the wiring layer 13, or only the insulating layer 15 may be provided on the wiring layer 13. In addition, as in this embodiment, a metal layer 14 and an insulating layer 15 may be sequentially disposed on the wiring layer 13. Filming of the insulating layer 15 is generally performed under a state where the substrate temperature is increased. Since the thermal load caused by increasing the substrate temperature may cause the conductivity of the wiring layer 13 to decrease, it is preferable to provide the metal layer 14 in this respect. In any aspect, the thickness of the insulating layer 15 is only required to prevent the oxidation of the wiring layer 13, and is preferably set to 50 nm or more and 500 nm or less, and more preferably 80 nm. Above and below 300 nm.

In the wiring structure 10, as the metal layer 14 described above, an alloy containing zirconium and the remainder containing copper and unavoidable impurities, that is, a copper-zirconium alloy is used. It is preferable to use an alloy containing zirconium and silicon and the remainder containing copper and unavoidable impurities, that is, a copper-zirconium-silicon alloy. By providing the metal layer 14 having the alloy composition on the wiring layer 13, it is easy to remove the intermediate layer 12 and the wiring layer 13 together into an arbitrary wiring pattern in the etching step when the wiring structure 10 is formed. Furthermore, as a result of studies conducted by the present inventors, it was found that by using such a layer structure, the oxidation of copper contained in the wiring layer 13 is effectively suppressed. Therefore, the wiring structure 10 becomes a person that is not easily affected by the oxidation due to the annealing even after the annealing is performed in an oxidizing atmosphere.

From the viewpoint of making the above-mentioned effect of suppressing oxidation more apparent, the copper-zirconium alloy constituting the metal layer 14 is preferably a molar number of zirconium to a total of the copper and zirconium molar numbers The ratio is 5 mol% or more and 33 mol% or less, more preferably 5 mol% or more and 25 mol% or less, and still more preferably 10 mol% or more and 20 mol% or less. .

When the metal layer 14 contains a copper-zirconium-silicon alloy, the copper-zirconium-silicon alloy has a molar number of zirconium relative to a total of the molar numbers of copper, zirconium, and silicon in terms of imparting heat resistance The ratio is preferably 1 mol% or more. On the other hand, from the viewpoint of making the metal layer 14 easier to etch and ensuring the ease of film formation in the manufacturing process, it is preferably 33 mol% or less, and more preferably 1 mol%. It is more than 25 mol%, and more preferably 2 mol% or more and 20 mol% or less, still more preferably, it is 4 mol% or more and 10 mol% or less. From the same viewpoint, the copper-zirconium-silicon alloy constituting the metal layer 14 preferably has a ratio of the mole number of silicon to the total mole number of copper, zirconium, and silicon to 1 mole%. It is more than 33 mol%, and more preferably 1 mol% or more and 25 mol% or less, more preferably 2 mol% or more and 20 mol% or less, and still more preferably It is 4 mol% or more and 10 mol% or less.

Furthermore, from the viewpoint of making the effect of suppressing oxidation more apparent, when the metal layer 14 contains a copper-zirconium-silicon alloy, the copper-zirconium-silicon alloy is preferably a molar number of zirconium and silicon. The ratio of the total to the total number of moles of copper, zirconium, and silicon is 2 mol% or more and 40 mol% or less, more preferably 2 mol% or more and 25 mol% or less, further preferably 4 Molar% or more and 20 Molar% or less, more preferably 8 Molar% or more and 16 Molar% or less.

The copper-zirconium alloy or copper-zirconium-silicon alloy constituting the metal layer 14 is preferably an alloy containing zirconium and the remainder containing copper and unavoidable impurities, or an alloy containing zirconium and silicon and the remainder containing copper and unavoidable impurities as described above. Of alloy. However, when the alloy has any composition, the alloy is allowed to contain trace elements other than copper, zirconium, and silicon to the extent that the effects of the present invention are exhibited.

Regardless of whether the copper-zirconium alloy and the copper-zirconium-silicon alloy contain other elements, the ratio of unavoidable impurities is preferably relative to the total number of moles of copper and zirconium, or the total number of moles of copper, zirconium, and silicon. 2 mol% or less, more preferably 1 mol% or less. The smaller the ratio of inevitable impurities, the better. The metal layer 14 can be formed by various thin film forming methods, for example. As a method for forming a thin film, a conventionally known method such as sputtering or vacuum deposition can be used.

The thickness of the metal layer 14 can be arbitrarily set according to the specific application of the wiring structure 10, and can be, for example, 10 nm or more and 100 nm or less. By setting the thickness of the metal layer 14 to 10 nm or more, the oxidation of copper contained in the wiring layer 13 which is an object to be protected can be effectively prevented. In addition, by setting the thickness of the metal layer 14 to 100 nm or less, the productivity of the metal layer 14 can be prevented.

In addition, the metal layer 14 only needs to cover a part necessary for the purpose of achieving oxidation resistance of the wiring layer 13. In this embodiment, only the entire area on the second surface 13b side of the wiring layer 13 is provided. However, if necessary, the entire area including the side surfaces of the wiring layer 13 and the intermediate layer 12 may be covered.

The wiring structure 10 is well manufactured by a method having the following steps: providing an intermediate layer 12 on the glass substrate 11; providing a wiring layer 13 containing copper on the intermediate layer 12; providing a metal layer 14 on the wiring layer 13; The laminated structure having these layers 12, 13, 14 is heat-treated. In addition, with this manufacturing method, during the manufacturing process of the wiring structure 10, the oxidation of the wiring layer 13 can be prevented even when heat treatment is performed in an oxidizing atmosphere such as the atmosphere.

The wiring structure 10 according to this embodiment has the advantages of the wiring structure of the embodiment shown in FIG. 1 described above, that is, all of (i) the adhesion between the glass substrate 11 and the wiring layer 13 and ( ii) suppression of an increase in resistance of the wiring layer 13 at a high temperature due to diffusion of the elements, and (iii) ease of etching, and (iv) suppression of oxidation of the wiring layer 13, these opposite characteristics.

The wiring structure 10 in each of the above embodiments can be used directly or used as various electronic devices after subsequent processing. Examples of the electronic device include various semiconductor devices such as a thin film transistor.

As mentioned above, although this invention was demonstrated based on the preferable embodiment, this invention is not limited to the said embodiment. For example, in the embodiment shown in FIG. 1, the insulating layer 15 is provided on the wiring layer 13, but the insulating layer 15 may not be provided. In the embodiment shown in FIG. 2, the metal layer 14 and the insulating layer 15 are provided on the wiring layer 13, but the insulating layer 15 may not be provided. It is not necessary to provide both the metal layer 14 and the insulating layer 15. Examples

Hereinafter, the present invention will be described in more detail through examples. However, the scope of the present invention is not limited to this embodiment.

[Example 1] Ingots of various starting materials were accurately weighed so as to have the composition shown in Table 1 below, and these ingots were put into a crucible made of carbon. The ingots were vacuum-heated in a high-frequency induction vacuum melting furnace to melt them. The molten metal thus obtained was cast using a carbon mold to obtain an ingot. The obtained ingot was cut out with a wire saw, and then processed to a thickness of 5 mm by lathe processing. One side of the target material thus obtained was welded to a backing plate with indium to produce a copper-zirconium-silicon alloy sputtering target for an intermediate layer.

A copper-zirconium-silicon alloy sputtering target for the intermediate layer obtained above and a sputtering target of pure copper with a purity of 6 N were used to produce a wiring structure. First, a copper-zirconium-silicon alloy sputtering target for an intermediate layer was used to perform sputtering under the following conditions to form an intermediate layer with a thickness of 25 nm on a glass substrate. Next, a sputtering target of pure copper was used to perform sputtering under the same conditions, and a wiring layer having a thickness of 400 nm was formed on the intermediate layer.

"Sputtering conditions" • Sputtering method: DC (direct current) magnetron sputtering • Exhaust device: rotary pump + cryopump • Ultimate vacuum: 1 × 10 ^-4 Pa or less • Argon (Ar) pressure: 0.4 Pa ・ Substrate temperature: 100 ° C ・ Sputtering power: 1000 W (power density 3.1 W / cm ² ) ・ Used substrate: EAGLE XG (Corning Co., Ltd./alkali-free glass for liquid crystal display, registered trademark), 50 mm (vertical) × 50 mm (horizontal) × 0.7 mm (thick)

The obtained laminated structure was used as a target, and the resist was patterned by a photolithography method so as to have a pattern of a specific shape shown in FIG. 3, and then a sulfuric acid hydrogen peroxide mixture (H ₂ SO ₄ : 0.5 wt. %, H ₂ O ₂ : 0.35 wt% aqueous solution). A PE-CVD device (PD-2202L) manufactured by SUMCO was used to perform CVD (chemical vapor deposition) under the following conditions, and a 200 nm-thick SiN insulating layer was formed on the wiring layer to obtain a wiring structure. . Further, annealing treatment (heat treatment) is performed in the atmosphere. The temperature of the annealing treatment was set to 500 ° C, and the annealing treatment time was set to 30 minutes.

"CVD Conditions" ・ Film-forming gas: SiH ₄ : 10 cm ³ / min, H ₂ : 90 cm ³ / min, NH ₃ : 10 cm ³ / min, N ₂ : 210 cm ³ / min ・ Film forming temperature: 350 ℃ ・ Film forming force: 80 Pa ・ Power: 250 W

[Examples 2 to 4] A copper-zirconium-silicon alloy sputtering target was produced by changing the amount of addition such that the ratio of copper, zirconium, and silicon became the values shown in Table 1. Using the obtained sputtering target, an intermediate layer was obtained in the same manner as in Example 1. Furthermore, in each example, a copper-zirconium-silicon alloy sputtering target for a metal layer having the same composition as the intermediate layer was used, sputtering was performed under the same conditions as the intermediate layer, and a thickness of 50 nm was formed on the wiring layer. Of the metal layer. Except for this, the wiring structure shown in FIG. 2 was obtained in the same manner as in Example 1.

[Examples 5 and 6] The copper-zirconium alloy sputtering target having the composition shown in Table 1 was used in place of the copper-zirconium-silicon alloy sputtering target used in Example 1, except that it was the same as in Example 1. Way to get the middle layer. Further, an insulating layer was formed on the intermediate layer by the same method as in Example 1 to obtain the wiring structure shown in FIG. 1.

[Comparative Example 1] In Example 1, an intermediate layer containing a copper-zirconium-silicon alloy was not formed. Except for this, a wiring structure was obtained in the same manner as in Example 1.

[Comparative Examples 2 and 3] Instead of using a copper-zirconium-silicon alloy sputtering target, a titanium sputtering target (Comparative Example 2) and a molybdenum sputtering target (Comparative Example 3) were used to form the intermediate layer. Except for this, a wiring structure was obtained in the same manner as in Example 1.

[Comparative Example 4] Instead of using a copper-zirconium-silicon alloy sputtering target, a copper-zirconium alloy sputtering target having a composition shown in Table 1 was used to form the intermediate layer. Except these, a wiring structure was obtained in the same manner as in Example 1.

[Comparative Example 5] Instead of using a copper-zirconium-silicon alloy sputtering target, a copper-zirconium alloy sputtering target having a composition shown in Table 1 was used to form the intermediate layer. Further, no copper-containing wiring layer was formed on the intermediate layer. Except these, a wiring structure was obtained in the same manner as in Example 1.

[Comparative Example 6] Instead of using a copper-zirconium-silicon alloy sputtering target, a copper-zirconium-silicon alloy sputtering target having a composition shown in Table 1 was used to form the intermediate layer. Except for this, a wiring structure was obtained in the same manner as in Example 1.

[Evaluation] With respect to the wiring structures obtained in the examples and comparative examples, the peel test was performed by the following method, and the oxidation resistance and the ease of etching were evaluated by the following method. Furthermore, the ratio of the copper-zirconium-silicon alloy in the sputtering target used by the Example and the comparative example was evaluated by the following method. The results are shown in Table 1.

[Peel test] A peel test was performed in accordance with JIS K5600-5-6. NT Cutter eL-500 was used to form a 25-grid 1 mm × 1 mm grid pattern on the laminated structure. Apply the tape 8705B made by TQC company to the cut part of the grid, and rub the tape with your fingers in a transparent and visible way to build up the laminated structure. Peel off the tape within 5 minutes after the tape is attached. The number of stripped areas in the grid was counted as the number of stripped ones.

[Evaluation of oxidation resistance] The volume resistivity of the obtained wiring structure was measured before and after the annealing treatment, respectively. The measurement system used a four-terminal resistance measurement device (B-1500A: manufactured by Agilent Technology). The measurement procedure is shown below. First, at the time of manufacturing the wiring structure, the wiring resistance including the metal layer and the conductive portion of the wiring layer is measured in advance in the state of the laminated structure before the annealing treatment. Specifically, by scanning the current value between the current application pads Pi and Pi shown in FIG. 3 and measuring the voltage value between the voltage measurement pads Pv and Pv, the wiring resistance value is obtained. The volume resistivity of the conductive portion is calculated based on the obtained wiring resistance value, the line width, length, and film thickness of the conductive portion. This value was set as the volume resistivity (Ω · cm) before the annealing treatment. Next, in the wiring structure after the annealing treatment, the volume resistivity is calculated by the same method as the measurement of the volume resistivity before the annealing treatment. This value was set as the volume resistivity (Ω · cm) after the annealing treatment. Then, the change rate of the volume resistivity before and after the annealing treatment was calculated. The change rate (%) of the volume resistivity is calculated based on {(volume resistivity after annealing treatment-volume resistivity before annealing treatment) / volume resistivity before annealing treatment} × 100.

[Ease of Etching] The wiring structures obtained in the examples and comparative examples were etched using a sulfuric acid and hydrogen peroxide mixture. The wiring structure after the etching was observed with a scanning electron microscope (SEM), and the pass or fail of the formation of the wiring pattern was evaluated based on the following criteria. E: The wiring pattern is extremely clear. G: The wiring pattern is clear. P: A large portion of the intermediate layer remaining on the substrate was observed.

[Ratio of copper-zirconium-silicon alloy in sputtering target] The ratio of copper-zirconium-silicon alloy in sputtering target is sputtering used for manufacturing the wiring structure of Examples 1 to 4 and Comparative Example 6. The surface of the target is an object and is calculated by an energy dispersive X-ray (EDX) analysis. Specifically, elemental analysis was performed using an energy dispersive X-ray analyzer (manufactured by Japan Electronics Co., Ltd., Dry SD100GV). The analysis results were phase-separated using multivariate image analysis software (manufactured by Thermo Fisher Scientific, NSS4) to calculate the ratio (%) of the area of the copper-zirconium-silicon alloy to the area of the entire image.

[Confirmation of the origin of the adhesion between the intermediate layer and the glass substrate] In order to investigate the origin of the adhesion between the intermediate layer and the glass substrate, the wiring structures of Examples 2, 4 and 5 were performed using an nitric acid + hydrogen peroxide-based etchant. After the etching, the surface of the glass substrate was measured by XPS (X-ray photoelectron spectroscope) (manufactured by ULVAC-PHI, Versa Prove III) under the following conditions.

"Measurement conditions" ・ Output: 50 W ・ X-ray diameter: 200 μmf ・ Pass Energy: 26 eV ・ Energy step: 0.1 eV ・ Take-off Angle: 45 ° ・Static neutralization: use low-speed ion gun and electron gun

The obtained peaks were analyzed by using analysis software (manufactured by ULVAC-PHI, Multipack 9.0), and the binding energy of Zr3d electrons was determined. In Example 5, a peak was found at a portion corresponding to the oxide of Zr. In Examples 2 and 4, a peak was confirmed on the higher energy side than in Example 5. From the above results, it can be seen that the adhesion of Zr added to Cu to the surface of the glass substrate in the form of an oxide is ensured. In addition, it was found that by adding Zr and Si together to Cu, the adhesion force was further increased.

[Table 1]

It is clear from the results shown in Table 1 that in each of the examples, the substrate and the copper wiring have high adhesion, and the increase in the volume resistivity of the copper wiring is suppressed. In contrast, in Comparative Example 1, it was found that the adhesion was low because the intermediate layer was not formed, and the volume resistivity of the copper wiring significantly increased. In Comparative Examples 2 and 3, although the adhesion between the substrate and the copper wiring was high, the wiring resistance increased, and it was estimated that the material of the intermediate layer diffused into the copper wiring. As for Comparative Examples 4 to 6, it was found that the adhesion was low. From Comparative Example 5, it can be seen that if the Zr concentration in Cu is increased to 5%, the volume resistivity increases sharply, and if it is only an alloy layer of Cu-Zr having such a composition, the conductivity is poor. Furthermore, it can be seen that the wiring structures of Examples 1 to 4 can form the wiring pattern by etching extremely well. [Industrial availability]

According to the present invention, in a wiring structure provided with a copper-containing wiring layer, it is possible to improve the adhesion between the wiring layer and the substrate without impairing the conductivity of the wiring layer.

10‧‧‧Wiring Structure

11‧‧‧ glass substrate

12‧‧‧ middle layer

13‧‧‧Wiring layer

13a‧‧‧Part 1

13b‧‧‧Part 2

14‧‧‧ metal layer

15‧‧‧ Insulation

Pi‧‧‧ Current Application Pad

Pv‧‧‧Voltage measurement pad

FIG. 1 is a schematic view showing a cross section along a thickness direction, which is an embodiment of a wiring structure of the present invention. FIG. 2 is a schematic view showing a cross section along a thickness direction of another embodiment of the wiring structure of the present invention. FIG. 3 is a schematic diagram of the upper surface of a pattern formed by a TEG (Test Element Group) for wiring resistance measurement.

Claims (10)

A wiring structure comprising a glass substrate, an intermediate layer provided on the glass substrate, and a wiring layer provided on the intermediate layer, wherein the wiring layer contains copper, the intermediate layer contains zirconium, and the remaining portion contains copper and non-conductive Impurities are avoided, and the ratio of the molar number of zirconium contained in the intermediate layer to the total molar number of copper and zirconium is 5 mol% or more and 33 mol% or less. The wiring structure according to claim 1, wherein the intermediate layer further contains silicon. For example, the wiring structure of claim 2, wherein the ratio of the molar number of zirconium to the total of the molar numbers of copper, zirconium, and silicon contained in the intermediate layer is 5 mol% or more and 33 mol% or less The molar ratio of silicon is 5 mol% to 33 mol%. The wiring structure according to claim 1 includes an insulating layer on the wiring layer. The wiring structure according to claim 4, wherein the insulating layer contains a nitride. The wiring structure according to claim 5, wherein the nitride includes silicon nitride. As in the wiring structure of claim 4, a metal layer is provided between the wiring layer and the insulating layer, and the metal layer contains zirconium and the remainder contains copper and unavoidable impurities. The wiring structure according to claim 7, wherein the metal layer further contains silicon. A target material used for manufacturing a wiring structure as claimed in claim 1, the target material containing zirconium and the remainder containing copper and unavoidable impurities. A target is used for manufacturing a wiring structure as claimed in claim 3, the target contains zirconium and silicon and the remaining portion contains copper and unavoidable impurities.