TW201924212A - Power amplifier circuit - Google Patents

Abstract

A power amplifier circuit includes a first transistor that amplifies a first signal and outputs a second signal, a second transistor that amplifies a signal corresponding to the second signal and outputs a third signal, a third transistor that supplies a first bias current or voltage to a base of the first transistor, and a fourth transistor that supplies a second bias current or voltage to a base of the second transistor. A ratio of an emitter area of the third transistor to an emitter area of the first transistor is larger than a ratio of an emitter area of the fourth transistor to an emitter area of the second transistor.

Description

 Power amplifier circuit  

The present invention relates to a power amplifying circuit.

In a mobile communication device such as a mobile phone, a power amplifying circuit is used to amplify the power of a radio frequency (RF: Radio-Frequency) signal transmitted to a base station. In the power amplifying circuit, a bias circuit for supplying a bias current to a transistor for power amplification is used. For example, Patent Document 1 discloses a power amplifying circuit using a bias circuit including an emitter follower. In the bias circuit, a bias current is output from the emitter of the transistor for supplying a bias current to the base of the transistor for amplification.

[Previous Technical Literature]

[Patent Literature]

[Patent Document 1] JP-A-2016-213557

In the bias circuit including the emitter follower as described above, the amount of current of the bias current is affected by the RF signal. Specifically, when the level of the RF signal is increased, a negative current (current from the base of the amplifying transistor to the emitter side of the transistor for supplying the bias current) is generated in the bias current. At this time, the negative current is cut off due to the rectifying property of the PN junction between the base and the emitter of the transistor for bias current supply. Thereby, the ratio of the bias current flowing in the positive direction increases, and the average value of the bias current becomes high. Therefore, the gain of the power amplifying circuit rises, and as a result, linear degradation of the gain in the power amplifying circuit is caused.

In order to cope with this problem, in the configuration disclosed in Patent Document 1, a current path through which a negative current passes is provided between the base and the emitter of the transistor for supplying a bias current, thereby the negative portion of the bias current. Will not be closed. As a result, even if the level of the RF signal is large, the increase in the average value of the bias current is suppressed.

However, since the capacitor is used as a path through which a negative current passes in the above configuration, the path has a frequency characteristic. Therefore, for example, when the frequency band of the RF signal is spread over a wide range as seen in the multi-band technology, there is a problem that the characteristics fluctuate with frequency.

The present invention has been made in view of such circumstances, and an object thereof is to provide a power amplifying circuit capable of suppressing linear degradation of gain in a wide frequency band.

In order to achieve such an object, a power amplifier circuit according to an aspect of the present invention includes: a first transistor that amplifies a first signal and outputs a second signal; and a second transistor that amplifies a signal corresponding to the second signal and outputs a second 3 signal; the third transistor supplies a first bias current or voltage to the base of the first transistor; and the fourth transistor supplies a second bias current or voltage to the base of the second transistor, third The ratio of the emitter area of the transistor to the emitter area of the first transistor is larger than the ratio of the emitter area of the fourth transistor to the emitter area of the second transistor.

According to the present invention, it is possible to provide a power amplifying circuit capable of suppressing linear degradation of gain in a wide frequency band.

100‧‧‧Power amplifier circuit

110, 111‧ ‧ amplifier

120, 121‧‧‧ bias circuit

Q1~Q8‧‧‧O crystal

R1~R4‧‧‧resistive components

C1~C4‧‧‧ capacitor

10‧‧‧Semiconductor substrate

20‧‧‧base layer

30a, 30b‧‧ ‧ the emitter layer

40a, 40b‧‧‧ collector layer

FIG. 1 is a view showing a configuration example of a power amplifier circuit according to an embodiment of the present invention.

FIG. 2 is a plan view showing a structure of one unit constituting the transistor Q1.

3 is a graph showing an example of a simulation result of the voltage Vbb in the power amplifier circuit according to the embodiment of the present invention.

4 is a graph showing an example of a simulation result of the gain of the previous stage in the power amplifier circuit according to the embodiment of the present invention.

FIG. 5 is a graph showing an example of a simulation result of ACLR characteristics in the power amplifier circuit of the comparative example of the present invention.

FIG. 6 is a graph showing an example of a simulation result of ACLR characteristics in the power amplifier circuit according to the embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, the same reference numerals are given to the same elements, and overlapping description will be omitted.

FIG. 1 is a view showing a configuration example of a power amplifier circuit according to an embodiment of the present invention. The power amplifier circuit 100 shown in FIG. 1 is mounted, for example, on a mobile communication device such as a mobile phone, and is used to amplify the power of a radio frequency (RF: Radio-Frequency) signal transmitted to the base station. The power amplifier circuit 100 is, for example, 2G (2nd generation mobile communication system), 3G (3rd generation mobile communication system), 4G (4th generation mobile communication system), 5G (5th generation mobile communication system), LTE (Long Term) Evolution: Long-term evolution) - FDD (Frequency Division Duplex), LTE-TDD (Time Division Duplex), LTE-Advanced, LTE-Advanced Pro, etc. . Further, the power amplifier circuit 100 amplifies the power of signals of a plurality of different frequency bands, for example. The frequency of the RF signal is, for example, several hundred MHz to several tens of GHz. Further, the communication specifications and frequencies of the signals amplified by the power amplifying circuit 100 are not limited thereto.

The power amplifier circuit 100 includes, for example, amplifiers 110 and 111 and bias circuits 120 and 121.

The amplifiers 110, 111 constitute a two-stage amplifier. The amplifier 110 of the preceding stage (drive section) amplifies the RF signal RF1 (first signal) and outputs an RF signal RF2 (second signal). The amplifier 111 of the subsequent stage (power section) further amplifies the RF signal RF2 and outputs an RF signal RF3 (third signal). In addition, the number of segments of the amplifier is not limited to two segments, and may be three or more segments.

Bias circuits 120, 121 provide bias currents or voltages to amplifiers 110, 111, respectively. Specifically, the bias circuit 120 (first bias circuit) supplies the bias current Ibias1 (first bias current) to the amplifier 110 of the previous stage. Further, the bias circuit 121 (second bias circuit) supplies the bias current Ibias2 (second bias current) to the amplifier 111 of the subsequent stage. The gain of the amplifiers 110, 111 is controlled by the amount of current of the bias currents Ibias1, Ibias2.

Further, although not shown, the power amplifier circuit 100 may include a matching circuit for matching the impedance between the circuits in the front stage and the rear stage of each of the amplifiers 110 and 111.

Next, a specific configuration example of the amplifiers 110 and 111 and the bias circuits 120 and 121 will be described.

The amplifier 110 of the previous stage includes, for example, a transistor Q1, a capacitor C1, and a resistance element R1. Similarly, the amplifier 111 in the subsequent stage includes, for example, a transistor Q2, a capacitor C2, and a resistance element R2.

The transistor Q1 (first transistor) and the transistor Q2 (second transistor) are, for example, bipolar transistors such as a Heterojunction Bipolar Transistor (HBT). The base of the transistor Q1 is supplied with an RF signal RF1 and a bias current Ibias1, the collector is supplied with a power supply voltage, and the emitter is grounded. Thereby, the transistor Q1 amplifies the RF signal RF1 and outputs the RF signal RF2 from the collector. The base of transistor Q2 is supplied with an RF signal RF2 and a bias current Ibias2, the collector is supplied with a supply voltage, and the emitter is grounded. Thereby, the transistor Q2 further amplifies the RF signal RF2, and outputs the RF signal RF3 from the collector.

Further, although the illustration is omitted, the power supply voltage may be supplied to the collectors of the transistors Q1, Q2 via the choke inductor.

The capacitors C1 and C2 are coupling capacitors that cut off the DC component included in the input RF signal and pass the AC component.

The resistance elements R1, R2 are connected between the bias circuits 120, 121 and the bases of the transistors Q1, Q2, respectively. By supplying the bias currents Ibias1, Ibias2 via the resistance elements R1, R2, the increase in the bias currents Ibias1, Ibias2 due to the temperature rise of the transistors Q1, Q2 is suppressed.

FIG. 2 is a plan view showing a structure of one unit constituting the transistor Q1. Further, the transistor Q2 can include the same unit as the unit shown in the figure.

As shown in the figure, one unit includes a base layer 20 formed on the main surface in a plan view of the main surface of the semiconductor substrate 10, and two emitter layers 30a and 30b formed on both outer sides of the base layer 20, respectively. And collector layers 40a and 40b formed on both outer sides of the two emitter layers 30a and 30b. Thereby, a unit transistor is formed. In addition, the term "unit transistor" means a structure including at least a base layer, a collector layer, and an emitter layer, and a minimum unit functioning as a transistor.

Further, although not shown in FIG. 2, elements corresponding to the capacitor C1 and the resistance element R1 may be integrally formed in each unit in addition to the unit transistor described above. In FIG. 1, each element included in each of the amplifiers 110 and 111 is illustrated by one circuit mark. However, the amplifiers 110 and 111 in the present embodiment each include a plurality of units. Further, between the plurality of cells, the collectors of the respective unit transistors, the emitters, and the bases are electrically connected to each other. Thereby, a plurality of units are connected in parallel, and the whole is operated as an amplifier. Although the number of units constituting the amplifier is not particularly limited, in the power amplifying circuit 100, since the power amplification circuit 100 has a larger amplification level than the power of the previous stage, the number of units in the subsequent stage (for example, 20) is larger than the number of units in the previous stage (for example, four). many.

Hereinafter, in each unit, the total area of the emitter layers in the plan view of the main surface of the semiconductor substrate 10 (the total area of the emitter layers 30a and 30b in FIG. 2) is also referred to as "the emitter area of the unit". ". Further, the total of the emitter areas of the plurality of cells constituting the amplifier is also referred to as "the emitter area of the amplifier (or the emitter area of the transistor)". For example, when the amplifier 110 includes four cells, when the area of the emitter layer 30a is set to 1, the emitter area of the amplifier 110 (the transistor Q1) is 1 × 2 × 4 cells = 8. Further, the number of the emitter layers included in one unit is not limited to two, and may be, for example, four. In the case where there are four emitter layers, the four emitter layers and the three base layers may be alternately formed side by side.

Returning to Fig. 1, the bias circuit 120 includes, for example, transistors Q3 to Q5, a resistor element R3, and a capacitor C3.

The transistors Q3 to Q5 are, for example, HBT. The collector of the transistor Q3 is connected to the base (hereinafter also referred to as "diode connection"), and the voltage Vb1 is supplied to the collector via the resistor element R3, and the emitter is connected to the collector of the transistor Q4. The transistor Q4 is connected to the diode, the collector is connected to the emitter of the transistor Q3, and the emitter is grounded. Thereby, a predetermined voltage (for example, about 2.6 V) is generated at the collector of the transistor Q3.

The collector of the transistor Q5 (third transistor) is supplied with the battery voltage Vbatt, the base is connected to the base of the transistor Q3, and the emitter is connected to the base of the transistor Q1 via the resistor element R1. Thereby, the bias current Ibias1 is output from the emitter of the transistor Q5. The transistor Q5, like the above-described transistors Q1 and Q2, includes, for example, a plurality of cells. In Fig. 1, as an example, it is schematically shown that the transistor Q5 includes three units.

A voltage Vb1 is supplied to one end of the resistive element R3, and the other end is connected to the collector of the transistor Q3. Further, instead of the voltage Vb1, the current Ib1 may be supplied from the current source to one end of the resistance element R3.

One end of the capacitor C3 is connected to the collector of the transistor Q3, and the other end is grounded. The capacitor C3 causes the AC component to flow into the ground, thereby suppressing the voltage amplitude of the base of the transistor Q3 due to the detection of the RF signal.

The bias circuit 121 includes, for example, transistors Q6 to Q8, a resistor element R4, and a capacitor C4. Further, since the structures of the transistors Q6, Q7, the resistance element R4, and the capacitor C4 are the same as those of the transistors Q3, Q4, the resistance element R3, and the capacitor C3 in the bias circuit 120, detailed description thereof will be omitted.

The collector of the transistor Q8 (fourth transistor) is supplied with the battery voltage Vbatt, the base is connected to the base of the transistor Q6, and the emitter is connected to the base of the transistor Q2 via the resistor element R2. Thereby, the bias current Ibias2 is output from the emitter of the transistor Q8. Similarly to the above-described transistors Q1 and Q2, the transistor Q8 may include a plurality of cells, for example. In Fig. 1, as an example, it is schematically shown that the transistor Q8 includes one unit.

Further, the bias circuits 120 and 121 can also control the current amounts of the bias currents Ibias1 and Ibias2 by adjusting the voltage values of the voltages Vb1 and Vb2 (or the current values of the currents Ib1 and Ib2).

Next, the previous stage (amplifier 110 and bias circuit 120) is taken as an example, and the suppression of the fluctuation of the current amounts of the bias currents Ibias1 and Ibias2 will be described.

In general, in a bias circuit composed of an emitter follower, the amount of current of the bias current may be affected by the RF signal. Specifically, in order to facilitate the use of the symbol shown in FIG. 1, in the case where the degree of the RF signal RF1 supplied to the base of the transistor Q1 is large, a negative current is generated in the bias current (from the transistor Q1). The base flows to the emitter side of the transistor Q5). Although the negative current flows from the emitter to the base of the transistor Q5, it is turned off due to the rectifying property of the PN connection between the base and the emitter of the transistor Q5. As described above, since the negative portion of the bias current is turned off, the average value of the emitter voltage (voltage Vbb) of the transistor Q5 increases as the degree of the RF signal increases, and the average value of the bias current Ibias1 also rises.

In response to this problem, for example, in the structure disclosed in Patent Document 1, a transistor that supplies a bias current is stacked, and it is desired to make a negative current flowing into the upper stage transistor (corresponding to the transistor Q5 in FIG. 1). A part flows to the transistor of the lower stage. However, in this configuration, the impedance of the collector of the lower stage of the transistor observed from the emitter of the upper stage transistor is very high. Therefore, it is considered that it is difficult for current to flow to the transistor of the lower stage.

Further, in the configuration disclosed in Patent Document 1, by providing a current path through which a negative current flows between the base and the emitter of the upper transistor, the negative portion of the bias current is not turned off. However, in the above configuration, since a capacitor is used as a path through which a negative current passes, the path has a frequency characteristic. Therefore, for example, as seen in the multi-band technique, when the frequency band of the RF signal is spread over a wide range, it is considered that the characteristic fluctuates with frequency.

In this regard, in the power amplifying circuit 100, it is designed such that the ratio of the emitter area of the transistor Q5 to the emitter area of the transistor Q1 of the preceding stage is larger than the emitter area of the transistor Q8 with respect to the transistor Q2 of the subsequent stage. The ratio of the area of the emitter. Here, the ratio of the area means the emitter area of the transistor for supplying a bias current (corresponding to the transistors Q5 and Q8) divided by the emitter of the transistor for amplification (corresponding to the transistors Q1 and Q2). The value obtained from the area. For example, it is assumed that the number of cells of the transistor Q1 is four in the previous stage, whereas the number of cells of the transistor Q5 is three. On the other hand, it is assumed that the number of cells of the transistor Q2 is 20 in the subsequent stage, whereas the number of cells of the transistor Q8 is one. At this time, if the emitter areas of the respective units are equal, the ratio of the emitter area is (transistor Q5/transistor Q1)=3/4 in the previous stage and (transistor Q8/transistor Q2) in the latter stage. 1/20. As described above, in the present embodiment, the ratio of the emitter area of the transistor for supplying the bias current in the front stage to the area of the emitter of the transistor for amplification is larger than that in the latter stage.

Here, it is known that the output impedance of the transistor formed by the emitter follower is inversely proportional to the amount of current of the emitter current. Therefore, when the total amount of the emitter current is constant, the larger the emitter area of the transistor, the smaller the current flowing per unit area of the emitter, and thus the higher the output impedance. In the present embodiment, since the ratio of the emitter area of the transistor Q5 to the emitter area of the transistor Q1 is larger than the ratio of the emitter area of the transistor Q8 to the emitter area of the transistor Q2, the emitter current is present. When the total amount is constant, the output impedance of the transistor Q5 becomes high. Therefore, even if the degree of the RF signal RF1 is large and the amplitude of the alternating current at the base of the transistor Q1 is large, the fluctuation of the alternating current of the current at the emitter of the transistor Q5 is suppressed. As described above, in the present embodiment, since the detection performance of the RF signal of the transistor Q5 is lowered, the generation of a negative current is suppressed, and as a result, an increase in the average value of the current amount of the bias current Ibias1 can be suppressed. Further, along with this, the rise of the voltage Vbb at the emitter of the transistor Q5 is also suppressed.

In other words, in the power amplifying circuit 100, fluctuations in the current amount of the bias current Ibias1 can be suppressed without using a capacitor connected between the splicing and the base-emitter. Therefore, compared with the result disclosed in Patent Document 1, the power amplifying circuit 100 can suppress the linear deterioration of the gain in the wide band regardless of the frequency band of the RF signal.

Further, although the emitter area of the transistor Q5 in the front stage is not particularly limited, for example, it is preferably one-half or more of the emitter area of the transistor Q1 for amplification. That is, for example, when the number of cells of the transistor Q1 is four, it is preferable that the number of cells of the transistor Q5 is two or more.

Further, in the latter stage, if the emitter area of the transistor Q8 of the bias circuit 121 is made too large, the power (Power) may be insufficient with respect to the amplification level of the power of the transistor Q2 for amplification. Therefore, it is preferable that the emitter area of the transistor Q8 in the subsequent stage is, for example, smaller than the emitter area of the transistor Q5 in the preceding stage. If the emitter area of the transistor Q8 is small, the average value of the bias current increases as the degree of the RF signal increases, and the gain may rise. Here, by lowering the gain in the preceding stage so that the rise of the gain in the subsequent stage is canceled, the linearity at the time of matching the front stage and the rear stage can be improved.

Further, the power amplifier circuit 100 may have, for example, a three-stage amplifier. In this case, for example, the above-described bias circuit 120 may be applied to the amplifier (first transistor) of the second stage, and the above-described bias circuit 121 may be applied to the amplifier (second transistor) of the third stage. The structure is thereby offset by the increase in gain in the amplifier of the third stage. Alternatively, the configuration of the above-described bias circuit 120 may be applied to the amplifier (first transistor) of the first stage, and the configuration of the above-described bias circuit 121 may be applied to the amplifier (second transistor) of the third stage. This offsets the rise in gain in the amplifier of the third stage.

3 is a graph showing an example of a simulation result of the voltage Vbb in the power amplifier circuit according to the embodiment of the present invention. Specifically, the graph shown in FIG. 3 shows that the number of cells of the transistor Q1 and the transistor Q5 is set to (Q1: Q5) = (4: 0.5), (4: 1), (4: 2), ( 4:3), (4:4), (4:5), (4:6), the relationship between the voltage Vbb at the emitter of the transistor Q5 and the output power Pout. Here, it is assumed that each unit constituting the transistor Q1 includes two emitter layers, and the emitter area of each unit is 3.0 × 40 × 2 = 240 μm ² . On the other hand, it is assumed that each unit constituting the transistor Q5 includes four emitter layers, and the emitter area of each unit is 3.0 × 20 × 4 = 240 μm ² . Further, the number of cells of the transistor Q5 is 0.5, which is a calculation result when the emitter area is 3.0 × 20 × 2 = 120 μm ² . In the graph shown in FIG. 3, the horizontal axis represents the output power Pout (dBm), and the vertical axis represents the voltage Vbb (V).

As shown in FIG. 3, when the number of cells with respect to the transistor Q1 is four and the number of cells of the transistor Q5 is two or more, an increase in the voltage Vbb accompanying an increase in output power is suppressed. Therefore, it can be said that the emitter area of the transistor Q5 is preferably one-half or more of the emitter area of the transistor Q1.

4 is a graph showing an example of a simulation result of the gain of the previous stage in the power amplifier circuit according to the embodiment of the present invention. Specifically, the graph shown in FIG. 4 shows that the number of cells of the transistor Q1 and the transistor Q5 is (Q1: Q5) = (4: 0.5), (4: 1), (4: 2), ( 4:3), (4:4), (4:5), (4:6), when the number of cells of the transistor Q2 and the transistor Q8 is (Q2: Q8) = (20: 2) The relationship between the gain in the front stage transistor Q1 and the output power Pout. Here, it is assumed that each unit constituting the transistor Q2 is two emitter layers, and the emitter area of each unit is 3.0 × 40 × 2 = 240 μm ² . On the other hand, it is assumed that each unit constituting the transistor Q8 includes four emitter layers, and the emitter area of each unit is 3.0 × 20 × 4 = 240 μm ² . Further, the same conditions as those of the above-described simulation shown in FIG. 3 are the same for the transistor Q1 and the transistor Q5. In the graph shown in FIG. 4, the horizontal axis represents the output power Pout (dBm), and the vertical axis represents the gain (dB) of the transistor Q1. Further, as a reference, an example of the gain of the transistor Q2 in the subsequent stage is indicated by a broken line.

As shown in FIG. 4, even in the case where the emitter area of the transistor Q5 is arbitrary, the gain of the front stage transistor Q1 is gently decreased as the output power is increased. On the other hand, the transistor Q2 in the subsequent stage can be set to increase in gain as the output power increases as shown in FIG. Therefore, it can be said that linear deterioration of the gain of the power amplifying circuit 100 can be suppressed by matching the gain characteristics.

FIG. 5 is a graph showing an example of a simulation result of ACLR characteristics in the power amplifier circuit of the comparative example of the present invention. Moreover, FIG. 6 is a graph showing an example of a simulation result of ACLR characteristics in the power amplifier circuit according to the embodiment of the present invention. The comparative example is a structure in which a capacitor is connected between the base and the emitter of the transistor Q5 shown in Fig. 1 . 5 and 6 show the Adjacent Channel Leakage Ratio (ACLR) when the power supply voltage is 3.4 V at room temperature and the RF signal frequency is 824 MHz, 849 MHz, 880 MHz, and 915 MHz. The relationship between the characteristics and the output power Pout. In the graphs shown in FIGS. 5 and 6, the horizontal axis represents the output power Pout (dBm), and the vertical axis represents the ACLR (dBc).

As shown in FIG. 5, in the comparative example, it is understood that the ACLR characteristics vary depending on the frequency band of the RF signal. Especially in a region where the degree of output power is small to medium, the variation in characteristics is remarkable, and it is considered to be linear deterioration.

On the other hand, as shown in FIG. 6, it is understood that the same ACLR characteristics are exhibited in any of the frequency bands in the power amplifier circuit 100, and the variation in the ACLR characteristics can be reduced as compared with the comparative example. Further, it can be seen that in the region where the degree of output power is moderately small, the ACLR is smaller and the linearity is improved as compared with the comparative example. As described above, according to the present embodiment, linear deterioration can be suppressed in a wide frequency band.

The exemplary embodiments of the present invention have been described above. The power amplifier circuit 100 includes transistors Q1 and Q2 for amplification and transistors Q5 and Q8 for supplying a bias current. The ratio of the emitter area of the transistor Q5 to the emitter area of the transistor Q1 is larger than that of the transistor Q8. The ratio of the polar area to the emitter area of the transistor Q2. As a result, since the output impedance of the transistor Q5 is increased, the detection performance of the RF signal of the transistor Q5 can be reduced without using an element having a frequency characteristic such as a capacitor. Therefore, according to the power amplifying circuit 100, linear degradation of the gain can be suppressed in a wide band.

Further, in the power amplifying circuit 100, the emitter area of the transistor Q5 is one-half or more of the emitter area of the transistor Q1. Thereby, the rise of the voltage Vbb at the emitter of the transistor Q5 accompanying the increase in the output power is suppressed. Therefore, linear degradation of the gain can be suppressed.

Further, in the power amplifying circuit 100, the emitter area of the transistor Q5 is larger than the emitter area of the transistor Q8. Thereby, it is possible to maintain the necessary ability in the latter stage and match the gain characteristics of the front stage transistor Q1 and the rear stage transistor Q2 to improve the linearity.

The embodiments described above are intended to facilitate the understanding of the invention and are not intended to limit the invention. The present invention can be modified or improved without departing from the spirit thereof, and equivalent parts thereof are also included in the present invention. In other words, those skilled in the art can appropriately implement design changes for the respective embodiments, and the present invention is also included in the scope of the present invention as long as it has the features of the present invention. For example, each element included in each embodiment, its preparation, materials, conditions, shape, size, and the like are not limited to the examples, and can be appropriately changed. Further, each element included in each embodiment can be combined as long as it is within the scope of the technology, and the combination of these elements is included in the scope of the present invention as long as it includes the features of the present invention.

Claims (3)

 A power amplifier circuit comprising: a first transistor that amplifies a first signal and outputs a second signal; and a second transistor that amplifies a signal corresponding to the second signal to output a third signal; and the third transistor a base of the transistor provides a first bias current or voltage; and a fourth transistor provides a second bias current or voltage to a base of the second transistor: and an emitter area of the third transistor is relatively The ratio of the emitter area of the first transistor is larger than the ratio of the emitter area of the fourth transistor to the emitter area of the second transistor.    The power amplifier circuit according to claim 1, wherein an area of an emitter of the third transistor is one-half or more of an area of an emitter of the first transistor.    The power amplifying circuit according to claim 1 or 2, wherein an area of an emitter of the third transistor is larger than an area of an emitter of the fourth transistor.