TW201916014A - Circuit for memory system and associated method - Google Patents

Abstract

A circuit for a memory system including a plurality of memories, including: a plurality of connection traces coupled in series, each connection trace having a first end, and a second end coupled to a terminal of a memory of the plurality of memories; wherein an equivalent impedance of a first connection trace of the plurality of connection traces is different with the equivalent impedance of the second connection trace of the plurality of connection traces, the first connection trace being coupled to the second connection trace in series.

Description

Circuits and related methods applied to a memory system

The present invention relates to a circuit for use in a memory system and related methods.

Memory in systems such as Solid State Device (SSD) or Double Data Rate (DDR) has traditionally been implemented using a star structure or a fly-by structure. 1 shows a star structure and a flying structure in the prior art. As shown in the sub-picture (A) of FIG. 1, a memory system 110 has a plurality of memory blocks FLASH1, FLASH2 arranged in a star structure. FLASH3 and FLASH4, and are driven by a controller 111 (such as a memory controller), wherein each memory block can include more than one memory, for example, the memory system 110 is a solid state hard disk system, and Each memory contained therein is a solid state hard disk. As shown in the sub-figure (B) of FIG. 1, the memory system 120 has a plurality of memories M1-M8 arranged in a fly-by structure, and is driven by a controller 121 (such as a memory controller), for example, The memory system 120 is a double data rate system, and each memory included therein is a double data rate synchronous dynamic random access memory (SDRAM), and the sub-picture of FIG. The star structure shown in (A) is suitable for a high speed application such as a solid state hard disk system, and the flying structure shown in the subgraph (B) of Fig. 1 usually has a long wire structure, and the wire is in two adjacent memories. The length (or impedance) between the bodies may be the same, causing the memory closest to the controller to be susceptible to severe transmission line signal reflections.

One of the objects of the present invention is to provide a circuit of a memory system and related methods to solve the above problems.

In accordance with an embodiment of the invention, a circuit for use in a memory system is disclosed that includes a plurality of memories. The circuit includes a plurality of connecting wires connected in series, each of the connecting wires having a first end and a second end, the second end being coupled to an end of one of the plurality of memories, the plurality of An equivalent impedance of a first one of the plurality of connecting lines is different from an equivalent impedance of a second one of the plurality of connecting lines, and the first connecting line and the second connecting line are connected in series .

In accordance with an embodiment of the invention, a method for applying to a memory system is disclosed that includes a plurality of memories. The method includes: connecting a plurality of connecting lines in series, wherein each connecting line has a first end and a second end, the second end being coupled to an end of one of the plurality of memories, the An equivalent impedance of a first one of the plurality of connecting lines is different from an equivalent impedance of a second one of the plurality of connecting lines, and the first connecting line is connected in series with the second connecting line connection.

Certain terms are used throughout the description and following claims to refer to particular elements. Those of ordinary skill in the art should understand that a hardware manufacturer may refer to the same component by a different noun. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection means. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the device. The second device is indirectly electrically connected to the second device through other devices or connection means.

As described above, for a memory system using a star structure, since the impedance formed by the metal connection lines is used to connect the memory, the same distance will have the same equivalent impedance, thus causing severe reflection. Decreased performance. 2 is a schematic diagram of a driving circuit 200 applied to a memory system 202 according to an embodiment of the present invention. The memory system 202 includes a plurality of memories M1, M2, M3, M4, M5, M6, M7, and M8. Those of ordinary skill in the art will appreciate that the memory M1-M8 can be equivalent to a plurality of capacitors as shown in FIG. It should be noted that the number of memories included in the memory system 202 is not a limitation of the present invention. For example, the memory system 202 can include more than one memory (eg, 2, 4, 6, 8, or even More memory), depending on the needs of the actual application. The driving circuit 200 includes a plurality of connecting lines T ₁ , T ₂ , T ₃ , T ₄ , T ₅ , T ₆ , T ₇ and T ₈ , wherein the connecting lines T ₁ -T ₈ are respectively L ₁ and L _{2 in} length , L ₃ , L ₄ , L ₅ , L ₆ , L ₇ , and L ₈ are realized by metal, and as shown in Fig. 2, the equivalent impedances of the connecting lines T1-T8 are Z ₁ , Z ₂ , and Z, respectively. ₃ , Z ₄ , Z ₅ , Z ₆ , Z ₇ , and Z ₈ . Each memory system memory M1-M8 in the memory 202 has one end coupled to an end point of one of the connecting line, wherein T ₁ -T _8, and in the memory M1-M8 on each of two memory It is separated by one of the connecting lines T ₁ -T ₈ .

The driving circuit 200 further includes a controller 201 (for example, a memory controller) including a driving voltage source Vs and a resistor Rs, and the controller 201 is coupled to the connecting lines T ₁ -T ₈ . The connection line T1 and the memory M1 can be regarded as a low-pass filter, the connection line T ₂ and the memory M2 can be regarded as another low-pass filter, and so on. For the memory M1, the required low-pass filter having _a connecting line impedance Z T ₁ of the memory M1 or consisting operating frequency by adjusting the length of the cutoff frequency axis T ₁ is connected to the set, such that The driving voltage signal generated by the driving voltage source Vs can pass. Similarly, the operating frequency or cutoff frequency required by the low-pass filter composed of the connection line T ₂ and the memory M2 can be set by adjusting the length of the connection line T ₂ , and by the connection line T ₃ and the memory M3 The operating frequency or cutoff frequency required for the low pass filter formed can be set by adjusting the length of the connection line T ₃ , and so on. The drive signal is thereby transmitted to the terminating resistor (e.g., the load impedance R _L shown in FIG. 2). In other embodiments, the terminating resistor is located in the memory that is furthest from the controller 201.

With the above embodiment, the reflection of the driving signal can be observed when the endpoints N ₁ , N ₂ , N ₃ , N ₄ , N ₅ , N ₆ , N _{7 ,} and N ₈ shown in FIG. ₂ can be Suppression/attenuation, the maximum eye diagram of the drive signal will be observed by the test instrument, and the performance is greatly improved.

It should be noted that the impedance of the connecting lines T ₁ -T ₈ can be adjusted not only by changing the length, but also by changing the width or by using different kinds of metals or materials. In addition to this, in this embodiment, the equivalent impedance of the connecting lines T ₁ -T ₈ is marked by a different name (ie Z ₁ -Z ₈ ), however, some of the connections T ₁ -T ₈ are connected Lines can have the same equivalent impedance. Figure 3 is a schematic diagram of a driving circuit 200 applied to a memory system in accordance with another embodiment of the present invention. In this embodiment, the impedances Z ₁ , Z ₃ , Z ₅ , and Z ₇ shown in Figure 2 have the same The impedance value ZV ₁ and the impedances Z ₂ , Z ₄ , Z ₆ , Z ₈ have the same impedance value ZV ₂ , where ZV ₁ ≠ZV ₂ . Referring to FIG. 4, which is a schematic diagram of a driving circuit in a memory system including at least two memories (for example, M1 and M2), and the driving circuit includes two different ones according to still another embodiment of the present invention. The series-coupled connecting lines have different impedance values ZV ₁ /2 and ZV ₂ /2 (the controller positions are not shown in the figure), and the driving circuit and the memories M1 and M2 can be regarded as a filter. It is used to filter a specific frequency band in which only signals having a frequency in the frequency band range can be allowed to pass or be transmitted to the memory. The driving circuit as shown in FIG. 4 can be used as an equivalent block diagram, and the driving circuit as shown in FIG. 3 can be formed by coupling the equivalent block diagram in series.

In another example, the impedances Z ₁ , Z ₂ , Z ₃ , Z ₄ , Z ₅ , Z _{6 ,} and Z ₇ have the same impedance value ZV ₁ and the impedance Z ₈ has an impedance value ZV ₂ , where ZV ₁ ≠ZV ₂ . In another example, all of the impedances Z ₁ -Z ₈ have different impedance values, in other words, as long as the reflection of the signal can be effectively suppressed/decreased and/or the eye diagram of the drive signal is maximized, the impedance Z ₁ -Z ₈ can have any impedance value. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

110, 120, 202‧‧‧ memory system

111, 201‧‧‧ controller

M1-M8‧‧‧ memory

FLASH1-FLASH4‧‧‧ memory block

200‧‧‧ drive circuit

T ₁ -T ₈ ‧‧‧ connecting line

Z ₁ -Z ₈ , ZV ₁ , ZV ₂ ‧‧‧ impedance

N ₁ -N ₈ ‧‧‧ endpoint

R _L ‧‧‧load impedance

Rs‧‧‧resistance

Vs‧‧‧ drive voltage source

Figure 1 is a schematic diagram of a star structure and a fly-by structure applied to a conventional memory system. 2 is a schematic diagram of a driving circuit applied to a memory system in accordance with an embodiment of the present invention. Figure 3 is a schematic diagram of a drive circuit applied to a memory system in accordance with another embodiment of the present invention. Fig. 4 is a schematic view showing a driving unit of the driving circuit shown in Fig. 3.

Claims (10)

A circuit applied to a memory system, wherein the memory system comprises a plurality of memories, the circuit comprising: a plurality of connecting lines, the plurality of connecting lines being connected in series, and each of the connecting lines having a first And a second end, the second end is coupled to an end of one of the plurality of memories; wherein an equivalent impedance of the first connection line of the plurality of connection lines and the plurality of An equivalent impedance of a second connecting line in the connecting line is different, and the first connecting line and the second connecting line are connected in series. The circuit of claim 1, further comprising: a controller, comprising: a driving voltage source coupled to the plurality of serially connected connecting lines, wherein the driving voltage source is configured to provide a driving voltage to the a plurality of memories; and a source impedance coupled between the plurality of connection lines and the driving voltage source. The circuit of claim 1, wherein the plurality of memories are a plurality of Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM). The circuit of claim 1, wherein the plurality of memories are a plurality of solid state disks (SSDs). The circuit of claim 1, wherein a length of the first connecting line is different from a length of the second connecting line. A method for a memory system, the memory system comprising a plurality of memories, wherein the method comprises: coupling a plurality of connecting lines in series, each of the plurality of connecting lines having a first end And a second end coupled to an end of one of the plurality of memories; wherein an equivalent impedance of a first one of the plurality of connecting lines is connected to the plurality of An equivalent impedance of a second connecting line in the line is different, and the first connecting line and the second connecting line are connected in series. The method of claim 6, further comprising: utilizing a driving voltage source coupled to the plurality of serially connected connecting lines, wherein the driving voltage source is configured to provide a driving voltage to the plurality of memories; And coupling a source impedance to the driving voltage source and between the plurality of connecting lines. The method of claim 6, wherein the plurality of memories are a plurality of Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM). The method of claim 6, wherein the plurality of memories are a plurality of solid state disks (SSDs). The method of claim 6, wherein a length of the first connecting line is different from a length of the second connecting line.