TW201903966A - Self-aligned through hole processing - Google Patents

Abstract

Processing methods may be performed to form semiconductor structures that may include self-aligned via structures. The methods may include depositing a first dielectric material on the semiconductor substrate. The first dielectric material may be selectively deposited on a second dielectric material relative to exposed regions of fill metal. The methods may further include subsequently depositing a cap material over the fill metal. The cap material may be selectively deposited on the fill metal relative to exposed regions of the first dielectric material.

Description

Self-aligned through hole processing

This technology relates to semiconductor systems, processing and equipment. More specifically, the present technology relates to systems and methods for selectively etching and selectively depositing layers of materials on a semiconductor device.

It is possible to fabricate an integrated circuit by processing a layer of intricately patterned material on the surface of the substrate. Producing a patterned material on a substrate requires a control method for removing the exposed material. Chemical etching is used for a variety of purposes, including transferring the pattern in the photoresist into the underlying layer, the thinned layer, or the thinned lateral dimension of features already present on the surface. It is generally desirable to have an etching process that etches one material faster than the other to facilitate, for example, pattern transfer processing or separate material removal. This etching process is said to be selective for the first material. Due to the variety of materials, circuits, and processes, etching processes have been developed that are selective for a variety of materials. However, the deposition process is typically performed using a blanket coating or conformal fill to continue across the substrate.

As device sizes continue to shrink in next-generation devices, selectivity can play a greater role when the material formed in a particular layer is only a few nanometers (especially when the material is critical in the formation of the transistor). Many different etch processing options have been developed between various materials, but standard selectivity may no longer be applicable to current and future device sizes. Moreover, based on the number of masking, forming, and removing operations required to form and protect the various critical dimensions of the features across the device, the processing time continues to increase while patterning and formation is performed elsewhere on the substrate.

Therefore, there is a need for a system and method that can be used to produce high quality devices and structural improvements. This technology addresses these and other needs.

A processing method can be performed to form a semiconductor structure that can include a self-aligned via structure. The method can include the step of depositing a first dielectric material on a semiconductor substrate. The first dielectric material can be selectively deposited on the second dielectric material relative to the exposed regions of the fill metal. The method can further include the step of subsequently depositing a cap material on the fill metal. The cover material can be selectively deposited on the fill metal relative to the exposed areas of the first dielectric material.

In some embodiments, the filler metal can be or include copper or cobalt. The first dielectric material may be or include tantalum carbonitride, tantalum nitride, tungsten oxide or aluminum oxide, and the second dielectric material may be or include tantalum oxide. The cover material can be a metal nitride or a metal oxide, or can include a metal nitride or a metal oxide. The method can be performed without performing a reactive ion etching operation. The deposition of the first dielectric material can be performed using a selectivity of the second dielectric material that is greater than or about 2: 1 with respect to the fill metal. Cover material deposition may be performed using a selectivity of the filler metal that is greater than or about 2: 1 relative to the first dielectric material. In some embodiments, the method can further include the step of depositing a third dielectric material over the exposed regions of the fill metal. The third dielectric material can be selectively deposited on the fill metal relative to the first dielectric material and the second dielectric material.

The present technology also includes a method of forming a semiconductor structure. The method can include the step of forming a plasma of a fluorine-containing precursor in a distal plasma region of the processing chamber. The method can include the step of contacting the semiconductor substrate with the effluent of the plasma. The semiconductor substrate can be housed in a processing region of the processing chamber. The method can include the step of selectively etching the fill metal below a level of the exposed area of the first dielectric material on the semiconductor substrate. The method can also include the step of subsequently depositing a cover material on the filler metal. The cover material can be selectively deposited on the fill metal relative to the exposed areas of the first dielectric material.

In an embodiment, the method may also include the step of depositing a second dielectric material. The second dielectric material can be selectively deposited on the fill metal relative to the cover material and the first dielectric material. The cover material can be a different material than the second dielectric material or comprise a different material than the second dielectric material. The cover material may be selected from the group consisting of carbonaceous materials, nitrogen-containing materials, and oxygen-containing materials. The second dielectric material may be selected from the group consisting of carbonaceous materials, nitrogen-containing materials, and oxygen-containing materials. In an embodiment, the second dielectric material can be different than the cover material. The oxygen containing material can be or include cerium oxide, tungsten oxide or aluminum oxide. The etching can be performed in the first processing chamber and the deposition can be performed in the second processing chamber. The method can further include the step of transferring the semiconductor substrate from the first processing chamber to the second processing chamber. In an embodiment, the transfer can be performed without breaking the vacuum. Etching can be performed using a selectivity of the fill metal that is greater than or about 10:1 relative to the first dielectric material. Deposition can be performed using a selectivity of the filler metal that is greater than or about 2: 1 relative to the first dielectric material.

The present technology also includes a method of forming a semiconductor structure. The method can include the step of depositing a first metal on the fill metal. The first metal can be selectively deposited on the fill metal relative to the exposed regions of the first dielectric material. The method can also include the step of subsequently depositing a cover material on the first metal. The cover material can be selectively deposited on the first metal relative to the exposed regions of the first dielectric material. In an embodiment, the method may also include the step of depositing a second dielectric material. The second dielectric material can be selectively deposited on the first metal relative to the first dielectric material.

Such techniques can provide many benefits over conventional systems and techniques. For example, processing can protect critical dimensions and provide improved selectivity by utilizing techniques that do not include reactive ion etching. In addition, by performing selective operations, fewer masking and removal operations can be performed, which can significantly reduce manufacturing queue time. These and other embodiments, as well as many advantages and features thereof, are described in more detail in conjunction with the following description and the accompanying drawings.

The techniques of the present invention include systems and components for semiconductor processing of small pitch features. In a conventional self-aligned formation process, materials on the substrate can be formed and etched alongside structures having similar or different materials to be maintained. For example, because the cap layer and spacers may be formed of a similar material (eg, tantalum nitride), the etching process used to remove such layers may not provide significant selectivity relative to other key features. During various open processes, the size of multiple critical dimensions may cause load effects, while etching exceeds the expected availability of materials. For example, conventional processing can include a masking layer followed by a reactive ion etching ("RIE") process that allows openings in the structure of the gap-filling layer. Although the RIE etch is a relatively anisotropic process, the RIE etch may still have selectivity for sidewall loss. Although it may be considered to budget for this loss during formation (eg, with over-formation of materials), because the regions within the etched structure have different sizes, the calculation of the amount of loss for one region may not be suitable for larger The amount of loss in the area. Thus, although a 5 nm loss may occur in one section of the budget, a loss of a larger section of 6-7 nm may still occur, resulting in a mismatch during manufacturing.

In addition, the RIE process produces etch byproducts or polymer residues (usually removed using a wet etch process). This wet etch often over-etches the sidewall protection layer beyond the critical dimension (which causes problems with the formation and spacing of adjacent transistor layers) and further etches the low-k nitride spacers and the interlayer dielectric oxide. In addition, the removal of metallic materials and dielectrics is typically performed using an anisotropic etch, and unless additional masks or protective layers are formed, it is possible to further reduce the exposed areas of the capping material and spacer material in other regions. Since the selectivity of such RIE removal may be in the range of 10:1, the amount of masking required may be large.

In conventional techniques utilizing the conformal development of blanket coatings or materials across materials of all exposed areas on a semiconductor substrate, deposition of both the masking material and other layers of material can be performed. These types of deposition may require further patterning and removal operations, which can significantly increase the queue time of device fabrication. Between the additional operations and defects of the RIE removal and the various operations used in conventional deposition, the stacking time of the individual device layers may increase by several hours. In addition, additional patterning and lithography may be required in order to access metal-filled vias having interconnect structure layers and to maintain specific structural lines within each layer. When not fully implemented, subsequent via formation may not be aligned with the underlying via and may cause shorts to other metal layers.

The present technology overcomes these problems by modifying the processing for removal and formation. These processes can be used to perform etching with higher selectivity than conventional RIE by performing selective etch processing in a particular device, which may allow for additional patterning operations that may not previously be possible, and may be critical Feature sizes provide extra protection. In addition, reduced masking, patterning, and removal can be utilized in structural formation by performing selective deposition operations in specific equipment. Such processing allows a particular mask to be used to protect certain metal lines and expose the vias and form a platform between the individual device layers. Moreover, by utilizing alternative etching to remove many of the patterning operations, such processing can save hours compared to conventional processing using RIE and standard deposition.

While the remainder of the disclosure will routinely identify particular etching and deposition processes utilizing the disclosed techniques, it should be understood that the systems and methods are equally applicable to the various other etching, deposition, and cleaning processes that may occur in the described chambers. Therefore, the technique should not be considered limited to the etching and deposition processes that can be used only. The present disclosure will discuss one possible system and chamber that can be used with the present technology to perform certain removal and deposition operations prior to the described operations of the exemplary processing sequences in accordance with the present technology.

FIG. 1 illustrates a top plan view of one embodiment of a processing system 100 for depositing, etching, baking, and curing chambers in accordance with an embodiment. In the drawings, a pair of front open pods (FOUPs) 102 are supplied with substrates of various sizes, which are received by robotic arms 104 and placed in a substrate processing chamber located in series sections 109a-c. Prior to one of 108a-f, it is placed into the low pressure holding area 106. The second robotic arm 110 can be used to transport substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and back. In addition to cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), wet etching, pre-cleaning, degassing, orientation, and other substrate processing, Each substrate processing chamber 108a-f is equipped to perform a number of substrate processing operations including dry etching processes and selective deposition as described herein.

The substrate processing chambers 108a-f can include one or more system components for depositing, annealing, curing, and/or etching a dielectric film on a substrate wafer. In one configuration, two pairs of processing chambers (eg, 108c-d and 108e-f) can be used to deposit a dielectric material or metal-containing material on the substrate, while a third pair of processing chambers (eg, 108a-b) It can be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (eg, 108a-f) can be configured to etch a dielectric film on the substrate. Any one or more of the processes described may be performed in a chamber separate from the manufacturing system shown in the different embodiments.

In some embodiments, the chamber specifically includes at least one etch chamber as described below and at least one deposition chamber as described below. All of the etching and deposition processes described below can be performed in a controlled environment by including such chambers and combining the processing sides of the factory interface. For example, the vacuum environment can be maintained on the processing side of the holding area 106 such that all of the chambers and transfers in the embodiment are maintained under vacuum. This also limits the contact of water vapor and other air components with the substrate being processed. It should be understood that system 100 can take into account additional configurations for deposition, etching, annealing, and curing of dielectric films.

2A illustrates a cross-sectional view of an exemplary processing chamber system 200 having separate plasma generating regions within a processing chamber. During film etching (for example, titanium nitride, tantalum nitride, tungsten, cobalt, aluminum oxide, tungsten oxide, tantalum, polycrystalline germanium, antimony oxide, antimony nitride, antimony oxynitride, antimony oxyhydroxide, etc.), the process gas can pass The gas inlet assembly 205 flows into the first plasma region 215. A remote plasma system (RPS) 201 can optionally be included in the system and can process the first gas that subsequently travels through the gas inlet assembly 205. The inlet assembly 205 can include two or more different gas supply passages, wherein if a second passage (not shown) is included, the second passage can bypass the RPS 201.

A cooling plate 203, a panel 217, an ion eliminator 223, a showerhead 225, and a substrate support 265 having a substrate 255 disposed thereon are illustrated, and each may be included in accordance with an embodiment. The pedestal 265 can have a heat exchange channel through which the heat exchange fluid flows to control the temperature of the substrate, and the temperature of the substrate can be manipulated during processing operations to heat and/or cool the substrate or wafer. An embedded resistive heater element can also be used while resistively heating a wafer support disk that can include pedestal 265 of aluminum, ceramic, or a combination thereof to achieve relatively high temperatures, such as from up to or about 100 °C to above or about 1100 °C.

Panel 217 may be pyramidal, conical or other similar structure having a narrow top portion that extends to a wide bottom portion. Additionally, panel 217 may be flat and include a plurality of through passages for dispensing process gases, as shown. Depending on the use of the RPS 201, the plasma generating gas and/or the plasma exciting material may pass through a plurality of holes in the panel 217 as shown in FIG. 2B for more uniform delivery into the first plasma region 215.

An exemplary configuration may include the gas inlet assembly 205 passing into the gas supply region 258 separated by the panel 217 from the first plasma region 215 such that gas/substance flows through the holes in the panel 217 into the first plasma region 215. Structural and operational features may be selected to prevent large amounts of plasma from the first plasma region 215 from flowing back into the supply region 258, the gas inlet assembly 205, and the fluid supply system 210. The insulating ring 220 between the features is shown with the panel 217 or the conductive top portion of the chamber and the showerhead 225 to allow an AC potential to be applied to the panel 217 relative to the showerhead 225 and/or the ion eliminator 223. . Insulation ring 220 can be positioned between panel 217 and showerhead 225 and/or ion eliminator 223 to allow capacitive coupling plasma (CCP) to be formed in the first plasma region. Additionally, a baffle (not shown) may be located in the first plasma region 215 or otherwise coupled to the gas inlet assembly 205 to affect the flow of fluid through the gas inlet assembly 205 into the region.

Ion eliminator 223 can include a plate or other geometry defining a plurality of pores throughout the structure, the plurality of pores being configured to eliminate migration of ionically charged species exiting first plasma region 215 while allowing uncharged neutrality Or the radical species pass through the ion eliminator 223 into the active gas delivery zone between the eliminator and the showerhead. In an embodiment, the ion eliminator 223 can comprise a multiwell plate having various pore configurations. Such uncharged materials can include highly active materials that are transported through the pores with less active gas carrier. As noted above, migration of ionic species through the pores may be reduced and, in some cases, completely eliminated. Controlling the amount of ionic species passing through the ion eliminator 223 can advantageously provide increased control of the gas mixture in contact with the underlying wafer substrate, which in turn can increase control of deposition and/or etch characteristics of the gas mixture. For example, the adjustment of the ion concentration of the gas mixture can significantly change its etch selectivity, for example, SiNx: SiOx etch rate, Si: SiOx etch rate, and the like. In an alternative embodiment of performing deposition, the balance of conformal flow deposition of the dielectric material can also be translated.

The plurality of apertures in ion eliminator 223 can be configured to control the passage of reactive gases (i.e., ions, free radicals, and/or neutral species) through ion eliminator 223. For example, the aspect ratio of the holes, or the diameter of the holes to the length, and/or the geometry of the holes, can be controlled such that the flow of ionically charged species in the reactive gas passing through the ion eliminator 223 is reduced. The holes in the ion eliminator 223 may include a tapered portion facing the plasma excitation region 215 and a cylindrical portion facing the showerhead 225. The cylindrical portion can be shaped and sized to control the flow of ionic species to the showerhead 225. An adjustable electrical bias can also be applied to the ion eliminator 223 as an additional means of controlling the flow of ionic species through the eliminator.

Ion eliminator 223 can be used to reduce or eliminate the amount of ionically charged species traveling from the plasma generating region to the substrate. Uncharged neutral and free radical species can still pass through the openings in the ion eliminator to react with the substrate. It should be noted that in an embodiment, complete elimination of the ionically charged species in the reaction zone surrounding the substrate may not be performed. In some cases, the ionic species are intended to reach the substrate to perform an etching and/or deposition process. In such cases, the ion eliminator can help control the concentration of ionic species in the reaction zone at a level that facilitates processing.

The showerhead 225 in combination with the ion eliminator 223 can allow plasma present in the first plasma region 215 to avoid direct excitation of gas in the substrate processing region 233 while still allowing the excited species to travel from the chamber plasma region 215. Go to substrate processing area 233. In this manner, the chamber can be configured to prevent plasma from contacting the substrate 255 in the etch. This can advantageously protect the various complex structures and films patterned on the substrate, and various complex structures and films can be damaged, displaced or otherwise bent if directly in contact with the plasma produced. Furthermore, the rate at which the oxide species is etched may be increased when the plasma is allowed to contact the substrate or near the substrate level. Thus, if the exposed area of the material is an oxide, the material can be further protected by maintaining the plasma at the distal end of the substrate.

The processing system can further include a power supply 240 electrically coupled to the processing chamber to provide electrical power to the panel 217, the ion eliminator 223, the showerhead 225, and/or the pedestal 265 for processing in the first plasma region 215 or A plasma is generated in the region 233. Depending on the processing performed, the power supply can be configured to deliver an adjustable amount of power to the chamber. This configuration can allow tunable plasma for processing in execution. Unlike a remote plasma unit that is typically presented with an on or off function, the tunable plasma can be configured to deliver a specific amount of power to the plasma region 215. This in turn may allow for the formation of specific plasma characteristics such that the precursor may be dissociated in a particular manner to enhance the etch profile created by such precursors.

The plasma may be excited in the chamber plasma region 215 above the showerhead 225 or the substrate processing region 233 below the showerhead 225. In an embodiment, the plasma formed in the substrate processing region 233 may be a DC bias plasma formed using a pedestal as an electrode. A plasma may be present in the chamber plasma region 215 to produce a free radical precursor from the influx of, for example, a fluorine-containing precursor or other precursor. Typically, an AC voltage in the radio frequency (RF) range can be applied between the conductive top portion of the processing chamber (eg, panel 217) and the showerhead 225 and/or ion eliminator 223 to excite the cavity during deposition. The plasma in the chamber plasma region 215. The RF power supply can produce a high RF frequency of 13.56 MHz, but other frequencies can be generated separately or combined with the 13.56 MHz frequency to produce other frequencies.

FIG. 2B illustrates a detailed view 253 of features affecting the distribution of process gases through panel 217. As shown in FIGS. 2A and 2B, panel 217, cooling plate 203, and gas inlet assembly 205 intersect to define a gas supply region 258 in which process gas can be delivered from gas inlet 205 into gas supply region 258. The gas may fill the gas supply region 258 and flow through the apertures 259 in the panel 217 to the first plasma region 215. The apertures 259 can be configured to direct flow in a substantially unidirectional manner such that process gases can flow into the processing region 233, but can be partially or completely prevented from flowing back into the gas supply region 258 after passing through the panel 217.

The gas distribution assembly (e.g., showerhead 225 for processing chamber section 200) may be referred to as a dual channel showerhead (DCSH) and is additionally illustrated in detail in the embodiment illustrated in FIG. The dual channel showerhead can provide an etch process to allow separation of the etchant outside of the processing region 233 to provide limited interaction with the chamber components and each other prior to delivery to the processing region.

The showerhead 225 can include an upper plate 214 and a lower plate 216. These plates can be coupled to each other to define a volume 218 between the plates. The coupling of the plates can provide a first fluid passage 219 through the upper and lower plates and a second fluid passage 221 through the lower plate 216. The formed passageway can be configured to provide a fluid inlet and outlet from the volume 218 alone through the second fluid passage 221 through the lower plate 216, while the first fluid passage 219 can be fluidly isolated from the volume 218 between the plate and the second fluid passage 221. The volume 218 can be vented through one side of the gas distribution assembly 225.

Figure 3 is a bottom plan view of a showerhead 325 for use with a processing chamber in accordance with an embodiment. The showerhead 325 can correspond to the showerhead 225 shown in FIG. 2A. The through holes 365 (the view of the first fluid passage 219 are illustrated) may have a plurality of shapes and configurations to control and influence the flow of the precursor through the showerhead 225. The small holes 375 (shown as a view of the second fluid passage 221) may be substantially evenly distributed over the surface of the showerhead (even in the through holes 365) and may help the precursor provide a ratio when leaving the showerhead. Other configurations are more evenly mixed.

Turning to FIG. 4, a schematic cross-sectional view of an atomic layer deposition system 400 or reactor in accordance with one or more embodiments of the present technology is illustrated. System 400 can include a load lock chamber 10 and a processing chamber 20. The processing chamber 20 can generally be a sealable outer casing that can be operated under vacuum or at least low pressure. The processing chamber 20 can be isolated from the load lock chamber 10 by an isolation valve 15. The isolation valve 15 can seal the process chamber 20 and the load lock chamber 10 in a closed position and can allow the substrate 60 to be transferred from the load lock chamber 10 through the valve to the process chamber 20 in the open position, and vice versa.

System 400 can include a gas distribution plate 30 that can dispense one or more gases across substrate 60. The gas distribution plate 30 can be any suitable distribution plate known to those skilled in the art, and the particular gas distribution plate should not be considered to limit the scope of the present technology. The output face of the gas distribution plate 30 may face the first surface 61 of the substrate 60.

The gas distribution plate 30 can include a plurality of gas crucibles and a plurality of vacuum crucibles, the plurality of gas crucibles configured to deliver one or more gas streams to the substrate 60, and a plurality of vacuum crucibles disposed between each gas crucible, And configured to deliver a flow of gas out of the processing chamber 20. As shown in FIG. 4, the gas distribution plate 30 can include a first precursor injector 420, a second precursor injector 430, and a purge gas injector 440. The injectors 420, 430, 440 can be controlled by a system computer (not shown) (e.g., a host) or by a chamber specific controller (e.g., a programmable logic controller). The precursor injector 420 can be configured to inject a continuous or pulsed stream of active precursors of Compound A through the plurality of gas helium 425 into the processing chamber 20. The precursor injector 430 can be configured to inject a continuous or pulsed stream of active precursors of Compound B through the plurality of gas helium 435 into the processing chamber 20. The purge gas injector 440 can be configured to inject a continuous or pulsed stream of inactive or purge gas through the plurality of gas ports 445 into the processing chamber 20. The purge gas can be configured to remove active material and active byproducts from the processing chamber 20. The purge gas is typically an inert gas such as nitrogen, argon and helium. A gas crucible 445 may be disposed between the gas crucible 425 and the gas crucible 435 to separate the precursor of the compound A from the precursor of the compound B, thereby avoiding cross-contamination between the precursors.

In another aspect, a distal plasma source (not shown) can be coupled to the precursor injector 420 and the precursor injector 430 prior to injecting the precursor into the processing chamber 20. The plasma of the active material can be produced by applying an electric field to the compound in the remote plasma source. Any power source capable of activating the intended compound can be used. For example, power sources using DC, RF, and microwave-type discharge techniques can be used. If an RF power source is used, it can be capacitively or inductively coupled. Activation can also be achieved by thermal basic techniques, gas dissociation techniques, high intensity light sources (eg, ultraviolet light sources), or exposure to x-ray sources.

System 400 can further include a pumping system 450 coupled to processing chamber 20. The pumping system 450 can be generally configured to evacuate the gas stream out of the processing chamber 20 by one or more vacuum ports 455. A vacuum crucible 455 can be disposed between each gas crucible to evacuate the gas stream out of the processing chamber 20 after the gas stream reacts with the substrate surface and further limit cross-contamination between the precursors.

System 400 can include a plurality of partitions 460 disposed on processing chamber 20 and between each turn. The lower portion of each partition may extend proximate to the first surface 61 of the substrate 60 (eg, about 0.5 mm or more from the first surface 61). In this manner, the lower portion of the partition 460 can be separated from the surface of the substrate by a distance sufficient to allow the flow of gas to flow around the lower portion toward the vacuum crucible 455 after the gas stream reacts with the surface of the substrate. Arrow 498 indicates the direction of the gas flow. Since partition 460 is operable as a physical barrier to gas flow, partition 460 can also limit cross-contamination between precursors. The configurations shown are for illustrative purposes only and are not to be considered as limiting the scope of the technology. Those of ordinary skill in the art will appreciate that the gas distribution system shown is only one possible distribution system and that other types of showerheads can be employed.

In operation, the substrate 60 (e.g., by a robot) can be delivered to the load lock chamber 10 and can be placed on the shuttle 65. After the isolation valve 15 is opened, the shuttle 65 can move along the rail 70. Once the shuttle 65 enters the processing chamber 20, the isolation valve 15 can be closed to seal the processing chamber 20. The shuttle 65 can then be moved through the processing chamber 20 for processing. In one embodiment, the shuttle 65 can move through the chamber in a linear path.

As the substrate 60 moves through the processing chamber 20, the first surface 61 of the substrate 60 may be repeatedly exposed to the precursor of the compound A from the gas crucible 425 and the precursor of the compound B from the gas crucible 435 with gas from the gas crucible 445 Purge the gas. The injection of the purge gas can be designed to remove unreacted material from the previous precursor prior to exposing the substrate surface 61 to the next precursor. After each exposure to various gas streams, the gas stream can be evacuated by vacuum pumping 455 through vacuum pumping 455. Since a vacuum crucible can be placed on both sides of each gas crucible, the gas flow can be evacuated by vacuum crucibles 455 on both sides. Thus, the gas flow can flow vertically downward from the individual gas helium toward the first surface 61 of the substrate 60, across the first surface 410 and around the lower portion of the partition 460, and finally upward toward the vacuum crucible 455. In this way, each gas can be evenly distributed across the substrate surface 61. The substrate 60 can also be rotated while exposed to various gas streams. Rotation of the substrate can be useful to prevent strip formation in the formed layer. The rotation of the substrate can be a continuous or separate step.

The extent to which the substrate surface 61 is exposed to each gas can be determined by, for example, the flow rate of each gas from the gas and the rate of movement of the substrate 60. In one embodiment, the flow rate of each gas can be configured without removing the absorbed precursor from the substrate surface 61. The width between each partition, the number of gas imperfections disposed on the processing chamber 20, and the number of times the substrate may be transferred back and forth may also determine the extent to which the substrate surface 61 is exposed to various gases. Therefore, the number and quality of deposited films can be optimized by varying the above factors.

In another embodiment, system 400 can include precursor injector 420 and precursor injector 430 without purge gas injector 440. Thus, as the substrate 60 moves through the processing chamber 20, the substrate surface 61 can be alternately exposed to the precursor of Compound A and the precursor of Compound B without being exposed to the purge gas therebetween.

The embodiment shown in Figure 4 has a gas distribution plate 30 above the substrate. While the embodiments have been described and illustrated with respect to this upright orientation, it should be understood that the opposite orientation is also possible. In this case, the first surface 61 of the substrate 60 may face downward, and the gas flowing toward the substrate may be directed upward. In one or more embodiments, at least one radiant heat source 90 can be positioned to heat the second side of the substrate.

In some embodiments, the shuttle 65 can be a base 66 for carrying the substrate 60. Generally, the pedestal 66 can be a carrier that helps to form a uniform temperature across the substrate. The pedestal 66 can be moved in both left-to-right and right-to-left directions between the load lock chamber 10 and the process chamber 20 with respect to the arrangement of FIG. The pedestal 66 can have a top surface 67 for carrying the substrate 60. The pedestal 66 can be a heated pedestal such that the substrate 60 can be heated for processing. As an example, the pedestal 66 can be heated by a radiant heat source 90 disposed below the susceptor 66, a heater plate, a resistive coil, or other heating device. Although illustrated as a lateral transition, embodiments of system 400 can also be used in a rotary system in which the wheel can be rotated clockwise or counterclockwise to continuously process one or more substrates located below the gas distribution system shown. It should be similarly understood that additional modifications are included in the present technology.

FIG. 5 illustrates a method 500 of forming a semiconductor structure in which a number of operations can be performed, for example, in the aforementioned chambers 200 and 400. Method 500 can include one or more operations prior to initiating the method, including front end processing, deposition, etching, grinding, cleaning, or any other operation that can be performed prior to the operation. The method can include a plurality of selectable operations shown in the figures, which may or may not be particularly associated with methods in accordance with the present techniques. For example, many operations are described in order to provide a broader range of structure formation, but are not critical to the technology, or may be performed by alternative methods, which are discussed further below. Method 500 describes the operations illustrated schematically in Figures 6A-6E, which will be described in conjunction with the operation of method 500. It should be understood that FIG. 6 is only a partial schematic view, and the substrate may include any number of transistor segments having the pattern shown in the figures.

Method 500 can involve operations performed on a substrate having a plurality of exposed regions, such as on a substrate that includes regions that are further developed to create a self-aligned via structure. As shown in FIG. 6A, a portion of the processed substrate 600 including the etch stop layer 605, the interlayer dielectric 610, and the fill metal 615 is illustrated. Filler metal 615 can include lines 615b and 615c, and lines 615b and 615c can be metal interconnects within a single layer. The filler metal may also include material (eg, fill metal 615a) that may be in the through-vias that extend between the structural layers on the substrate. Such materials may have been formed in previous operations and may have been polished to a particular height while exposing the fill metal 615 and interlayer dielectric 610 on the top surface of the substrate. The operation of method 500 can be performed to limit or eliminate masking operations, to limit or eliminate RIE processing including ashing and cleaning, and to reduce processing time for providing cover material during production of self-aligned via structures. Treatment may also provide additional protection to fill metal 615b and fill metal 615c.

The method 500 may initially include the step of recessing the filler metal 615 as shown in FIG. 6A. The filler metal 615 can be recessed in an etch chamber similar to the chamber 200 previously described. Once positioned within the processing region of the semiconductor processing chamber, the method can include forming a plasma of the fluorine-containing precursor in the distal plasma region of the processing chamber at operation 505. The distal plasma region may be fluidly coupled to the processing region, but may be physically separated to confine the plasma at the substrate level, which may damage the exposed structure or material. The effluent of the plasma can flow into the processing region and can be contacted with the semiconductor substrate at operation 510. At operation 515, the fill metal can be selectively etched under a height of the exposed region of the interlayer dielectric 610.

At optional operation 520, the substrate can be transferred from the etch chamber to the deposition chamber. The transfer can be done under vacuum, while both chambers can reside on the same cluster tool to allow the transfer to occur in a controlled environment. For example, vacuum conditions can be maintained during transfer and transfer can be performed without breaking the vacuum. Once in the deposition chamber (eg, chamber 400 described above), at operation 525, a cap material may be formed or deposited on the recessed fill metal 615. As shown in FIG. 6B, the cover material 620 may be formed directly on the recessed fill metal 615 or in contact with the recessed fill metal 615. The deposition operation can be selective deposition wherein the cap material is preferably formed on the fill metal 615 relative to the exposed interlayer dielectric 610. Operation 525 may directly perform a subsequent etching operation 515 with respect to conventional techniques that may include additional masking operations.

Although substrate transfer can be performed, other substrate processing may not be performed between selective etching and selective deposition. As will be explained in further detail below, although substrate transfer between operations can be performed in an embodiment, while selective deposition can include multiple operations, the entire deposition process can be performed directly after a set of etching operations. Since blanket deposition or formation of cover material 620 may require additional masking and removal techniques, by performing selective etching and selective deposition in accordance with method 500, the grid time can be significantly reduced over conventional techniques. Method 500 may not utilize any RIE operation, which may reduce polymer buildup and the necessary ashing and cleaning operations associated with RIE. Furthermore, as explained further below, etching can be performed with higher or much higher selectivity than RIE, while reducing critical dimension losses on the gate spacers, and reducing or eliminating gate spacers and contact dielectrics The mask.

As shown in FIG. 6C, after deposition of the cover material 620, an optional operation 530 can be performed to selectively remove the cover material from metal lines (eg, fill metal 615b and 615c) that do not extend through the layers of the structure. 620. This operation may include lithography operations to cover line 615a as well as other interconnect materials across the substrate while leaving exposed other cover material. Once this has been done, the still exposed cover material 620 can be selectively removed from the substrate and the minimum or no material removed from the interlayer dielectric 610. Subsequently, operation 530 may expose fill metal 615b and 615c, which may be metal lines within the layers of the structure.

The method 500 can also include the step of depositing additional dielectric material on the exposed fill metal 615b and 615c. As shown in FIG. 6D, a second dielectric material 625 can then be deposited on the exposed fill metal 615 at operation 535. Operation 535 may also involve selective deposition, wherein second dielectric material 625 is preferably deposited on exposed fill metal 615b and 615c and in a dielectric material including interlayer dielectric 610 and exposed portions of cover material 620. The upper limit is not deposited. Subsequently, contact platform 630 can be formed in operation 540. This operation may include removing the remaining cover material 620. Depending on the previous operation, the cover material 620 may only remain to cover the fill metal 615a, and the fill metal 615a may be an interconnect metal extending between the layers of the structure. Removal of the cover material 620 can expose underfill metal that may extend to the platform 630. Removing the cover material 620 may involve selective etching of the cover material 620 relative to the second dielectric material 625 and the interlayer dielectric 610, or may involve additional lithographic removal. Additionally, the extension of the fill metal 615 to the contact platform 630 can include selective deposition of a metallic material. Because the filler metals 615b and 615c may not be exposed by the second dielectric material 625, the metal may be selectively deposited on the metal relative to the dielectric material. Additional deposition including electroplating and other metal fill deposition can also be performed.

Various materials can be utilized in the process, while etching and deposition can be selective for multiple components. Thus, the present technology may not be limited to a single set of materials. For example, filler metal 615 can be several conductive materials used in semiconductor processing. Filler metal 615 can be or can include copper, cobalt, or any other conductive metal that can act as a filler metal or interconnect metal. The interlayer dielectric 610 can be or include ruthenium oxide, although other insulating materials can also be used. The cover material 620 may include an insulating material, and may include a germanium-containing material, a nitrogen-containing material, an oxygen-containing material, a carbonaceous material, or some combination of such materials (eg, tantalum nitride, tantalum carbonitride, tungsten oxide, aluminum oxide, or other materials). The second dielectric material 625 may also include an insulating material, and may also include a germanium-containing material, a nitrogen-containing material, an oxygen-containing material, a carbonaceous material, or some combination of such materials (eg, tantalum nitride, tantalum carbonoxide, oxidation). Tungsten, alumina or other materials).

Since the cover material 620 can be exposed during selective deposition of the second dielectric material 625, the cover material 620 can be a different material than the second dielectric material in the embodiment, but in additional embodiments, the two materials Can be similar. Although different materials, the cover material 620 and the second dielectric material 625 may be one or more materials selected from the group consisting of carbonaceous materials, nitrogen-containing materials, and oxygen-containing materials, and may be the above Any material. However, the cover material 620 may be a different material than the material used for the second dielectric material 625.

The fill metal etch operation can involve additional precursors along with a particular fluorine-containing precursor. In some embodiments, nitrogen trifluoride can be used to produce a plasma effluent. Additional or alternative fluorine precursors may also be utilized. For example, the fluorine-containing precursor may flow into the distal plasma region, and the fluorine-containing precursor may include a group selected from the group consisting of atomic fluorine, diatomic fluorine, bromine trifluoride, chlorine trifluoride, nitrogen trifluoride, hydrogen fluoride, and six. At least one precursor of the group of sulfur fluoride and germanium difluoride. The distal plasma zone can be in a different module than the processing chamber or in a compartment within the processing chamber. As shown in FIG. 2, both the RPS unit 201 and the first plasma region 215 can serve as a distal plasma region. The RPS can allow the plasma effluent to dissociate without damaging other chamber components, while the first plasma region 215 can provide a shorter path length to the substrate during which recombination can occur.

Additional precursors can also be delivered to the remote plasma region to enhance the fluorine-containing precursor. For example, a carbon or hydrogen containing precursor or hydrogen precursor can be delivered with a fluorine-containing precursor. For example, the additional precursor can also be a fluorine-containing precursor (eg, fluoromethane). Precursors containing hydrogen or carbon and hydrogen may be included to maintain a specific H:F atomic ratio for the plasma effluent. In an embodiment, etching may be performed using an H:F ratio greater than one, which may provide increased selectivity to tungsten or other metals relative to the dielectric material described above. In an embodiment, the H:F atomic flow ratio can be maintained greater than 2:1 or greater than 3:1, which can be controlled by adjusting the relative flow rate of the fluorine-containing precursor to the hydrogen-containing precursor.

Selective etching of the capping material 620 can be performed with respect to the interlayer dielectric 610, and similar or different precursors from selective etching of the filler metal 615 for operation 515 can be used. For example, although the material may be any of the materials previously described, in an embodiment, the capping material 620 may be tantalum nitride or include tantalum nitride, and the interlayer dielectric 610 may be hafnium oxide or include oxidation. Hey. The selective etching of tantalum nitride relative to yttrium oxide may utilize a fluorine-containing precursor as previously described, and may also include an oxygen-containing precursor. The oxygenated precursor can be delivered to the distal plasma zone along with the fluoride precursor, or the oxygenated precursor can be bypassed to the distal plasma zone for direct delivery into the processing zone. In some embodiments, the capping material 620 etch operation may not include a hydrogen-containing precursor during etching and may be performed in a hydrogen-free environment.

In an embodiment, the etching operation can be performed below about 10 Torr, and in embodiments can be performed below or about 5 Torr. In embodiments, the treatment may also be performed at temperatures below about 100 °C and may be performed below about 50 °C. As performed in variations of the chamber 200 or such chambers, or in different chambers capable of performing similar operations, the process may be selective to the interlayer dielectric 610 to remove portions of the fill metal 615. Operation may also remove portions of the cover material 620 that are selective to the interlayer dielectric 610.

When performing the method, the etch selectivity to a fill metal (eg, copper, cobalt, tungsten, or other metal) relative to other features exposed on the surface of the substrate can be greater than or about 10:1, greater than or about 20: 1. Greater than or about 50:1, or greater than or about 100:1, or greater, for use in forming various materials on a substrate and may be exposed to the plasma effluent. In the disclosed embodiments, the etch selectivity with respect to the (many) erbium filler metal can be greater than or about 100:1, greater than or about 150:1, greater than or about 200:1, or greater than or about 250. :1. In embodiments, the etch selectivity to the filler metal of yttria may be greater than or about 15:1, greater than or about 25:1, greater than or about 30:1, or greater than or about 40:1. In embodiments, the etch selectivity with respect to the filler metal of the lanthanum oxyhydroxide may be greater than or about 10:1, greater than or about 20:1, greater than or about 30:1, or greater than or about 40:1. In embodiments, the etch selectivity of the filler metal relative to other oxides may be greater than or about 10:1, greater than or about 20:1, greater than or about 50:1, or greater than or about 100:1.

Thus, depending on the feature size, the fill metal can be removed from the surface of the substrate while other exposed materials can be reduced by less than 1 nm. For example, the feature width between the fill metal lines can be less than or about 100 nm, and can be less than between about 10 nm and about 30 nm. In an embodiment, the depth of the recess used to fill the metal 615 can be less than or about 50 nm, and can be less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, or less. The amount of filling used in the selective deposition operation can reach a height within any of these ranges. Due to this etch depth, a minimum amount of interlayer dielectric can be removed, which can be less than or about 3 nm, less than or about 1 nm, less than or about 0.5 nm, or the material can be substantially or substantially unchanged. Thus, the feature of the filler metal etch relative to any exposed dielectric material can be any of the above-described options for the material of each structure.

Selective deposition can be performed in a chamber capable of deposition and capable of atomic layer deposition, including chamber 400 described above. The deposition may be preset to selectively deposit an insulating material on a metallic material relative to another insulating material. For example, the cap material 620 can be formed substantially on the fill metal 615 while being minimally formed on the interlayer dielectric 610 or limited to the interlayer dielectric 610. Selective deposition may be performed by a variety of operations, which may include forming a self-assembled monolayer to facilitate selective deposition, or may include actively inhibiting the formation of a dielectric on other dielectric materials.

A self-assembled monolayer can be formed over the area of the structure to tune the deposition. For example, a first self-assembled monolayer can be formed structurally and subsequently exposed to a lithographic mask to remove a single layer from fill metal 615. A single layer can be maintained on the interlayer dielectric 610. The monolayer may have a capping moiety that may or may not interact with the subsequently delivered precursor. For example, in embodiments, the capping moiety can be hydrophobic and can be capped with a hydrogen containing moiety (eg, a methyl group) that can not interact with the additional precursor. The second self-assembled monolayer may be formed on the fill metal 615, but may be hydrophilic or react with one or more precursors used to create the cap material 620. The second self-assembled monolayer can be selectively formed on the fill metal 615 because the material can be repelled from the first self-assembled monolayer or can be selectively stretched to the metal. The second self-assembled monolayer may be capped with a hydroxyl or other hydrophilic moiety, or partially capped with an interaction with an additional precursor used to form the capping material 620.

Subsequently, atomic layer deposition may be performed using two or more precursors to develop the cover material 620. The deposited precursor can include a metal-containing precursor and includes a precursor configured to interact with a portion of the capped second self-assembled monolayer (rather than the first self-assembled monolayer). For example, when a hydrophilic and hydrophobic capping monolayer is used, one of the atomic layer deposition precursors can include water. In this way, deposition may not be formed on the first self-assembled monolayer which may be hydrophobic. If the cap material comprises a metal oxide (eg, tungsten oxide or aluminum oxide), the precursor for atomic layer deposition may include a tungsten-containing precursor or an aluminum-containing material and water. In other embodiments, a ruthenium containing precursor can be used. Subsequently, during a half reaction with water, water may not interact with the first self-assembled monolayer formed on the interlayer dielectric 610, and thus the deposition will not form on the first self-assembled monolayer. In this manner, the capping material 620 can be selectively formed over the fill metal 615 without forming a mask layer that can be chemically etched.

After the cover material 620 has been formed to a suitable height, the first self-assembled monolayer may be exposed to UV light and removed from the substrate, or some other removal may be made. Thus, the first self-assembled monolayer can be formed directly after selective etching of the metal gate, or after transfer to the additional chamber but prior to additional processing operations, without structurally requiring chemical removal or etching. Additional mask layer. Similarly, after selective deposition, it may not be necessary to etch cover material 620 (and possibly additional masking) to ensure selective formation of cover material 620 on the metal gate material. In this way, multiple operations used in conventional formations can be eliminated, which can significantly reduce the queue time (eg, several hours). In other embodiments, a slight depression may be performed after selective deposition to remove residual material from the interlayer dielectric 610, depending on the operation performed.

Embodiments may also utilize an inhibitor to selectively form cap material 620 on fill metal 615 without forming cap material 620 on inter-layer dielectric 610. For example, the sprayed inhibitor can be applied across the surface of the substrate and can be applied along the top surface of the substrate and can not penetrate into the recessed portion of the substrate. The inhibitor can be any number of materials, and the material can be characterized by a siloxane backbone (e.g., a decane) or a tetrafluoroethylene backbone (e.g., PTFE), as well as other oily or surfactant materials. Material may be applied across the surface of the substrate to cover the exposed portions of the interlayer dielectric 610. By using a spray or coating application, the material may not be applied to the recessed portion of the substrate and may not contact the fill metal 615. Subsequently, the capping material 620 can be formed, for example, by atomic layer deposition or other vapor deposition or physical deposition mechanisms.

The inhibitor material can prevent adhesion or adsorption of materials that can be normally formed or deposited on the filler metal 615. A cover material 620 is then formed and a remover can be applied to the substrate to remove the inhibitor material. The remover can be a wet etchant, a reactant or a surfactant cleaner, and the residual inhibitor material that exposes the underlying interlayer dielectric 610 can be removed. Thus, the inhibitor can be applied directly after selective etching, or after substrate transfer, but prior to other processing operations that affect the substrate. The use of an inhibitor may allow for the formation of a cap material in a defined area without the need for patterning and/or etching definition through subsequent blanket films. By removing the previous and subsequent patterning operations, the processing can further reduce the queue time of conventional processing.

The inhibitor may also be the product of a plasma application that can neutralize the surface of the substrate or render the surface of the substrate inert. For example, the modified plasma can be formed from one or more precursors, and can include an inert precursor. The plasma may be applied to the surface of the substrate while the top surface of the substrate may be altered and may not penetrate into the recessed portion of the substrate. For example, a nitrogen-containing precursor (which may be nitrogen) can be delivered to the plasma processing zone of the processing chamber that produces the plasma. The plasma effluent (which may include a nitrogen-containing plasma effluent) may be delivered to the substrate and a nitrided surface (which may include interlayer dielectric 610) may be formed along the exposed surface of the substrate along the top surface.

The plasma effluent may or may not flow within the recessed portion of the substrate, but may fill the pure or unreacted surface of the metal 615. Subsequently, the capping material 620 can be formed using one or more deposition techniques, which can include atomic layer deposition or other vapor or physical deposition. For example, the plasma effluent can be subsequently processed using atomic layer deposition techniques. After each cycle of deposition, the nitrogen-containing plasma can be reapplied to the surface region of the substrate (eg, on the interlayer dielectric 610). In this manner, the surface of the interlayer dielectric 610 can be passivated to prevent or limit the formation of the cap material 620 on the regions. Utilizing such plasma effluents on the non-recessed portions of the substrate may allow for the formation of the cap material in the defined regions without the need for patterning and/or etching definitions through subsequent blanket films. By removing the previous and subsequent patterning operations, the processing can further reduce the queue time of conventional processing.

Any of these techniques may selectively deposit or form a dielectric or insulating material on the metal-containing region relative to one or more non-metal, dielectric or insulating regions. The selectivity may be complete, i.e., the cover material is formed only on the fill metal 615 or the intermediate layer, and the cover material may be formed entirely on the interlayer dielectric region. In other embodiments, the selectivity may not be complete, and the ratio of deposition on the metal-containing material relative to the dielectric or insulating material may be greater than about 2:1. The selectivity may also be greater than or about 5:1, greater than or about 10:1, greater than or about 15:1, greater than or about 20:1, greater than or about 25:1, greater than or about 30:1, greater than or about 35. : 1. greater than or about 40:1, greater than or about 45:1, greater than or about 50:1, greater than or about 75:1, greater than or about 100:1, greater than or about 200:1, or more. The cover material can be formed to the aforementioned height, the thickness can be less than or about 50 nm, and can be less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, less than or about 5 nm, or less. Thus, a selectivity below 50:1 may be acceptable to completely deposit the cap material 620 while forming a limited amount of material or substantially no material formation on the interlayer dielectric material 610.

The deposition operation can be performed at any of the foregoing temperatures or pressures, and can be performed at temperatures greater than or about 50 ° C, and can be greater than or about 100 ° C, greater than or about 150 ° C, greater than or about 200 ° C, greater than or about Execution is carried out at 250 ° C, greater than or about 300 ° C, greater than or about 350 ° C, greater than or about 400 ° C, greater than or about 450 ° C, greater than or about 500 ° C or higher. For example, during an atomic layer deposition operation, a temperature greater than or about 100 °C can be used to activate the precursors to interact with one another as the material layers are formed.

Additionally, the present technology includes a technique for forming contact pads and/or self-aligned vias using selective etching and selective deposition. Similar to the techniques previously described, the process may not utilize active ion etching or associated operations of ashing or cleaning, which may damage fragile features and may increase the queue time. FIG. 7 illustrates a method 700 of forming a semiconductor structure in which a number of operations can be performed, for example, in the aforementioned chambers 200 and 400. Method 700 can include one or more operations prior to initiating the method, including front end processing, deposition, etching, grinding, cleaning, or any other operation that can be performed prior to the operation. The etching process, deposition process, and many materials from method 700 can be similar to those discussed above with respect to method 500, and any of the operations, materials, or parameters discussed above can be used or included in method 700, which will be discussed below.

The method can include a plurality of selectable operations shown in the figures, which may or may not be particularly associated with methods in accordance with the present techniques. For example, many operations are described in order to provide a broader range of structure formation, but are not critical to the technology, or can be performed by including alternative methods utilizing any of the selective deposition techniques described above. Method 700 describes the operations illustrated schematically in Figures 8A-8E, which are described in conjunction with the operation of method 700. It should be understood that FIG. 8 is only a partial schematic view, and the substrate may include any number of transistor segments having the pattern shown in the figures.

Method 700 can involve operations performed on a substrate having a plurality of exposed regions, such as on a substrate that includes regions that are further developed to create a self-aligned via structure. As shown in FIG. 8A, a portion of the processed substrate 800 including the etch stop layer 805, the interlayer dielectric 810, and the fill metal 815 is illustrated. Filler metal 815 can include lines 815b and 815c, which can be metal wiring or interconnects within a single layer. The fill metal may also include a material (eg, fill metal 815a) in the via vias (which may be interconnects extending between structural layers on the substrate). Such materials may have been formed in previous operations and may have been polished to a particular height while exposing the fill metal 815 and interlayer dielectric 810 on the top surface of the substrate. The operation of method 700 can be performed to limit or eliminate masking operations, to limit or eliminate RIE processing including ashing and cleaning, and to reduce processing time for providing cover material during production of self-aligned via structures. Treatment may also provide additional protection to fill metal 815b and fill metal 815c.

The method 700 may initially include the step of depositing the first dielectric material 820 in operation 705 as shown in FIG. 8A. The first dielectric material can be deposited in a chamber similar to the chamber 400 previously described. As shown in FIG. 8A, a first dielectric material 820 can be deposited on the interlayer dielectric 810. The deposition operation can be selective deposition, wherein a first dielectric material is preferably formed on the interlayer dielectric 810 with respect to the exposed fill metal 815.

Subsequent selective deposition of cover material 825 can be performed in operation 710 as shown in FIG. 8B. Cover material 825 may be selectively deposited on fill metal 615 relative to first dielectric material 820, while first dielectric material 820 may cover interlayer dielectric 810. In some embodiments, portions of interlayer dielectric 810 may also be exposed, while cover material deposition may also be selectively performed for those regions. The selective deposition can be similar to operation 525 previously described, but can be modified in accordance with the composition of the first dielectric material 820. As shown in FIG. 8C, at optional operation 715, cap material 825 may be selectively removed from fill metal 815b and 815c, which may be metal wires maintained within a single level of the structure, but any region Segments can be uncovered. In some embodiments, the cover material 825 can be maintained on the fill metal 815a, which can be an interconnect extending between the layers of the structure. Removal may be similar to removal operation 530 and may include any of the operations or precursors discussed.

As shown in FIG. 8D, at operation 720, method 700 can also include the step of selectively depositing a third dielectric material 830 on exposed fill metal 815b and 815c. Selective deposition may preferably deposit a third dielectric material 830 on the fill metal 815 and may produce minimal or no deposition on the first dielectric material 820 or cap material 825 that may cover the fill metal 815a. Deposition operation 720 can be similar to operation 535 previously described. Subsequently, as shown in FIG. 8E, in optional operation 725, contact platform 835 can be formed. Operation 725 can be similar to operation 540 previously discussed, and can include any of the techniques previously described.

Various materials may be utilized in the process, and may include any of the materials previously described, while etching and deposition may be selective for multiple components. Thus, the present technology may not be limited to a single set of materials. For example, fill metal 815 can be several conductive materials used in semiconductor processing. Filler metal 815 can be or can include copper, cobalt, tungsten, or any other conductive metal that can act as a fill or interconnect metal. Any of the first dielectric material, the second dielectric material (which may be the interlayer dielectric 810), the third dielectric material, and the cover material may be one or more of the previously mentioned insulating materials. In an embodiment, each material can be similar or different from any other layer.

Similarly, while selective etching and deposition operations may be adjusted depending on the materials used with respect to other materials formed or removed, other insulating materials may be used in other embodiments. The first dielectric material 820 can include additional insulating material and can include a metal oxide or nitride material. For example, the first dielectric material 820 can be or include yttrium oxide, lanthanum lanthanum oxide, tantalum nitride, tungsten oxide, aluminum oxide, or can be selectively deposited on the interlayer dielectric 810 relative to the selected filler metal material. Other materials on it. In an embodiment, the interlayer dielectric may be yttria and may be any other insulating material mentioned. In an embodiment, the first dielectric material 820 and the interlayer dielectric 810 may be the same material, but may be different from each other in other embodiments. Cover material 825 may also include a metal oxide or nitride material. For example, the capping material 825 can be or can include tantalum nitride, tantalum carbonitride, tantalum oxide, tungsten oxide, aluminum oxide, or can be selectively deposited on copper, cobalt or tungsten relative to the first dielectric material 820. Other materials, while the potential interlayer dielectric 810 should remain exposed after deposition of the first dielectric material 820. The third dielectric material 830 can be or include tantalum nitride, tantalum carbon oxide, tantalum oxide, tungsten oxide, aluminum oxide, or can be selectively deposited in copper, cobalt, or with respect to the first dielectric material 820 and the capping material 825. Other materials on tungsten.

In some embodiments, the first dielectric material 820, the cover material 825, and the third dielectric material 830 can be different from each other. Because one or more may be exposed during each deposition, different materials may be used to facilitate deposition relative to other materials, but any of the three materials may be similar in additional embodiments. Although different materials, each of the first dielectric material 820, the cover material, and the third dielectric material 830 may be selected from the group consisting of a carbonaceous material, a nitrogen-containing material, and an oxygen-containing material. One or more materials, and in embodiments, any of the three materials may be any of the previously mentioned materials, or any additional dielectric material that may be selectively deposited relative to another dielectric material. .

Method 700 can be performed without any RIE processing or associated processing. Similarly, the method can reduce the queue time by removing many of the patterning and removal operations that can be performed before, during, or after the formation in a conventional process. Additionally, the formation of the third dielectric material 830 can protect the fill metal 815b and 815c, while the short circuit can be reduced during subsequent contact processing with the interconnect material or fill metal 815a. The deposition or etching process can include any of the aspects of method 500 described above, and includes any of the operations described at the selectivity. Moreover, the deposition process can include any of the processes previously described and can include operations at any of the options described. By utilizing the present technology, manufacturing can be performed with more selective formation and removal than conventional techniques, and can reduce the queue time by several hours compared to conventional processing.

As mentioned, any of the selective deposition techniques previously described can be used in multiple deposition operations, and can include any of the previously mentioned preferences for similar or other materials. Additional selective deposition techniques may also be used, which may include an alternative mechanism for selectively depositing dielectric materials. For example, although cover material 825 and third dielectric material 830 are deposited on a metal (eg, fill metal 815), first dielectric material 820 can be deposited on another dielectric material (eg, interlayer dielectric) Quality 810). For example, a self-assembled monolayer can be formed as previously described. Any previous capping group may be formed on the interlayer dielectric to facilitate formation of the first dielectric material 820 and maintain the fill metal 815 without the first dielectric material or have a separate deposition on the fill metal 815 Self-assembling a single layer to repel at least one of the precursors for deposition. Depending on the material used for the particular first dielectric material 820, the self-assembled monolayer can be adjusted toward the material. As previously mentioned, water can be one of the precursors, and as previously described, the self-assembled monolayer can be structured (eg, including a hydroxyl-terminated material on the interlayer dielectric relative to the filler metal) Promote formation on the material). In addition, the nitrogen-containing material can serve as one of the self-assembled monolayers on the material used for deposition (eg, one of the capping portions of the monolayer), while allowing for attraction to form the previously described material. Specific precursor of one or more.

Due to the structure of the metal, the fill metal 815 can also be etched or passivated to reduce activity relative to the dielectric material, while allowing for increased deposition on the dielectric material (eg, interlayer dielectric) relative to the fill metal 815. Filler metal passivation can include exposing the fill metal 815 to a germanium substituted or halogen substituted material, which can limit the deposition of the dielectric material. For example, the oxidation of the filler metal can utilize an oxygen-containing material or a halogen-containing material, which can allow for preferential deposition on the dielectric material. Once oxidized (e.g., by exposure to an oxygen-containing material), atomic layer deposition can be performed similar to that described, wherein one of the precursors can include an oxygen-containing material, which may not interact with the oxidized metal. In this manner, as an example, the first dielectric material can be or include ruthenium oxide, which can be selectively deposited on the interlayer dielectric 810 relative to the fill metal 815.

The selectivity may be complete, that is, the first dielectric material is formed only on the interlayer dielectric 810 and may not be formed entirely on the fill metal 815. In other embodiments, the selectivity may not be complete, and the ratio of deposition on the dielectric or insulating material to the metal-containing material may be greater than about 2:1. The selectivity may also be greater than or about 5:1, greater than or about 10:1, greater than or about 15:1, greater than or about 20:1, greater than or about 25:1, greater than or about 30:1, greater than or about 35. : 1. greater than or about 40:1, greater than or about 45:1, greater than or about 50:1, greater than or about 75:1, greater than or about 100:1, greater than or about 200:1, or more. Any dielectric material can be formed to the aforementioned heights, can be less than or about 50 nm thick, and can be less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, less than or about 5 nm, or less. Thus, a selectivity below 50:1 may be acceptable to completely deposit the first dielectric material 820 while forming a limited amount of material on the fill metal 815 or substantially no material formation.

Additionally, the present technology includes a technique for forming contact pads and/or self-aligned vias using selective etching and selective deposition. Similar to the techniques previously described, the process may not utilize active ion etching or associated operations of ashing or cleaning, which may damage fragile features and may increase the queue time. FIG. 9 illustrates a method 900 of forming a semiconductor structure in which a number of operations can be performed, for example, in the aforementioned chambers 200 and 400. Method 900 can include one or more operations prior to initiating the method, including front end processing, deposition, etching, grinding, cleaning, or any other operation that can be performed prior to the operation. The etching process, deposition process, and many materials from method 900 can be similar to those discussed above with respect to method 500 or method 700, and any of the operations, materials, or parameters discussed above can be used or included in method 900, which will be discussed below. .

The method can include a plurality of selectable operations shown in the figures, which may or may not be particularly associated with methods in accordance with the present techniques. For example, many operations are described in order to provide a broader range of structure formation, but are not critical to the technology, or can be performed by including alternative methods utilizing any of the selective deposition techniques described above. Method 900 describes the operations illustrated schematically in Figures 10A through 10F, which are described in connection with the operation of method 900. It should be understood that FIG. 10 illustrates only a partial schematic view, and the substrate may include any number of transistor segments having the pattern shown in the figures.

Method 900 can involve operations performed on a substrate having a plurality of exposed regions, such as on a substrate that includes regions that are further developed to create a self-aligned via structure. As shown in FIG. 10A, a portion of the processed substrate 1000 including the etch stop layer 1005, the interlayer dielectric 1010, and the fill metal 1015 is illustrated. Filler metal 1015 can include lines 1015b and 1015c, and lines 1015b and 1015c can be metal lines within a single layer. The fill metal may also include a material (eg, fill metal 1015a) in the via via (which may be an interconnect extending between the structural layers on the substrate). Such materials may have been formed in previous operations and may have been polished to a particular height while exposing the fill metal 1015 and interlayer dielectric 1010 on the top surface of the substrate. The operations of method 900 can be performed to limit or eliminate masking operations, limit or eliminate RIE processing including ashing and cleaning, and can reduce the processing time required to provide cover material during production of self-aligned via structures. The treatment may also provide additional protection to the filler metal 1015b and the filler metal 1015c.

The method 900 may initially include the step of depositing the first metal 1020 in operation 905 as shown in FIG. 10A. The first metal can be deposited in a chamber similar to the chamber 400 previously described. As shown in FIG. 10A, the first metal 1020 may be deposited on the filler metal 1015. The deposition operation can be selective deposition, wherein a first metal is preferably formed on the exposed fill metal 1015 with respect to the interlayer dielectric 1010. Subsequent metal material formation can promote separation above the interlayer dielectric 1010. For example, in an embodiment, the first metal 1020 can be formed to a height less than 20 nm, and the formed height can be less than or about 15 nm, less than or about 10 nm, less than or about 8 nm, less than or about 6 nm, less than or about 5 nm, less than or about 4 nm, less than or about 3 nm, less than or about 2 nm, less than or about 1 nm, or less. Moreover, the height formed by the first metal 1020 can be within any of these ranges, or within a small range contained within any of the ranges described herein.

Subsequent selective deposition of the cap material 1025 can be performed in operation 910 as shown in FIG. 10B. The cover material 1025 can be selectively deposited as a pillar on the first metal 1020 with respect to the interlayer dielectric 1010. The selective deposition can be similar to operation 525 previously described, but can be modified in accordance with the composition of interlayer dielectric 1010. As shown in FIG. 10C, at optional operation 915, an additional amount of interlayer dielectric 1010 can be deposited to extend the height of the interlayer dielectric to the level of cover material 1025. In some embodiments, an additional blanket coating can be applied to the structure followed by a polishing operation to expose the cover material 1025.

As shown in FIG. 10D, at optional operation 920, cover material 1025 can be selectively removed from metal fills 1015b and 1015c, which can be metal lines maintained within a single level of the structure, but Any section can be uncovered. In some embodiments, the cover material 1025 can be maintained on the first metal 1020 and the fill metal 1015a, and the first metal 1020 and the fill metal 1015a can be interconnects that extend between the layers of the structure. Removal may be similar to removal operation 530 and may include any of the operations or precursors discussed. In an embodiment, additional removal of the first metal 1020 can be performed to remove the first metal from the fill metal 1015b and 1015c.

As shown in FIG. 10E, at operation 925, method 900 can also include the step of selectively depositing second dielectric material 1030 on exposed fill metal 1015b and 1015c. Selective deposition may preferably deposit a second dielectric material 1030 on the fill metal 1015 and may produce minimal or no deposition on the interlayer dielectric 1010 or cover material 1025 that may cover the fill metal 1015a. Deposition operation 925 can be similar to operation 535 previously described. Subsequently, as shown in FIG. 10F, in an optional operation 930, a contact platform 1035 can be formed. Operation 930 can be similar to operation 540 previously discussed and can include any of the techniques previously described.

Various materials may be utilized in the process, and may include any of the materials previously described, while etching and deposition may be selective for multiple components. Thus, the present technology may not be limited to a single set of materials. For example, filler metal 1015 can be several conductive materials used in semiconductor processing. Filler metal 1015 can be or can include copper, cobalt, tungsten, or any other conductive metal that can act as a fill or interconnect metal. Additionally, the first metal 1020 can be any of the same materials or can be different than the filler metal 1015. For example, in one embodiment, the filler metal 1015 can be copper or cobalt, and the first metal 1020 can be tungsten. Any of the second dielectric material or the cover material may be one or more of the previously mentioned insulating materials. In an embodiment, each material may be similar or different from the other layers.

Similarly, while selective etching and deposition operations may be adjusted depending on the materials used with respect to other materials formed or removed, other insulating materials may be used in other embodiments. The cover material 1025 can be or include a metal oxide or nitride material. For example, the capping material 1025 can be or include tantalum nitride, tantalum carbonitride, tantalum oxide, tungsten oxide, aluminum oxide, or can be selectively deposited on copper, cobalt or tungsten relative to the interlayer dielectric 1010. other materials. The second dielectric material 1030 may be or include tantalum nitride, tantalum carbon oxide, tantalum oxide, tungsten oxide, aluminum oxide, or may be selectively deposited on copper, cobalt or with respect to the interlayer dielectric 1010 and the capping material 1025. Other materials on tungsten.

In some embodiments, the cover material 1025 and the second dielectric material 1030 can be different from each other. Because one or more may be exposed during each deposition, different materials may be used to facilitate deposition relative to other materials, but in additional embodiments the two materials may be similar. Although different materials, each of the cover material 1025 and the second dielectric material 1030 may be one or more materials selected from the group consisting of carbonaceous materials, nitrogen-containing materials, and oxygen-containing materials. In embodiments, any of the materials may be any of the materials previously mentioned, or any additional dielectric material that may be selectively deposited relative to another dielectric material.

Method 900 can be performed without any RIE processing or associated processing. Similarly, the method can reduce the queue time by removing many of the patterning and removal operations that can be performed before, during, or after the formation in a conventional process. Additionally, the formation of the second dielectric material 1030 can protect the fill metal 1015b and 1015c, while the short circuit can be reduced during subsequent contact processing with the interconnect material or fill metal 1015a. The deposition or etching process can include any of the methods 500 or 700 described above, and includes any of the operations described at the selectivity. Moreover, the deposition process can include any of the processes previously described and can include operations at any of the options described. By utilizing the present technology, manufacturing can be performed with more selective formation and removal than conventional techniques, and can reduce the queue time by several hours compared to conventional processing.

Again, any of the selective deposition techniques previously described can be used in multiple deposition operations, and can include any of the previously mentioned preferences for similar or other materials. Additional selective deposition techniques may also be used, which may include an alternative mechanism for selectively depositing metallic materials. For example, the first metal 1020 can be deposited on the fill metal 1015 and can utilize a deposition process that is specific to metal to metal deposition. Any of the deposition techniques previously described may also be utilized, including the formation of the self-assembled monolayers previously described. Furthermore, the passivation previously described can be performed. For example, interlayer dielectric 1010 can include ruthenium oxide, for example, can be processed to tailor the end group to ruthenium, hydrogen, or halogen. This may allow preferential deposition of the metallic material on the filler metal 1015. In other embodiments, the nitrogen-containing precursor can be used in one or both of the atomic layer deposition processes, which can be preferentially deposited on the metal surface relative to the yttrium oxide surface (eg, can be used for interlayer dielectric 1010) .

The selectivity may be complete, that is, the first metal is formed only on the fill metal 1015 and may not be formed entirely on the interlayer dielectric 1010. In other embodiments, the selectivity may not be complete, and the ratio of deposition on the metal-containing material relative to the dielectric or insulating material may be greater than about 2:1. The selectivity may also be greater than or about 5:1, greater than or about 10:1, greater than or about 15:1, greater than or about 20:1, greater than or about 25:1, greater than or about 30:1, greater than or about 35. : 1. greater than or about 40:1, greater than or about 45:1, greater than or about 50:1, greater than or about 75:1, greater than or about 100:1, greater than or about 200:1, or more. The first metal may be formed to a height as described above, may be less than or about 50 nm thick, and may be less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, less than or about 5 nm, less than or about 3 nm, less than Or about 1 nm, or less. Thus, a selectivity below 50:1 may be acceptable to completely deposit the first metal 1020 while forming a limited amount of material or substantially no material formation on the interlayer dielectric 1010. By utilizing the present technology, manufacturing can be performed with more selective formation and removal than conventional techniques, and can reduce the queue time by several hours compared to conventional processing.

In the previous description, numerous details have been set forth in order to provide an understanding of various embodiments of the present invention. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without some of the details.

The invention has been described in terms of a number of modifications, alternative constructions and equivalents. Moreover, many of the known processes and elements are not described in order to avoid unnecessarily obscuring the present technology. Therefore, the above description should not be taken as limiting the scope of the technology.

When a range of values is provided, it is to be understood that unless the context clearly dictates otherwise, each intermediate value between the upper and lower limits of the range is specifically disclosed. Any narrower range between any stated or un recited intermediate value in the range and any other stated or intermediate value in the range. The upper and lower limits of such smaller ranges may be independently included in the range or excluded, and each of the smaller ranges including one or both of the upper and lower limits , depending on the limits specifically excluded in the range. Where the stated range includes one or both of the limitations, the scope of one or both of the limitations included.

The singular forms "a", "an" and "the" Thus, for example, reference to "a" or "an" or "an" or "an"

In addition, the words "including", "including", "including", "including", "including" and "including" are used in the specification and the following claims. Or the existence of an operation, but does not exclude the presence or addition of one or more other features, integers, components, operations, acts or groups.

10‧‧‧Loading lock chamber

15‧‧‧Isolation valve

20‧‧‧Processing chamber

30‧‧‧ gas distribution board

60‧‧‧Substrate

61‧‧‧ first surface

65‧‧‧ Shuttle

70‧‧‧ Track

90‧‧‧radiation heat source

100‧‧‧Processing system

102‧‧‧ Front open combined wafer cassette

104‧‧‧Machine arm

106‧‧‧holding area

108a‧‧‧Processing chamber

108b‧‧‧Processing chamber

108c‧‧‧Processing chamber

108d‧‧‧Processing chamber

108e‧‧‧Processing chamber

108f‧‧‧Processing chamber

109a‧‧‧Series section

109b‧‧‧Series section

109c‧‧‧Series section

110‧‧‧Second robotic arm

200‧‧‧ chamber

201‧‧‧RPS unit

203‧‧‧Cooling plate

205‧‧‧ gas inlet assembly

210‧‧‧Fluid Supply System

214‧‧‧Upper board

215‧‧‧First plasma area

216‧‧‧ Lower board

217‧‧‧ panel

218‧‧‧ volume

219‧‧‧First fluid passage

220‧‧‧Insulation ring

221‧‧‧Second fluid channel

223‧‧‧Ion suppressor

225‧‧‧Sprinkler

233‧‧‧Substrate processing area

240‧‧‧Power supply

253‧‧‧Detailed view

255‧‧‧Substrate

258‧‧‧ gas supply area

259‧‧‧ pores

265‧‧‧ pedestal

325‧‧‧Sprinkler

365‧‧‧through hole

375‧‧‧Small holes

400‧‧‧ chamber

420‧‧‧Syringe

425‧‧‧ gas 埠

430‧‧‧Syringe

435‧‧‧ gas 埠

440‧‧‧Syringe

445‧‧‧ gas 埠

450‧‧‧ pumping system

455‧‧‧vacuum

460‧‧‧ partition

498‧‧‧ arrow

500‧‧‧ method

505‧‧‧ operation

510‧‧‧ operation

515‧‧‧ operation

520‧‧‧ operation

525‧‧‧ operation

530‧‧‧ operation

535‧‧‧ operation

540‧‧‧ operation

600‧‧‧Substrate

605‧‧‧etch stop layer

610‧‧‧ interlayer dielectric

615a‧‧‧Filling metal

615b‧‧‧Filling metal

615c‧‧‧Filling metal

620‧‧‧ Cover material

625‧‧‧Second dielectric material

630‧‧‧Contact platform

700‧‧‧ method

705‧‧‧ operation

710‧‧‧ operation

715‧‧‧ operation

720‧‧‧ operation

725‧‧‧ operation

800‧‧‧Substrate

805‧‧‧etch stop layer

810‧‧‧Interlayer dielectric

815a‧‧‧Filling metal

815b‧‧‧Filling metal

815c‧‧‧Filling metal

820‧‧‧First dielectric material

825‧‧‧ Cover material

830‧‧‧ Third dielectric material

835‧‧‧Contact platform

900‧‧‧ method

905‧‧‧ operation

910‧‧‧ operation

915‧‧‧ operation

920‧‧‧ operations

925‧‧‧ operation

930‧‧‧ operation

1000‧‧‧Substrate

1005‧‧‧etch stop layer

1010‧‧‧Interlayer dielectric

1015a‧‧‧Filling metal

1015b‧‧‧Filling metal

1015c‧‧‧Filling metal

1020‧‧‧First metal

1025‧‧‧Cover materials

1030‧‧‧Second dielectric material

1035‧‧‧Contact platform

A further understanding of the nature and advantages of the disclosed technology can be realized by reference to the description and the accompanying drawings.

FIG. 1 illustrates a top plan view of an exemplary processing system in accordance with an embodiment of the present technology.

2A illustrates a schematic cross-sectional view of an exemplary processing chamber in accordance with an embodiment of the present technology.

2B illustrates a detailed view of an exemplary panel in accordance with an embodiment of the present technology.

FIG. 3 illustrates a bottom plan view of an exemplary showerhead in accordance with an embodiment of the present technology.

FIG. 4 illustrates a schematic cross-sectional view of an exemplary processing chamber in accordance with an embodiment of the present technology.

FIG. 5 illustrates selected operations in a method of forming a semiconductor structure in accordance with an embodiment of the present technology.

6A through 6E illustrate schematic cross-sectional views of an exemplary substrate in accordance with an embodiment of the present technology.

FIG. 7 illustrates selected operations in a method of forming a semiconductor structure in accordance with an embodiment of the present technology.

8A through 8E illustrate schematic cross-sectional views of an exemplary substrate in accordance with an embodiment of the present technology.

FIG. 9 illustrates selected operations in a method of forming a semiconductor structure in accordance with an embodiment of the present technology.

10A through 10F illustrate schematic cross-sectional views of an exemplary substrate in accordance with an embodiment of the present technology.

Several of the figures are included as schematics. It should be understood that the drawings are for illustrative purposes only and should not be construed as a In addition, the drawings are provided as a schematic diagram to aid understanding, and may not include all aspects or information as compared to the actual representation, and may include exaggerated materials for illustrative purposes.

Similar components and/or features may have the same component symbols in the accompanying drawings. Furthermore, various components of the same type may be distinguished by the use of letters after the component symbols to distinguish similar components. If only the foremost component symbol is used in the specification, the description applies to any similar component having the same topmost component symbol, regardless of the letter.

Domestic deposit information (please note according to the order of the depository, date, number)

Foreign deposit information (please note in the order of country, organization, date, number)

Claims (20)

A method of forming a semiconductor structure, the method comprising the steps of: depositing a first dielectric material on a semiconductor substrate, wherein the first dielectric material is selectively deposited in a second dielectric with respect to an exposed region of the filler metal And subsequently depositing a capping material on the filler metal, wherein the capping material is selectively deposited on the filler metal relative to the exposed regions of the first dielectric material. A method of forming a semiconductor structure according to claim 1, wherein the filler metal comprises copper or cobalt. A method of forming a semiconductor structure according to claim 1, wherein the first dielectric material comprises tantalum carbonitride, tantalum nitride, tungsten oxide or aluminum oxide, and wherein the second dielectric material comprises hafnium oxide. A method of forming a semiconductor structure according to claim 1, wherein the capping material comprises a metal nitride or a metal oxide. A method of forming a semiconductor structure as described in claim 1, wherein the method is performed without performing a reactive ion etching operation. A method of forming a semiconductor structure according to claim 1 wherein the first dielectric material deposition is performed using a selectivity of the second dielectric material relative to the fill metal of greater than or about 2:1. A method of forming a semiconductor structure according to claim 1, wherein the deposition of the cap material is performed using a selectivity of the filler metal relative to the first dielectric material that is greater than or about 2:1. The method of forming a semiconductor structure according to claim 1, further comprising the step of depositing a third dielectric material on the exposed region of the filler metal, wherein the third dielectric material is opposite to the first dielectric material The second dielectric material is selectively deposited on the fill metal. A method of forming a semiconductor structure, the method comprising the steps of: forming a plasma of a fluorine-containing precursor in a distal plasma region of a processing chamber; contacting a semiconductor substrate with the effluent of the plasma The semiconductor substrate is housed in a processing region of the processing chamber; a filler metal is selectively etched under a height of the exposed region of the first dielectric material on the semiconductor substrate; and subsequently the filler metal A capping material is deposited thereon, wherein the capping material is selectively deposited on the filler metal relative to the exposed regions of the first dielectric material. The method of forming a semiconductor structure according to claim 9, further comprising the step of depositing a second dielectric material, wherein the second dielectric material is selectively deposited with respect to the cover material and the first dielectric material The filler metal is on. A method of forming a semiconductor structure according to claim 10, wherein the cover material comprises a material different from the second dielectric material. A method of forming a semiconductor structure according to claim 11, wherein the cap material is selected from the group consisting of a carbonaceous material, a nitrogen-containing material, and an oxygen-containing material. The method of forming a semiconductor structure according to claim 12, wherein the second dielectric material is selected from the group consisting of a carbonaceous material, a nitrogen-containing material, and an oxygen-containing material, and wherein the second dielectric layer The electrical material is different from the cover material. A method of forming a semiconductor structure according to claim 13, wherein the oxygen-containing material comprises cerium oxide, tungsten oxide or aluminum oxide. A method of forming a semiconductor structure as recited in claim 9, wherein the etching step is performed in a first processing chamber and the depositing step is performed in a second processing chamber. The method of forming a semiconductor structure according to claim 9, further comprising the step of transferring the semiconductor substrate from the first processing chamber to the second processing chamber, and wherein the transferring step is performed without breaking the vacuum. Execute in case. A method of forming a semiconductor structure as recited in claim 9, wherein the etching step is performed using a selectivity of the fill metal relative to the first dielectric material that is greater than or about 10:1. A method of forming a semiconductor structure as recited in claim 9, wherein the depositing is performed using a selectivity of the fill metal relative to the first dielectric material that is greater than or about 2:1. A method of forming a semiconductor structure, the method comprising the steps of: depositing a first metal on a fill metal, wherein the first metal is selectively deposited on the fill metal with respect to an exposed region of a first dielectric material; A capping material is then deposited over the first metal, wherein the capping material is selectively deposited on the first metal relative to the exposed regions of the first dielectric material. The method of forming a semiconductor structure according to claim 9, further comprising the steps of: depositing a second dielectric material, wherein the second dielectric material is selectively deposited on the first metal relative to the first dielectric material on.