TW201903885A - Selective formation of silicon-containing spacer - Google Patents

Abstract

Processing methods may be performed to form semiconductor structures that may include nanowire structures. The methods may include forming a plasma of a fluorine-containing precursor in a remote plasma region of a processing chamber. The methods may include contacting a semiconductor substrate with effluents of the plasma, and the semiconductor substrate may be housed in a processing region of the processing chamber. The methods may include laterally recessing a silicon-containing material selectively from the semiconductor substrate. The methods may further include subsequently depositing a spacer material adjacent the silicon-containing material. The spacer material may be selectively deposited on the silicon-containing material relative to exposed regions of a gate formation and a nanowire material exposed on the substrate.

Description

Selective formation of germanium-containing spacers

This technology relates to semiconductor systems, processing, and equipment. More specifically, the present technology relates to systems and methods for selectively etching and selectively depositing layers of materials on a semiconductor device.

It is possible to fabricate an integrated circuit by processing a layer of intricately patterned material on the surface of the substrate. Producing a patterned material on a substrate requires a control method for removing the exposed material. Chemical etching is used for a variety of purposes, including transferring a pattern in a photoresist into a layer underneath, thinning a layer, or thinning the lateral dimension of a feature that has been rendered on a surface. It is generally desirable to have an etching process that etches one material faster than the other to facilitate, for example, pattern transfer processing or separate material removal. This etching process is said to be selective for the first material. Due to the variety of materials, circuits, and processes, etching processes have been developed that are selective for a variety of materials. However, a blanket coating or conformal filling is typically used to continue the deposition process across the substrate.

As device sizes continue to shrink in next-generation devices, selectivity can play a greater role when the material formed in a particular layer is only a few nanometers (especially when the material is critical in the formation of the transistor). Many different etch processing options have been developed between various materials, but standard selectivity may no longer be applicable to current and future device sizes. Moreover, based on the number of shielding, forming, and removing operations required to form and protect the various critical dimensions of the features across the device, the processing time continues to increase while patterning and formation is performed elsewhere on the substrate.

Therefore, there is a need for a system and method that can be used to produce high quality devices and structural improvements. This technology addresses these and other needs.

A processing method can be performed to form a semiconductor structure that can include a nanowire structure. The method can include the step of forming a plasma of a fluorine-containing precursor in a distal plasma region of the processing chamber. The method can include the steps of contacting the semiconductor substrate with the effluent of the plasma, and the semiconductor substrate can be housed in the processing region of the processing chamber. The method can include the step of selectively recessing the germanium-containing material from the semiconductor substrate. The method can further include the step of subsequently depositing a spacer material adjacent to the germanium containing material. The spacer material can be selectively deposited on the germanium containing material relative to exposed regions of the gate formation and nanowire material exposed on the substrate.

In some embodiments, the etching can be performed in the first processing chamber and the deposition can be performed in the second processing chamber. The method can include the steps of transferring the semiconductor substrate from the first processing chamber to the second processing chamber, and the transferring can be performed without breaking the vacuum. The cerium-containing material may include cerium telluride. The gate formation may comprise an exposed dielectric material and the nanowire material may comprise germanium. The spacer material may comprise a metal nitride or a metal oxide. The method can be performed without performing a reactive ion etching operation. Etching can be performed using a germanium-containing material with a selectivity greater than or about 10: 1 relative to the gate formation and nanowire material. Deposition can be performed using a cerium-containing material with a selectivity greater than or about 2: 1 relative to the gate formation and nanowire material. The step of selectively depositing the spacer material can include the step of forming a self-assembled monolayer on the germanium-containing material. The self-assembled monolayer can interact with one or more precursors used to form the spacer material.

The present technology may also include a method of forming a semiconductor substrate. The method can include the step of laterally etching the first ruthenium-containing material relative to the second ruthenium-containing material. The first ruthenium-containing material and the second ruthenium-containing material may be disposed perpendicular to each other, and the first ruthenium-containing material may be vertically positioned between the two regions of the second ruthenium-containing material. The method can include the step of forming a spacer material in a recess defined by lateral etching between two regions of the second bismuth-containing material. The method can also include the step of selectively recessing the spacer material to separate the individual spacers.

In some embodiments, the second cerium-containing material comprises cerium. The spacer material may be selected from the group consisting of a carbonaceous material, a nitrogen-containing material, and an oxygen-containing material. The first bismuth-containing material may be partially recessed from both sides of the gate formation. The first cerium-containing material may include cerium telluride. The etching can be performed in the first processing chamber and the deposition can be performed in the second processing chamber. The method can also include the steps of transferring the semiconductor substrate from the first processing chamber to the second processing chamber, and the transferring can be performed without breaking the vacuum. The method can be performed without performing a reactive ion etching operation. Etching can be performed using a selectivity of the first cerium-containing material relative to the second cerium-containing material that is greater than or about 10:1. Deposition may be performed using a selectivity of the first rhodium-containing material that is greater than or about 2:1 relative to the second rhodium-containing material.

Such techniques can provide many benefits over conventional systems and techniques. For example, processing can protect critical dimensions and provide improved selectivity by utilizing techniques that do not include reactive ion etching. In addition, by performing selective operations, fewer masking and removal operations can be performed, which can significantly reduce manufacturing queue time. These and other embodiments, as well as many of its advantages and features, are described in more detail in conjunction with the following description and accompanying drawings.

The techniques of the present invention include systems and components for semiconductor processing of small pitch features. In conventional gates and other transistor structures, the material on the substrate can be formed and etched alongside structures having similar or different materials to be maintained. For example, because the cap layer and spacers may be formed of similar materials (eg, tantalum nitride), the etching process used to remove these layers may not provide sufficient selectivity relative to other key features. During various recess processes, the size of multiple critical dimensions may cause load effects, while etching exceeds the expected availability of materials. For example, conventional processing can include a mask layer followed by a reactive ion etching ("RIE") process that allows the structure of the gap-fill layer to be opened. Although the RIE etch is a relatively anisotropic process, the RIE etch may still have selectivity for sidewall loss. Although it may be considered to budget for this loss during formation (eg, with over-formation of materials), because the regions within the etched structure have different sizes, the calculation of the amount of loss for one region may not be suitable for larger The amount of loss in the area. Thus, although a 5 nm loss may occur in one section of the budget, a loss of a larger section of 6-7 nm may still occur, resulting in a mismatch during manufacturing that may be prolonged during subsequent operations.

In addition, the RIE process produces etch byproducts or polymer residues (usually removed by ashing and wet etching processes). The ashing process affects the carbonaceous material, so if the material recessed by the RIE itself includes carbon, the ashing process may remove carbon from the material being maintained. In addition, wet etching often over-etches the sidewall protection layer beyond critical dimensions (which causes problems with the formation and spacing of adjacent transistor layers) and further etches low-k nitride spacers and interlayer dielectric oxide. The removal of the metal material and dielectric is typically performed using an anisotropic etch, which may further reduce the exposed areas of the cap material and spacer material in other regions unless an additional shield or protective layer is formed. Since the selectivity of such RIE removal may be in the range of 10:1, the amount of shielding required may be large.

In conventional techniques utilizing the conformal development of blanket coatings or materials across materials of all exposed areas on a semiconductor substrate, deposition of both the masking material and other layers of material can be performed. These types of deposition may require further patterning and removal operations, which can significantly increase the grid time of device fabrication. Between the additional operations and defects of the RIE removal and the various operations used in conventional deposition, the stacking time of the individual device layers may increase by several hours.

The present technology overcomes these problems by modifying the processing for removal and formation. These processes can be used to etch with higher selectivity than conventional RIEs by utilizing a selective etch process performed in a particular device, which may allow for additional patterning operations that may not previously be possible, and may be critical Feature sizes provide extra protection. In addition, reduced shielding, patterning, and removal operations can be utilized in structural formation by performing selective deposition operations in specific equipment. These processes can save hours and can protect the deposited material from RIE removal to produce an improved structure compared to conventional processing using RIE and standard deposition.

While the remainder of the disclosure will routinely identify particular etching and deposition processes utilizing the disclosed techniques, it should be understood that the systems and methods are equally applicable to various other etching, deposition, and cleaning processes that may occur in the described chambers. . Therefore, the technique should not be considered limited to the etching and deposition processes that can be used only. The present disclosure will discuss one possible system and chamber that can be used with the present technology to perform certain removal and deposition operations prior to the described operations of the exemplary processing sequences in accordance with the present technology.

FIG. 1 illustrates a top plan view of one embodiment of a processing system 100 for depositing, etching, baking, and curing chambers in accordance with an embodiment. In the drawings, a pair of front open combined wafer cassettes (FOUPs) 102 are supplied with substrates of various sizes, which are received by robotic arms 104 and placed in substrate processing chambers located in series sections 109a-c. Prior to one of the chambers 108a-f, it is placed into the low pressure holding area 106. The second robotic arm 110 can be used to transport substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and back. In addition to cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), wet etching, pre-cleaning, degassing, orientation, and other substrate processing, Each of the substrate processing chambers 108a-f can be provided to perform a number of substrate processing operations including dry etching processes and selective deposition as described herein.

The substrate processing chambers 108a-f can include one or more system components for depositing, annealing, curing, and/or etching a dielectric film on a substrate wafer. In one configuration, two pairs of processing chambers (eg, 108c-d and 108e-f) can be used to deposit a dielectric material or metal-containing material on the substrate, while a third pair of processing chambers (eg, 108a-b) It can be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (eg, 108a-f) can be configured to etch a dielectric film on the substrate. Any one or more of the processes described may be performed in a chamber separate from the manufacturing system shown in the different embodiments.

In some embodiments, the chamber specifically includes at least one etch chamber as described below and at least one deposition chamber as described below. All of the etching and deposition processes described below can be performed in a controlled environment by including these chambers and combining the processing sides of the factory interface. For example, the vacuum environment can be maintained on the processing side of the holding area 106 such that all of the chambers and transfers in the embodiment are maintained under vacuum. This also limits the contact of water vapor and other air components with the substrate being processed. It should be understood that system 100 can take into account additional configurations for deposition, etching, annealing, and curing of dielectric films.

2A illustrates a cross-sectional view of an exemplary processing chamber system 200 having separate plasma generating regions within a processing chamber. During film etching (for example, titanium nitride, tantalum nitride, tungsten, cobalt, aluminum oxide, tungsten oxide, tantalum, polycrystalline germanium, antimony oxide, antimony nitride, antimony oxynitride, antimony oxyhydroxide, etc.), the process gas can pass The gas inlet assembly 205 flows into the first plasma region 215. A remote plasma system (RPS) 201 can optionally be included in the system and can process the first gas that subsequently travels through the gas inlet assembly 205. The inlet assembly 205 can include two or more different gas supply passages, wherein if a second passage (not shown) is included, the second passage can bypass the RPS 201.

A cooling plate 203, a panel 217, an ion suppressor 223, a showerhead 225, and a substrate support 265 having a substrate 255 disposed thereon are illustrated, and each may be included in accordance with an embodiment. The pedestal 265 can have a heat exchange channel through which the heat exchange fluid flows to control the temperature of the substrate, and the temperature of the substrate can be manipulated during processing operations to heat and/or cool the substrate or wafer. It is also possible to use an embedded resistive heater element while resistively heating a wafer support disk of pedestal 265 comprising aluminum, ceramic, or a combination thereof to achieve relatively high temperatures, for example from up to or about 100 ° C to above or about 1100 ° C. temperature.

Panel 217 may be pyramidal, conical, or other similar structure having a narrow top portion that extends to a wide bottom portion. Additionally, panel 217 may be flat and include a plurality of through passages for dispensing process gases, as shown. Depending on the use of the RPS 201, the plasma generating gas and/or the plasma exciting material may pass through a plurality of holes in the panel 217 as shown in FIG. 2B for more uniform delivery into the first plasma region 215.

An exemplary configuration may include passing gas inlet assembly 205 into gas supply region 258 separated from first plasma region 215 by panel 217 such that gas/substance flows through a hole in panel 217 into first plasma region 215 . Structural and operational features may be selected to prevent large amounts of plasma from the first plasma region 215 from flowing back into the supply region 258, the gas inlet assembly 205, and the fluid supply system 210. The illustrated conductive panel 217 or the electrically conductive top portion of the chamber and the showerhead 225 have an insulating ring 220 between the features that allows an AC potential to be applied to the panel 217 relative to the showerhead 225 and/or the ion suppressor 223. Insulation ring 220 can be positioned between panel 217 and showerhead 225 and/or ion suppressor 223 to enable capacitive coupling plasma (CCP) to be formed in the first plasma region. Additionally, a baffle (not shown) may be located in the first plasma region 215 or otherwise coupled to the gas inlet assembly 205 to affect the flow of fluid through the gas inlet assembly 205 into the region.

Ion suppressor 223 can include a plate or other geometry defining a plurality of pores throughout the structure, the plurality of pores configured to inhibit migration of ionically charged species exiting first plasma region 215 while allowing uncharged neutrality Or a radical species passes through ion suppressor 223 into the active gas delivery zone between the suppressor and the showerhead. In an embodiment, ion suppressor 223 can comprise a multiwell plate having various pore configurations. These uncharged materials can include highly active materials that are transported through the pores with less active carrier gas. As noted above, migration of ionic species through the pores may be reduced and, in some cases, completely inhibited. Controlling the amount of ionic species passing through ion suppressor 223 can advantageously provide increased control of the gas mixture in contact with the underlying wafer substrate, which in turn can increase control of deposition and/or etch characteristics of the gas mixture. For example, the adjustment of the ion concentration of the gas mixture can significantly change its etch selectivity, for example, SiNx: SiOx etch rate, Si: SiOx etch rate, and the like. In an alternative embodiment of performing deposition, the balance of conformal flow deposition of the dielectric material can also be translated.

The plurality of pores in the ion suppressor 223 can be configured to control the reactive gas (ie, ions, free radicals, and/or neutral species) to pass through the ion suppressor 223. For example, the aspect ratio of the holes, or the ratio of the diameter of the holes to the length, and/or the geometry of the holes can be controlled such that the flow of the ionically charged species in the reactive gas passing through the ion suppressor 223 is reduced. The holes in the ion suppressor 223 may include a tapered portion facing the plasma excitation region 215 and a cylindrical portion facing the showerhead 225. The cylindrical portion can be shaped and sized to control the flow of ionic species to the showerhead 225. An adjustable electrical bias can also be applied to the ion suppressor 223 as an additional means of controlling the flow of ionic species through the suppressor.

Ion suppressor 223 can be used to reduce or eliminate the amount of ionically charged species traveling from the plasma generating region to the substrate. Uncharged neutral and free radical species can still pass through the openings in the ion suppressor to react with the substrate. It should be noted that in an embodiment, complete elimination of the ionically charged species in the reaction zone surrounding the substrate may not be performed. In some cases, the ionic species are intended to reach the substrate to perform an etching and/or deposition process. In these cases, the ion suppressor can help control the concentration of ionic species in the reaction zone at the level that facilitates processing.

The showerhead 225 in combination with the ion suppressor 223 may allow plasma to be present in the first plasma region 215 to avoid direct excitation of gas in the substrate processing region 233 while still allowing the excited species to travel from the chamber plasma region 215. Go to substrate processing area 233. In this manner, the chamber can be configured to prevent plasma from contacting the substrate 255 in the etch. This can advantageously protect the various complex structures and films patterned on the substrate, and various complex structures and films can be damaged, displaced, or otherwise bent if directly in contact with the plasma produced. Furthermore, the rate at which the oxide species is etched may be increased when the plasma is allowed to contact the substrate or near the substrate level. Thus, if the exposed area of the material is an oxide, the material can be further protected by maintaining the plasma away from the substrate.

The processing system can further include a power supply 240 electrically coupled to the processing chamber to provide electrical power to the panel 217, the ion suppressor 223, the showerhead 225, and/or the pedestal 265 to be in the first plasma region 215 or Plasma is generated in the treatment zone 233. Depending on the processing performed, the power supply can be configured to deliver an adjustable amount of power to the chamber. This configuration can allow tunable plasma for processing in execution. Unlike a remote plasma unit that is typically presented with an on or off function, the tunable plasma can be configured to deliver a specific amount of power to the plasma region 215. This in turn may allow for the formation of specific plasma characteristics such that the precursors may be dissociated in a particular manner to enhance the etch profile created by these precursors.

The plasma may be excited in the chamber plasma region 215 above the showerhead 225 or the substrate processing region 233 below the showerhead 225. In an embodiment, the plasma formed in the substrate processing region 233 may be a DC bias plasma formed using a pedestal as an electrode. A plasma may be present in the chamber plasma region 215 to produce a free radical precursor from the influx of, for example, a fluorine-containing precursor or other precursor. Typically, an AC voltage in the radio frequency (RF) range can be applied between the conductive top portion of the processing chamber (eg, panel 217) and the showerhead 225 and/or ion suppressor 223 to excite the cavity during deposition. The plasma in the chamber plasma region 215. The RF power supply can produce a high RF frequency of 13.56 MHz, but other frequencies can be generated separately or combined with the 13.56 MHz frequency to produce other frequencies.

FIG. 2B illustrates a detailed view 253 of features affecting the distribution of process gases through panel 217. As shown in FIGS. 2A and 2B, panel 217, cooling plate 203, and gas inlet assembly 205 intersect to define a gas supply region 258 in which process gas can be delivered from gas inlet 205 into gas supply region 258. The gas may fill the gas supply region 258 and flow through the apertures 259 in the panel 217 to the first plasma region 215. The apertures 259 can be configured to direct flow in a substantially unidirectional manner such that process gases can flow into the processing region 233, but can be partially or completely prevented from flowing back into the gas supply region 258 after passing through the panel 217.

The gas distribution assembly (e.g., for use in processing the showerhead 225 in the chamber section 200) may be referred to as a dual channel showerhead (DCSH) and is additionally illustrated in detail in the embodiment illustrated in FIG. The dual channel showerhead can provide an etch process to allow separation of the etchant outside of the processing region 233 to provide limited interaction with the chamber components and each other prior to delivery to the processing region.

The showerhead 225 can include an upper plate 214 and a lower plate 216. The plates can be coupled to one another to define a volume 218 between the plates. The coupling of the plates can provide a first fluid passage 219 through the upper and lower plates and a second fluid passage 221 through the lower plate 216. The formed passageway can be configured to provide a fluid inlet and outlet from the volume 218 alone through the second fluid passage 221 through the lower plate 216, while the first fluid passage 219 can be fluidly isolated from the volume 218 between the plate and the second fluid passage 221. The volume 218 can be vented through one side of the gas distribution assembly 225.

Figure 3 is a bottom plan view of a showerhead 325 for use with a processing chamber in accordance with an embodiment. The showerhead 325 can correspond to the showerhead 225 shown in FIG. 2A. The through holes 365 (the view of the first fluid passage 219 are illustrated) may have a plurality of shapes and configurations to control and influence the flow of the precursor through the showerhead 225. A small aperture 375 (shown as a view of the second fluid passage 221) can be distributed substantially evenly over the surface of the showerhead (even in the through hole 365) and can help the precursor provide a ratio when exiting the showerhead. Other configurations are more evenly mixed.

Turning to FIG. 4, a schematic cross-sectional view of an atomic layer deposition system 400 or reactor in accordance with one or more embodiments of the present technology is illustrated. System 400 can include a load lock chamber 10 and a processing chamber 20. The processing chamber 20 can generally be a sealable outer casing that can be operated under vacuum or at least low pressure. The processing chamber 20 can be isolated from the load lock chamber 10 by an isolation valve 15. The isolation valve 15 can seal the process chamber 20 and the load lock chamber 10 in a closed position and can allow the substrate 60 to be transferred from the load lock chamber 10 through the valve to the process chamber 20 in the open position, and vice versa.

System 400 can include a gas distribution plate 30 that can dispense one or more gases across substrate 60. The gas distribution plate 30 can be any suitable distribution plate known to those skilled in the art, and the particular gas distribution plate should not be considered to limit the scope of the present technology. The output face of the gas distribution plate 30 may face the first surface 61 of the substrate 60.

The gas distribution plate 30 can include a plurality of gas crucibles and a plurality of vacuum crucibles, the plurality of gas crucibles configured to deliver one or more gas streams to the substrate 60, and a plurality of vacuum crucibles disposed between each gas crucible, And configured to deliver a flow of gas out of the processing chamber 20. As shown in FIG. 4, the gas distribution plate 30 can include a first precursor injector 420, a second precursor injector 430, and a purge gas injector 440. The injectors 420, 430, 440 can be controlled by a system computer (not shown) (e.g., a host) or by a chamber specific controller (e.g., a programmable logic controller). The precursor injector 420 can be configured to inject a continuous or pulsed stream of active precursors of Compound A into the processing chamber 20 through a plurality of gas helium 425. The precursor injector 430 can be configured to inject a continuous or pulsed stream of active precursors of Compound B into the processing chamber 20 through a plurality of gas helium 435. The purge gas injector 440 can be configured to inject a continuous or pulsed stream of inactive or purge gas into the processing chamber 20 through a plurality of gas ports 445. The purge gas can be configured to remove active material and active byproducts from the processing chamber 20. The purge gas is typically an inert gas such as nitrogen, argon, and helium. A gas crucible 445 may be disposed between the gas crucible 425 and the gas crucible 435 to separate the precursor of the compound A from the precursor of the compound B, thereby avoiding cross-contamination between the precursors.

In another aspect, a distal plasma source (not shown) can be coupled to the precursor injector 420 and the precursor injector 430 prior to injecting the precursor into the processing chamber 20. The plasma of the active material can be produced by applying an electric field to the compound in the remote plasma source. Any power source capable of activating the intended compound can be used. For example, power sources using DC, RF, and microwave-type discharge techniques can be used. If an RF power source is used, it can be capacitively or inductively coupled. Activation can also be produced by thermal basic techniques, gas dissociation techniques, high intensity light sources (eg, ultraviolet light sources), or exposure to x-ray sources.

System 400 can further include a pumping system 450 coupled to processing chamber 20. The pumping system 450 can be generally configured to evacuate the gas stream out of the processing chamber 20 by one or more vacuum ports 455. A vacuum crucible 455 can be disposed between each gas crucible to evacuate the gas stream out of the processing chamber 20 after the gas stream reacts with the substrate surface and further limit cross-contamination between the precursors.

System 400 can include a plurality of partitions 460 disposed on processing chamber 20 and between each turn. The lower portion of each partition may extend proximate to the first surface 61 of the substrate 60 (eg, about 0.5 mm or more from the first surface 61). In this manner, the lower portion of the partition 460 can be separated from the surface of the substrate by a distance sufficient to allow the flow of gas to flow around the lower portion toward the vacuum crucible 455 after the gas stream reacts with the surface of the substrate. Arrow 498 indicates the direction of the gas flow. Since partition 460 is operable as a physical barrier to gas flow, partition 460 can also limit cross-contamination between precursors. The configurations shown are for illustrative purposes only and are not to be considered as limiting the scope of the technology. Those of ordinary skill in the art will appreciate that the gas distribution system shown is only one possible distribution system and that other types of showerheads can be employed.

In operation, the substrate 60 (e.g., by a robot) can be delivered to the load lock chamber 10 and can be placed on the shuttle 65. After the isolation valve 15 is opened, the shuttle 65 can move along the rail 70. Once the shuttle 65 enters the processing chamber 20, the isolation valve 15 can be closed to seal the processing chamber 20. The shuttle 65 can then be moved through the processing chamber 20 for processing. In one embodiment, the shuttle 65 can move through the chamber in a linear path.

As the substrate 60 moves through the processing chamber 20, the first surface 61 of the substrate 60 may be repeatedly exposed to the precursor of the compound A from the gas crucible 425 and the precursor of the compound B from the gas crucible 435 with gas from the gas crucible 445 Purge the gas. The injection of the purge gas can be designed to remove unreacted material from the previous precursor prior to exposing the substrate surface 61 to the next precursor. After each exposure to various gas streams, the gas stream can be evacuated by vacuum pumping 455 through vacuum pumping 455. Since a vacuum crucible can be placed on both sides of each gas crucible, the gas flow can be evacuated by vacuum crucibles 455 on both sides. Thus, the gas stream can flow vertically downward from the respective gas crucible toward the first surface 61 of the substrate 60, across the first surface 410 and around the lower portion of the partition 460, and finally upwardly toward the vacuum crucible 455. In this way, each gas can be evenly distributed across the substrate surface 61. The substrate 60 can also be rotated while exposed to various gas streams. Rotation of the substrate can be useful to prevent strip formation in the formed layer. The rotation of the substrate can be a continuous or separate step.

The extent to which the substrate surface 61 is exposed to each gas can be determined by, for example, the flow rate of each gas from the gas and the rate of movement of the substrate 60. In one embodiment, the flow rate of each gas can be configured without removing the absorbed precursor from the substrate surface 61. The width between each partition, the number of gas imperfections disposed on the processing chamber 20, and the number of times the substrate may be transferred back and forth may also determine the extent to which the substrate surface 61 is exposed to various gases. Therefore, the number and quality of deposited films can be optimized by varying the above factors.

In another embodiment, system 400 can include precursor injector 420 and precursor injector 430 without purge gas injector 440. Thus, as the substrate 60 moves through the processing chamber 20, the substrate surface 61 can be alternately exposed to the precursor of Compound A and the precursor of Compound B without being exposed to the purge gas therebetween.

The embodiment shown in Figure 4 has a gas distribution plate 30 above the substrate. While the embodiments have been described and illustrated with respect to this upright orientation, it should be understood that the opposite orientation is also possible. In that case, the first surface 61 of the substrate 60 may face downward, and the gas flowing toward the substrate may be directed upward. In one or more embodiments, at least one radiant heat source 90 can be positioned to heat the second side of the substrate.

In some embodiments, the shuttle 65 can be a base 66 for carrying the substrate 60. Generally, the pedestal 66 can be a carrier that helps to form a uniform temperature across the substrate. The pedestal 66 can be moved in both left-to-right and right-to-left directions between the load lock chamber 10 and the process chamber 20 with respect to the arrangement of FIG. The pedestal 66 can have a top surface 67 for carrying the substrate 60. The pedestal 66 can be a heated pedestal such that the substrate 60 can be heated for processing. As an example, the pedestal 66 can be heated by a radiant heat source 90 disposed below the susceptor 66, a heater plate, a resistive coil, or other heating device. Although illustrated as a lateral transition, embodiments of system 400 can also be used in a rotary system in which the wheel can be rotated clockwise or counterclockwise to continuously process one or more substrates located below the gas distribution system shown. It should be similarly understood that additional modifications are included in the present technology.

FIG. 5 illustrates a method 500 of forming a semiconductor structure in which a number of operations can be performed, for example, in the aforementioned chambers 200 and 400. Method 500 can include one or more operations prior to initiating the method, including front end processing, deposition, etching, grinding, cleaning, or any other operation that can be performed prior to the operation. The method can include a plurality of selectable operations shown in the figures, which may or may not be particularly associated with methods in accordance with the present techniques. For example, many operations are described in order to provide a broader range of structure formation, but are not critical to the technology, or may be performed by alternative methods, which are discussed further below. Method 500 describes the operations illustrated schematically in Figures 6A-6C, which are described in conjunction with the operation of method 500. It should be understood that FIG. 6 is only a partial schematic view, and the substrate may include any number of transistor segments having the pattern shown in the figures.

Method 500 can involve optional operations to develop a semiconductor structure to a particular fabrication operation. As shown in Fig. 6A, the semiconductor structure can represent a device after some transistor forming operation occurs. These materials may have been formed in previous operations and may have been polished to a specific height while exposing each of the materials on the top and side surfaces of the substrate. The operation of method 500 can be performed to limit or eliminate shielding operations, to limit or eliminate RIE processing including ashing and cleaning, and to reduce processing time for forming nanowire structures.

As shown, structure 600 can include substrate 601 made of tantalum or some other semiconductor substrate material or containing germanium or some other semiconductor substrate material. The structure 600 may have a plurality of transistor structures formed to cover the substrate 601. For example, dummy gate material 605 can be formed on substrate 601, which can be removed later in the process to create a metal gate. The dummy gate 605 may have a cap material 607 formed to cover the dummy gate 605. Additionally, a dielectric material 609 can be formed around the dummy gate 605. The dielectric material 609 can be blanketed onto the structure and then patterned into the illustrated structure, or the dielectric material 609 can be selectively deposited around the cap material 607 and the dummy gate 605.

In some embodiments, the dummy gate can be a polysilicon or germanium containing material. The cover material 607 can be a dielectric material and can be, for example, tantalum nitride. Dielectric material 609 can also be tantalum nitride or can be an oxide (eg, hafnium oxide). As shown, structure 600 can be an N-MOS region, and although not shown, a similar P-MOS region can be associated with the structure. Several of the operations discussed below may be performed on one side of the structure while the other side remains shielded or may be selectively performed without the need for shielding. If shielding is used on two areas, the masking can be switched by removal and reformation, and similar operations can be performed on other structures, and other structures can be selective in the exposed area. These options are described further below, but it should be understood that any of the regions may be processed before other regions, and such methods are not limited by the examples described.

A multilayer material can be formed vertically on the source/drain regions of the substrate 601 for use in developing nanowires in accordance with the present technology. The layer may include at least one layer of the first cerium-containing material 611 and at least one layer of the second cerium-containing material 613, and may include alternating layers of material. As shown in Figure 6A, there are three layers of each part on the source and drain, but it should be understood that there may be less than three (eg, two or one layer each) and more than three (eg, 4, 5, 6, 7, 10, or more layers per one). As shown, in an embodiment, layer 613 can be the same material as substrate material 601 or comprise the same material as substrate material 601.

Depending on whether the described operation is included in the N-MOS region or the P-MOS region, the first germanium-containing material and the second germanium-containing material may differ depending on the particular nanowire structure formed. For example, on the N-MOS side of the illustrated structure, the nanowires may be formed of tantalum, and thus the second tantalum-containing material 613 may be tantalum or may include tantalum, and the first tantalum-containing material 611 may be, for example, A level of sputum. However, on the P-MOS side of the structure (not shown but may be similar), the nanowire may be formed of, for example, germanium or germanium, and thus the second germanium-containing material may be higher than the first A cerium content of the second cerium content, and the first cerium-containing material may be, for example, cerium.

As shown in FIG. 6B, a lateral etching operation can be performed on the first germanium-containing material. Lateral etching may be performed isotropically to remove the first germanium-containing material from both sides of the gate structure (eg, on both sides of the dummy gate 605), and the first germanium-containing material may not be completely removed. Lateral etching can be performed in chamber 200 as previously described, or in different chambers capable of performing similar etching operations. Once positioned within the processing region of the semiconductor processing chamber, the method can include forming a plasma of the fluorine-containing precursor in the distal plasma region of the processing chamber at operation 505. The distal plasma region can be fluidly coupled to the processing region, but can be physically separated to confine the plasma at the substrate level, which can damage the exposed structure or material. The effluent of the plasma can flow into the processing region where it can be contacted with the semiconductor substrate at operation 510.

Lateral etching can then be performed at operation 515 to form a recess 617 defined between the layers of material. For example, the recess 617 may be formed between each of the second bismuth-containing materials 613 and above the substrate 601. Recesses 617 may also be formed on each side of the gate structure or on each side of the remaining portion of the first ruthenium containing material 611. The length of the recess may be less than or about 10 nm in embodiments, and may be less than or about 8 nm, less than or about 6 nm, less than or about 4 nm, between about 3 nm and about 8 nm, or between about 5 nm and about 7 nm in embodiments. between. The treatment may maintain a quantity of the first bismuth-containing material, the first bismuth-containing material may be located perpendicular to the dummy gate material, and may be similar in size or slightly larger than the dummy gate material.

For example, the first ruthenium-containing material can maintain a width equal to the dummy gate, which width can be greater than or about 10 nm, greater than or about 20 nm, greater than or about 30 nm, greater than or about 40 nm, greater than or about 50 nm, greater than or about 60 nm, greater than or about 70 nm, greater than or about 80 nm, greater than or about 90 nm, or greater. In addition, the width of the first germanium-containing material may be slightly larger than the width of the dummy gate, and may be as much as 0.5 nm or about 0.5 nm on each side of the dummy gate, and may be more on each side. Up to 1 nm or about 1 nm, up to 2 nm or about 2 nm on each side, up to 3 nm or about 3 nm on each side, up to 4 nm or about 4 nm on each side, at each Up to 5 nm or about 5 nm on one side, up to 6 nm or about 6 nm on each side, and up to 7 nm or about 7 nm, or more on each side.

The lateral etch process may selectively remove the first ruthenium-containing material 611 (which may be ruthenium telluride) relative to the second ruthenium-containing material 613 (which may be ruthenium). In an embodiment, the operation may have a selectivity of greater than or about 50: 1 relative to the first cerium-containing material of the second cerium-containing material, which may allow the first cerium-containing material to dent while substantially maintaining or substantially maintaining The second bismuth-containing material. In some embodiments, the second germanium-containing material can be etched less than or about 1 nm during the lateral etch operation 515 and can be etched less than or about 0.8 nm, less than or about 0.6 nm, less than or about 0.4 nm, less At or about 0.2 nm, less than or about 0.1 nm, or less.

At optional operation 520, the substrate can be transferred from the etch chamber to the deposition chamber. The transfer can be done under vacuum, while both chambers can reside on the same cluster tool to allow the transfer to occur in a controlled environment. For example, vacuum conditions can be maintained during transfer and transfer can be performed without breaking the vacuum. Once in the deposition chamber (eg, chamber 400 described above), at operation 525, spacer material may be formed or deposited adjacent to the recessed ruthenium containing material 611. As shown in FIG. 6C, the spacer material 620 may be formed directly on the recessed ruthenium-containing material 611 or in contact with the recessed ruthenium-containing material 611. This lateral deposition may be a timed deposition to form spacer material 620 within recess 617 while limiting formation on other exposed surfaces. Spacer material 620 can be formed around the ruthenium containing material and formed within previously formed recess 617. The spacer material 620 can be laminated between the regions of the second bismuth-containing material and can completely fill the recess 617 to contact the remainder of the first bismuth-containing material defined between the layers of the second bismuth-containing material.

In an embodiment, the spacer material 620 may be a germanium containing material and may be or include tantalum nitride, tantalum carbide, tantalum carbon oxide, or include carbon doped germanium oxide, a porous material, or a feature having a low dielectric constant. Low-k materials for other materials. The deposition operation may be selective deposition, wherein the spacer material is preferentially formed on the germanium containing material 611 with respect to the exposed second germanium containing material 613, capping material 607, and dielectric material 609. Operation 525 may directly perform subsequent etching operations 515 with respect to conventional techniques that may include additional shielding operations.

Although substrate transfer can be performed, other substrate processing may not be performed between selective etching and selective deposition. As will be explained in further detail below, selective deposition may include multiple operations, although substrate transfer between operations may be performed in embodiments, but the entire deposition process may be performed directly after a set of etching operations. Since blanket deposition or formation of spacer material 620 may require additional shielding and removal techniques, by performing selective etching and selective deposition in accordance with method 500, the grid time can be significantly reduced over conventional techniques. Method 500 may not utilize any RIE operation, which may reduce polymer buildup and the necessary ashing and cleaning operations associated with RIE. Furthermore, as explained further below, etching can be performed with higher or much higher selectivity than RIE, which can reduce critical size losses on the gate spacers and can reduce or eliminate gate spacers and contact dielectrics Shielding.

While conventional techniques can blanket the spacer material and then perform the RIE operation, such processing with relatively low selectivity may etch the sidewalls, the underlying substrate, and the deposited material. Furthermore, when a carbonaceous material is used within the spacer material, ashing performed by RIE may remove carbon from the formed dielectric, which will increase the dielectric constant of the material and disrupt the formation. By not performing RIE subsequent deposition of the spacer material, the carbon content of the spacer material can be retained, which can maintain a lower dielectric constant of the material. In some embodiments, a slight etch back operation can be performed after deposition by transferring the substrate back to the etch chamber. Subsequent dry etching can clean the sidewalls of the spacer to ensure sufficient separation at operation 530, and the selectivity of the etch can be any of those described elsewhere to ensure that substantially all other exposed materials are maintained.

Various materials can be utilized in the process, while etching and deposition can be selective for multiple components. Thus, the present technology may not be limited to a single set of materials. For example, the first cerium-containing material 611 can be several materials as described above, and in embodiments may include a carbonaceous material. Dielectric material 609 can include an insulating material and can include a germanium containing material, an oxygen containing material, a carbon containing material, or some combination of these materials (eg, hafnium oxide or tantalum nitride). The cover material 607 may also include an insulating material, and may also include a niobium containing material, an oxygen containing material, a carbonaceous material, or some combination of these materials (eg, hafnium oxide or tantalum nitride).

Similarly, while selective etching and deposition operations may be adjusted depending on the materials used with respect to other materials formed or removed, other insulating materials may be similarly used in other embodiments. In an embodiment, the cover material 607 and the dielectric material 609 may be the same material or may be different materials. For example, in one embodiment, the dielectric material can be yttrium oxide or can include yttrium oxide, while the capping material can be tantalum nitride or can include tantalum nitride.

The etching operation can involve additional precursors along with a particular fluorine-containing precursor. In some embodiments, nitrogen trifluoride can be used to produce a plasma effluent. Additional or alternative fluorine precursors may also be utilized. For example, the fluorine-containing precursor can flow into the distal plasma region, and the fluorine-containing precursor can include a group selected from the group consisting of atomic fluorine, diatomic fluorine, carbon tetrafluoride, bromine trifluoride, chlorine trifluoride, and trifluoride. At least one precursor of the group of nitrogen, hydrogen fluoride, sulfur hexafluoride, and antimony difluoride. The distal plasma zone can be in a different module than the processing chamber or in a compartment within the processing chamber. As shown in FIG. 2, both the RPS unit 201 and the first plasma region 215 can serve as a distal plasma region. The RPS can allow the plasma effluent to dissociate without damaging other chamber components, while the first plasma region 215 can provide a shorter path length to the substrate during which recombination can occur. Additional precursors can also be delivered to the remote plasma region to enhance the fluorine-containing precursor (eg, other carbon-containing precursors, hydrogen-containing precursors, or oxygen-containing precursors).

In an embodiment, the etching operation can be performed below about 10 Torr, and in embodiments can be performed below or about 5 Torr. In embodiments, the treatment may also be performed at temperatures below about 100 °C and may be performed below about 50 °C. The process may be removed for the second ruthenium containing material 613, the cover material 607, and the dielectric material 609 as performed in the chamber 200 or a variation of such a chamber, or in a different chamber capable of performing similar operations. A portion of the first cerium-containing material 611 that is selective.

When performing the method, the etch selectivity of the first bismuth-containing material relative to other features exposed on the surface of the substrate can be greater than or about 10:1, greater than or about 20:1, greater than or about 50:1. Or greater than or about 100: 1, or greater for various materials formed on the substrate and may be exposed to the plasma effluent. Thus, depending on the feature size, the first germanium-containing material can be removed from the surface of the substrate while other exposed materials can be reduced by less than 1 nm. For example, the feature width from one gate segment to the second gate segment can be between about 50 nm and about 70 nm, and can extend down to between about 20 nm and about 30 nm. In the embodiments described above, the depth of the lateral recess for the first germanium-containing material 611 may be less than or about 50 nm, and may be less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, Or less. Due to this etch depth, a minimum amount of other exposed material may be removed, which may be less than or about 3 nm, less than or about 1 nm, less than or about 0.5 nm, or the material may remain substantially or substantially unchanged. Thus, the first ruthenium-containing material etched feature relative to other exposed materials can be any of the above-described identities for the materials of each structure.

Selective deposition can be performed in a chamber capable of deposition and capable of atomic layer deposition, including chamber 400 described above. The deposition may be preset to selectively deposit an insulating material on a semiconductor material relative to another insulating material or another semiconductor material. For example, the spacer material 620 can be formed substantially on the first ruthenium-containing material 611 while being minimally formed or confined on the second ruthenium-containing material 613 or the exposed cover material 607 or dielectric material 609. . Selective deposition can be performed by a variety of operations, which can include forming a self-assembled monolayer to facilitate selective deposition, or can include actively inhibiting the formation of a dielectric on other dielectric materials.

A self-assembled monolayer can be formed over the area of the structure to tune the deposition. For example, a first self-assembled monolayer can be formed on the structure and then the first self-assembled monolayer can be removed from the first bismuth-containing material 611. A single layer can be maintained on the second ruthenium containing material 613 and the exposed top surface. The monolayer may have a capping moiety that may or may not interact with the subsequently delivered precursor. For example, in embodiments, the capping moiety can be hydrophobic and can be capped with a hydrogen containing moiety (eg, a methyl group) that can not interact with the additional precursor. A second self-assembled monolayer may be formed on the first ruthenium containing material 611, which may be hydrophilic or react with one or more precursors used to create the spacer material 620. The second self-assembled monolayer can be selectively formed on the first ruthenium-containing material 611 because the material can be repelled from the first self-assembled monolayer or can be selectively stretched to the material. The second self-assembled monolayer can be capped with a hydroxyl or other hydrophilic moiety, or partially capped with an additional precursor that interacts specifically with the spacer material 620.

Atomic layer deposition can then be performed using two or more precursors to develop spacer material 620. The deposited precursor can include a plurality of precursors including a precursor comprising a ruthenium precursor and a moiety configured to interact with a portion of the capped second self-assembled monolayer (rather than the first self-assembled monolayer) . For example, when a hydrophilic and hydrophobic capping monolayer is used, one of the atomic layer deposition precursors can include water. In this way, deposition may not be formed on the first self-assembled monolayer which may be hydrophobic. If the spacer material comprises an oxide (eg, ruthenium oxide or ruthenium oxycarbide), the precursor for atomic layer deposition may include a ruthenium containing precursor and water. Then, during a half reaction with water, the water may not interact with the first self-assembled monolayer formed on the second cerium-containing material and the dielectric material, and thus the deposition will not form on the first self-assembled monolayer. In this manner, the spacer material 620 can be selectively formed on the first ruthenium-containing material 611 without forming a mask layer that can be chemically etched.

After the spacer material 620 has formed a suitable thickness, the first self-assembled monolayer can be exposed to UV light and the first self-assembled monolayer can be removed from the substrate. Thus, the first self-assembled monolayer can be formed directly after the selective etching of germanium, or after transfer to the additional chamber but prior to the additional processing operation, without structurally eliminating the need for chemical removal or etching. Additional shielding layer. Similarly, after selective deposition, spacer material 620 may not be required (and additional shielding may be required) to ensure selective formation of spacer material 620 on the germanium containing material. In this way, multiple operations used in conventional formations can be eliminated, which can significantly reduce the queue time (eg, several hours).

Embodiments may also utilize an inhibitor to selectively form spacer material 620 on first tantalum-containing material 611 without forming spacer material 620 on cover material 607 and dielectric material 609. For example, the sprayed inhibitor can be applied across the surface of the substrate, which can be applied along the top surface of the substrate and can not penetrate into the recessed portion of the substrate. The inhibitor can be any number of materials, and the material can be characterized by a siloxane backbone (e.g., a decane) or a tetrafluoroethylene backbone (e.g., PTFE), as well as other oily or surfactant materials. Material may be applied across the surface of the substrate to cover the exposed portions of cover material 607 and dielectric material 609. By using a spray coating or coating application, the material may not be applied to the recessed portion of the substrate and may not contact the first ruthenium-containing material 611. Spacer material 620 can then be formed, for example, by atomic layer deposition or other vapor deposition or physical deposition mechanisms.

The inhibitor material can prevent adhesion or adsorption of a material that can be normally formed or deposited on the first cerium-containing material 611. A spacer material 620 is then formed and a remover can be applied to the substrate to remove the inhibitor material. The remover can be a wet etchant, a reactant, or a surfactant cleaner that can remove residual inhibitor material that exposes the underlying gate structure. Thus, the inhibitor can be applied directly after selective etching, or after substrate transfer, but prior to other processing operations that affect the substrate. The use of an inhibitor may allow spacer material to be formed in a defined area without the need for patterning and/or etching definition through subsequent blanket films. By removing the previous and subsequent patterning operations, the processing can further reduce the queue time of conventional processing.

The inhibitor may also be the product of a plasma application that can neutralize the surface of the substrate or render the surface of the substrate inert. For example, the modified plasma can be formed from one or more precursors, which can include an inert precursor. The plasma may be applied to the surface of the substrate, which may change the top surface of the substrate and may not penetrate into the recessed portion of the substrate. For example, a nitrogen-containing precursor (which may be nitrogen) can be delivered to the plasma processing zone of the processing chamber that produces the plasma. The plasma effluent (which may include a nitrogen-containing plasma effluent) may be delivered to the substrate and may form a nitrided surface (which may include cover material 607 and dielectric material 609) along the exposed portion of the substrate along the top surface.

The plasma effluent may or may not flow within the recessed portion of the substrate, while maintaining a pure or unreacted surface of the first cerium-containing material 611. The spacer material 620 can then be formed using one or more deposition techniques, which can include atomic layer deposition or other vapor or physical deposition. For example, atomic layer deposition techniques can be utilized, followed by treatment with a plasma effluent. After each cycle of deposition, the nitrogen-containing plasma can be reapplied to the surface area of the substrate (eg, on cover material 607 and dielectric material 609). In this manner, the surface of cover material 607 and dielectric material 609 can be passivated to prevent or limit the formation of spacer material 620 on those areas. Utilizing these plasma effluents on the non-recessed portions of the substrate may allow spacer material to be formed in the defined regions without the need for patterning and/or etching definition through subsequent blanket films. By removing the previous and subsequent patterning operations, the processing can further reduce the queue time of conventional processing. Furthermore, deposition can occur on both the first and second ruthenium-containing materials, but can occur at a faster rate on the first ruthenium-containing material, which can allow for subsequent etching similar to that previously described, and then from the second Excess spacer material is removed from the exterior of the crucible material.

Any of these techniques may selectively deposit or form a dielectric or insulating material over the semiconductor-containing region relative to one or more other semiconductor, dielectric, or insulating regions. The selectivity may be complete, i.e., the spacer material is formed only on the first ruthenium containing material 611 or the intermediate layer, and the spacer material may be formed entirely on the cover material 607 and the dielectric material 609. In other embodiments, the selectivity may not be complete, and the ratio of deposition on the semiconductor-containing material relative to the dielectric or insulating material may be greater than about 2:1. The selectivity may also be greater than or about 5:1, greater than or about 10:1, greater than or about 15:1, greater than or about 20:1, greater than or about 25:1, greater than or about 30:1, greater than or about 35. : 1. greater than or about 40:1, greater than or about 45:1, greater than or about 50:1, greater than or about 75:1, greater than or about 100:1, greater than or about 200:1, or more. The spacer material can be formed to the aforementioned thickness, the thickness can be less than or about 50 nm, and can be less than or about 40 nm, less than or about 30 nm, less than or about 20 nm, less than or about 10 nm, less than or about 5 nm, or less. Thus, a selectivity below 50:1 may be acceptable to completely deposit the spacer material 620 while forming a limited amount of material or substantially no material on the cover material 607 and dielectric material 609.

The deposition operation can be performed at any of the foregoing temperatures or pressures, and can be performed at temperatures greater than or about 50 ° C, and can be greater than or about 100 ° C, greater than or about 150 ° C, greater than or about 200 ° C, greater than or about 200 ° C, greater than or about 250 ° C, greater than or about 300 ° C, greater than or about 350 ° C, greater than or about 400 ° C, greater than or about 450 ° C, greater than or about 500 ° C, greater than or about 600 ° C, greater than or about 700 ° C Executed at temperatures greater than or about 800 ° C, or higher. For example, during an atomic layer deposition operation, temperatures greater than or about 400 ° C can be used to activate the precursors to interact with one another as the layers of material form.

Method 500 can be performed without any RIE processing or associated processing, which can better maintain the composition of the spacer material and maintain a low k value of the spacer material. Similarly, the method can reduce the queue time by removing many of the patterning and removal operations that can be performed before, during, or after the formation of the conventional process. By utilizing the present technology, manufacturing can be performed with more selective formation and removal than conventional techniques, which can protect the formed material and can reduce the array time by several hours compared to conventional processing.

In the previous description, numerous details have been set forth in order to provide an understanding of various embodiments of the present invention. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

The invention has been described in terms of a number of modifications, alternative constructions, and equivalents, which can be used in the art without departing from the spirit of the embodiments. Moreover, many of the known processes and elements are not described in order to avoid unnecessarily obscuring the present technology. Therefore, the above description should not be taken as limiting the scope of the technology.

When a range of values is provided, it is to be understood that unless the context clearly dictates otherwise, each intermediate value between the upper and lower limits of the range is specifically disclosed. Any narrower range between any of the stated or non-described intermediate values in the range and any other stated or intermediate value in the range. Unless the stated range has any specific exclusions, the upper and lower limits of these smaller ranges may be independently included or excluded, and either or both of the upper and lower limits are included or not included. Each of the ranges is also included in the technology. Where the stated range includes one or two limitations, the scope of the one or both of the

The singular forms "a", "an" and "the" Thus, for example, reference to "a" or "an" or "an" or "an"

In addition, the words "including", "including", "including", "including", "including", and "including" are used in the specification and the following claims. The existence of a component, or operation, does not exclude the presence or addition of one or more other features, components, components, operations, acts, or groups.

10‧‧‧Loading lock chamber

15‧‧‧Isolation valve

20‧‧‧Processing chamber

30‧‧‧ gas distribution board

60‧‧‧Substrate

61‧‧‧ first surface

65‧‧‧ Shuttle

70‧‧‧ Track

90‧‧‧radiation heat source

100‧‧‧Processing system

102‧‧‧ Front open combined wafer cassette

104‧‧‧Machine arm

106‧‧‧holding area

108a‧‧‧Processing chamber

108b‧‧‧Processing chamber

108c‧‧‧Processing chamber

108d‧‧‧Processing chamber

108e‧‧‧Processing chamber

108f‧‧‧Processing chamber

109a‧‧‧Series section

109b‧‧‧Series section

109c‧‧‧Series section

110‧‧‧Second robotic arm

200‧‧‧ chamber

201‧‧‧RPS unit

203‧‧‧Cooling plate

205‧‧‧ gas inlet assembly

210‧‧‧Fluid Supply System

214‧‧‧Upper board

215‧‧‧First plasma area

216‧‧‧ Lower board

217‧‧‧ panel

218‧‧‧ volume

219‧‧‧First fluid passage

220‧‧‧Insulation ring

221‧‧‧Second fluid channel

223‧‧‧Ion suppressor

225‧‧‧Sprinkler

233‧‧‧Substrate processing area

240‧‧‧Power supply

253‧‧‧Detailed view

255‧‧‧Substrate

258‧‧‧ gas supply area

259‧‧‧ pores

265‧‧‧ pedestal

325‧‧‧Sprinkler

365‧‧‧through hole

375‧‧‧Small holes

400‧‧‧ chamber

420‧‧‧Syringe

425‧‧‧ gas 埠

430‧‧‧Syringe

435‧‧‧ gas 埠

440‧‧‧Syringe

445‧‧‧ gas 埠

450‧‧‧ pumping system

455‧‧‧vacuum

460‧‧‧ partition

498‧‧‧ arrow

500‧‧‧ method

505‧‧‧ operation

510‧‧‧ operation

515‧‧‧ operation

520‧‧‧ operation

525‧‧‧ operation

530‧‧‧ operation

600‧‧‧ structure

601‧‧‧Substrate

605‧‧‧virtual gate material

607‧‧‧ Cover material

609‧‧‧ dielectric materials

611‧‧‧First containing materials

613‧‧‧Second bismuth-containing material

617‧‧‧ recess

620‧‧‧ spacer material

A further understanding of the nature and advantages of the disclosed technology can be realized by reference to the description and the accompanying drawings.

FIG. 1 illustrates a top plan view of an exemplary processing system in accordance with an embodiment of the present technology.

2A illustrates a schematic cross-sectional view of an exemplary processing chamber in accordance with an embodiment of the present technology.

2B illustrates a detailed view of an exemplary showerhead in accordance with an embodiment of the present technology.

FIG. 3 illustrates a bottom plan view of an exemplary showerhead in accordance with an embodiment of the present technology.

FIG. 4 illustrates a schematic cross-sectional view of an exemplary processing chamber in accordance with an embodiment of the present technology.

FIG. 5 illustrates selected operations in a method of forming a semiconductor structure in accordance with an embodiment of the present technology.

6A through 6C illustrate schematic cross-sectional views of an exemplary substrate in accordance with an embodiment of the present technology.

Several of the figures are included as schematics. It should be understood that the drawings are for illustrative purposes only and should not be construed as a In addition, the drawings are provided as a schematic diagram to aid understanding, and may not include all aspects or information as compared to the actual representation, and may include exaggerated materials for illustrative purposes.

Similar components and/or features may have the same component symbols in the accompanying drawings. Furthermore, various components of the same type may be distinguished by the use of letters after the component symbols to distinguish similar components. If only the foremost component symbol is used in the specification, the description applies to any similar component having the same topmost component symbol, regardless of the letter.

Domestic deposit information (please note according to the order of the depository, date, number)

Foreign deposit information (please note in the order of country, organization, date, number)

Claims (20)

A method of forming a semiconductor structure, the method comprising the steps of: forming a plasma of a fluorine-containing precursor in a distal plasma region of a processing chamber; contacting a semiconductor substrate with the effluent of the plasma The semiconductor substrate is housed in a processing region of the processing chamber; selectively recessing a germanium-containing material from the semiconductor substrate; and subsequently depositing a spacer material adjacent to the germanium-containing material, wherein the spacer The material is selectively deposited on the germanium containing material relative to a gate formation and an exposed area of a nanowire material. A method of forming a semiconductor structure according to claim 1, wherein the etching step is performed in a first processing chamber, and the depositing step is performed in a second processing chamber. The method of forming a semiconductor structure according to claim 2, further comprising the step of transferring the semiconductor substrate from the first processing chamber to the second processing chamber, and wherein the transferring step is performed without breaking the vacuum Execution in case of. A method of forming a semiconductor structure according to claim 1, wherein the germanium-containing material comprises germanium germanium. A method of forming a semiconductor structure according to claim 1, wherein the gate formation comprises an exposed dielectric material, and wherein the nanowire material comprises germanium. A method of forming a semiconductor structure according to claim 1, wherein the spacer material comprises a metal nitride or a metal oxide. A method of forming a semiconductor structure as described in claim 1, wherein the method is performed without performing a reactive ion etching operation. A method of forming a semiconductor structure according to claim 1 wherein the etching step is performed using a selectivity of the germanium-containing material relative to the gate formation and the nanowire material by greater than or about 10:1. A method of forming a semiconductor structure according to claim 1, wherein the depositing is performed using a selectivity of the germanium-containing material relative to the gate formation and the nanowire material of greater than or about 2:1. The method of forming a semiconductor structure according to claim 1, wherein the step of selectively depositing the spacer material comprises the steps of: forming a self-assembled monolayer on the germanium-containing material, wherein the self-assembled monolayer is used for One or more precursor interactions that form the spacer material. A method of forming a semiconductor structure, the method comprising the steps of: laterally etching a first germanium-containing material relative to a second germanium-containing material, wherein the first germanium-containing material and the second germanium-containing material are disposed perpendicular to each other, and Wherein the first bismuth-containing material is vertically positioned between two regions of the second bismuth-containing material; in a recess defined by the lateral etch between the two regions of the second bismuth-containing material Forming a spacer material; and selectively recessing the spacer material to separate the individual spacers. A method of forming a semiconductor structure according to claim 11, wherein the second ruthenium-containing material comprises ruthenium. A method of forming a semiconductor structure according to claim 12, wherein the spacer material is selected from the group consisting of a carbonaceous material, a nitrogen-containing material, and an oxygen-containing material. A method of forming a semiconductor structure according to claim 11, wherein the first germanium-containing material is partially recessed from both sides of a gate formation. A method of forming a semiconductor structure according to claim 11, wherein the first ruthenium-containing material comprises ruthenium telluride. A method of forming a semiconductor structure as recited in claim 11, wherein the etching step is performed in a first processing chamber and the depositing step is performed in a second processing chamber. The method of forming a semiconductor structure according to claim 11, further comprising the step of transferring the semiconductor substrate from the first processing chamber to the second processing chamber, and wherein the transferring step is performed without breaking the vacuum Execution in case of. A method of forming a semiconductor structure as described in claim 11, wherein the method is performed without performing a reactive ion etching operation. A method of forming a semiconductor structure as recited in claim 11, wherein the etching step is performed using a selectivity of the first germanium-containing material relative to the second germanium-containing material that is greater than or about 10:1. A method of forming a semiconductor structure according to claim 11, wherein the depositing step is performed using a selectivity of the first cerium-containing material relative to the second cerium-containing material by greater than or about 2:1.