TW201902119A - Device with a voltage multiplier - Google Patents

Abstract

A device includes a level shifter and a voltage multiplier. The level shifter is responsive to a first clock signal configured to shift the first clock signal to a second clock signal at a higher level than the first clock signal based on a node voltage. The voltage multiplier is responsive to the second clock signal for generating the node voltage. The node voltage is output from the voltage multiplier for driving a load and is further fed back to the level shifter for generating the second clock signal.

Description

Device with voltage doubler

Embodiments of the invention relate to devices having voltage doublers.

A device uses a voltage doubler to generate a voltage greater than (e.g., twice) one supply voltage. For example, a device (such as a memory device) can read a memory cell at a read voltage equal to one of the supply voltages and write to the memory cell at a write voltage that is twice the supply voltage.

In accordance with an embodiment of the present invention, an apparatus includes a one-bit shifter responsive to a first clock signal configured to shift the first clock signal to be higher than the node voltage a second clock signal at one of the first clock signals; and a voltage multiplier that generates the node voltage in response to the second clock signal, wherein the node voltage is output from the voltage doubler A load is driven and further fed back to the level shifter to generate the second clock signal. According to an embodiment of the invention, an apparatus includes: a clock generator configured to receive a supply voltage and generate a first clock signal based on the supply voltage; and a quasi-shifter Configuring to receive a node voltage greater than the supply voltage and configured to shift the first clock signal to be higher than the first clock signal based on the node voltage in response to the first clock signal One of the second clock signals at the level. According to an embodiment of the invention, a method includes: generating a first clock signal based on a supply voltage; generating a node voltage greater than the supply voltage in response to a second clock signal; and based on the node voltage Shifting the first clock signal to the second clock signal at a level higher than one of the first clock signals, wherein shifting the first clock signal to the second clock signal comprises: Receiving the node voltage at a quasi-shift node; periodically coupling an output node to the level shift node in response to the first clock signal; and outputting the second clock signal from the output node .

The following disclosure provides many different embodiments or examples for implementing different features of the subject matter provided. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are examples only and are not intended to be limiting. For example, in the following description, forming a first member over a second member or forming on a second member may include an embodiment in which the first member and the second member are in direct contact, and may also An embodiment is disclosed in which an additional member can be formed between the first member and the second member such that the first member and the second member are not in direct contact. Additionally, the present disclosure may repeat element symbols and/or letters in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed. In addition, space-relative terms (such as "bottom", "lower", "lower", "above", "upper" and the like) may be used herein to describe a component or component and another. The relationship of the component or component(s) as shown in the figure. Spatially relative terms are intended to encompass different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or according to other orientations) and the spatially relative descriptors used herein can also be interpreted accordingly. The systems and methods described herein include a device that operates in multiple voltage domains, such as a memory device. For example, a memory device can read a memory cell at a read voltage equal to one of the nominal supply voltages, and simultaneously write the memory cell at a write voltage that is approximately twice the nominal supply voltage. . In another example, the load converts time information into one time-to-bit digital converter (TDC) of a digital code. For example, the TDC can output a series of 1 and 0 signal indication levels at a particular point in time. This circuit can be used in an all-digital phase-locked loop (ADPLL) system. Unlike a conventional device that drives a full load according to a nominal voltage (eg, a supply voltage) that operates according to the nominal voltage, the disclosure provides a device (eg, device 100 of FIG. 1) in various embodiments. ), which is configured to operate with a nominal voltage (eg, about 0.4 V) for some operations while driving a load for other operations at a load voltage greater than one of the nominal voltages (eg, about 0.8 V). This enables the apparatus 100 of the present disclosure to be adapted to operate at a low voltage in a nominal state while providing a substantially constant high voltage for functionality as needed. In further detail, FIG. 1 is a schematic block diagram of an illustrative device 100 in accordance with some embodiments. An exemplary device 100 (eg, an integrated circuit) is coupled between a supply node and a reference node and includes a clock generator 110, a one-bit shifter 120, and a voltage doubler 130. The supply node is configured to receive a supply voltage (Vdd), such as 0.4V. The reference node is configured to receive a reference voltage (Vss) below the supply voltage (Vdd), such as 0 V. The circuits 110, 120, 130 depicted in Figure 1 are configured to provide a substantial use of timing interactions with a capacitive element (e.g., capacitive element (C1) in Figure 3) using two level shift signals. The upper constant load voltage (V _LOAD ) (which has a voltage higher than one of the supply voltages (Vdd)). The clock generator 110 is configured to operate at a supply voltage (Vdd) (eg, about 0.4 V) and generate a first clock signal and a second clock provided to the level shifter 120 based on the supply voltage (Vdd). Signal (CLK1, CLK2). For example, the clock generator 110 includes a first module and a second module. The first module (eg, a cross-coupled flip-flop) is configured to receive an input signal and generate a first clock signal and a second clock signal (CLK1, CLK2), a first clock signal, and a second time The pulse signals (CLK1, CLK2) each correspond to the input signal and are between a low signal level (eg, a reference voltage (Vss) level) and a high signal level (eg, a supply voltage (Vdd) level) alternately. The second module is configured to introduce a delay between one of the falling/rising edges of the first clock signal (CLK1) and one of the rising/falling edges of the second clock signal (CLK2), such as in FIG. Time (t1). In one embodiment, the second module includes a pair of inverters connected in series. The level shifter 120 is configured to generate a third clock signal and a fourth clock signal (CLK3, CLK4) according to a shift voltage (eg, 0.8 V). Although the voltage is supplied by the first clock signal and the second clock signal (CLK1, CLK2) according to the nominal voltage, the level shifter 120 can utilize a feedback path from the voltage multiplier 130 (eg, node (N1)). This voltage shift is achieved as will be described in further detail below. The voltage multiplier 130 generates a greater than supply voltage (Vdd) in response to the third clock signal and the fourth clock signal (CLK3, CLK4) from the level shifter 120. One of the substantially constant load voltages (V _LOAD ) (eg, about 0.8 V) and uses a timing level shifter clock signal (CLK3, CLK4) from the level shifter 120 to drive a load 190. For example, During a high third clock signal (CLK3) level, voltage doubler 130 charges a capacitive element (such as capacitive element (C1) in Figure 3) to a supply voltage (Vdd). During the fourth clock signal (CLK4) level, the voltage multiplier 130 causes the capacitive element to be connected in series with the supply voltage (Vdd) to produce a superposition effect, resulting in a load voltage (V _LOAD ) that is substantially twice the supply voltage ( Vdd). This further causes one of the node voltages at the node (N1) to be substantially twice the supply voltage (Vdd), which The node voltage is fed back to the level shifter 120 to generate a third clock signal and a fourth clock signal (CLK3, CLK4). As will be described below, without expanding the physical size of the capacitive element (C1) The efficiency of the voltage multiplier 130 is increased by increasing the capacitance of one of the capacitive elements (C1) (eg, via the capacitive element (C1) structure.) Further details regarding the clock signals (CLK1, CLK2, CLK3, CLK4) 2A-2D are schematic timing diagrams showing an exemplary relationship between clock signals (CLK1, CLK2, CLK3, CLK4) according to some embodiments. As shown in FIG. 2A and FIG. 2B, the first Each of the clock signal and the second clock signal (CLK1, CLK2) is at a low signal level (eg, a reference voltage (Vss) level) and a high signal level (eg, a supply voltage (Vdd) level) The high signal level of the first clock signal (CLK1) and the high signal level of the second clock signal (CLK2) do not overlap each other in time. For example, one of the first clock signals (CLK1) falls/ There is a time (t1) between the rising edge and one of the rising edge/falling edge of the second clock signal (CLK2). As depicted in Figure 2C and Figure 2D Each of the third clock signal and the fourth clock signal (CLK3, CLK4) is at a low signal level (eg, a reference voltage (Vss) level) and a high signal level (eg, a supply voltage (Vdd) bit) Two times, which are higher than the first clock signal and the high signal level of the second clock signal (CLK1, CLK2), respectively. In the example of FIG. 2A to FIG. 2D, the third/fourth time The pulse signal (CLK3/CLK4) is substantially in phase with the first/second clock signal (CLK1/CLK2). Therefore, similar to the first clock signal and the second clock signal (CLK1, CLK2), the high signal level of the third clock signal (CLK3) and the high signal level of the fourth clock signal (CLK4) are mutually timed. There is no overlap, and there is a time (t2) substantially equal to time (t1) between one of the falling/rising edge of the third clock signal (CLK3) and one of the rising/falling edges of the fourth clock signal (CLK4). . In an alternate embodiment, the third/fourth clock signal (CLK3/CLK4) is 180 out of phase with the first/second clock signal (CLK1/CLK2). As will be understood from the following discussion, time (t1) is determined to ensure that the time (t2) duration (eg, about 0.5 μs) is sufficiently long that the third clock signal (CLK3) falls/rises and the fourth clock The rising/falling edges of the signal (CLK4) do not overlap to prevent shorting of the supply node and the reference node. The time (t1) is further determined to ensure that the time (t2) duration is sufficiently short that the load 190 is driven by the voltage multiplier 130 at a substantially constant load voltage (V _LOAD ). In some embodiments, the voltage multiplier 130 generates a voltage greater than one of the supply voltages (Vdd) in response to the third clock signal and the fourth clock signal (CLK3, CLK4). FIG. 3 is a schematic circuit diagram of an exemplary voltage doubler 130 in accordance with some embodiments. The example voltage multiplier 130 includes a first node and a second node (N1, N2), a first capacitive element and a second capacitive element (C1, C2), a first switching unit 310 and a second switching unit 320, and A load node 330. The first capacitive element (C1) is connected between the first node (N1) and the second node (N2). The first switching unit 310 includes a first switch and a second switch (SW1, SW2) and is configured to receive a third clock signal (CLK3). A first switch (SW1) is coupled between a supply node 340 and the first node (N1) and configured to selectively connect the first node (N1) to the supply in response to the third clock signal (CLK3) Node 340. A second switch (SW2) is coupled between the second node (N2) and a reference node 350 and configured to selectively connect the second node (N2) to the reference in response to the third clock signal (CLK3) The node 350 disconnects the second node (N2) from the reference node 350. The second switching unit 320 includes a third switch and a fourth switch (SW3, SW4) and is configured to receive a fourth clock signal (CLK4). A third switch (SW3) is coupled between the supply node 340 and the second node (N2) and configured to selectively connect the second node (N2) to the supply node in response to the fourth clock signal (CLK4) 340 and disconnecting the second node (N2) from the supply node 340. A fourth switch (SW4) is coupled between the first node (N1) and the load node 330 and configured to selectively connect the first node (N1) to the load node in response to the fourth clock signal (CLK4) 330 and disconnecting the first node (N1) from the load node 330. In this embodiment, the switches (SW1 to SW4) are n-type FETs. In some embodiments, at least one of the switches (SW1 to SW4) is a p-type FET. In other embodiments, at least one of the switches (SW1 to SW4) is any type of transistor (eg, a bipolar junction transistor (BJT)) or other type of switch. A second capacitive element (C2) (eg, a metal oxide semiconductor capacitor (MOSCAP), a metal-insulator-metal (MIM) capacitor, a combination of other types of capacitors, or the like) is coupled to the load node 330 and the reference node Between 350. In some embodiments, device 100 includes a load 190. In other embodiments, device 100 does not include load 190 and load 190 can be coupled between load node 330 and reference node 350 outside of device 100. As can be seen from an experimental result, the device 100 provides a substantially constant load voltage (Vload) (eg, about 91% to about 99 of the supply voltage (Vdd)) by a given current (eg, 400 μA) flowing through one of the loads 190. %) and a relatively small chopping voltage (eg, about 20 mV to about 30 mV). In addition, device 100 outputs a substantially constant load voltage (Vload) for a short period of time (eg, about 1 μs after device 100 receives the supply voltage (Vdd)). In some embodiments, the first capacitive element (C1) has a structure that increases its capacitance to increase the efficiency of the voltage multiplier 130 without expanding its physical size. For example, FIG. 4A is a schematic cross-sectional view of an exemplary first capacitive element (C1) in accordance with some embodiments. The first capacitive element (C1) includes a substrate 410, a first well region 420 and a second well region 430, and a transistor 440. The substrate 410 has a p-type conductivity and is connected to a reference node 350 (see FIG. 3). The substrate 410 can be a bulk substrate, a semiconductor-on-insulator (SOI) substrate, or a combination thereof. Examples of materials for substrate 410 include, but are not limited to, tantalum, niobium, any suitable semiconductor material, or a combination thereof. A first well region 420, such as is formed in one portion of the substrate 410 by implantation. The first well region 420 can comprise the same material as the substrate 410, but is doped with an n-type impurity and thus has an n-type conductivity. 4B is a schematic circuit diagram of an exemplary first capacitive element (C1) in accordance with some embodiments. As can be seen from FIG. 4B, since the substrate 410 and the first well region 420 have different conductivity types, the substrate 410 and the first well region 420 cooperate to form a diode (D1). The second well region 430 is implanted in a portion of the first well region 420, comprising the same material as the substrate 410, having a p-type conductivity and connected to the second node (N2). The first well region 420 extends deeper into the substrate 410 than the second well region 430. As can be seen from FIG. 4B, since the first well region 420 and the second well region 430 have different conductivity types, the first well region 420 and the second well region 430 cooperatively form a diode connected to one of the diodes (D1). Body (D2). The transistor 440 is located above the second well region 430 and includes: a source region 440a and a drain region 440b, which have an n-type conductivity and are implanted in the second well region 430; and a gate region 440c. Located above a channel region between the source region 440a and the drain region 440b. As can be seen from FIG. 4B, since the source region 440a and the drain region 440b are connected to each other and to the second node (N2), a capacitor is formed by the transistor 440. The second well zone 430 is connected to the second node (N2) so as not to float the second well zone 430. The first well region 420 and the gate region 440c are connected to each other and to the first node (N1) (see FIG. 3). This causes the capacitance of the capacitive element (C1) to increase when the first well region 420 and the gate region 440c are disconnected from each other (eg, by about 10% from one of the capacitances) to increase the efficiency of the device 100 by up to 12 %. In some embodiments, the level shifter 120 is configured to generate a node voltage (V _N1 ) from the voltage multiplier 130 in response to the first clock signal and the second clock signal (CLK1, CLK2). (Refer to FIG. 3), the first clock signal and the second clock signal (CLK1, CLK2) are respectively shifted to be higher than the first clock signal and the second clock signal (CLK1, CLK2). The three-clock signal and the fourth clock signal (CLK3, CLK4). FIG. 5 is a schematic circuit diagram of an exemplary level shifter 120 in accordance with some embodiments. The example level shifter 120 includes a pair of switches (D3, D4), a third switching unit 510, a third capacitive element (C3), and a fifth switch (SW5). Each of the switches (D3, D4) is connected between the supply node 340 and the one-bit shift node 520. In some embodiments, each of the switches (D3, D4) includes one or more diodes. In the example of Figure 5, each of the switches (D3, D4) includes a diode in the form of a diode-connected FET. The third switching unit 510 includes a pair of cross-coupled inverters 530, 540. The inverter 530 includes a first transistor and a second transistor (M1, M2) connected between the level shift node 520 and the reference node 350. Similarly, inverter 540 includes a third transistor and a fourth transistor (M3, M4) coupled between level shift node 520 and reference node 350. In the example of FIG. 5, the first transistor and the third transistor (M1, M3) are p-type FETs, and the second transistor and the fourth transistor (M2, M4) are n-type FETs. A first input node 550 is coupled to the second transistor (M2). A first output node 560 is connected between the third transistor (M3) and the fourth transistor (M4). A second input node 570 is coupled to the fourth transistor (M4). A second output node 580 is connected between the first transistor (M1) and the second transistor (M2). A third capacitive element (C3) (eg, a MOSCAP, a MIM capacitor, a combination of other types of capacitors, or the like) is coupled between the level shifting node 520 and the reference node 350. The fifth switch (SW5) is connected to the first node (N1) (see FIG. 3), the level shift node 520, and the second output node 580. As will be described below, the fifth switch (SW5) periodically connects the level shift node 520 to the first node (N1) in response to the fourth clock signal (CLK4). In this embodiment, the fifth switch (SW5) is an n-type FET. In some embodiments, the fifth switch (SW5) is a p-type FET. In other embodiments, the fifth switch (SW5) is any type of transistor (eg, a BJT) or other type of switch. The level shifter 120 circuits described above are for illustration only and other suitable level shifter 120 circuits are within the scope of the present disclosure. 6 is a flow chart of an exemplary method 600 of operation of a voltage multiplier 130 in accordance with some embodiments. For ease of understanding, the example method 600 will be described with further reference to FIGS. 1, 3, and 5. It should be appreciated that the method 600 can be applied to structures other than the structures of FIGS. 1, 3, and 5. Moreover, method 600 is not limited to the operations discussed below. Rather, the operations may be added/removed, the order of operations may be changed, the operations may be combined/separated, and/or the operations may be modified without departing from the scope of the disclosure. In operation 610, the clock generator 110 generates a first clock signal and a second clock signal based on a supply voltage (Vdd) (eg, 0.4 V), such as the first clock signal and the second clock in FIG. Signal (CLK1, CLK2). In operation 620, the voltage multiplier 130 generates a greater than supply voltage in response to the third clock signal and the fourth clock signal (eg, the third clock signal and the fourth clock signal (CL3K, CLK4) in FIG. 2) (Vdd) One of the node voltages (V _N1 ). FIG. 7 is a flow chart showing one exemplary operation 620 of method 600 in accordance with some embodiments. In operation 710, the first switching unit 310 receives a third clock signal (CLK3) that transitions from a low signal level to a high signal level, and thus in operation 720, the first switch (SW1) will be the first node (N1) is connected to the supply node 340 and the second switch (SW2) connects the second node (N2) to the reference node 350, whereby in operation 730, the first capacitive element (C1) is charged to the supply voltage (Vdd) ). At this time, the second switching unit 320 receives a low fourth clock signal (CLK4) level, and therefore, the third switch (SW3) disconnects the second node (N2) from the supply node 340 and the fourth switch (SW4) The first node (N1) is disconnected from the load node 330. Next, the first switching unit 310 receives the third clock signal (CLK3) that transitions from the high signal level back to the low signal level, and thus, the first switch (SW1) disconnects the first node (N1) from the supply node 340. The second switch (SW2) disconnects the second node (N2) from the reference node 350. After a specific time (eg, about 0.5 ns (t1)), in operation 740, the second switching unit 320 receives a fourth clock signal (CLK4) that transitions from a low signal level to a high signal level, and Thus in operation 750, the third switch (SW3) connects the second node (N2) to the supply node 340 and the fourth switch (SW4) connects the first node (N1) to the load node 330, whereby in operation 760 The first node (N1) receives a node voltage (V _N1 ) (eg, about 0.8 V), and the node voltage (V _N1 ) is substantially equal to the supply voltage (Vdd) at the supply node 340 and across the first capacitive element (C1) ) The sum of one of the charging voltages. Next, in operation 770, the second capacitive element (C2) is charged to a load voltage (Vload) that is substantially equal to one of the node voltages (V _N1 ), such as about 0.8 V. Thus, in operation 780, voltage doubler 130 drives load 190 at a load voltage (Vload) that is greater than (eg, about twice) the supply voltage (Vdd). Referring back to FIG. 6, in operation 630, the level shifter 120 shifts the first clock signal and the second clock signal (CLK1, CLK2) to be higher than the first time based on the node voltage (V _N1 ), respectively. The third clock signal and the fourth clock signal (CLK3, CLK4) at the level of the pulse signal and the second clock signal (CLK1, CLK2). FIG. 8 is a flow chart showing one exemplary operation 630 of method 600 in accordance with some embodiments. In operation 805, the supply node 340 receives the supply voltage (Vdd). This causes the switches (D3, D4) to be forward biased, and thus in operation 810, the switches (D3, D4) connect the level shift node 520 to the supply node 340, whereby in operation 815, the level shift Node 520 receives a level shift voltage (V _LS ) that is less than the supply voltage (Vdd) (ie, substantially equal to the difference between the supply voltage (Vdd) and the voltage drop across one of the switches (D3, D4). Next, the second input node 570 receives a second clock signal (CLK2) that transitions from a low signal level to a high signal level. This activates the fourth transistor (M4), and thus, the fourth transistor (M4) connects the first output node 560 to the reference node 350, whereby the first output node 560 outputs a low third clock signal (CLK3). Level. This in turn activates the first transistor (M1), and thus in operation 820, the first transistor (M1) connects the second output node 580 to the level shift node 520, whereby in operation 825, the second output Node 580 outputs a high fourth clock signal (CLK4) level. Next, in operation 830, the fifth switch (SW5) receives the high fourth clock signal (CLK4) level, and thus in operation 835, the fifth switch (SW5) connects the level shift node 520 to the first Node (N1), whereby in operation 840, the level shift node 520 receives the node voltage (V _N1 ). This increases the level shift voltage (V _LS ) to be substantially equal to the node voltage (V _N1 ), and thus, in operation 845, the third capacitive element (C3) is charged to a level shift voltage (V _{LS )} ). This in turn causes the switches (D3, D4) to be reverse biased, and thus in operation 850, the switches (D3, D4) disconnect the level shifting node 520 from the supply node 340. In a subsequent operation, the second input node 570 receives a second clock signal (CLK2) that transitions from a high signal level back to a low signal level. This disables the fourth transistor (M4), and thus, the fourth transistor (M4) disconnects the first output node 560 from the reference node 350. After a particular time (e.g., time (t1)), in operation 855, the first input node 550 receives a first clock signal (CLK1) that transitions from a low signal level to a high signal level. This activates the transistor (M2), and thus in operation 860, the second transistor (M2) connects the second output node 580 to the reference node 350, whereby in operation 865, the second output node 580 outputs a low Four-clock signal (CLK4) level. This in turn activates the third transistor (M3), and thus, the third transistor (M3) connects the first output node 560 to the level shift node 520, whereby the first output node 560 outputs a high third clock. Signal (CLK3) level. In an alternate embodiment, the level shifter 120 is configured to output a third clock signal (CLK3) from the second output node 580 and output a fourth clock signal (CLK4) from the first output node 560. In this alternative embodiment, the fifth switch (SW5) is coupled to the first output node 560 instead of the second output node 580. Referring back to FIG. 1, in some embodiments, device 100 does not include one of clock generator 110 and voltage multiplier 130. In some such embodiments, the clock generator 110 or voltage multiplier 130 can be coupled to the level shifter 120 external to the device 100. In one embodiment, a device includes a one-position shifter and a voltage doubler. The level shifter is configured to shift the first clock signal to be higher than one of the first clock signals based on a node voltage in response to a first clock signal. Clock signal. The voltage multiplier generates the node voltage in response to the second clock signal. The node voltage is output from the voltage multiplier to drive a load and further fed back to the level shifter to generate the second clock signal. In another embodiment, an apparatus includes a clock generator and a level shifter. The clock generator is configured to receive a supply voltage and generate a first clock signal based on the supply voltage. The level shifter is configured to receive a node voltage greater than the supply voltage and is responsive to the first clock signal configured to shift the first clock signal to be higher than the node voltage One of the first clock signals is one of the second clock signals. In another embodiment, a method includes: generating a first clock signal based on a supply voltage; generating a node voltage greater than one of the supply voltages in response to a second clock signal; The first clock signal is shifted to the second clock signal at a level higher than one of the first clock signals. Shifting the first clock signal to the second clock signal includes: receiving the node voltage at a quasi-shift node; periodically coupling an output node to the first clock signal a level shifting node; and outputting the second clock signal from the output node. The features of several embodiments have been summarized above so that those skilled in the art can better understand the aspects of the disclosure. Those skilled in the art will appreciate that the present disclosure can be readily utilized as a basis for designing or modifying other procedures and structures to achieve the same objectives and/or achieve the same advantages of the embodiments herein. It should be understood by those skilled in the art that the present invention is not to be construed as limited to the details of the invention.

100‧‧‧ device

110‧‧‧ Clock Generator

120‧‧‧ position shifter

130‧‧ ‧ Pressure multiplier

190‧‧‧load

310‧‧‧First switch unit

320‧‧‧Second switch unit

330‧‧‧Load node

340‧‧‧Supply node

350‧‧‧ reference node

410‧‧‧Substrate

420‧‧‧First Well Area

430‧‧‧Second well area

440‧‧‧Optoelectronics

440a‧‧‧ source area

440b‧‧‧Bungee area

440c‧‧‧ gate area

510‧‧‧3rd switch unit

520‧‧‧bit shift node

530‧‧‧Inverter

540‧‧‧Inverter

550‧‧‧first input node

560‧‧‧First output node

570‧‧‧second input node

580‧‧‧second output node

600‧‧‧ method

610‧‧‧ operation

620‧‧‧ operation

630‧‧‧ operation

710‧‧‧ operation

720‧‧‧ operation

730‧‧‧ operation

740‧‧‧ operation

750‧‧‧ operation

760‧‧‧ operation

770‧‧‧ operation

780‧‧‧ operation

805‧‧‧ operation

810‧‧‧ operation

815‧‧‧ operation

820‧‧‧ operation

825‧‧‧ operation

830‧‧‧ operation

835‧‧‧ operation

840‧‧‧ operation

845‧‧‧ operation

850‧‧‧ operation

855‧‧‧ operation

860‧‧‧ operation

865‧‧‧ operation

C1‧‧‧First capacitive element

C2‧‧‧Second capacitive element

C3‧‧‧ third capacitive element

CLK1‧‧‧ first clock signal

CLK2‧‧‧ second clock signal

CLK3‧‧‧ third clock signal

CLK4‧‧‧ fourth clock signal

D1‧‧‧ diode

D2‧‧‧ diode

D3‧‧‧ switch

D4‧‧‧ switch

M1‧‧‧first transistor

M2‧‧‧second transistor

M3‧‧‧ third transistor

M4‧‧‧ fourth transistor

N1‧‧‧ first node

N2‧‧‧ second node

SW1‧‧‧ first switch

SW2‧‧‧second switch

SW3‧‧‧ third switch

SW4‧‧‧fourth switch

SW5‧‧‧ fifth switch

Vdd‧‧‧ supply voltage

V _LOAD ‧‧‧Load voltage

V _LS ‧‧‧bit shift voltage

V _N1 ‧‧‧ node voltage

Vss‧‧‧reference voltage

The embodiment of the present invention is best understood from the following description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various components are not drawn to scale. In fact, the dimensions of the various components can be arbitrarily increased or decreased for clarity of discussion. 1 is a schematic block diagram of an illustrative device in accordance with some embodiments. 2A-2D are schematic timing diagrams showing an exemplary relationship between clock signals in accordance with some embodiments. 3 is a schematic circuit diagram of an exemplary voltage doubler in accordance with some embodiments. 4A is a schematic cross-sectional view of an illustrative capacitive element in accordance with some embodiments. 4B is a schematic circuit diagram of an exemplary capacitive element in accordance with some embodiments. FIG. 5 is a schematic circuit diagram of an exemplary level shifter in accordance with some embodiments. 6 is a flow chart of an exemplary method of operation of a voltage doubler in accordance with some embodiments. FIG. 7 is a flow chart showing an exemplary operation of one of the methods in accordance with some embodiments. FIG. 8 is a flow chart showing an exemplary operation of one of the methods in accordance with some embodiments.

Claims (1)

An apparatus comprising: a one-bit shifter configured to shift the first clock signal to be higher than the first clock signal based on a node voltage in response to a first clock signal a second clock signal; and a voltage doubler responsive to the second clock signal to generate the node voltage, wherein the node voltage is output from the voltage multiplier to drive a load and further feedback The level shifter is applied to the level to generate the second clock signal.