TW201901447A - Memory module and memory system including the same - Google Patents

Abstract

A memory module includes memory devices; data buffers suitable for receiving write data transferred from a memory controller and transmitting read data to the memory controller; a buffer control signal generation circuit suitable for generating buffer control signals for controlling the data buffers, by using a command transferred from the memory controller; a command delay circuit suitable for generating an effective command by delaying the command by a delay amount of the buffer control signal generation circuit in a read operation and a write operation; a data processing circuit suitable for processing write data transferred from the data buffers and transferring processed write data to the memory devices, and processing read data transferred from the memory devices and transferring processed read data to the data buffers, in response to the effective command; and a command buffer circuit suitable for transferring the effective command to the memory devices.

Description

Memory module and memory system including the same

The invention relates to a semiconductor device. In particular, the present invention relates to a memory module and a memory system including the same.

In recent years, as mobile communication terminals such as smartphones and tablet PCs have become popular, and social networking services (SNS), machine-to-machine (M2M) networks, and sensor networks have increased, the amount of data, Production speed and diversity are all increasing rapidly.

In order to process big data, not only the speed of the memory device is important, but the storage capacity of the memory device and the memory module including the memory device also needs to be large.

Various embodiments are intended to provide a technique for increasing the capacity of a memory module while enabling the memory module to work stably.

In one embodiment, a memory module may include: a plurality of memory devices; a plurality of data buffers, which are adapted to receive write data transmitted from the memory controller and transmit the read data to the memory control Buffer control signal generating circuit, adapted to generate a buffer control signal for controlling the plurality of data buffers based on a command transmitted from a memory controller; a command delay circuit, suitable for reading operations and The write operation generates a valid command based on the delay amount of the command delay buffer control signal generating circuit; the data processing circuit is adapted to process the write data transmitted from the plurality of data buffers in response to the valid command and The processed write data is transmitted to the plurality of memory devices, and is adapted to process the read data transmitted from the plurality of memory devices and transmit the processed read data to the plurality of data buffers. And a command buffer circuit, adapted to transmit valid commands to the plurality of memory devices.

In one embodiment, a memory system may include: a memory module; and a memory controller, which is adapted to transmit commands, addresses, and write data to the memory module, and is adapted to receive data from the memory module. To receive read data, the memory module includes: a plurality of memory devices; a plurality of data buffers, adapted to receive the write data transmitted from the memory controller and transmit the read data to the memory controller; the buffer A controller control signal generating circuit is adapted to generate a buffer control signal for controlling the plurality of data buffers based on the command; a command delay circuit is adapted to apply the command in a read operation and a write operation based on the command The delay buffer controls a delay amount of the signal generating circuit to generate a valid command. A data processing circuit is adapted to process the write data transmitted from the plurality of data buffers and transmit the processed write data in response to the valid command. To the plurality of memory devices, and adapted to process read data transmitted from the plurality of memory devices and process the processed data Reading data to the plurality of data buffers; and a command buffer circuit, adapted to transmit a valid command to the plurality of memory devices.

Cross-References to Related Applications: This application claims priority to Korean Application No. 10-2017-0062760, filed on May 22, 2017, which is incorporated herein by reference in its entirety.

Various embodiments will be described in more detail below with reference to the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and these embodiments will fully convey the scope of the invention to those skilled in the art. Throughout the present invention, the same element symbols always represent the same parts in the various drawings and embodiments of the present invention.

FIG. 1 is a diagram illustrating a configuration of a memory system according to an exemplary embodiment.

Referring to FIG. 1, the memory system may include a memory controller 1 and a memory module 100 of the host.

The memory controller 1 of the host can transmit the command CMD, address ADD and clock CLK to the memory module 100 to control the memory module 100, and can transmit data DATA to and from the memory module 100 The module 100 receives data DATA. The memory controller 1 may be included in a processor such as a central processing unit (CPU), a graphics processing unit (GPU), and an application processor (AP) or may exist in a separate semiconductor wafer outside the processor. The memory controller 1 may be adopted by various systems using a memory module 100 such as a PC, a server system, and a mobile system.

The memory module 100 may include a register clock driver (RCD) 110, a data buffer 120_0 ~ 120_7, and a memory device 130_0 ~ 130_7. The memory module 100 shown in FIG. 1 is called a load reduced dual in-line memory module (LRDIMM).

The temporary clock driver 110 can buffer the commands CMD, the address ADD and the clock CLK provided from the memory controller 1, and provide them to the memory devices 130_0 ~ 130_7. The temporarily stored clock driver 110 may also provide the clock CLK to the data buffers 120_0 to 120_7. In addition, the temporary clock driver 110 can process the information about the command CMD and the address ADD (which will be provided to the data buffers 120_0 ~ 120_7) into a form suitable for the buffer communication bus BCOM <0: 3>, And the processed information can be provided to the data buffers 120_0 ~ 120_7 via the buffer communication bus BCOM <0: 3>.

The data buffers 120_0 ~ 120_7 can receive data DATA from the memory controller 1 in a write operation and transfer data to the memory device 130_0 ~ 130_7, and can receive data DATA from the memory device 130_0 ~ 130_7 in a read operation And transfer the data to the memory controller 1. Since the data buffers 120_0 ~ 120_7 in the memory module 100 directly exchange data DATA with the memory controller 1, during the write operation, the data buffers 120_0 ~ 120_7 can be written from the memory controller 1 The data DATA is received from the memory controller 1 at a time when a write latency (WL) has passed from the moment of the command. In addition, in the read operation, the data buffers 120_0 ~ 120_7 can transmit data DATA to the memory controller at a time that has passed the CAS latency (CL) from the moment when the memory controller 1 applied the read command. 1. Therefore, the data buffers 120_0 ~ 120_7 may need information about the application time of the write command and the application command read time, and may provide information on the temporary clock driver 110 via the buffer communication bus BCOM <0: 3> Information on when the write and read commands are applied. In addition, the information for setting the data buffers 120_0 to 120_7 can be provided from the temporary clock driver 110 to the data buffers 120_0 to 120_7 via the buffer communication bus BCOM <0: 3>.

The memory devices 130_0 ~ 130_7 can work based on the commands CMD, address ADD, and clock CLK transmitted from the temporary clock driver 110, and can also work by transmitting and receiving data DATA through the data buffers 120_0 ~ 120_7. Each of the memory devices 130_0 to 130_7 may be one of various types of memory, such as dynamic random access memory (DRAM), resistive random access memory (resistive random access memory) access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), and magnetic random access memory (magnetic random access memory (MRAM).

In the figure, DATA_INT can represent a bus for transmitting data between the data buffers 120_0 ~ 120_7 and the memory device 130_0 ~ 130_7 in the memory module 100, and CMD / ADD / CLK_INT can represent the memory module 100 The command, address, and clock are transmitted from the temporary clock driver 110 to the buses of the memory devices 130_0 to 130_7, and CLK_INT can indicate that the clock is transmitted from the temporary clock driver 110 in the memory module 100 Bus for data buffers 120_0 ~ 120_7.

FIG. 2 is a timing diagram for a read operation according to an exemplary embodiment, in which a read command is transmitted to the memory devices 130_0 to 130_7 and the data buffers 120_0 to 120_7.

In FIG. 2, CMD may represent a command transmitted from the memory controller 1 to the temporary clock driver 110, and CMD_INT may represent a command transmitted from the temporary clock driver 110 to the memory device 130_0 to 130_7.

Referring to FIG. 2, at time 201, a read command RD may be transmitted from the memory controller 1 to the temporary clock driver 110.

Then, at a time 203 where three clocks have elapsed from time 201, the temporarily stored clock driver 110 may transmit the buffered read command RD to the memory devices 130_0 ~ 130_7. In addition, at the same time 203, the temporary clock driver 110 can transmit a read command in the form of a buffer control signal to be transmitted via the buffer communication bus BCOM <0: 3> to the data buffer 120_0 ~ 120_7. Among the buffer control signals to be transmitted via the buffer communication bus BCOM <0: 3>, RD may indicate a buffer control signal indicating that a read command has been applied, and DAT0 may indicate a selected memory bank. Buffer control signals, and PAR can indicate buffer control signals for parity check of read commands and data.

Referring to FIG. 2, at the same time 203 according to an exemplary embodiment, the temporary storage clock driver 110 transmits a read command informing that a read operation has been instructed from the memory controller 1 to the memory devices 130_0 to 130_7 and data Buffers 120_0 ~ 120_7. In the read operation, at the same time according to an exemplary embodiment, a notification that a read command has been applied may be transmitted to the memory devices 130_0 to 130_7 and the data buffers 120_0 to 120_7. One reason for this embodiment is as follows: When the read delay of the memory devices 130_0 ~ 130_7 and the read delay of the data buffers 120_0 ~ 120_7 match each other, the time of data output from the memory device 130_0 ~ 130_7 and the data buffer 120_0 The time when ~ 120_7 buffers the data output from the memory devices 130_0 ~ 130_7 and transfers it to the memory controller 1 is unlikely to mismatch each other.

FIG. 3 is a timing diagram for a write operation according to an example, in which a write command is transmitted to the memory devices 130_0 to 130_7 and the data buffers 120_0 to 120_7.

Referring to FIG. 3, at time 301, a write command WT may be transmitted from the memory controller 1 to the temporary clock driver 110.

Then, at a time 303 where three clocks have elapsed from time 301, the temporary storage clock driver 110 may transmit the buffered write command WT to the memory devices 130_0 to 130_7. In addition, at the same time 303, the temporary storage clock driver 110 may transmit a write command in the form of a buffer control signal to be transmitted via the buffer communication bus BCOM <0: 3> to the data buffer 120_0 ~ 120_7. Among the buffer control signals to be transmitted via the buffer communication bus BCOM <0: 3>, WT may indicate a buffer control signal indicating that a write command has been applied, and DAT0 may indicate a selected memory bank. Buffer control signals, and PAR can indicate buffer control signals for parity check of write commands and data.

Referring to FIG. 3, at the same time 303 according to an exemplary embodiment, the temporary storage clock driver 110 transmits a write command informing that a write operation has been instructed from the memory controller 1 to the memory devices 130_0 ~ 130_7 and data Buffers 120_0 ~ 120_7. In the write operation, similar to the read operation, at the same time according to one embodiment, a notification that a write command has been applied is transmitted to the memory devices 130_0 ~ 130_7 and the data buffers 120_0 ~ 120_7. One reason for this embodiment is as follows: When the write delay of the memory device 130_0 ~ 130_7 and the write delay of the data buffer 120_0 ~ 120_7 match each other, the data buffer 120_0 ~ 120_7 buffers the data transferred from the memory controller 1. Data and the time when the buffered data is transmitted to the memory device 130_0 ~ 130_7 and the time when the memory device 130_0 ~ 130_7 receives the data transmitted from the data buffer 120_0 ~ 120_7 will be less likely to mismatch each other.

FIG. 4 is a diagram illustrating a configuration of a memory system according to an exemplary embodiment.

Referring to FIG. 4, the memory system may include a memory controller 4 and a memory module 400 of the host.

The memory controller 4 of the host can transmit the command CMD, address ADD and clock CLK to the memory module 400 to control the memory module 400, and can transmit data DATA to the memory module 400 and from the memory. The module 400 receives data DATA. The memory controller 4 may be included in a processor such as a central processing unit (CPU), a graphics processing unit (GPU), and an application processor (AP) or may exist in a separate semiconductor wafer outside the processor. The memory controller 4 may be adopted by various systems using a memory module 400 such as a PC, a server system, and a mobile system.

The memory module 400 may include a module controller 410, a data buffer 420_0 ~ 420_7, and a memory device 430_0 ~ 430_7.

Each of the memory devices 430_0 to 430_7 may have a considerable capacity. To this end, according to one embodiment, each of the memory devices 430_0 to 430_7 may include a plurality of stacked memory chips. For example, each of the memory devices 430_0 to 430_7 may include eight memory chips, and the entire memory device 430_0 to 430_7 of the memory module 400 may include 64 memory chips. In the case where a plurality of memory chips are stacked to increase the capacity of the memory device 430_0 ~ 430_7, since the load increases and a large number of signal routing becomes difficult, the memory device 430_0 ~ The delay of 430_7 tends to increase, and there are several errors. Each of the memory devices 430_0 ~ 430_7 can be one of various types of memory, such as dynamic random access memory (DRAM), resistive random access memory (RRAM), phase change random access memory Memory (PRAM), ferroelectric random access memory (FRAM), and magnetic random access memory (MRAM).

The module controller 410 may buffer the command CMD, the address ADD, and the clock CLK provided from the memory controller 4, and provide them to the memory devices 430_0 ~ 430_7. The module controller 410 may also provide the clock CLK to the data buffers 420_0 ~ 420_7. In addition, the module controller 410 may process the information about the command CMD and the address ADD (which is to be provided to the data buffers 420_0 ~ 420_7) into a form suitable for the buffer communication bus BCOM <0: 3>, and The processed information can be provided to the data buffers 420_0 ~ 420_7 via the buffer communication bus BCOM <0: 3>. The operation of the above-mentioned module controller 410 may be the same as that of the temporary clock driver 110.

However, unlike the temporary clock driver 110, the module controller 410 may perform a function of transmitting data DATA between the data buffers 420_0 ~ 420_7 and the memory devices 430_0 ~ 430_7. In the write operation, the module controller 410 may generate an error correction code (ECC) by using the write data transmitted from the data buffers 420_0 to 420_7. The module controller 410 can transmit the write data and the error correction code to the memory devices 430_0 ~ 430_7, so that the write data and the error correction code can be written into the memory devices 430_0 ~ 430_7. In addition, during the reading operation, the module controller 410 can correct errors in the data read from the memory devices 430_0 ~ 430_7 by using the error correction codes read from the memory devices 430_0 ~ 430_7, and can correct the errors The read data is transferred to the data buffers 420_0 ~ 420_7. Therefore, data can be transmitted between the data buffers 420_0 ~ 420_7 and the module controller 410 via the internal data bus DATA_INT1, and data and error correction codes can be transmitted between the module controller 410 and the memory device via the internal data bus DATA_INT2 Transfer between 430_0 ~ 430_7. Through the error correction code generating operation and the correcting operation of the module controller 410, the errors that tend to increase in the memory devices 430_0 ~ 430_7 due to the expanded capacity and the stacked memory chips can be corrected.

In addition, in order to increase the data capacity of the memory devices 430_0 to 430_7, the module controller 410 may perform operations of compressing and decompressing data. For example, by compressing the data in the write operation and transmitting the compressed data to the memory device 430_0 ~ 430_7, and by decompressing the data read from the memory device 430_0 ~ 430_7 in the read operation and transmitting the decompressed data To the data buffers 420_0 ~ 420_7, a larger amount of data can be stored in the memory devices 430_0 ~ 430_7.

Different from the memory system of FIG. 2, in the memory system of FIG. 4, the module controller 410 and the data buffers 420_0 to 420_7 can directly transmit and receive data in a read operation and a write operation. Therefore, according to an embodiment, the data transmission and reception timing of the module controller 410 may need to match the data transmission and reception timing of the data buffers 420_0 to 420_7.

FIG. 5 is a diagram illustrating a configuration of a module controller 410 shown in FIG. 4 according to an exemplary embodiment.

5, the module controller 410 may include a buffer control signal generating circuit 510, a command delay circuit 520, an address delay circuit 530, a command buffer circuit 540, an address buffer circuit 550, a clock buffer circuit 560, and a data processing circuit. 570.

The buffer control signal generating circuit 510 can generate a buffer control signal for controlling the data buffers 420_0 to 420_7 by using a command CMD and an address ADD (that is, to be loaded into the buffer communication bus BCOM <0: 3> On the signal). The buffer control signal generating circuit 510 can convert the information necessary for the operation of the data buffers 420_0 ~ 420_7 from the information transmitted in the command CMD and the address ADD into a protocol conforming to the buffer communication bus BCOM <0: 3> Buffer control signal. All the bits of the address ADD or a part of the bits of the address ADD may be input to the buffer control signal generating circuit 510.

In the read operation and the write operation, the command delay circuit 520 may generate a valid command CMD_EFF by delaying the command CMD by the delay amount of the buffer control signal generating circuit 510. For example, if a three-clock delay occurs in the buffer control signal generating circuit 510 by using the command CMD and the address ADD to generate the buffer control signal, the command delay circuit 520 may delay the command CMD by three Clock to generate a valid command CMD_EFF. However, for commands other than read and write operations, the command delay circuit 520 may not delay the command CMD, but may simply generate a valid command CMD_EFF to be the same as the command CMD (for example, without any delay). In other words, for commands other than read operations and write operations, the delay value of the command delay circuit 520 may be set to zero. The command delay circuit 520 may distinguish a read operation and a write operation from other operations based on the received command CMD.

In the read operation and the write operation, the address delay circuit 530 may generate the effective address ADD_EFF by delaying the address ADD delay buffer control signal generating circuit 510. However, for commands other than read operations and write operations, the address delay circuit 530 may not delay the address ADD, but may only generate a valid address ADD_EFF to be the same as the address ADD. In other words, because the command delay circuit 520 may or may not delay the command CMD, the address delay circuit 530 may generate the effective address ADD_EFF by delaying or not delaying the address ADD in the same manner. The read / write signal RD / WT is a signal for instructing the delay circuit 520 to notify the address delay circuit of the read operation and the write operation. That is, the read / write signal RD / WT is a signal that is started in a read operation and a write operation.

The command buffer circuit 540 may buffer the valid command CMD_EFF and transmit the buffered command to the memory devices 430_0 to 430_7. The address buffer circuit 550 can buffer the effective address ADD_EFF and transfer the buffered address to the memory devices 430_0 ~ 430_7. The clock buffer circuit 560 can buffer the clock CLK transmitted from the memory controller 4 and transmit the buffered clock to the memory devices 430_0 to 430_7 and the data buffers 420_0 to 420_7. The commands buffered by the command buffer circuit 540, the addresses buffered by the address buffer circuit 550, and the clock buffered by the clock buffer circuit 560 can be transmitted to the memory devices 430_0 ~ 430_7 via the bus CMD / ADD / CLK_INT. In addition, the clock buffered by the clock buffer circuit 560 can be transferred to the data buffers 420_0 to 420_7 via the bus CLK_INT.

The data processing circuit 570 may include a first serial-to-parallel and parallel-to-serial conversion section 571, an error correction code generation section 572, an error correction section 573, a compression section 574, a decompression section 575, a selection section 576, and a second serial To parallel and parallel to serial conversion section 577 and data processing control section 578.

The first serial-to-parallel and parallel-to-serial conversion section 571 may perform serial-to-parallel conversion on the data DATA transmitted from the data buffers 420_0 to 420_7 in a write operation and transmit the converted data to the error correction code generation. The unit 572 may perform parallel-to-serial conversion on the data DATA transmitted from the error correction unit 573 in a read operation and transmit the converted data to the data buffers 420_0 to 420_7. This is to enable the error correction code generation section 572 and the error correction section 573 to process data in parallel, thereby reducing the time required to generate the error correction code ECC and correct the error.

In the writing operation, the error correction code generation section 572 may generate the error correction code ECC by using data DATA transmitted from the first serial-to-parallel and parallel-to-serial conversion section 571. In the reading operation, the error correction section 573 can correct any error in the data DATA by using the error correction code ECC transmitted from the second serial-to-parallel and parallel-to-serial conversion section 577 or the decompression section 575.

In the writing operation, the compression section 574 can compress the data DATA and the error correction code ECC, thereby reducing their number of bits. In the figure, the data DATA 'and the error correction code ECC' represent compressed copies of the data DATA and the error correction code ECC, respectively. The decompression section 575 can decompress the data DATA 'and the error correction code ECC' in a read operation.

The selection section 576 is a component for selecting whether to use the compression section 574 and the decompression section 575. In an embodiment in which the compression function is not used, the selection section 576 may electrically couple the error correction code generation section 572 and the error correction section 573 with the second serial-to-parallel and parallel-to-serial conversion section 577. In other words, the compression section 574 and the decompression section 575 may be bypassed. In an embodiment using a compression function, the selection section 576 may electrically couple the compression section 574 and the decompression section 575 with the second serial-to-parallel and parallel-to-serial conversion section 577.

The second serial-to-parallel and parallel-to-serial conversion section 577 may perform parallel-to-serial conversion of data and error correction codes in a write operation, and may perform serial-to-serial conversion of data and error correction codes in a read operation. Parallel conversion. In other words, the second serial-to-parallel and parallel-to-serial conversion section 577 can perform operations opposite to those of the first serial-to-parallel and parallel-to-serial conversion section 571.

The data processing control section 578 may control the operations and operation timings of the components 571 to 577 in the data processing circuit 570 in response to the valid command CMD_EFF. In the figure, the symbol CTRL between the data processing control unit 578 and the components 571 to 577 instructs the data processing control unit 578 to control the components 571 to 577. Since the timing control operation of the data processing control section 578 is not implemented in response to the command CMD, but is implemented in response to the effective command CMD_EFF, the data processing timing of the data processing control section 578 and the data processing timing of the data buffers 420_0 to 420_7 may Match each other. These two data processing timings are unlikely to mismatch each other, because the data buffers 420_0 ~ 420_7 respond to the control signals on the buffer communication bus BCOM <0: 3> (which has the same timing information as the valid command CMD_EFF) While working.

Although it is illustrated in FIG. 5 that the module controller 410 includes a buffer control signal generating circuit 510, a command delay circuit 520, an address delay circuit 530, a command buffer circuit 540, an address buffer circuit 550, a clock buffer circuit 560, and The data processing circuit 570, but it should be noted that depending on its design, some of them may be omitted. For example, in a case where an error correction operation is not required, the error correction code generation section 572 and the error correction section 573 may be omitted in the data processing circuit 570. In addition, in a case where a data compression operation is not required, the compression section 574, the decompression section 575, and the selection section 576 may be omitted in the data processing circuit 570.

In addition, although a buffer control signal generating circuit 510, a command delay circuit 520, an address delay circuit 530, a command buffer circuit 540, an address buffer circuit 550, a clock buffer circuit 560, and a data processing circuit 570 are illustrated in FIG. 5 It is included in the module controller 410, but it should be noted that some of them may be provided outside the module controller 410. In addition, each functional module (for example, delay circuits and sections) shown in FIG. 5 may include suitable circuit elements suitable for performing the above-mentioned functions. For example, the command delay circuit 520 may include a hardware circuit adapted to delay the received command CMD and output the delayed command CMD_EFF.

FIG. 6 is a timing diagram for a read operation in the memory module 400. In the read operation, a read command is transmitted to the data processing circuit 570 and the data buffers 420_0 to 420_7.

Referring to FIG. 6, at time 601, a read command RD may be transmitted from the memory controller 4 to the memory module 400.

Then, at time 603 where three clocks have elapsed from time 601, the buffer control signal (ie, the buffer control signal notifying the application of the read command RD) generated by the buffer control signal generating circuit 510 may pass through the buffer The communication bus BCOM <0: 3> is transmitted to the data buffers 420_0 ~ 420_7.

In addition, at the same time 603, a valid read command RD_EFF generated by the command delay circuit 520 may be transmitted to the data processing circuit 570.

Since the notification to which the read command RD has been applied is transmitted to the data buffers 420_0 to 420_7 and the data processing circuit 570 at the same time, the data buffers 420_0 to 420_7 and the data processing circuit 570 may not experience a timing mismatch. Transmission and reception of data.

FIG. 7 is a timing diagram for a write operation in the memory module 400. In the write operation, a write command is transmitted to the data processing circuit 570 and the data buffers 420_0 to 420_7.

Referring to FIG. 7, at time 701, a write command WT may be transmitted from the memory controller 4 to the memory module 400.

Then, at time 703 where three clocks have elapsed from time 701, the buffer control signal generated by the buffer control signal generating circuit 510 (ie, the buffer control signal notifying the application of the write command WT) may pass through the buffer The communication bus BCOM <0: 3> is transmitted to the data buffers 420_0 ~ 420_7.

In addition, at the same time 703, a valid write command WT_EFF generated by the command delay circuit 520 may be transmitted to the data processing circuit 570.

Since the notification that the write command WT has been applied is transmitted to the data buffers 420_0 ~ 420_7 and the data processing circuit 570 at the same time, the data buffers 420_0 ~ 420_7 and the data processing circuit 570 can not experience timing mismatch. Transmission and reception of data.

According to various embodiments, the memory module can be made to work stably while increasing the capacity of the memory module.

Although various embodiments have been described for the purpose of illustration, it will be apparent to those skilled in the art that various modifications can be made without departing from the spirit and scope of the invention as defined in the scope of the appended patent applications. Changes and modifications.

1‧‧‧Memory Controller

100‧‧‧Memory Module

110‧‧‧Temporary clock driver

120_0 ~ 120_7‧‧‧Data buffer

130_0 ~ 130_7‧‧‧Memory device

201‧‧‧time

203‧‧‧time

301‧‧‧time

303‧‧‧time

4‧‧‧Memory Controller

400‧‧‧Memory Module

410‧‧‧Module Controller

420_0 ~ 420_7‧‧‧Data buffer

430_0 ~ 430_7‧‧‧Memory device

510‧‧‧Buffer control signal generating circuit

520‧‧‧command delay circuit

530‧‧‧Address Delay Circuit

540‧‧‧command buffer circuit

550‧‧‧Address buffer circuit

560‧‧‧clock buffer circuit

570‧‧‧data processing circuit

571‧‧‧First serial-to-parallel and parallel-to-serial conversion unit

572‧‧‧Error correction code generation unit

573‧‧‧Error Correction Department

574‧‧‧Compression Department

575‧‧‧Decompression Department

576‧‧‧Selection Department

577‧‧‧Second serial-to-parallel and parallel-to-serial conversion unit

578‧‧‧Data Processing Control Department

601‧‧‧time

603‧‧‧ time

701‧‧‧time

703‧‧‧time

ADD‧‧‧Address

ADD_EFF‧‧‧Valid address

BCOM ＜ 0: 3 ＞ ‧‧‧Buffer communication bus

CLK‧‧‧ clock

CLK_INT‧‧‧Bus

CMD‧‧‧Order

CMD_EFF‧‧‧Valid Command

CMD_INT‧‧‧Command

CMD / ADD / CLK_INT‧‧‧Bus

CTRL‧‧‧Control

DATA‧‧‧Data

DATA’‧‧‧data

DAT0‧‧‧Buffer control signal

DATA_INT‧‧‧Bus

DATA_INT1‧‧‧ Internal data bus

DATA_INT2‧‧‧ Internal data bus

DB‧‧‧Data Buffer

ECC‧‧‧Error Correction Code

ECC’‧‧‧ Error Correction Code

P2S‧‧‧ Parallel to Serial

PAR‧‧‧Buffer control signal

RCD‧‧‧Temporary clock driver

RD‧‧‧Read command

RD_EFF‧‧‧Valid read command

S2P‧‧‧‧Serial to Parallel

WT‧‧‧Write command

WT_EFF‧‧‧Valid write command

FIG. 1 is a diagram illustrating a configuration of a memory system according to an embodiment. FIG. 2 is a timing diagram for a read operation in the memory module 100 according to an embodiment. FIG. 3 is a timing diagram for a write operation in the memory module 100 according to an embodiment. FIG. 4 is a diagram illustrating a configuration of a memory system according to an embodiment. FIG. 5 is a diagram illustrating a configuration of the module controller 410 shown in FIG. 4. FIG. 6 is a timing diagram for a read operation in the memory module 400 according to an embodiment. FIG. 7 is a timing diagram for a write operation in the memory module 400 according to an embodiment.

no

Claims (20)

A memory module includes: a plurality of memory devices; a plurality of data buffers, adapted to receive write data transmitted from the memory controller and transmit read data to the memory controller; buffer control signals A generation circuit adapted to generate a buffer control signal for controlling the plurality of data buffers based on a command transmitted from a memory controller; a command delay circuit adapted to perform a read operation and a write operation based on The command delay buffer controls the delay amount of the signal generating circuit to generate a valid command. The data processing circuit is adapted to process the write data transmitted from the plurality of data buffers and respond to the processed command in response to the valid command. Transmitting to the plurality of memory devices, and processing read data transmitted from the plurality of memory devices and transmitting the processed read data to the plurality of data buffers; and a command buffer circuit, applicable For transmitting a valid command to the plurality of memory devices. The memory module according to claim 1, wherein the command delay circuit is adapted to generate a valid command in an operation other than a read operation and a write operation to be the same as the command. The memory module according to claim 2, further comprising: an address delay circuit, adapted to generate a control signal generating circuit based on an address delay buffer transmitted from the memory controller during a read operation and a write operation. To generate an effective address; and an address buffer circuit, which is adapted to transmit the effective address to the plurality of memory devices. The memory module according to claim 3, wherein the address delay circuit is adapted to generate a valid address to be the same as the address in an operation other than a read operation and a write operation. The memory module according to claim 4, further comprising: a clock buffer circuit, adapted to transmit a clock transmitted from the memory controller to the plurality of memory devices. The memory module according to claim 1, wherein the buffer control signal generating circuit, the command delay circuit, the data processing circuit, and the command buffer circuit are included in a module controller. The memory module according to claim 1, wherein the data processing circuit includes: an error correction code generating unit, adapted to generate a request based on write data transmitted from the plurality of data buffers during a write operation. An error correction code stored in the plurality of memory devices together with the write data; and an error correction section adapted to correct the slave data based on the error correction code read from the plurality of memory devices in a read operation An error in the read data read by the plurality of memory devices. The memory module according to claim 7, wherein the data processing circuit further comprises: a compression unit adapted to compress the write data and the error correction code to be stored in the plurality of memory devices during a write operation. And a decompression unit, adapted to decompress the read data and the error correction code read from the plurality of memory devices in a read operation. The memory module according to claim 7, wherein the data processing circuit further comprises: a data processing control section adapted to control operations of the error correction code generating section and the error correction section in response to a valid command. The memory module according to claim 1, wherein each of the plurality of memory devices is a dynamic random access memory (DRAM), and wherein the memory module is dual In-line memory module (DIMM) type. A memory system includes: a memory module; and a memory controller, which is adapted to transmit commands, addresses, and write data to the memory module, and receive read data from the memory module. The group includes: a plurality of memory devices; a plurality of data buffers adapted to receive write data transmitted from the memory controller and to transmit read data to the memory controller; a buffer control signal generating circuit adapted to Generating a buffer control signal for controlling the plurality of data buffers based on the command; a command delay circuit, which is suitable for reading and writing operations based on delaying the command delay buffer control signal generating circuit A delay amount to generate a valid command; a data processing circuit adapted to process the write data transmitted from the plurality of data buffers in response to the valid command and transmit the processed write data to the plurality of memory devices , And processing the read data transmitted from the plurality of memory devices and transmitting the processed read data to the plurality of A data buffer; and a command buffer circuit, adapted to transmit a valid command to the plurality of memory devices. The memory system according to claim 11, wherein the command delay circuit is adapted to generate a valid command in an operation other than a read operation and a write operation as the command. The memory system according to claim 12, wherein the memory module further comprises: an address delay circuit, which is suitable for reading and writing operations based on an address delay buffer transmitted from the memory controller. The controller controls a delay amount of the signal generating circuit to generate an effective address; and an address buffer circuit is suitable for transmitting the effective address to the plurality of memory devices. The memory system according to claim 13, wherein the address delay circuit is adapted to generate a valid address as the address in an operation other than a read operation and a write operation. The memory system according to claim 14, wherein the memory module further comprises: a clock buffer circuit, which is adapted to transmit the clock transmitted from the memory controller to the plurality of memory devices. The memory system according to claim 15, wherein the buffer control signal generating circuit, the command delay circuit, the data processing circuit, the command buffer circuit, the address delay circuit, the address buffer circuit, and the clock buffer circuit are included in the memory. The module controller in the body module. The memory system according to claim 11, wherein the data processing circuit includes: an error correction code generating unit, adapted to generate, in a write operation, a write operation based on write data transmitted from the plurality of data buffers. Write data are stored in the plurality of memory devices together with an error correction code; and an error correction unit is adapted to correct, from the error correction codes read from the plurality of memory devices, a slave device in a read operation based on the error correction codes read from the plurality of memory devices; The errors in the read data read by the plurality of memory devices are described. The memory system according to claim 17, wherein the data processing circuit further comprises: a compression unit adapted to compress the write data and the error correction code to be stored in the plurality of memory devices during a write operation; And a decompression unit, adapted to decompress the read data and the error correction code read from the plurality of memory devices in a read operation. The memory system according to claim 18, wherein the data processing circuit further comprises: a data processing control section adapted to control operations of the error correction code generating section and the error correction section in response to a valid command. The memory system according to claim 11, wherein each of the plurality of memory devices is a dynamic random access memory (DRAM), and wherein the memory modules are dual-rank Dual in-line memory module (DIMM) type.