TW201909182A - Non-volatile memory device performing programming operation and operation method thereof - Google Patents

Abstract

A nonvolatile memory device includes: a plurality of word lines that are stacked; a vertical channel region suitable for forming a cell string along with the word lines; and a voltage supplier suitable for supplying a plurality of biases required for a program operation on the word lines, where a negative bias is applied to neighboring word lines disposed adjacent to a selected word line at an end of a pulsing section of a program voltage which is applied to the selected word line.

Description

Non-volatile memory device performing programming operation and operation method thereof

Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a non-volatile memory device that performs a programming operation.

Due to recent changes in the computing environment, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers has rapidly increased. These portable electronic devices typically use a memory system with a memory device (ie, a data storage device). The data storage device is used as a main memory device or an auxiliary memory device of a portable electronic device.

Data storage devices using memory devices provide good stability, durability, high information access speed, and low power consumption due to the lack of mobile components. Examples of a data storage device having these advantages include a universal serial bus (USB) memory device, a memory card with various interfaces, and a solid state drive (SSD).

Various embodiments are directed to a non-volatile memory device capable of suppressing a shift in a cell threshold voltage (ie, Z due to a charge trapped in a region between adjacent word lines due to a marginal field generated in a programming operation, that is, Z -interference).

In one embodiment, a non-volatile memory device includes: a plurality of stacked word lines; a vertical channel region adapted to form a cell string with the word lines; and a voltage supply unit adapted to supply counter words A plurality of bias voltages required for a programming operation of a meta line, wherein, at an end of a pulse section of a program voltage applied to a selected word line, a negative bias is applied to the phase of the selected word line. Adjacent character lines.

In one embodiment, a method for operating a non-volatile memory device having a plurality of word lines forming a cell string includes applying a programming voltage to a selected word line and applying a pass voltage to an unselected And a negative bias voltage is applied to the adjacent word lines adjacent to the selected word line among the unselected word lines while applying the programming voltage to the selected word lines. Yuan line.

Cross-References to Related Applications: This application claims priority from US Provisional Patent Application No. 62 / 526,632 entitled "PROGRAMMING METHOD FOR REDUCING CHARGE-TRAPPING BETWEEN ADJACENT WORD LINES" filed on June 29, 2017, It is incorporated herein by reference in its entirety.

Various embodiments will be described in more detail below with reference to the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout the present invention, the same drawing reference numerals represent the same components in the various drawings and embodiments of the present invention.

FIG. 1 is a block diagram illustrating a data processing system including a memory system according to an embodiment.

Referring to FIG. 1, the data processing system 100 may include a host 102 and a memory system 110.

The host 102 may include, for example, a portable electronic device such as a mobile phone, an MP3 player, and a laptop computer, or an electronic device such as a desktop computer, a game console, a television, and a projector.

The memory system 110 may operate in response to a request from the host 102, and specifically, stores data to be accessed by the host 102. That is, the memory system 110 may serve as a main memory system or an auxiliary memory system of the host 102. According to a host interface protocol that is electrically coupled to the host 102, the memory system 110 may be implemented using any one of various storage devices. The memory system 110 may use various memory devices such as a solid state drive (SSD), a multimedia card (MMC), an embedded MMC (eMMC), a reduced size MMC (RS-MMC) and a miniature MMC, a secure digital (SD) card , Mini SD, micro SD, universal serial bus (USB) storage device, universal flash memory storage (UFS) device, compact flash memory (CF) card, smart media (SM) card, memory stick, etc.) To achieve any of them.

The storage device for the memory system 110 may be a volatile memory device (such as dynamic random access memory (DRAM) and static random access memory (SRAM)) or a non-volatile memory device (such as: Read memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric random access memory (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM) and resistive RAM (RRAM)).

The memory system 110 may include a memory device 150 that stores data to be accessed by the host 102 and a controller 130 that may control the storage of data in the memory device 150.

The controller 130 and the memory device 150 may be integrated into one semiconductor device. For example, the controller 130 and the memory device 150 may be integrated into one semiconductor device to configure a solid-state hard disk (SSD). When the memory system 110 is used as an SSD, the operation speed of the host 102 electrically coupled with the memory system 110 can be significantly increased.

The controller 130 and the memory device 150 may be integrated into one semiconductor device to configure a memory card. The controller 130 and the memory device 150 may be integrated into a semiconductor device to configure a memory card (such as a personal computer memory card international association (PCMCIA) card, a compact flash memory (CF) card, a smart media (SM) card (SMC), memory stick, multimedia card (MMC), RS-MMC, micro MMC, secure digital (SD) card, mini SD, micro SD, SDHC, and universal flash memory storage (UFS) device).

As another example, the memory system 110 may be configured with a computer, a UMPC, a workstation, a small laptop, a personal digital assistant (PDA), a portable computer, a network tablet, a tablet computer, a wireless phone, a mobile phone, and a smart phone. Mobile phones, e-books, portable multimedia players (PMP), portable game consoles, navigation equipment, black boxes, digital cameras, digital multimedia broadcast (DMB) players, three-dimensional (3D) televisions, smart TVs, digital recorders, digital audio players , Digital picture recorder, digital picture player, digital video recorder, digital video player, storage that configures the data center, equipment that can send and receive information in a wireless environment, one of various electronic devices that configure a home network, One of various electronic devices configured with a computer network, one of various electronic devices configured with a remote information processing network, an RFID device, or one of various constituent elements configured with a computing system.

The memory device 150 of the memory system 110 can retain the stored data when the power is interrupted, and specifically, stores the data provided from the host 102 during the write operation, and provides the stored data to the read operation during the read operation. Host 102. The memory device 150 may include a plurality of memory blocks, a memory block 152, a memory block 154, and a memory block 156. Each of the memory blocks 152, 154, and 156 may include a plurality of pages. Each page may include a plurality of memory cells electrically coupled to a plurality of word lines (WL). The memory device 150 may be a non-volatile memory device (eg, a flash memory). The flash memory may have a three-dimensional (3D) stacked structure. The structure of the memory device 150 and the three-dimensional (3D) stacked structure of the memory device 150 will be described in detail later with reference to FIGS. 2 to 11.

The controller 130 of the memory system 110 may control the memory device 150 in response to a request from the host 102. The controller 130 may provide data read from the memory device 150 to the host 102 and store data provided from the host 102 into the memory device 150. Accordingly, the controller 130 may control overall operations (such as a read operation, a write operation, a program operation, and an erase operation) of the memory device 150.

Specifically, the controller 130 may include a host interface unit 132, a processor 134, an error correction code (ECC) unit 138, a power management unit 140 (PMU), a NAND flash memory controller 142 (NFC), and a memory 144.

The host interface unit 132 can process commands and data provided from the host 102, and can pass various interface protocols such as universal serial bus (USB), multimedia card (MMC), peripheral component interconnect express (PCI-E), serial attachment Connect at least one of SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Device Circuit (IDE) A communication with the host 102.

The ECC unit 138 may detect and correct errors in the data read from the memory device 150 during a read operation. When the number of error bits is greater than or equal to the threshold number of correctable error bits, the ECC unit 138 may not correct the error bits, and may output an error correction failure signal indicating that the error bit correction failed.

The ECC unit 138 may be based on coded modulations such as low density parity check (LDPC) codes, Boss-Johry-Hockvenheim (BCH) codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, Recursive system code (RSC), trellis coded modulation (TCM), block coded modulation (BCM), etc.) to perform error correction operations. The ECC unit 138 may include all circuits, systems, or devices for error correction operations.

The PMU 140 may provide and manage power for the controller 130 (ie, power for constituent elements included in the controller 130).

The NFC 142 may serve as a memory interface between the controller 130 and the memory device 150 to allow the controller 130 to control the memory device 150 in response to a request from the host 102. The NFC 142 may generate a control signal for the memory device 150, and when the memory device 150 is a flash memory, and specifically, when the memory device 150 is a NAND flash memory, the NFC 142 may be at the processor 134 Processing data under the control of

The memory 144 can be used as a working memory of the memory system 110 and the controller 130, and stores data for driving the memory system 110 and the controller 130. The controller 130 may control the memory device 150 in response to a request from the host 102. For example, the controller 130 may provide data read from the memory device 150 to the host 102 and store the data provided from the host 102 in the memory device 150. When the controller 130 controls the operation of the memory device 150, the memory 144 may store data used by the controller 130 and the memory device 150 for such operations (such as a read operation, a write operation, a program operation, and an erase operation). data.

The memory 144 may be implemented by a volatile memory. The memory 144 may be implemented by a static random access memory (SRAM) or a dynamic random access memory (DRAM). As described above, the memory 144 may store data used by the host 102 and the memory device 150 for read operations and write operations. To store data, the memory 144 may include a programming memory, a data memory, a write buffer, a read buffer, a mapping buffer, and the like.

In response to a write request or a read request from the host 102, the processor 134 can control the overall operation of the memory system 110 and the write operation or read operation for the memory device 150. The processor 134 may drive firmware (which is referred to as a flash translation layer (FTL)) to control the overall operation of the memory system 110. The processor 134 may be implemented by a microprocessor or a central processing unit (CPU).

A management unit (not shown) may be included in the processor 134 and may perform bad block management of the memory device 150. The management unit may discover bad memory blocks (which are in an unsatisfactory state in further use) included in the memory device 150 and perform bad block management on the bad memory blocks. When the memory device 150 is a flash memory (for example, a NAND flash memory), a programming failure may occur during a write operation (for example, during a program operation) due to characteristics of a NAND logic function. During bad block management, the data of failed memory blocks or bad memory blocks can be programmed into new memory blocks. In addition, a bad memory block due to a programming failure severely degrades the utilization rate of the memory device 150 having a 3D stacked structure and the reliability of the memory system 100, and therefore, reliable bad block management is required.

FIG. 2 is a schematic diagram illustrating the memory device 150 shown in FIG. 1.

Referring to FIG. 2, the memory device 150 may include a plurality of memory blocks, such as the 0th block to the (N-1) th block 210 to 240. Each of the plurality of memory blocks 210 to 240 may include a plurality of pages, for example, 2 ^M pages (2 ^M pages), and the present invention is not limited thereto. Each of the plurality of pages may include a plurality of memory cells electrically coupled to a plurality of word lines.

In addition, according to the number of bits that can be stored or expressed in each memory cell, the memory device 150 may include a plurality of memory blocks, such as a unit quasi-cell (SLC) memory block and a multi-level cell (MLC) ) Memory block. The SLC memory block may include a plurality of pages implemented with a plurality of memory cells capable of storing 1-bit data per memory cell. The MLC memory block may include a plurality of pages implemented with a plurality of memory cells capable of storing multi-bit data (for example, two-bit data or more) per memory cell. An MLC memory block including a plurality of pages implemented with a plurality of memory cells capable of storing 3 bits of data per memory cell may be defined as a TLC memory block.

Each of the plurality of memory blocks 210-240 can store data provided from the host 102 during a write operation, and can provide the stored data to the host 102 during a read operation.

FIG. 3 is a circuit diagram showing one memory block among the plurality of memory blocks 152 to 156 shown in FIG. 1.

Referring to FIG. 3, the memory block 152 of the memory device 150 may include a plurality of cell strings 340 electrically coupled to the bit lines BL0-BLm-1, respectively. The cell string 340 of each row may include at least one drain selection transistor DST and at least one source selection transistor SST. The plurality of memory cells or the plurality of memory cell transistors MC0 ~ MCn-1 may be electrically coupled in series between the selection transistor DST and the selection transistor SST. Each memory cell MC0 ~ MCn-1 can be configured by a multi-level cell (MLC), and each multi-level cell stores a plurality of bits of data information. The strings 340 may be electrically coupled to the corresponding bit lines BL0 ~ BLm-1, respectively. For reference, in FIG. 3, "DSL" indicates a drain selection line, "SSL" indicates a source selection line, and "CSL" indicates a common source line.

Although FIG. 3 shows a memory block 152 configured by a NAND flash memory unit as an example, it should be noted that the memory block 152 of the memory device 150 according to this embodiment is not limited to a NAND flash memory. And it can be implemented by a NOR flash memory, a hybrid flash memory combining at least two memory units, or a single NAND flash memory whose controller is built into a memory chip. The operating characteristics of the semiconductor device can be applied not only to a flash memory device in which the charge storage layer is configured by a conductive floating gate, but also to a charge trapping flash memory (CTF) in which the charge storage layer is configured of a dielectric layer.

The voltage supply 310 of the memory device 150 may provide a word line voltage (for example, a programming voltage, a read voltage, and a pass voltage) to be supplied to a corresponding word line according to an operation mode, and a block (for example, forming a Well region of the memory cell). The voltage supplier 310 may perform a voltage generating operation under the control of a control circuit (not shown). The voltage supply 310 can generate a plurality of variable read voltages to generate a plurality of read data. Under the control of the control circuit, one of the memory blocks or sections in the memory cell array is selected, and the selected memory is selected. One of the character lines of the volume block, and the character line voltage is provided to the selected character line and the unselected character line.

The read / write circuit 320 of the memory device 150 may be controlled by a control circuit, and may function as a sense amplifier or a write driver according to an operation mode. During the verify / normal read operation, the read / write circuit 320 can function as a sense amplifier for reading data from the memory cell array. In addition, during a programming operation, the read / write circuit 320 may function as a write driver that drives a bit line according to data to be stored in a memory cell array. During a programming operation, the read / write circuit 320 may receive data to be written into the memory cell array from a buffer (not shown), and may drive a bit line according to the inputted data. The read / write circuit 320 may include a plurality of page buffers corresponding to a row or bit line or a pair of rows or pair of bit lines, respectively, a page buffer 322, a page buffer 324, and a page buffer. 326, and a plurality of latches (not shown) may be included in each of the page buffer 322, the page buffer 324, and the page buffer 326.

4 to 11 are schematic diagrams illustrating the memory device 150 shown in FIG. 1.

FIG. 4 is a block diagram illustrating an example of a plurality of memory blocks 152 to 156 of the memory device 150 shown in FIG. 1.

Referring to FIG. 4, the memory device 150 may include a plurality of memory blocks BLK0 ~ BLKN-1, and each of the memory blocks BLK0 ~ BLKN-1 may have a three-dimensional (3D) structure or a vertical structure to realise. Each of the memory blocks BLK0 to BLKN-1 may include a structure extending in a first direction to a third direction (for example, an x-axis direction, a y-axis direction, and a z-axis direction).

Each memory block BLK0 ~ BLKN-1 may include a plurality of NAND strings NS extending in the second direction. A plurality of NAND strings NS can be set in the first direction and the third direction. Each NAND string NS may be electrically coupled to a bit line BL, at least one source selection line SSL, at least one ground selection line GSL, a plurality of word lines WL, at least one dummy word line DWL, and a common source line CSL. That is, each memory block BLK0 ~ BLKN-1 can be electrically coupled to a plurality of bit lines BL, a plurality of source selection lines SSL, a plurality of ground selection lines GSL, a plurality of character lines WL, and a plurality of dummy words. The element line DWL and a plurality of common source lines CSL.

FIG. 5 is a perspective view of one memory block BLKi among the plurality of memory blocks BLK0 to BLKN-1 shown in FIG. 4. FIG. 6 is a cross-sectional view taken along a line I-I 'of the memory block BLKi shown in FIG. 5. FIG.

Referring to FIGS. 5 and 6, the memory block BLKi among the plurality of memory blocks of the memory device 150 may include a structure extending in a first direction to a third direction.

A substrate 5111 may be provided. The substrate 5111 may include a silicon material doped with a first type of impurity. The substrate 5111 may include a silicon material doped with a p-type impurity, or may be a p-type well (for example, a pouch-shaped p-well) and include an n-type well surrounding the p-type well. Although it is assumed that the substrate 5111 is p-type silicon, it should be noted that the substrate 5111 is not limited to p-type silicon.

A plurality of doped regions 5311 to 5314 extending in the first direction may be provided on the substrate 5111. The plurality of doped regions 5311 to 5314 may include a second type of impurity different from the substrate 5111. The plurality of doped regions 5311 to 5314 may be doped with n-type impurities. Although the first to fourth doped regions 5311 to 5314 are n-type in this embodiment, it should be noted that the first to fourth doped regions 5311 to 5314 are not limited to n-type.

In a region between the first doped region 5311 and the second doped region 5312 above the substrate 5111, the plurality of dielectric materials 5112 extending in the first direction may be sequentially disposed in the second direction. The dielectric material 5112 and the substrate 5111 may be separated from each other by a predetermined distance in the second direction. The dielectric materials 5112 may be separated from each other by a predetermined distance in the second direction. The dielectric material 5112 may include a dielectric material such as silicon oxide.

In the region between the first doped region 5311 and the second doped region 5312 above the substrate 5111, a plurality of sequentially arranged in the first direction and passing through the dielectric material 5112 in the second direction may be provided. Post 5113. The plurality of pillars 5113 may pass through the dielectric material 5112 and may be electrically coupled to the substrate 5111, respectively. Each pillar 5113 may be composed of a variety of materials. The surface layer 5114 of each pillar 5113 may include a silicon material doped with a first type impurity. The surface layer 5114 of each pillar 5113 may include a silicon material doped with the same type of impurities as the substrate 5111. Although it is assumed herein that the surface layer 5114 of each pillar 5113 may include p-type silicon, the surface layer 5114 of each pillar 5113 is not limited to be p-type silicon.

The inner layer 5115 of each pillar 5113 may be formed of a dielectric material. The inner layer 5115 of each pillar 5113 may be filled with a dielectric material such as silicon oxide.

In a region between the first doped region 5311 and the second doped region 5312, a dielectric layer 5116 may be disposed along the exposed surfaces of the dielectric material 5112, the pillar 5113, and the substrate 5111. The thickness of the dielectric layer 5116 may be less than half the distance between the dielectric materials 5112. That is, a region in which materials other than the dielectric material 5112 and the dielectric layer 5116 may be disposed may be provided on (i) the dielectric layer 5116 provided above the bottom surface of the first dielectric material of the dielectric material 5112 and (ii) provided on the dielectric The material 5112 is between the dielectric layers 5116 above the top surface of the second dielectric material. A dielectric material 5112 is located below the first dielectric material.

In a region between the first doped region 5311 and the second doped region 5312, conductive materials 5211 to 5291 may be disposed above the exposed surface of the dielectric layer 5116. The conductive material 5211 extending in the first direction may be disposed between the dielectric material 5112 and the substrate 5111 adjacent to the substrate 5111. Specifically, the conductive material 5211 extending in the first direction may be provided on (i) a dielectric layer 5116 provided above the substrate 5111 and (ii) a dielectric provided above a bottom surface of the dielectric material 5112 adjacent to the substrate 5111. Between layers 5116.

The conductive material extending in the first direction may be provided on (i) a dielectric layer 5116 provided above a top surface of one of the dielectric materials 5112 and (ii) a bottom of another dielectric material provided on the dielectric material 5112. Between the dielectric layers 5116 above the surface, the conductive material is arranged above a certain dielectric material 5112. The conductive materials 5221 to 5281 extending in the first direction may be disposed between the dielectric materials 5112. A conductive material 5291 extending in the first direction may be disposed above the uppermost dielectric material 5112. The conductive materials 5211 to 5291 extending in the first direction may be metal materials. The conductive materials 5211 to 5291 extending in the first direction may be conductive materials such as polycrystalline silicon.

In the region between the second doped region 5312 and the third doped region 5313, the same structure as that between the first doped region 5311 and the second doped region 5312 may be provided. For example, in a region between the second doped region 5312 and the third doped region 5313, a plurality of dielectric materials 5112 extending in the first direction may be provided in sequence and arranged in the first direction. A plurality of pillars 5113 passing through the plurality of dielectric materials 5112 in two directions, a dielectric layer 5116 disposed above the exposed surfaces of the plurality of dielectric materials 5112 and the plurality of pillars 5113, and a plurality of conductive materials extending in the first direction 5212 ~ 5292.

In the region between the third doped region 5313 and the fourth doped region 5314, the same structure as that between the first doped region 5311 and the second doped region 5312 may be provided. For example, in a region between the third doped region 5313 and the fourth doped region 5314, a plurality of dielectric materials 5112 extending in the first direction may be provided in sequence and arranged in the first direction. A plurality of pillars 5113 passing through the plurality of dielectric materials 5112 in two directions, a dielectric layer 5116 disposed above the exposed surfaces of the plurality of dielectric materials 5112 and the plurality of pillars 5113, and a plurality of conductive materials extending in the first direction 5213 ~ 5293.

The drain electrodes 5320 may be respectively disposed above the plurality of pillars 5113. The drain 5320 may be a silicon material doped with a second type of impurity. The drain 5320 may be a silicon material doped with an n-type impurity. Although the drain 5320 includes n-type silicon in this embodiment, it should be noted that the drain 5320 is not limited to being n-type silicon. In addition, the width of each drain electrode 5320 may be larger than the width of each corresponding pillar 5113. Each drain electrode 5320 may be provided in the shape of a pad above the top surface of each corresponding pillar 5113.

The conductive materials 5331 to 5333 extending in the third direction may be disposed above the drain electrode 5320. The conductive materials 5331 to 5333 may be sequentially arranged in the first direction. Each of the conductive materials 5331 to 5333 may be electrically coupled to the drain 5320 of the corresponding region. The drain electrode 5320 and the conductive materials 5331 to 5333 extending in the third direction can be electrically coupled through the contact plug. The conductive materials 5331 to 5333 extending in the third direction may be metal materials. The conductive materials 5331 to 5333 extending in the third direction may be conductive materials such as polycrystalline silicon.

In FIGS. 5 and 6, each pillar 5113 may form a string together with the dielectric layer 5116 and conductive materials 5211 to 5291, conductive materials 5212 to 5292, and conductive materials 5213 to 5293 extending in the first direction. Each pillar 5113 may form a NAND string NS together with the dielectric layer 5116 and the conductive materials 5211 to 5291, the conductive materials 5212 to 5292, and the conductive materials 5213 to 5293 extending in the first direction. Each NAND string NS may include a plurality of transistor structures TS.

FIG. 7 is a cross-sectional view of the transistor structure TS shown in FIG. 6.

Referring to FIG. 7, in the transistor structure TS shown in FIG. 6, the dielectric layer 5116 may include a first sub-dielectric layer 5117, a second sub-dielectric layer 5188, and a third sub-dielectric layer 5119.

A surface layer 5114 of p-type silicon in each pillar 5113 can be used as a main body. The first sub-dielectric layer 5117 adjacent to the pillar 5113 may serve as a tunneling dielectric layer, and may include a thermal oxide layer.

The second sub-dielectric layer 5118 may serve as a charge storage layer. The second sub-dielectric layer 5118 may serve as a charge trapping layer, and may include a nitride layer or a metal oxide layer (such as an aluminum oxide layer, a hafnium oxide layer, etc.).

The third sub-dielectric layer 5119 adjacent to the conductive material 5233 may serve as a blocking dielectric layer. The third sub-dielectric layer 5119 adjacent to the conductive material 5233 extending in the first direction may be formed as a single layer or multiple layers. The third sub-dielectric layer 5119 may be a high-k dielectric layer (such as an aluminum oxide layer, a hafnium oxide layer, etc.), which has a larger dielectric constant than the first and second sub-dielectric layers 5117 and 5118.

The conductive material 5233 can be used as a gate or a control gate. That is, the gate or control gate 5233, the blocking dielectric layer 5119, the charge storage layer 5118, the tunneling dielectric layer 5117, and the main body 5114 may form a transistor or a memory cell transistor structure. For example, the first to third sub-dielectric layers 5117 to 5119 may form an oxide-nitride-oxide (ONO) structure. In this embodiment, for convenience, the surface layer 5114 of the p-type silicon in each pillar 5113 will be referred to as the main body in the second direction.

The memory block BLKi may include a plurality of pillars 5113. That is, the memory block BLKi may include a plurality of NAND strings NS. Specifically, the memory block BLKi may include a plurality of NAND strings NS extending in the second direction or a direction perpendicular to the substrate 5111.

Each NAND string NS may include a plurality of transistor structures TS arranged in the second direction. At least one transistor structure in the plurality of transistor structures TS of each NAND string NS can be used as a string source transistor SST. At least one transistor structure in the plurality of transistor structures TS of each NAND string NS may be used as a ground selection transistor GST.

The gate electrode or the control gate electrode may correspond to conductive materials 5211 to 5291, conductive materials 5212 to 5292, and conductive materials 5213 to 5293 extending in the first direction. That is, the gate or control gate may extend in the first direction and form a word line, at least two selection lines, at least one source selection line SSL, and at least one ground selection line GSL.

The conductive materials 5331 to 5333 extending in the third direction may be electrically coupled to one end of the NAND string NS. The conductive materials 5331 to 5333 extending in the third direction can be used as the bit line BL. That is, in one memory block BLKi, a plurality of NAND strings NS may be electrically coupled to one bit line BL.

The second type doped regions 5311 to 5314 extending in the first direction may be provided to the other end of the NAND string NS. The second type doped regions 5311 to 5314 extending in the first direction can serve as the common source line CSL.

In addition, the memory block BLKi may include a plurality of NAND strings NS extending in a direction (such as a second direction) perpendicular to the substrate 5111, and may be a NAND flash memory block such as a charge trapping memory, The plurality of NAND strings NS are electrically coupled to one bit line BL.

Although the conductive materials 5211 to 5291, the conductive materials 5212 to 5292, and the conductive materials 5213 to 5293 that are extended in the first direction are shown in FIGS. 5 to 7 as being provided in 9 layers, it should be noted that The conductive materials 5211 to 5291, the conductive materials 5212 to 5292, and the conductive materials 5213 to 5293 extending in the direction are not limited to being provided in 9 layers. For example, the conductive material extending in the first direction may be provided as 8 layers, 16 layers, or any multilayer. That is, in one NAND string NS, the number of transistors may be 8, 16, or more.

Although it is shown in FIG. 5 to FIG. 7 that 3 NAND strings NS are electrically coupled to one bit line BL, it should be noted that this embodiment is not limited to a circuit having 3 bits electrically coupled to one bit line BL. NAND strings NS. In the memory block BLKi, m NAND strings NS may be electrically coupled to one bit line BL, and m is a positive integer. According to the number of NAND strings NS electrically coupled to one bit line BL, the number of conductive materials 5211 ~ 5291, conductive materials 5212 ~ 5292, and conductive materials 5213 ~ 5293 extending in the first direction, and the common source line 5311 ~ The number of 5314 can also be controlled.

In addition, although three NAND strings NS are electrically coupled to one conductive material extending in the first direction in FIG. 5 to FIG. 7, it should be noted that this embodiment is not limited to having electrically coupled to Three NAND strings NS of one conductive material extending in the first direction. For example, n NAND strings NS may be electrically coupled to one conductive material extending in the first direction, and n is a positive integer. According to the number of NAND strings NS electrically coupled to one conductive material extending in the first direction, the number of bit lines 5331 to 5333 can also be controlled.

FIG. 8 is an equivalent circuit diagram showing a memory block BLKi having a first structure described with reference to FIGS. 5 to 7.

Referring to FIG. 8, in the memory block BLKi having the first structure, the NAND strings NS11 to NS31 may be disposed between the first bit line BL1 and the common source line CSL. The first bit line BL1 may correspond to the conductive material 5331 extending in the third direction in FIGS. 5 and 6. The NAND strings NS12 to NS32 may be disposed between the second bit line BL2 and the common source line CSL. The second bit line BL2 may correspond to the conductive material 5332 extending in the third direction in FIGS. 5 and 6. The NAND strings NS13 to NS33 may be disposed between the third bit line BL3 and the common source line CSL. The third bit line BL3 may correspond to the conductive material 5333 extending in the third direction in FIGS. 5 and 6.

The source selection transistor SST of each NAND string NS may be electrically coupled to a corresponding bit line BL. The ground selection transistor GST of each NAND string NS may be electrically coupled to a common source line CSL. The memory cell MC may be disposed between the source selection transistor SST and the ground selection transistor GST of each NAND string NS.

In this example, the NAND string NS may be defined by a unit of rows and columns, and the NAND string NS electrically coupled to one bit line may form one row. The NAND strings NS11 ~ NS31 electrically coupled to the first bit line BL1 may correspond to the first row, and the NAND strings NS12 ~ NS32 electrically coupled to the second bit line BL2 may correspond to the second row, and are electrically coupled The NAND strings NS13 to NS33 to the third bit line BL3 may correspond to the third row. The NAND strings NS electrically coupled to one source selection line SSL may form a column. The NAND strings NS11 ~ NS13 electrically coupled to the first source selection line SSL1 can form a first column, and the NAND strings NS21 ~ NS23 electrically coupled to the second source selection line SSL2 can form a second column, and are electrically coupled The NAND strings NS31 to NS33 to the third source selection line SSL3 may form a third column.

In each NAND string NS, a height can be defined. In each NAND string NS, the height of the memory cell MC1 adjacent to the ground selection transistor GST may have a value of "1". In each NAND string NS, since the memory cell is closer to the source selection transistor SST when measured from the substrate 5111, the height of the memory cell can be increased. In each NAND string NS, the height of the memory cell MC6 adjacent to the source selection transistor SST may be seven.

The source selection transistors SST of the NAND strings NS in the same column can share the source selection line SSL. The source selection transistors SST of the NAND strings NS in different columns may be electrically coupled to different source selection lines SSL1, source selection line SSL2, and source selection line SSL3, respectively.

The memory cells MC at the same height in the NAND strings NS in the same column can share the word line WL. That is, at the same height, the word lines WL electrically coupled with the memory cells MC of the NAND strings NS in different columns may be electrically coupled. The dummy memory cells DMC at the same height in the NAND strings NS in the same column can share the dummy word line DWL. That is, at the same height or the same level, the dummy word lines DWL electrically coupled with the dummy memory cells DMC of the NAND strings NS in different columns may be electrically coupled.

The word lines WL or the dummy word lines DWL located at the same level or the same height or the same layer may be provided with conductive materials 5211 to 5291, conductive materials 5212 to 5292, and conductive materials 5213 to 5293 that extend in the first direction. The layers are electrically coupled to each other. The conductive materials 5211 to 5291, the conductive materials 5212 to 5292, and the conductive materials 5213 to 5293 extending in the first direction can be electrically connected to the upper layer through contact in common. At the upper layer, conductive materials 5211 to 5291, conductive materials 5212 to 5292, and conductive materials 5213 to 5293 extending in the first direction may be electrically coupled. The ground selection transistors GST of the NAND strings NS in the same column may share the ground selection line GSL. In addition, the ground selection transistors GST of the NAND strings NS in different columns may share the ground selection line GSL. That is, the NAND strings NS11 to NS13, the NAND strings NS21 to NS23, and the NAND strings NS31 to NS33 may be electrically coupled to the ground selection line GSL.

The common source line CSL may be electrically coupled to the NAND string NS. Above the active region and above the substrate 5111, the first to fourth doped regions 5311 to 5314 may be electrically coupled. The first to fourth doped regions 5311 to 5314 may be electrically coupled to an upper layer through a contact, and at the upper layer, the first to fourth doped regions 5311 to 5314 may be electrically coupled.

As shown in FIG. 8, the word lines WL of the same height or the same level may be electrically coupled. Therefore, when the word line WL at a certain height is selected, all the NAND strings NS electrically coupled with the word line WL can be selected. The NAND strings NS in different columns may be electrically coupled to different source selection lines SSL. Therefore, among the NAND strings NS electrically coupled to the same word line WL, by selecting one of the source selection lines SSL1 to SSL3, the NAND string NS in the unselected column can be combined with the bit. The element wires BL1 ~ BL3 are electrically isolated. In other words, by selecting one of the source selection lines SSL1 to SSL3, a column of NAND strings NS can be selected. In addition, by selecting one bit line among the bit lines BL1 to BL3, the NAND string NS in the selected column can be selected in a row unit.

In each NAND string NS, a dummy memory cell DMC may be set. In FIG. 8, the dummy memory cell DMC may be disposed between the third memory cell MC3 and the fourth memory cell MC4 in each NAND string NS. That is, the first to third memory cells MC1 to MC3 may be disposed between the dummy memory cell DMC and the ground selection transistor GST. The fourth to sixth memory cells MC4 to MC6 may be disposed between the dummy memory cell DMC and the source selection transistor SST. The memory cell MC of each NAND string NS may be divided into a memory cell group by a dummy memory cell DMC. Among the divided memory cell groups, the memory cells (for example, MC1 to MC3) adjacent to the ground selection transistor GST can be referred to as the lower memory cell group, while those adjacent to the source selection transistor SST Memory cells (for example, MC4 to MC6) can be referred to as upper memory cell groups.

Hereinafter, it will be described in detail with reference to FIGS. 9 to 11, which illustrate a memory system according to an embodiment implemented with a three-dimensional (3D) non-volatile memory device different from the first structure. Memory device.

FIG. 9 is a perspective view schematically showing a memory device implemented with a three-dimensional (3D) non-volatile memory device different from the first structure described above with reference to FIGS. 5 to 8, and shows a plural number of FIG. 4. Memory block BLKj of the memory blocks. FIG. 10 is a cross-sectional view illustrating a memory block BLKj taken along a line VII-VII ′ of FIG. 9.

Referring to FIG. 9 and FIG. 10, a memory block BLKj among the plurality of memory blocks of the memory device 150 of FIG. 1 may include a structure extending in a first direction to a third direction.

A substrate 6311 may be provided. For example, the substrate 6311 may include a silicon material doped with a first type of impurity. For example, the substrate 6311 may include a silicon material doped with a p-type impurity or may be a p-type well (for example, a pouch-shaped p-well), and include an n-type well surrounding the p-type well. Although the substrate 6311 is p-type silicon in this embodiment, it should be noted that the substrate 6311 is not limited to being p-type silicon.

The first to fourth conductive materials 6321 to 6324 extending in the x-axis direction and the y-axis direction may be disposed above the substrate 6311. The first to fourth conductive materials 6321 to 6324 may be separated by a predetermined distance in the z-axis direction.

The fifth conductive material 6325 to the eighth conductive material 6328 extending in the x-axis direction and the y-axis direction may be disposed above the substrate 6311. The fifth to eighth conductive materials 6325 to 6328 may be separated by a predetermined distance in the z-axis direction. The fifth to eighth conductive materials 6325 to 6328 may be separated from the first to fourth conductive materials 6321 to 6324 in the y-axis direction.

A plurality of lower pillars DP passing through the first conductive material 6321 to the fourth conductive material 6324 may be provided. Each lower pillar DP extends in the z-axis direction. In addition, a plurality of upper pillars UP passing through the fifth conductive material 6325 to the eighth conductive material 6328 may be provided. Each upper pillar UP extends in the z-axis direction.

Each of the lower pillar DP and the upper pillar UP may include an inner material 6361, an intermediate layer 6362, and a surface layer 6363. The intermediate layer 6362 can be used as a channel of a unit transistor. The surface layer 6363 may include a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer.

The lower pillar DP and the upper pillar UP may be electrically coupled via a pipe gate PG. The pipe gate PG may be provided in the base 6311. For example, the pipe gate PG may include the same material as the lower pillar DP and the upper pillar UP.

A second type of doping material 6312 extending in the x-axis direction and the y-axis direction may be disposed above the lower pillar DP. For example, the second type of doped material 6312 may include an n-type silicon material. The second type of doped material 6312 may serve as the common source line CSL.

The drain electrode 6340 may be disposed above the upper pillar UP. The drain electrode 6340 may include an n-type silicon material. A first upper conductive material 6351 and a second upper conductive material 6352 extending in the y-axis direction may be disposed above the drain electrode 6340.

The first upper conductive material 6351 and the second upper conductive material 6352 may be separated in the x-axis direction. The first upper conductive material 6351 and the second upper conductive material 6352 may be formed of a metal. The first upper conductive material 6351 and the second upper conductive material 6352 and the drain electrode 6340 may be electrically coupled through a contact plug. The first upper conductive material 6351 and the second upper conductive material 6352 serve as the first bit line BL1 and the second bit line BL2, respectively.

The first conductive material 6321 can be used as the source selection line SSL, the second conductive material 6322 can be used as the first dummy word line DWL1, and the third conductive material 6323 and the fourth conductive material 6324 can be used as the first main word line MWL1 and The second main character line MWL2. The fifth conductive material 6325 and the sixth conductive material 6326 serve as the third main character line MWL3 and the fourth main character line MWL4, respectively. The seventh conductive material 6327 can serve as the second dummy word line DWL2, and the eighth conductive material 6328. Can be used as a drain select line DSL.

The lower pillar DP and the first to fourth conductive materials 6321 to 6324 adjacent to the lower pillar DP form a lower string. The upper pillar UP and the fifth to eighth conductive materials 6325 to 6328 adjacent to the upper pillar UP form an upper string. The lower string and the upper string may be electrically coupled via a pipe gate PG. One end of the lower string may be electrically coupled to the second type doping material 6312 as the common source line CSL. One end of the upper string can be electrically coupled to the corresponding bit line through the drain 6340. A lower string and an upper string form a unit string, which is electrically coupled to the second type doping material 6312 as the common source line CSL and the upper conductive material layer 6351 and the upper conductive material as the bit line BL Between the corresponding one of the layers 6352.

That is, the lower string may include a source selection transistor SST, a first dummy memory cell DMC1, and a first main memory cell MMC1 and a second main memory cell MMC2. The upper string may include a third main memory unit MMC3 and a fourth main memory unit MMC4, a second dummy memory unit DMC2, and a drain selection transistor DST.

In FIGS. 9 and 10, the upper and lower strings may form a NAND string NS, and the NAND string NS may include a plurality of transistor structures TS. Since the transistor structure included in the NAND string NS in FIGS. 9 and 10 is described in detail above with reference to FIG. 7, a detailed description thereof will be omitted herein.

FIG. 11 is a circuit diagram showing an equivalent circuit of the memory block BLKj having the second structure as described above with reference to FIGS. 9 and 10. For convenience, only the first string and the second string forming a pair in the memory block BLKj of the second structure are shown.

Referring to FIG. 11, in a memory block BLKj having a second structure among a plurality of memory blocks of the memory device 150, a cell string may be set in a manner of limiting a plurality of pairs, where each cell string is composed of This is achieved by one upper string and one lower string electrically coupled via the pipe gate PG as described above with reference to FIGS. 9 and 10.

That is, in a memory block BLKj having a second structure, memory cells CG0 to CG31 (for example, at least one source selection gate SSG1 and at least one drain electrode) stacked along the first channel CH1 (not shown). Select gate DSG1) can form a first string ST1, and memory cells CG0 ~ CG31 (eg, at least one source select gate SSG2 and at least one drain select gate) stacked along a second channel CH2 (not shown) DSG2) can form a second string ST2.

The first string ST1 and the second string ST2 may be electrically coupled to the same drain selection line DSL and the same source selection line SSL. The first string ST1 may be electrically coupled to the first bit line BL1, and the second string ST2 may be electrically coupled to the second bit line BL2.

Although it is described in FIG. 11 that the first string ST1 and the second string ST2 are electrically coupled to the same drain selection line DSL and the same source selection line SSL, it is contemplated that the first string ST1 and the second string ST2 may be electrically connected. Coupled to the same source select line SSL and the same bit line BL, the first string ST1 can be electrically coupled to the first drain select line DSL1, and the second string ST2 can be electrically coupled to the second drain select Line DSL2. In addition, it is conceivable that the first string ST1 and the second string ST2 may be electrically coupled to the same drain selection line DSL and the same bit line BL, and the first string ST1 may be electrically coupled to the first source selection line SSL1. The second string ST2 can be electrically coupled to the second source selection line SSL2.

FIG. 12 illustrates a line offset in a programming operation of a non-volatile memory device according to an embodiment of the present invention, and illustrates a vertical cross-section of a pillar structure forming a transistor in a 3D NAND cell string. Herein, although a 3D NAND flash memory having a vertical channel region as shown in FIGS. 5 and 6 is described as an example, the concept and spirit of the present invention may not be limited thereto.

Referring to FIG. 12, a 3D NAND cell string of a non-volatile memory device according to an embodiment of the present invention may include a plurality of word lines WL stacked between a source selection line SSL and a drain selection line DSL, and a vertical channel The region CH crosses the character line in the vertical direction. Herein, the gate dielectric structure GD may be inserted between the vertical channel region CH and the stacked line, and the gate dielectric structure GD may include a blocking dielectric that is sequentially stacked in a direction from the word line WL toward the vertical channel region CH. Layer / charge-trapping layer / tunneling dielectric layer.

Generally, when a 3D NAND cell string is selected and a program operation is performed, a program operation may be sequentially performed from a word line provided near the source selection line SSL to a word line provided near the drain selection line DSL. Of course, not all word lines of the selected cell string can be programmed. When a 3D NAND cell string is selected, the source selection line SSL can be biased with a ground voltage GND, and the drain selection line DSL can be biased with a drain selection voltage VDSL.

During a program operation, a program voltage Vpgm may be applied to a program target word line (for example, the N-th WL), and a pass voltage Vpass may be applied to the remaining word lines. Here, the charge entered from the vertical channel region CH can be captured in the gate dielectric structure GD overlapping the word line (ie, the Nth WL) that is performing a programming operation, and the captured charge can increase the corresponding cell Threshold voltage. It can be said that the cells are programmed. However, the strong electric field caused by the programming voltage Vpgm may cause a marginal field, and the marginal field may inadvertently cause charge trapping into the word line (Nth WL) being programmed and the adjacent word line (N + 1th) WL). At the same time, the charge trapped in the area between the two character lines (the Nth WL and the N + 1th WL), where the area is represented by the dotted line in the figure, can affect the subsequent character lines ( The N + 1th WL) programming operation also results in an unintentional shift of the cell threshold voltage, which typically occurs in the form of an expanded cell threshold voltage distribution. This interference phenomenon is commonly referred to as Z interference, and it is one of the most critical interference modes in 3D NAND flash memory.

According to an embodiment of the present invention, when a program operation is performed on a word line (Nth WL) (that is, when a programming voltage Vpgm is applied to a section adjacent to the word line (N + 1th) WL), A negative bias voltage Vnega is additionally applied to the pass voltage Vpass. This negative bias Vnega may be applied to the end of the pulse section of the program voltage Vpgm, and during the section where the negative bias Vnega is applied, the program target word line (Nth WL) may be discharged until all words The yuan wire is pre-charged. Herein, the bias voltage for each line in the above programming operation may be provided by the voltage supplier 310 shown in FIG. 3. The electric field caused by the negative bias Vnega can compensate the positive marginal field based on the programming voltage Vpgm, and the area between two adjacent word lines (Nth WL and N + 1th WL) (in the diagram The charge trapped in (represented by the dotted line) can be discharged or trapped in this region.

FIG. 13A is a diagram illustrating an offset waveform in a program operation illustrated in FIG. 12, and FIG. 13B is a flowchart illustrating a program operation of a nonvolatile memory device according to an embodiment of the present invention.

When there is a write request from the outside (for example, the host) of the non-volatile memory device, the memory controller may perform the erase operation based on the memory block, and then execute based on the page (for example, the word line) Program operation. From the perspective of the cell string, the programming operation can be performed sequentially from the word line near the source selection line SSL toward the word line near the drain selection line DSL based on the data input with the command. 13A and 13B illustrate a case where an N-th character line (N-th WL) is selected among the character lines included in the cell string.

First, in step S100, the programming voltage Vpgm may be applied to the selected word line (Nth WL), and at the same time, the pass voltage Vpass may be applied to the remaining unselected word lines. Here, before each word line is biased with the programming voltage Vpgm or by the voltage Vpass, each word line may be precharged with, for example, a ground voltage GND level. In addition, when the program voltage Vpgm and the pass voltage Vpass are applied, a multi-step rising method may be used. In the case of the programming voltage Vpgm, first, a pass voltage level may be applied, and then the voltage level is gradually increased to a predetermined programming voltage level, and the level is maintained for a predetermined time. In the case of a character line (N-1th WL and N + 1th WL) adjacent to a character line (Nth WL) that is performing a programming operation among unselected character lines, An initial pass voltage level having a lower level than a predetermined pass voltage level may be applied, and in a section where a selected word line (Nth WL) maintains a predetermined programming voltage level, may be applied The predetermined pass voltage level. By using the multi-step rising method, the word line offset level difference caused by the difference in the load value of the word line WL from the voltage supply 310 can be reduced. At the same time, for the unselected character lines (N-2nd WL, N + 2th WL, etc.), except for the character lines that are arranged adjacent to the character line (Nth WL) that is performing a programming operation (N-1th WL and N + 1th WL), a predetermined pass voltage level can be directly applied without using a multi-step rising method.

Subsequently, in step S110, at the end of the pulse section of the programming voltage Vpgm, a negative bias voltage Vnega may be applied to the word line disposed adjacent to the word line (Nth WL) that is performing a program operation, The selected word line (Nth WL) maintains a predetermined programming voltage level. According to an embodiment of the present invention, among the character lines (N-1th WL and N + 1th WL) disposed adjacent to the character line (Nth WL) performing a programming operation, the negative The bias voltage Vnega is applied only to the adjacent word lines (N + 1th WL) which are sequentially programmed in the order of the programming operation. In the case of a word line (N-1th WL), applying a negative bias Vnega can change the state of the previous programming. At the same time, the negative bias Vnega can have a lower level than the ground voltage GND, and the lower the level, the stronger the compensation electric field that can be formed. In addition, the longer the section where the negative bias Vnega is applied becomes, the more favorable it is. However, in this case, the overall programming time may increase excessively. Therefore, the length of a segment may have to be determined with an appropriate length.

Subsequently, in step S120, each word line WL may be precharged. In the case of the precharge operation, a method of simultaneously stopping the supply of the bias voltage applied to the word line WL may be used. In addition, various other pre-charging methods can be applied. FIG. 13A shows a case where a method of discharging a word line (Nth WL) biased with a programming voltage Vpgm to a ground voltage GND level is applied.

First, in step S122, in a section where the selected word line (Nth WL) maintains a predetermined programming voltage level, the word line can be discharged to a ground voltage GND level. In this paper, a negative bias Vnega can be applied to adjacent word lines (N + 1th WL), and can be reduced by coupling two word lines (Nth WL and N + 1th WL). The level of the negative bias Vnega. This word line discharge operation can prevent the redistribution of the charge that is normally trapped in the gate dielectric structure GD that overlaps the selected word line (the Nth WL).

Subsequently, in step S124, the voltages applied to the respective word lines WL may be equalized to the same level (for example, a predetermined pass voltage Vpass level), and then the respective word line voltages may be reset. When the word line voltage is reset, the word line can be lowered to a precharge level (for example, the ground voltage GND level).

As described above, in the embodiment of the present invention, a negative bias voltage Vnega may be applied to an adjacent word with respect to the selected word line (the Nth WL) at the end of the pulse section of the programming voltage Vpgm. Yuan line (N + 1th WL). The electric field caused by the negative bias Vnega can compensate the positive marginal field based on the programming voltage Vpgm to charge trapped in the region between two adjacent word lines (Nth WL and N + 1th WL) Perform discharge or suppress charge trapping in this area. In other words, Z interference can be reduced, which means that the threshold voltage distribution of the cell can be kept narrow.

Although it is shown in this embodiment that the programming voltage Vpgm is pulsed once (as shown in FIG. 13A), the technique of the present invention can also be applied to the case where an incremental step pulse programming (ISPP) method is also used during a programming operation . In other words, while the programming voltage Vpgm is increased by the step voltage ΔV, the programming cycle may be repeated until the memory cells coupled to the word lines are programmed to a desired level. In this case, regardless of the level of each pulse of each programming voltage Vpgm rising, a negative bias voltage Vnega can be applied at a constant level. Whenever the level of each pulse of the programming voltage Vpgm increases, a method of lowering the level of the negative bias Vnega by a predetermined level may also be used.

Although in this embodiment, a 3D NAND flash memory having a vertical channel region is described as an example, the concept and spirit of the present invention can be applied to a non-volatile memory device (for example, a block-type NAND flash memory) The non-volatile memory device has a plurality of word lines forming a cell string and sequentially programes the word lines.

14 to 22 are diagrams schematically illustrating an exemplary application of the data processing system of FIG. 1.

FIG. 14 is a diagram schematically showing an example of a data processing system including a memory system according to the present embodiment. FIG. 14 schematically illustrates a memory card system to which the memory system according to the present embodiment is applied.

Referring to FIG. 14, the memory card system 6100 may include a memory controller 6120, a memory device 6130, and a connector 6110.

More specifically, the memory controller 6120 may be connected to a memory device 6130 implemented by a non-volatile memory, and may access the memory device 6130. For example, the memory controller 6120 may control a read operation, a write operation, an erase operation, and a background operation of the memory device 6130. The memory controller 6120 can provide an interface connection between the memory device 6130 and the host and is used to control the driving firmware of the memory device 6130. That is, the memory controller 6120 may correspond to the controller 130 of the memory system 110 described with reference to FIG. 1, and the memory device 6130 may correspond to the memory device 150 of the memory system 110 described with reference to FIG. 1.

Therefore, the memory controller 6120 may include a RAM, a processing unit, a host interface, a memory interface, and an error correction unit.

The memory controller 6120 can communicate with an external device (for example, the host 102 in FIG. 1) through the connector 6110. For example, as described with reference to FIG. 1, the memory controller 6120 may communicate through various communication protocols such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), and a peripheral component interconnect (PCI). , PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (EDSI), Integrated Device Circuit (IDE), FireWire, Universal Flash One or more of Memory Storage (UFS), WIFI, and Bluetooth) to communicate with external devices. Therefore, the memory system and the data processing system according to this embodiment can be applied to a wired / wireless electronic device or a mobile electronic device.

The memory device 6130 may be implemented by a non-volatile memory. For example, the memory device 6130 may be composed of various non-volatile memory devices such as erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, Phase Change RAM (PRAM), Resistive RAM (ReRAM), Ferroelectric RAM (FRAM) and Spin Torque Transfer Magnetic RAM (STT-RAM)). The memory device 6130 may include a plurality of dies in the memory device 150 as shown in FIG. 1.

The memory controller 6120 and the memory device 6130 may be integrated into a single semiconductor device. For example, the memory controller 6120 and the memory device 6130 may construct a solid-state hard disk (SSD) by being integrated into a single semiconductor device. In addition, the memory controller 6120 and the memory device 6130 can construct a memory card such as a PC card (PCMCIA: Personal Computer Memory Card International Association), a compact flash memory (CF) card, and a smart media card such as SM and SMC ), Memory sticks, multimedia cards (such as MMC, RS-MMC, MMC micro and eMMC), SD cards (such as SD, mini SD, micro SD and SDHC), and universal flash memory storage (UFS).

FIG. 15 is a diagram schematically showing another example of a data processing system including a memory system according to the present embodiment.

Referring to FIG. 15, the data processing system 6200 may include a memory device 6230 having one or more non-volatile memories and a memory controller 6220 for controlling the memory devices 6230. The data processing system 6200 shown in FIG. 15 can be used as a storage medium (such as a memory card (CF, SD, micro SD, etc.)) or a USB device as described with reference to FIG. 1. The memory device 6230 may correspond to the memory device 150 in the memory system 110 shown in FIG. 1, and the memory controller 6220 may correspond to the controller 130 in the memory system 110 shown in FIG. 1.

The memory controller 6220 may control a read operation, a write operation, or an erase operation of the memory device 6230 in response to a request from the host 6210, and the memory controller 6220 may include one or more CPUs 6221, buffer memory (Such as RAM) 6222, ECC circuit 6223, host interface 6224, and memory interface (such as NVM interface) 6225.

The CPU 6221 can control overall operations of the memory device 6230, such as read operations, write operations, file system management operations, and bad page management operations. The RAM 6222 can be operated according to the control of the CPU 6221, and can be used as working memory, buffer memory or cache memory. When the RAM 6222 is used as working memory, data processed by the CPU 6221 can be temporarily stored in the RAM 6222. When the RAM 6222 is used as a buffer memory, the RAM 6222 can be used to buffer data sent from the host 6210 to the memory device 6230 or from the memory device 6230 to the host 6210. When the RAM 6222 is used as a cache memory, the RAM 6222 can assist the low-speed memory device 6230 to operate at a high speed.

The ECC circuit 6223 may correspond to the ECC unit 138 of the controller 130 shown in FIG. 1. As described with reference to FIG. 1, the ECC circuit 6223 may generate an error correction code (ECC) for correcting a failed bit or an error bit of the data provided from the memory device 6230. The ECC circuit 6223 may perform error correction coding on the data provided to the memory device 6230, thereby using data having parity bits. The parity bit may be stored in the memory device 6230. The ECC circuit 6223 can perform error correction decoding on the data output from the memory device 6230. At this time, the ECC circuit 6223 can use parity check bits to correct errors. For example, as described with reference to FIG. 1, the ECC circuit 6223 may correct an error using an LDPC code, a BCH code, a turbo code, a Reed-Solomon code, a convolutional code, an RSC, or a coded modulation such as TCM or BCM.

The memory controller 6220 can send / receive data to / from the host 6210 through the host interface 6224, and send / receive data to / from the memory device 6230 through the NVM interface 6225. The host interface 6224 can be connected to the host 6210 through a PATA bus, a SATA bus, SCSI, USB, PCIe, or NAND interface. The memory controller 6220 may have a wireless communication function using a mobile communication protocol such as WiFi or Long Term Evolution (LTE). The memory controller 6220 may be connected to an external device (for example, the host 6210 or another external device), and then send / receive data to / from the external device. Specifically, since the memory controller 6220 can communicate with external devices through one or more of various communication protocols, the memory system and the data processing system according to this embodiment can be applied to wired / wireless electronic devices or particularly Mobile electronics.

FIG. 16 is a diagram schematically showing another example of a data processing system including a memory system according to an embodiment of the present invention. FIG. 16 schematically illustrates an SSD to which the memory system according to the present embodiment is applied.

Referring to FIG. 16, the SSD 66300 may include a controller 66320 and a memory device 66340 including a plurality of non-volatile memories. The controller 66320 may correspond to the controller 130 in the memory system 110 of FIG. 1, and the memory device 66340 may correspond to the memory device 150 in the memory system of FIG. 1.

More specifically, the controller 66320 can be connected to the memory device 66340 through a plurality of channels CH1 to CHi. The controller 66320 may include one or more processors 66321, a buffer memory 66325, an ECC circuit 66322, a host interface 66324, and a memory interface (eg, a non-volatile memory interface) 66326.

The buffer memory 66325 may temporarily store data provided from the host 66310 or data provided from a plurality of flash memory NVMs included in the memory device 66340, or temporarily store metadata of the plurality of flash memory NVMs (for example, including Mapping information of the mapping table). The buffer memory 66325 may be implemented by a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM or a non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM. For ease of description, FIG. 16 illustrates that the buffer memory 66325 exists in the controller 66320. However, the buffer memory 66325 may exist outside the controller 66320.

The ECC circuit 66322 may calculate an ECC value of data to be programmed to the memory device 66340 during a program operation, perform an error correction operation on the data read from the memory device 66340 based on the ECC value during a read operation, and recover from a failed data An error correction operation is performed on the data recovered from the memory device 66340 during the operation.

The host interface 66324 may provide an interface connection function with an external device (for example, the host 66310), and the nonvolatile memory interface 66326 may provide an interface connection function with a memory device 66340 connected through a plurality of channels.

In addition, a plurality of SSDs 66300 applying the memory system 110 of FIG. 1 may be provided to implement a data processing system (eg, a redundant array of independent disks (RAID) system). At this time, the RAID system may include a plurality of SSD 66300 and a RAID controller for controlling the plurality of SSD 66300. When the RAID controller performs a programming operation in response to a write command provided from the host 66310, the RAID controller may perform a RAID operation according to a plurality of RAID levels (ie, RAID level information of the write command provided from the host 66310 in the SSD 66300). ) And select one or more memory systems or SSD 66300, and output the data corresponding to the write command to the selected SSD 66300. In addition, when the RAID controller performs a read operation in response to a read command provided from the host 66310, the RAID controller may perform a read operation based on a plurality of RAID levels (the RAID level of the read command provided from the host 66310 in the SSD 66300). Information) to select one or more memory systems or SSD 66300, and provide data read from the selected SSD 66300 to the host 66310.

FIG. 17 is a diagram schematically showing another example of a data processing system including a memory system according to an embodiment of the present invention. FIG. 17 schematically illustrates an embedded multimedia card (eMMC) to which the memory system according to the embodiment is applied.

Referring to FIG. 17, the eMMC 6400 may include a controller 6430 and a memory device 6440 implemented by one or more NAND flash memories. The controller 6430 may correspond to the controller 130 in the memory system 110 of FIG. 1, and the memory device 6440 may correspond to the memory device 150 in the memory system 110 of FIG. 1.

More specifically, the controller 6430 may be connected to the memory device 6440 through a plurality of channels. The controller 6430 may include one or more cores 6432, a host interface 6431, and a memory interface (eg, a NAND interface 6433).

The core 6432 can control the overall operation of the eMMC 6400, the host interface 6431 can provide the interface connection function between the controller 6430 and the host 6410, and the NAND interface 6433 can provide the interface connection function between the memory device 6440 and the controller 6430. For example, the host interface 6431 may serve as a parallel interface (for example, the MMC interface described with reference to FIG. 1). In addition, the host interface 6431 can be used as a serial interface (for example, an ultra-high-speed (UHS-I / UHS-II) interface).

18 to 21 are diagrams schematically illustrating other examples of a data processing system including a memory system according to an embodiment of the present invention. 18 to 21 schematically illustrate a universal flash memory (UFS) system to which the memory system according to the embodiment is applied.

18 to 21, the UFS system 6500, UFS system 6600, UFS system 6700, and UFS system 6800 may include a host 6510, a host 6610, a host 6710, and a host 6810, a UFS device 6520, a UFS device 6620, a UFS device 6720, and UFS, respectively Device 6820 and UFS card 6530, UFS card 6630, UFS card 6730 and UFS card 6830. The host 6510, the host 6610, the host 6710, and the host 6810 can be used as application processors for wired / wireless electronic devices or especially mobile electronic devices. The UFS device 6520, UFS device 6620, UFS device 6720, and UFS device 6820 can be used as embedded UFS devices And UFS card 6530, UFS card 6630, UFS card 6730 and UFS card 6830 can be used as external embedded UFS device or removable UFS card.

Hosts 6510, 6610, 6710 and 6810, UFS device 6520, UFS device 6620, UFS device 6720 and UFS device 6820, and UFS card in the corresponding UFS system 6500, UFS system 6600, UFS system 6700, and UFS system 6800 6530, UFS card 6630, UFS card 6730, and UFS card 6830 can communicate with external devices (such as wired / wireless electronic devices or mobile electronic devices) through the UFS protocol, and UFS device 6520, UFS device 6620, UFS device 6720, and UFS The device 6820 and the UFS card 6530, UFS card 6630, UFS card 6730, and UFS card 6830 can be implemented through the memory system 110 shown in FIG. For example, in UFS system 6500, UFS system 6600, UFS system 6700, and UFS system 6800, UFS device 6520, UFS device 6620, UFS device 6720, and UFS device 6820 may use the data processing system 6200 described with reference to FIGS. 15 to 17 , SSD 66300, or eMMC 6400, and UFS card 6530, UFS card 6630, UFS card 6730, and UFS card 6830 may be implemented in the form of a memory card system 6100 described with reference to FIG.

In addition, in the UFS system 6500, UFS system 6600, UFS system 6700, and UFS system 6800, the host 6510, host 6610, host 6710 and host 6810, UFS device 6520, UFS device 6620, UFS device 6720 and UFS device 6820, and UFS card The 6530, UFS card 6630, UFS card 6730, and UFS card 6830 can communicate with each other through UFS interfaces (for example, the unified protocols (MIPI M-PHY and MIPI UniPro) in the Mobile Industry Processor Interface (MIPI)). In addition, UFS device 6520, UFS device 6620, UFS device 6720, and UFS device 6820, and UFS card 6530, UFS card 6630, UFS card 6730, and UFS card 6830 can pass various protocols other than the UFS protocol (for example, UFD, MMC, SD , Mini SD and micro SD) to communicate with each other.

In the UFS system 6500 shown in FIG. 18, each of the host 6510, the UFS device 6520, and the UFS card 6530 may include UniPro. The host 6510 can perform a switching operation to communicate with the UFS device 6520 and the UFS card 6530. Specifically, the host 6510 can communicate with the UFS device 6520 or the UFS card 6530 through a link layer switch (for example, L3 switch at UniPro). At this time, the UFS device 6520 and the UFS card 6530 can communicate with each other through a link layer switch at the UniPro of the host 6510. In this embodiment, for convenience of description, a configuration in which one UFS device 6520 and one UFS card 6530 are connected to the host 6510 has been exemplified. However, a plurality of UFS devices and UFS cards may be connected to the host 6510 in parallel or in a star form, and a plurality of UFS cards may be connected to the UFS device 6520 in parallel or in a star form, or connected in series or in a chain. UFS 装置 6520.

In the UFS system 6600 shown in FIG. 19, each of the host 6610, the UFS device 6620, and the UFS card 6630 may include UniPro, and the host 6610 may perform the switching operation through a switching module 6640 (for example, by executing at UniPro The switching module 6640 for link layer switching (such as L3 switching) communicates with UFS device 6620 or UFS card 6630. UFS device 6620 and UFS card 6630 can communicate with each other through the link layer switching of the switching module 6640 at UniPro. In the present embodiment, for convenience of description, a configuration in which one UFS device 6620 and one UFS card 6630 are connected to the switching module 6640 has been exemplified. However, a plurality of UFS devices and UFS cards may be connected to the switching module 6640 in parallel or in a star form, and a plurality of UFS cards may be connected to the UFS device 6620 in series or in a chain form.

In the UFS system 6700 shown in FIG. 20, each of the host 6710, the UFS device 6720, and the UFS card 6730 may include UniPro, and the host 6710 may perform the switching operation through a switching module 6740 (for example, by executing at the UniPro A switching module 6740 for link layer switching (for example, L3 switching) communicates with a UFS device 6720 or a UFS card 6730. At this time, the UFS device 6720 and the UFS card 6730 can communicate with each other through the link layer switching of the switching module 6740 at UniPro, and the switching module 6740 and the UFS device 6720 can be integrated as a module in the UFS device 6720. Inside or outside. In this embodiment, for convenience of description, a configuration in which one UFS device 6720 and one UFS card 6730 are connected to the switching module 6740 has been exemplified. However, each of the plurality of modules including the switching module 6740 and the UFS device 6720 may be connected to the host 6710 in parallel or in a star form, or connected to each other in series or in a chain form. In addition, a plurality of UFS cards can be connected to the UFS device 6720 in parallel or in a star form.

In the UFS system 6800 shown in FIG. 21, each of the host 6810, the UFS device 6820, and the UFS card 6830 may include M-PHY and UniPro. The UFS device 6820 may perform a switching operation to communicate with the host 6810 and the UFS card 6830. Specifically, the UFS device 6820 can switch operations between the M-PHY and the UniPro module for communication with the host 6810 and the switch operation between the M-PHY and the UniPro module for communication with the UFS card 6830. (For example, through a target identification code (ID) switching operation) to communicate with the host 6810 or UFS card 6830. At this time, the host 6810 and the UFS card 6830 can communicate with each other by switching the target ID between the M-PHY and the UniPro module of the UFS device 6820. In the present embodiment, for convenience of description, a configuration in which one UFS device 6820 is connected to the host 6810 and one UFS card 6830 is connected to the UFS device 6820 has been exemplified. However, a plurality of UFS devices may be connected to the host 6810 in parallel or in a star form, or connected to the host 6810 in series or in a chain, and a plurality of UFS cards may be connected to the UFS device 6820 in parallel or in a star form. Connected to UFS device 6820 either in series or in a chain.

FIG. 22 is a diagram schematically showing another example of a data processing system including a memory system according to an embodiment of the present invention. FIG. 22 is a diagram schematically showing a user system to which the memory system according to the present embodiment is applied.

Referring to FIG. 22, the user system 6900 may include an application processor 6930, a memory module 6920, a network module 6940, a storage module 6950, and a user interface 6910.

More specifically, the application processor 6930 may drive components (eg, operating system (OS)) included in the user system 6900, and includes a controller, interface, and graphics engine that controls the components included in the user system 6900. The application processor 6930 may be configured as a system-on-chip (SoC).

The memory module 6920 can be used as the main memory, working memory, buffer memory, or cache memory of the user system 6900. The memory module 6920 may include volatile RAM (such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDARM, LPDDR3 SDRAM, or LPDDR3 SDRAM) or non-volatile RAM (such as PRAM, ReRAM, MRAM, or FRAM). For example, the application processor 6930 and the memory module 6920 may be packaged and installed based on a package-on-package (PoP).

The network module 6940 can communicate with external devices. For example, the network module 6940 can support not only wired communication, but also various wireless communication protocols such as code division multiple access (CDMA), Global System for Mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, Multiple Access (TDMA), Long Term Evolution (LTE), Global Microwave Access Interoperability (Wimax), Wireless Local Area Network (WLAN), Ultra Wide Band (UWB), Bluetooth, Wireless Display (WI-DI)), Thereby communicating with wired / wireless electronic devices or especially mobile electronic devices. Therefore, the memory system and the data processing system according to the embodiments of the present invention can be applied to wired / wireless electronic devices. The application processor 6930 may include a network module 6940.

The storage module 6950 can store data (for example, data received from the application processor 6930), and then can send the stored data to the application processor 6930. The memory module 6950 can be composed of non-volatile semiconductor memory devices such as phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (ReRAM), NAND flash memory, NOR flash memory, and 3D NAND Flash memory), and is set as a removable storage medium (such as a memory card or external drive) for the user system 6900. The memory module 6950 may correspond to the memory system 110 described with reference to FIG. 1. In addition, the memory module 6950 may be implemented as an SSD, eMMC, and UFS as described above with reference to FIGS. 16 to 21.

The user interface 6910 may include an interface for inputting data or commands to the application processor 6930 or outputting data to an external device. For example, the user interface 6910 may include a user input interface (such as a keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensing And piezoelectric elements) and user output interfaces (such as liquid crystal displays (LCD), organic light emitting diode (OLED) display devices, active matrix OLED (AMOLED) display devices, LEDs, speakers, and motors).

In addition, when the memory system 110 of FIG. 1 is applied to the mobile electronic device of the user system 6900, the application processor 6930 can control the overall operation of the mobile electronic device, and the network module 6940 can be used to control the external device. Communication module for wired / wireless communication. The user interface 6910 can display the data processed by the processor 6930 on the display / touch module of the mobile electronic device, or support the function of receiving data from the touch panel.

Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that without departing from the spirit and scope of the invention as defined in the scope of the appended patent applications Various changes and improvements.

100‧‧‧ Data Processing System

102‧‧‧host

110‧‧‧Memory System

130‧‧‧controller

132‧‧‧Host Interface Unit

134‧‧‧Processor

138‧‧‧Error correction code unit

140‧‧‧Power Management Unit

142‧‧‧NAND Flash Memory Controller

144‧‧‧Memory

150‧‧‧Memory device

152‧‧‧Memory Block

154‧‧‧Memory Block

156‧‧‧Memory Block

210 ~ 240‧‧‧Memory block

310‧‧‧Voltage Supply

320‧‧‧Read / write circuit

322‧‧‧Page Buffer

324‧‧‧Page Buffer

326‧‧‧Page Buffer

340‧‧‧ cell string

5111‧‧‧ substrate

5112‧‧‧Dielectric material

5113‧‧‧Cylinder

5114‧‧‧ surface layer

5115‧‧‧Inner layer

5116‧‧‧Dielectric layer

5117‧‧‧first sub-dielectric layer

5188‧‧‧Second sub-dielectric layer

5119‧‧‧Third sub-dielectric layer

5211 ~ 5291‧‧‧‧Conductive material

5212 ~ 5292 ‧‧‧ conductive materials

5213 ~ 5293‧‧‧ conductive materials

5320‧‧‧ Drain

5311 ~ 5314‧‧‧‧First doped region ~ Fourth doped region

5331 ~ 5333‧‧‧Conductive material

6100‧‧‧Memory Card System

6110‧‧‧Connector

6120‧‧‧Memory Controller

6130‧‧‧Memory device

6200‧‧‧Data Processing System

6220‧‧‧Memory Controller

6221‧‧‧CPU

6222‧‧‧Buffer memory

6223‧‧‧ECC circuit

6224‧‧‧Host Interface

6225‧‧‧Memory Interface

6230‧‧‧Memory device

6311‧‧‧ substrate

6312‧‧‧Doped materials

6321 ~ 6328‧‧‧The first conductive material to the eighth conductive material

6340‧‧‧Drain

6351‧‧‧First conductive material

6352‧‧‧Second upper conductive material

6361‧‧‧Internal materials

6362‧‧‧Middle floor

6363‧‧‧ surface layer

66300‧‧‧SSD

66310‧‧‧Host

66320‧‧‧Controller

66321‧‧‧Processor

66322‧‧‧ECC circuit

66324‧‧‧Host Interface

66325‧‧‧Buffer memory

66326‧‧‧Memory Interface

66340‧‧‧Memory device

6400‧‧‧eMMC

6410‧‧‧Host

6430‧‧‧ Controller

6431‧‧‧Host Interface

6432‧‧‧core

6433‧‧‧NAND interface

6440‧‧‧Memory device

6500‧‧‧UFS system

6510‧‧‧Host

6520‧‧‧UFS device

6530‧‧‧UFS Card

6600‧‧‧UFS system

6610‧‧‧Host

6620‧‧‧UFS device

6630‧‧‧UFS Card

6700‧‧‧UFS system

6710‧‧‧Host

6720‧‧‧UFS device

6730‧‧‧UFS Card

6800‧‧‧UFS system

6810‧‧‧Host

6820‧‧‧UFS device

6830‧‧‧UFS Card

6900‧‧‧user system

6910‧‧‧user interface

6920‧‧‧Memory Module

6930‧‧‧Application Processor

6940‧‧‧Network Module

6950‧‧‧Memory module

BL‧‧‧bit line

BL0‧‧‧Bit Line

BL1‧‧‧bit line

BLm-1‧‧‧bit line

BL0 ~ BLm-1‧‧‧bit line

BLK0 ~ BLKN-1‧‧‧Memory block

BLKi‧‧‧Memory Block

BLKj‧‧‧Memory Block

CG0 ~ CG31‧‧‧Memory unit

CH‧‧‧ vertical channel area

CH1 ~ Chi‧‧‧channel

CSL‧‧‧Common Source Line

DMC‧‧‧Dummy Memory Unit

DMC1‧‧‧First dummy memory unit

DMC2‧‧‧Second Virtual Memory Unit

DP‧‧‧ lower cylinder

DSG1‧‧‧Drain selection gate

DSG2‧‧‧Drain selection gate

DSL‧‧‧Drain Selection Line

DST‧‧‧Drain Selection Transistor

DWL‧‧‧Dummy Character Line

DWL1‧‧‧First dummy character line

DWL2‧‧‧Second Dummy Character Line

DST‧‧‧Drain Selection Transistor

DWL‧‧‧Dummy Character Line

GD‧‧‧Gate dielectric structure

GND‧‧‧ ground voltage

GSL‧‧‧Ground Selection Line

GST‧‧‧Ground Selection Transistor

MC‧‧‧Memory Unit

MC0 ~ MCn-1‧‧‧Memory unit

MC0‧‧‧Memory Unit

MC1‧‧‧Memory Unit

MCn-2‧‧‧Memory Unit

MCn-1‧‧‧Memory Unit

MMC1‧‧‧First main memory unit

MMC2‧‧‧Second main memory unit

MMC3‧‧‧Third Main Memory Unit

MMC4‧‧‧ Fourth main memory unit

MWL1‧‧‧first main character line

MWL2‧‧‧Second main character line

MWL3‧‧‧third main character line

MWL4‧‧‧ Fourth main character line

NS‧‧‧NAND String

NS11 ~ NS31‧‧‧NAND String

NS12 ~ NS32‧‧‧NAND String

NS13 ~ NS33‧‧‧NAND String

NVM‧‧‧Flash Memory

PB‧‧‧Page Buffer

PG‧‧‧pipe lock

S100 ~ S124‧‧‧step

SSG1‧‧‧Source select gate

SSG2‧‧‧Source select gate

SSL‧‧‧Source selection line

SSL1‧‧‧Source Selection Line

SSL2‧‧‧Source Selection Line

SSL3‧‧‧Source Selection Line

SST‧‧‧Serial Source Transistor

SST‧‧‧Source Selection Transistor

ST1‧‧‧string

ST2‧‧‧string

TS‧‧‧Transistor Structure

UP‧‧‧ Upper cylinder

VDSL‧‧‧Drain selection voltage

Vnega‧‧‧Negative Bias

Vpass‧‧‧pass voltage

Vpgm‧‧‧ Programming voltage

WL‧‧‧Character Line

WL0‧‧‧Character line

WL1‧‧‧Character line

WL n-2‧‧‧Character line

WL n-1‧‧‧Character line

WL N + 2‧‧‧Character line

WL N + 1‧‧‧Character line

WL N‧‧‧Character Line

WL N -1‧‧‧Character line

FIG. 1 is a diagram illustrating a data processing system including a memory system according to one embodiment. FIG. 2 is a diagram showing a memory device in the memory system shown in FIG. 1. FIG. 3 is a circuit diagram illustrating a memory block in a memory device according to an embodiment. 4 to 11 are diagrams schematically showing the memory device shown in FIG. 2. FIG. 12 is a diagram illustrating a line offset in a program operation of a non-volatile memory device according to an embodiment of the present invention. FIG. 13A is a diagram showing an offset waveform in a program operation shown in FIG. 12. 13B is a flowchart illustrating a program operation of a non-volatile memory device according to an embodiment of the present invention. 14 to 22 are diagrams schematically illustrating an exemplary application of the data processing system shown in FIG. 1 according to various embodiments of the present invention.

no

Claims (20)

A non-volatile memory device includes: a plurality of stacked word lines; a vertical channel region adapted to form a cell string with the word lines; and a voltage supplier adapted to supply a programming operation on the word lines The required plurality of bias voltages, wherein, at the end of the pulse section of the programming voltage applied to the selected word line, a negative bias voltage is applied to adjacent words disposed adjacent to the selected word line Yuan line. The non-volatile memory device according to claim 1, wherein, among the adjacent word lines disposed adjacent to the selected word line, a negative bias voltage is applied after the selected word line. Line of programmed characters. The non-volatile memory device according to claim 1, wherein a negative bias is applied to a word line among adjacent word lines disposed adjacent to the selected word line. The non-volatile memory device according to claim 2, wherein all unselected words in the cell string are before a negative bias is applied to the word line to be programmed after the selected word line. The element line is biased with a pass voltage. The non-volatile memory device according to claim 2, wherein the selected word line is discharged after a negative bias is applied. The non-volatile memory device according to claim 5, wherein the selected word line is discharged using a ground voltage level. The non-volatile memory device according to claim 4, wherein all the word lines in the cell string including the selected word line being discharged and the adjacent word line to which a negative bias is applied utilize a pass voltage to Balanced and all word line voltages are reset. The non-volatile memory device according to claim 1, wherein the program voltage applied to the selected word line is applied in a multi-step rising method. The non-volatile memory device according to claim 8, wherein a pass voltage applied to an adjacent word line disposed adjacent to the selected word line is applied in a multi-step rising method. A method for operating a non-volatile memory device having a plurality of word lines forming a cell string, comprising: applying a programming voltage to a selected word line and applying a pass voltage to an unselected word line And while applying a programming voltage to the selected word line, a negative bias voltage is applied to the adjacent word lines disposed adjacent to the selected word line among the unselected word lines. The method according to claim 10, wherein, among the adjacent word lines disposed adjacent to the selected word line, a negative bias is applied to a character to be programmed subsequent to the selected word line. line. The method according to claim 10, wherein a negative bias is applied to a character line among adjacent character lines disposed adjacent to the selected character line. The method according to claim 11, further comprising: precharging all word lines included in the cell string after applying a negative bias voltage. The method according to claim 11, further comprising: discharging a selected word line after applying a negative bias voltage. The method according to claim 14, further comprising: after discharging the selected word line, using a pass voltage to equalize the selected word line including the discharged word line and the adjacent word line to which a negative bias voltage is applied All word lines in the cell string, and then reset all word line voltages. The method according to claim 10, wherein the program voltage applied to the selected word line is applied in a multi-step rising method. The method according to claim 16, wherein, when a pass voltage is applied to the unselected word line, adjacent words arranged adjacent to the selected word line among the unselected word lines are applied. The passing voltage of the element wires is applied in a multi-step rising method. A non-volatile memory device includes: a plurality of word lines that form a cell string; and a voltage supplier that is adapted to supply a plurality of bias voltages required for a programming operation on the word lines, wherein At the end of the pulsed section of the programming voltage of the selected word line, a negative bias is applied to adjacent word lines disposed adjacent to the selected word line. The non-volatile memory device according to claim 18, wherein, among the adjacent word lines disposed adjacent to the selected word line, a negative bias voltage is applied after the selected word line. Line of programmed characters. The non-volatile memory device according to claim 19, wherein all unselected words in the cell string are before a negative bias is applied to the word line to be programmed after the selected word line. The element line is biased with a pass voltage.