TW201907225A - Mask, producing method of the same and mother plate - Google Patents

Abstract

The present invention relates to a mask and a method for manufacturing a mask, and a mother plate and a method for manufacturing a mother plate. A mask according to the present invention, which is manufactured by electroforming, comprises a mask body and a plurality of mask patterns, wherein the mask body comprises a plurality of masking cells and a center part of each of the masking cells has a greater thickness than an edge part of each of the masking cells.

Description

Mask, manufacturing method thereof, and mother board

FIELD OF THE INVENTION The present invention relates to a mask, a method of manufacturing the same, and a mother board, and more particularly to a mask that can be plated in a tunnel space of an insulating portion to form a fine pattern, a method of manufacturing the same, and a mother board .

Background Art Recently, research on electroforming plating has been conducted in the manufacture of thin sheets. In the electroforming plating method, the anode body and the cathode body are immersed in an electrolytic solution, and a power source is applied to electrically attach the metal thin plate to the surface of the cathode body. Therefore, it is a method capable of producing an extremely thin sheet and expecting mass production.

On the other hand, as a technique for forming a pixel in an OLED manufacturing step, a FMM (Fine Metal Mask) method is mainly used, in which a metal mask (Shadow Mask) of a film is closely attached to a substrate. And the organic matter is evaporated to the desired position.

FIG. 1 is a schematic diagram showing a conventional pixel forming step.

Referring to Fig. 1(a), in order to use the pixel formation step of the FMM method, first, the substrate 10 and the patterned shadow mask 13 are adhered to each other to the maximum extent. Further, a material source 17 such as an organic substance or a low molecule is vapor-deposited through the material supply mechanism 15. The pixels 18 are sequentially deposited by sequentially depositing the R, G, and B source 17 while aligning the shadow mask 13. However, as shown in FIG. 1(a), if the pattern (PP') of the shadow mask 13 is formed vertically, the shadow effect which is blocked by the pattern wall by the evaporation path of the material source 17 may not be accurate. The problem of vapor deposition is consistent with the pixel pattern (F). Accordingly, the following method has been proposed: as shown in Fig. 1(b), the pattern (PP) of the shadow mask 13' is obliquely formed into a taper shape (S), and the error is minimized. In addition, in the FMM method, in order to improve the pattern accuracy, the thickness of the shadow mask 13, the interval between the substrate 10 and the shadow mask 13, the arrangement of the shadow mask 13, and the like are considered.

Fig. 2 is a schematic view showing a conventional high-resolution shadow mask 13' for OLED formation.

In order to achieve a high resolution OLED, the size of the pattern is reduced. As shown in Fig. 2, in order to specifically realize the high-resolution pixel 18, it is necessary to reduce the pixel interval, the pixel size, and the like in the shadow mask 13'. The pixel size can be achieved by reducing the pattern (PP) width of the shadow mask 13'. However, there is a limit to reducing the pixel spacing. Although the pixels 18 can be spaced apart by P→P', however, considering the thickness of the shadow mask 13' and the tapered shape (S), it is not possible to go further than the shadow mask 13'' having a P' size width. Ground to reduce the width. That is, the size of P' may be limited by P' = 2T / tan θ (T is the thickness of the shadow mask, and θ is the taper angle). Further, in the process of forming the (S) pattern obliquely on the shadow mask 13' having a thickness of about 30 to 50 μm, since the patterning 13'' of the pixel pitch and the pixel size is difficult to be performed, there is a processing step. The problem of poor productivity.

Disclosure of the Invention Problems to be Solved by the Invention An object of the present invention is to provide a mask, a method of manufacturing the same, and a mother board which can form a mask pattern finely and realize an ultra-high-quality OLED.

Further, an object of the present invention is to provide a mask which can be electroformed and plated in a space between lower portions of an insulating portion to form a mask pattern, a method for producing the same, and a mother board.

Means for Solving the Problems The foregoing object of the present invention can be achieved by a mask which is manufactured by electroforming plating, and further includes a mask body and a plurality of mask patterns, and the mask body includes A plurality of shielding units, and a thickness of a central portion of the shielding unit is thicker than a thickness of the shielding unit frame portion.

A space is formed between the predetermined mask pattern and the mask pattern adjacent to the mask pattern, and the shielding unit is integrally coupled to the adjacent shielding unit through the connecting portion.

The joint portion may be the thinnest portion formed in the mask body.

The side cross-sectional shape of the connecting portion may be a triangle, or at least one of the side and the rib may be a circular arc shape.

A shielding unit may be formed in a space between the predetermined mask pattern and the second mask pattern adjacent thereto.

The central portion of the shielding unit may be the thickest portion formed in the mask body.

The mask can be made of Invar or Super Invar.

Moreover, the above object of the present invention can be attained by the following method for manufacturing a mask: a method for manufacturing a mask by electroforming plating, comprising the following steps: (a) a step of providing a cathode body, The cathode body includes a conductive substrate, and a plurality of insulating portions formed on one surface of the substrate as a pattern; and (b) a step of at least a part of the cathode body and the anode body (Anode body) disposed apart from the cathode body Immersed in a plating solution to apply an electric field between the cathode body and the anode body; and (c) a step of forming a plating film on the surface of the cathode body to form a mask body including a plurality of shielding units, and insulating The surface of the portion prevents the formation of the plating film to form a plurality of mask patterns; at least a part of the frame portion of the shielding unit is plated in the tunnel space of the insulating portion, and is formed to have a thickness thinner than the central portion of the shielding unit.

The tunnel space is formed by overlapping at least an upper portion of the insulating portion adjacent to the nearest insulating portion.

The plating film formed in the tunnel space can constitute a joint portion that integrally connects the shielding units.

In the step (c), after the plating film has been formed in the tunnel space, plating is further performed to form a shielding unit.

The predetermined insulating portion and the second insulating portion adjacent thereto are disposed apart from each other without overlapping portions, and the plating film formed in the partition space constitutes a shielding unit.

Moreover, the above object of the present invention can be achieved by a mother plate which is used for manufacturing a mask by electroforming plating, comprising: a conductive substrate; and a plurality of insulating portions, The insulating portion is disposed on one surface of the conductive substrate to form a pattern, and the insulating portion has a shape in which the width gradually decreases from the upper portion toward the lower portion, and the predetermined insulating portion and at least an upper portion of the insulating portion adjacent thereto are coupled to each other.

At least a lower portion of the predetermined insulating portion and the insulating portion adjacent thereto is not connected, and a tunnel space can be formed.

The insulating portion and the upper portion of the insulating portion adjacent thereto are partially overlapped, or the apex portion of the upper portion is partially overlapped.

The conductive substrate may be a doped single crystal germanium material.

The doping is performed at least 10 ¹⁹ cm ^-3 or more.

The mother board is used as a cathode body in electroforming plating.

Advantageous Effects of Invention According to the present invention configured as described above, an OLED having a super high image quality can be specifically formed by forming a mask pattern finely.

Moreover, according to the present invention, the mask pattern can be formed by electroforming plating in the lower space between the insulating portions.

MODE FOR CARRYING OUT THE INVENTION The detailed description of the present invention will be described with reference to the accompanying drawings. The embodiments are described in detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the invention are different from each other, but are not necessarily mutually exclusive. For example, the specific shapes, structures, and characteristics described herein may be embodied in other embodiments without departing from the spirit and scope of the invention. In addition, it is to be understood that the position and arrangement of the individual components in the embodiments disclosed herein may be modified without departing from the spirit and scope of the invention. Therefore, the detailed description is not intended to be limiting, and the scope of the present invention is limited only by the appended claims and the scope of the claims. Similar reference symbols in the drawings have the same or similar functions in various aspects, and the length, the area, the thickness, and the like are convenient and sometimes exaggerated.

The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.

FIG. 3 is a schematic diagram showing an OLED pixel evaporation apparatus 200 using the FMM 100. Figure 4 is a schematic view showing a mask.

Referring to FIG. 3, in general, the OLED pixel vapor deposition apparatus 200 includes a magnetic plate 300 that houses a magnet 310 and is provided with a cooling water line 350, and a vapor deposition source supply unit 500 that is self-contained from the lower portion of the magnetic plate 300. An organic source 600 is supplied.

A target substrate 900 such as glass on which the organic material source 600 is vapor-deposited may be interposed between the magnetic plate 300 and the vapor deposition source supply unit 500. The FMM 100 that evaporates the organic material source 600 according to the pixel is in close contact with the target substrate 900 or is disposed in close proximity. The magnet 310 generates a magnetic field, and the FMM 100 can be in close contact with the target substrate 900 by the attraction force caused by the magnetic field.

The mask 100 (see FIG. 4) must be aligned before being in close contact with the target substrate 900. A mask or a plurality of masks can be combined with the frame 800. The frame 800 is fixed in the OLED pixel evaporation device 200, and the mask is combined with the frame 800 via an additional attachment and soldering step.

The vapor deposition source supply unit 500 reciprocates the left and right paths and supplies the organic material source 600. The organic material source 600 supplied from the vapor deposition source supply unit 500 can be vapor-deposited on the target substrate 900 by the pattern (PP) which has been formed in the FMM mask 100. One side. The organic source 600 evaporated by the pattern of the FMM mask 100 functions as a pixel 700 of the OLED.

In order to prevent uneven evaporation of the pixel 700 due to the shadow effect, the pattern (PP) of the FMM mask 100 may be obliquely formed (S) (or formed into a tapered shape (S)). The organic matter source 600 passing through the pattern (PP) along the inclined surface in the diagonal direction can also contribute to the formation of the pixel 700, and therefore, the pixel 700 can be entirely vapor-deposited with a uniform thickness.

Referring to FIG. 4, a plurality of display patterns (DP) may be formed on the body of the mask 100. The display pattern (DP) is a pattern corresponding to a display of a smart phone or the like. When the display pattern (DP) is enlarged, a plurality of pixel patterns (PP) corresponding to R, G, and B can be confirmed. The pixel pattern (PP) may have a side inclined shape, a tapered shape, an inverted tapered shape, or the like (refer to FIG. 6). Various pixel patterns (PP) are grouped to form one display pattern (DP), and a plurality of display patterns (DP) may be formed on the mask 100.

That is, in the present specification, the display pattern (DP) is not a concept of representing one pattern, and should be understood as a concept corresponding to a plurality of pixel patterns (PP) clustering of one display. Hereinafter, the pixel pattern (PP) is mixed with the mask pattern (PP).

Fig. 5 is an enlarged view of a mask according to an embodiment of the present invention. Fig. 6 is a side cross-sectional view taken along line A-A', B-B', and C-C' of Fig. 5.

Referring to FIGS. 5 and 6, the body of the mask 100 may include a plurality of shielding units 110. The shielding unit 110 is regarded as a unit constituent element constituting the main body of the mask 100, and may have other forms depending on the mask pattern (PP). In FIG. 5, four rectangular mask patterns (PP) (PP1 to PP4) are arranged one after another, and the mask 100 portion of the space between the mask patterns (PP) is considered as the shielding unit 110. . In the following description, the connection portion 115 connecting the shielding unit 110 and the adjacent shielding unit 110 is distinguished by the term different from the shielding unit 110. However, the shielding unit 110 is not physically distinguished from the connection portion 115. The element should be understood to belong to the concept that the connecting portion 115 is included in the shielding unit 110. In other words, the connecting portion 115 is a part or all of the frame portion and the rib portion of the shielding unit 110 included in the shielding unit 110, and the connecting portion 115 is integrally connected to the central portion 111 of the shielding unit 110, and the grouping is a matrix. For mask 100.

The mask 100 of the present invention is characterized in that the thickness of the central portion 111 of the shielding unit 110 is thicker than the thickness of the shielding unit frame portion 115. The frame portion 115 should be understood to include the concept of a frame, an rib, or a portion or all of the shielding unit 110. The frame portion 115 is also referred to as a joint portion 115.

Referring to AA' and FIG. 6(a) of FIG. 5, a space between a predetermined mask pattern (PP) and a mask pattern (PP) adjacent to the second mask may be formed to form a shielding unit 110 (center portion 111). . For example, the mask patterns that are closest to the mask pattern PP1 and are adjacent to each other are PP2 and PP4, and the mask pattern that is adjacent to the second and adjacent is PP3. A shielding unit 110 (center portion 111) is formed between the mask pattern PP1 and the mask pattern PP3, and may be formed to have a thickness T1. The thickness T1 is regarded as the thickness of the mask 100, which can be said to be the thickest thickness in the body of the mask 100. That is, the central portion 111 of the shielding unit 110 may be the portion that is formed to be the thickest in the body of the mask 100.

The shape of the shielding unit 110 (center portion 111) in the A-A' side section may be a tapered shape or an inverted tapered shape (in the case of turning over). The pattern (PP) of the mask 100 under the A-A' side section is similar to the general pyramid shape mask pattern.

Referring to B-B' and FIG. 6(b) of FIG. 5, a space between the predetermined mask pattern (PP) and the mask pattern (PP) adjacent thereto may be formed to form the joint portion 115 (or the shield unit 110). edge). For example, the mask patterns that are closest to the mask pattern PP1 and are adjacent to each other are PP2 and PP4, and the mask pattern that is adjacent to the second and adjacent is PP3. The joint portion 115 is formed between the mask pattern PP1 and the mask pattern PP2, the mask pattern PP1, and the mask pattern PP4, and may be formed to have a thickness T2. The thickness T2 has a value smaller than T1, which can be said to be the thinnest thickness in the body of the mask 100. That is, the coupling portion 115 (frame portion, rib portion) of the shielding unit 110 may be the portion that is formed to be the thinnest in the body of the mask 100. To be finished, the mask 100 may have a thickness of the thickest T1 at the central portion 111 of the shielding unit 110, and may have the thinnest thickness of T2 at the joint portion 115 (frame portion, rib portion).

The shielding unit 110 is integrally coupled to the adjacent shielding unit 110 through the connecting portion 115. In other words, the shielding unit 110 includes the connecting portion 115 and is integrally coupled to the adjacent shielding unit 110 through the connecting portion 115. In other words, the central portion 111 of the pair of shielding units 110 can be integrally coupled to each other through the connecting portion 115.

Referring to C-C' and Fig. 6(c) of Fig. 5, it is confirmed that only the mask unit 110 is removed by subtracting the mask pattern (PP). The shielding unit 110 alternately arranges the central portion 111 indicated by the width (R1) and the connecting portion 115 indicated by the width (R2).

The side cross-sectional shape of the joint portion 115 may have a triangular shape. The triangle also includes at least one of the sides and the ribs, and all of them are triangular. As will be described later, the upper portion of the pair of insulating portions 51 and 52 of the mother substrate 40 of the present invention is partially overlapped (OR), and the tunnel space (TR) generated at the lower portion is formed as a plating film (see FIG. 10 (c2)). ).

The mask 100 shown in FIG. 6 is invertible and is in close contact with the target substrate 900 in a state in which the mask pattern (PP) is displayed in a tapered shape (refer to FIG. 3). The connecting portion 115 has a thickness T2 thinner than the thickness T1 of the mask 100 and has a non-tapered triangular shape. Therefore, the interval between the mask patterns (PP) can be further shortened, and the OLED pixel 700 can be shortened to such an extent. interval. The gap (P) between the mask patterns (PP) in FIG. 6(a) corresponds to the width of the shielding unit 110 (the center portion 111), and on the other hand, the mask pattern (PP) in FIG. 6(b). The interval (P'') corresponds to the width of the connecting portion 115, and it can be easily confirmed to what extent the interval of the OLED pixels 700 is shortened. The OLED pixel 700 is formed by an organic source 600 that has been evaporated by a mask pattern (PP), and thus, the spacing of the mask patterns (PP) may directly correspond to the spacing of the OLED pixels 700.

As described above with reference to FIG. 2, the thickness of the mask forming the portion of the mask pattern (PP) cannot be adjusted in the past, and therefore, the pixel interval is limited by P'=2✽T/tan θ (here, T is a mask). The thickness, θ is the angle of the cone). In the present invention, the pixel interval P''=2✽T2/tanθ can be greatly reduced in accordance with the degree of reducing the thickness (T2) of the joint portion 115 (here, T is the thickness of the mask, and θ is the taper angle). ). If the thickness (T2) of the connecting portion 115 is 50% larger than the thickness (T1) of the central portion 111, the pixel interval (P'') is shortened to half compared to the conventional pixel interval, and therefore, the analysis is performed. The degree rises to 4 times its square effect. The thickness (T2) of the connecting portion 115 can be adjusted to 50% or less in comparison with the thickness (T1) of the central portion 111 in accordance with the thickness of the upper portion (OR) of the insulating portions 51 and 52. Therefore, the resolution can be reduced. The square of the thickness increases sharply.

Therefore, the mask 100 of the present invention has an effect of forming a mask pattern (PP) more finely and realizing an OLED of ultra-high quality. The invention can exceed the image quality of 500~600PPI (pixel per inch) and the pixel size reaches about 30~50μm, and realizes the ultra-high 4K UHD and 8K UHD with resolutions of ~860PPI and ~1600PPI. Quality, or higher quality.

On the other hand, in FIG. 5, in order to compare the central portion 111 of the shielding unit 110 with the connecting portion 115 and the mask pattern (PP) present therebetween, the illustration includes both the A-A' side section and the B-B' side section. Two types of masks 100 are described. However, in order to further achieve ultra-high image quality, the mask pattern (PP) may be displayed in the form of a B-B' side cross section so that the upper portions of all the insulating portions 51, 52 overlap (OR), and The lower space (tunnel space (TR)) forms a plating film, thereby completing the manufacture of the mask 100 (refer to FIG. 9). At this time, in all portions of the mask 100, the side cross-sectional shape of the body of the mask 100 may have a triangular shape. That is, the mask 100 does not have the tapered central portion 111, and the body portion of all the masks 100 has a shape like the connecting portion 115.

Referring again to FIG. 5, as an example, four mask patterns (PP1 to PP4) are disposed around one of the shielding units 110, and the edge of the mask pattern (PP) and the edge of the shielding unit 110 may be formed in an arc shape. Further, the mask pattern (PP) and the shielding unit 110 are alternately arranged in a lattice shape. There may be a so-called Ppentile configuration.

Fig. 7 is an electron micrograph of a mask according to an embodiment of the present invention. Fig. 7(a) shows a mask pattern (PP) and a shielding unit 110 which are alternately arranged in a lattice shape, Fig. 7(b) shows an enlarged shielding unit 110, and Fig. 7(c) shows a side sectional shape of the shielding unit 110.

Referring to Fig. 7(a), it is confirmed that the center portion 111 of the shielding unit 110 is formed thickly, and the connecting portion 115 (edge portion, frame portion) is formed thin. Moreover, referring to FIG. 7(b), it can be confirmed that the cross section of the connecting portion 115 has a triangular shape, and the interval between the two mask patterns (PP) is formed to be very close to each other via the connecting portion 115. Further, referring to Fig. 7(c), it can be confirmed that the center portion 111 displays a taper angle of about 45°.

Figure 8 is a perspective view of a motherboard 40, 40' in accordance with various embodiments of the present invention. Fig. 8 is an exaggerated representation of a portion of the mother board 40, 40', which is understood to be not limited to the configuration shown in Fig. 8.

Referring to Fig. 8, a mother board 40 according to an embodiment of the present invention may include a conductive substrate 41 and a plurality of insulating portions 50.

The mother board 40 is used as a cathode body in electroforming plating. In order to perform electroforming plating, the mother substrate 40 preferably contains a conductive substrate 41.

As a conductive material, in the case of a metal, a metal oxide may be formed on the surface, and an impurity may flow in the metal production process. In the case of a polycrystalline germanium substrate, there may be inclusions or grain boundaries (Grain Boundary). In the case of a conductive polymer substrate, there is a high possibility of containing impurities, and the strength, acid resistance, and the like are weak. An element that uniformly forms an electric field on the surface of the mother substrate 40 like a metal oxide, an impurity, an inclusion, or a grain boundary is called a "defect". Due to the defect, the cathode body of the above material cannot apply a uniform electric field, and a part of the plating film 100 may be unevenly formed. Moreover, in the case of the polycrystalline substrate material, the heat treatment step for reducing the thermal expansion coefficient of the electroformed plating film changes the position of the pattern formed on the mask due to the unevenness between the crystal grains, which involves The problem of changing the position of the pixel evaporation.

When the ultra-high-quality pixels of the UHD level or higher are specifically realized, the unevenness of the plating film 100 and the plating film pattern (PP) may adversely affect the formation of the pixels. The pattern of the FMM and the shadow mask (PP) may be formed in a size of several to several tens of μm, and desirably, a size of less than 40 μm, so that even a defect of a size of several μm is occupied in the pattern size of the mask. The size of the large proportion.

Further, in order to remove the defects of the cathode body of the above-mentioned material, an additional step for removing metal oxides, impurities, and the like is performed, and in the process, the cathode material or the like is etched, and other defects may be further caused.

Therefore, the substrate 41 of a single crystal germanium material can be used in the present invention. In order to have conductivity, the substrate 41 is doped at a high concentration of 10 ¹⁹ or more. The doping may be performed on the entire substrate 41 or only on the surface portion of the substrate 41.

A plurality of insulating portions 50 (51, 52, ...) may be formed on at least one surface of the conductive substrate 41. The insulating portion 50 is formed to protrude from one surface of the substrate 41 (by letterpress printing), and may have insulating properties in order to prevent the formation of the plating film 100. Thereby, the insulating portion 50 can be formed of a material of any one of a photoresist material, yttrium oxide, and tantalum nitride. The insulating portion 50 may be formed of ruthenium oxide or tantalum nitride on the substrate 41 by a method such as vapor deposition, and a thermal oxidation (Thermal Oxidation) or a thermal nitridation method may be used on the substrate 41 as a base. A photoresist material can also be formed using a printing method or the like. When a pattern is formed using a photoresist material, a multiple exposure method, a method in which the exposure intensity is different for each region, and the like can be used. The insulating portion 50 may be thicker than the plating film 100 and have a thickness of about 5 μm to 20 μm.

Each of the insulating portions 50 may have a shape in which the width gradually narrows from the upper portion toward the lower portion. For example, the vertical side section of the insulating portion 50 may have an inverted tapered shape.

The insulating portion 50 can be formed to have a pattern on the conductive substrate 41. That is, the region occupied by the insulating portion 50 on the conductive substrate 41 has a pattern, and the region occupied by the insulating portion 50 can correspond to the mask pattern (PP). The plating film 100 is formed on the surface exposed from the substrate 41 in the electroforming plating process to be described later, and the pattern (PP) can be formed in the region where the insulating portion 50 is disposed to prevent the formation of the plating film 100. Since the mother board 40 can form a pattern even during the formation of the plating film 100, it is described in combination with the mold and the cathode body.

The mother board 40 of the present invention is characterized in that the insulating portion 50 has a shape in which the width gradually narrows from the upper portion toward the lower portion, and any of the insulating portions 51 and at least the upper portions 51a and 52a of the insulating portion 52 adjacent thereto are connected (OR). That is, the upper portions 51a and 52a of the insulating portions 51 and 52 adjacent to each other are connected, and the lower portions 51b and 52b are not connected. Here, the upper portions 51a and 52a are connected to each other (OR), and it is understood that the upper portions of the insulating portions 51 and 52 are further provided with an insulating portion of the same material and the two insulating portions 51 and 52 are connected. Alternatively, the upper portions 51a and 52a are overlapped by forming a space in which the insulating portions 51 and 52 having the same shape are formed in a narrow manner. Accordingly, the portion in which the upper portions 51a and 52a are connected and overlapped (OR) is also referred to as a "bridge". Fig. 8(a) is regarded as a form in which the upper portions 51a and 52a are overlapped (OR), and Fig. 8(b) is considered to have a smaller degree of overlap (OR) and is close to the upper portion of the insulating portions 51' and 52'.

Further, referring to Fig. 8, the insulating portion 51 and the lower portions 51b and 52b of the insulating portion 52 adjacent thereto are not connected, and a void space (TR) can be formed. Here, the void space (TR) is also referred to as "tunnel space" (TR).

The height, width, size, and the like of the tunnel space (TR) can be changed by the (reverse) taper angle of the insulating portions 50 (51, 52, ...), the thickness of the upper portions 51a, 52a of the joint/overlap (OR), and the like. Therefore, the pixel interval can be variously controlled.

In the electroforming plating process, the formation of the plating film 100 is prevented on the insulating portion 50, and the plating film 100 has a pattern (PP), and the plating film 100 can be formed in the tunnel space (TR). Therefore, the height, width, size, and the like of the control tunnel space (TR) may correspond to the size of the mask pattern (PP) for controlling the plating film 100 (mask 100), and the control of the mask pattern (PP) size corresponds to the pixel. Control of the interval. As an example, the width of the mask pattern (PP) may be formed to a size smaller than 40 μm, and therefore, the distance between the tunnel space (TR) and the adjacent tunnel space (TR) is preferably formed to be smaller than 40 μm.

Of course, the height of the tunnel space (TR) is formed to be smaller than the height of the insulating portion 50. When the insulating portion 50 has an inverted tapered shape, the vertical side sectional shape of the tunnel space (TR) may have a triangular shape. The triangle also includes edges and corners that are rounded and all triangular.

Fig. 8(a) shows an insulating portion 50 having an inverted quadrangular shape on the upper and lower substantially quadrangular shapes, and an arbitrary insulating portion 51 and an upper portion 51a, 52a of the insulating portion 52 adjacent thereto are partially overlapped (OR). The plurality of insulating portions 50 are arranged in one direction in a state of being overlapped (OR). Here, the form in which the tunnel space (TR) is opened in one direction is revealed.

Fig. 8(b) shows an insulating portion 50' having an inverted quadrangular shape in a substantially quadrangular upper portion and a lower portion, and an arbitrary insulating portion 51' and an upper portion of the insulating portion 52' adjacent thereto are connected to the apex portion (OR' ) (or overlap (OR)). The plurality of insulating portions 50 are arranged in two directions (for example, X and Y axis directions) in a state of being connected to each other (OR'). Here, the tunnel space (TR') is opened in two directions.

Fig. 9 is an electron micrograph showing the form of an insulating portion according to various embodiments of the present invention.

Fig. 9(a) shows a conventional mother board 40''. It is an electron micrograph of the mother board 40 ′′, and the mother board 40 ′′ includes an insulating portion 50 ′′ of a general inverted tapered shape in which the insulating portions 50 ′′ are not connected or overlapped with each other and the tunnel space (TR) is not formed. .

Fig. 9(b) is an electron micrograph of the mother board 40. The mother board 40 is provided with a plurality of insulating portions 50 in one direction shown in Fig. 8(a), and the upper portion of the insulating portion 50 is overlapped, and a tunnel is formed at the lower portion. Space (TR).

9(c) and 9(d) are electron micrographs of the mother board 40'. The mother board 40' is provided with a plurality of insulating portions 50' along the two directions shown in Fig. 8(b), and the insulating portion The upper portion of the 50' overlaps (OR') and forms a tunnel space (TR') at the lower portion.

As described above, the mother board 40, 40' of the present invention can form the mask 100 only by forming a plating film in the tunnel space (TR, TR'), and the side cross-sectional shape has a triangular shape in all portions of the mask 100. That is, when the mother board 40, 40' is used for electroforming plating, the mask 100 does not have the tapered center portion 111 (see FIG. 5), and all of the masks 100 have the connection portion 115 ( Refer to the shape of Figure 5). With such a mother board 40, 40', an ultra-high quality OLED can be further realized.

Figure 10 is a schematic view showing the manufacturing process of the mask 100 according to an embodiment of the present invention. Hereinafter, a process of manufacturing the mask 100 including the A-A' side section and the B-B' side section of Fig. 5 using the mother board 40 of Fig. 8(a) will be described. The formation process of the A-A' side cross-sectional shape is shown in (b1), (c1), (d1), and the formation process of the B-B' side cross-sectional form is shown in (b2), (c2), and (d2).

First, referring to Fig. 10 (a), a conductive substrate 41 is prepared for electroforming plating. The mother substrate 40 containing the conductive substrate 41 is used as a cathode body in electroforming plating. The conductive substrate 41 can be used as described above.

Next, referring to FIG. 10 (b1) and FIG. 10 (b2), the insulating portion 50 can be formed on at least one surface of the substrate 41. The insulating portion 50 preferably has an inverted tapered shape. On the other hand, referring to Fig. 10 (b2), at least the upper portions 51a, 52a of the plurality of insulating portions 50 (51, 52, ...) can be connected (OR) (or overlapped (OR)). That is, the predetermined insulating portion 51 is connected (OR) (or overlapped (OR)) with at least the upper portions 51a, 52a of the insulating portion 52 adjacent thereto to form a bridge, and the lower portions 51b, 52b are not overlapped to form a void space ( TR), tunnel space (TR).

Next, referring to Fig. 10 (c1) and Fig. 10 (c2), an anode body (not shown) facing the mother board 40 (or the cathode body 40) is prepared. The anode body (not shown) is immersed in a plating solution (not shown), and the mother board 40 is immersed in a plating solution (not shown) in whole or in part. The plating film 100 can be electrically deposited on the surface of the mother substrate 40 by an electric field formed between the mother substrate 40 (or the cathode body 40) and the opposing anode body. However, the plating film 100 is formed only on the surface on which the conductive substrate 41 is exposed, and the plating film 100 is not formed on the surface of the insulating portion 50. Therefore, the pattern (PP) can be formed on the plating film 100.

The plating solution is an electrolyte solution and can be used as a material for the plating film 100 constituting the mask 100. As an embodiment, when a constant steel sheet belonging to an iron-nickel alloy is produced as the plating film 100, a mixed solution of a solution containing Ni ions and a solution containing Fe ions can be used as the plating solution. In another embodiment, when a super-constant steel sheet belonging to an iron-nickel-cobalt alloy is produced as the plating film 20, a mixture of a solution containing Ni ions, a solution containing Fe ions, and a solution containing Co ions may be used as plating. Apply fluid. Invariant steel sheets and super-constant steel sheets are used in the manufacture of OLEDs as FMMs and shadow masks. Moreover, the thermal expansion coefficient of the invariable steel sheet is about 1.0×10 ^-6 /°C, and the thermal expansion coefficient of the ultra-Huangfan steel sheet is about 1.0×10 ^-7 /°C, which is very low. Therefore, the pattern shape of the mask is deformed by thermal energy. It is small and is mainly used in high-resolution OLED manufacturing. In addition to this, the plating solution with respect to the desired plating film 100 can also be used without limitation. In the present specification, assuming that a constant steel sheet is manufactured as a main example.

Since the plating film 100 is thickly adhered from the surface of the substrate 41, it is preferable to form the plating film 100 only before the upper end of the insulating portion 50. That is, the thickness of the plating film 100 is smaller than the thickness of the insulating portion 50. Since the plating film 100 is filled and electrically adhered to the pattern space of the insulating portion 50, it can be formed into a tapered shape having a reverse phase with the pattern of the insulating portion 50 (see FIG. 10 (c1)).

Since the insulating portion 50 has an insulating property, no electric field is formed between the insulating portion 50 and the anode body, or only a weak electric field which is hard to be plated is formed. Therefore, the portion of the mother board 40 corresponding to the insulating portion 50 where the plating film 100 is not formed may constitute a pattern, a hole, or the like of the plating film 100. In other words, the insulating portion 50 can respectively form a mask pattern (PP) corresponding to R, G, and B of the body of the mask 100. The side cross-sectional shape of the mask pattern (PP) may be formed to be inclined to be substantially tapered, and the inclination angle (taper angle) may be about 45 to 65 degrees.

In FIG. 10 (c1), the shielding unit 110 (center portion 111) having a tapered side cross-sectional shape is electrically connected to the insulating portion 50. The shielding unit 110 may be formed not to exceed the thickness (T1) of the insulating portion 50.

On the other hand, in FIG. 10(c2), the shielding unit 110 having a side cross-sectional shape of a triangle having at least one of a triangle or a side and an edge of an arc shape can be electrically attached to the tunnel space (TR) ( Connection portion 115). The shielding unit 110 (the joint portion 115) may be formed not to exceed the thickness (T2) of the tunnel space (TR). The method of electroforming plating in the tunnel space (TR) is called "tunnel plating", and the mask plated in the tunnel space (TR) is called "tunnel mask". That is, the connecting portion 115 may also be referred to as a tunnel mask.

The plating film formed in the tunnel space (TR) can integrally connect the connection portion 115 between the shielding units 110 (the center portion 111). Since the plating film 100 is formed on the surface of the conductive substrate 41 during the electroforming plating, the plating film is formed in the tunnel space (TR) having a small thickness (low height) to form the connecting portion 115, and then, When electroforming plating is performed to further thicken the plating film 100, the shielding unit 110 (center portion 111) can be formed.

On the other hand, after the plating film 100 is formed, the plating film 100 can be heat-treated. The heat treatment can be carried out at a temperature of from 300 ° C to 800 ° C. In general, the constant thermal steel sheet produced by electroforming plating has a high coefficient of thermal expansion as compared with the invariable steel sheet produced by calendering. Accordingly, the thermal expansion coefficient can be lowered by heat-treating the invariable steel sheet, however, the constant steel sheet may undergo some deformation during the heat treatment. Therefore, when the mother board 40 (or the substrate 41) is heat-treated in a state in which the mask 100 is next, the form of the mask pattern (PP) formed in the space portion of the insulating portion 50 of the mother board 40 can be kept constant. It has the advantage of preventing micro-deformation caused by heat treatment. Further, after the mother substrate 40 (or the substrate 41) is separated from the plating film 100, even if the mask 100 having the mask pattern (PP) is subjected to heat treatment, the thermal expansion coefficient of the constant steel sheet is lowered.

Therefore, by further reducing the thermal expansion coefficient of the mask 100, deformation of the μm-scale pattern (PP) can be prevented, and there is an advantage that a mask 100 capable of evaporating ultra-high-quality OLED pixels can be manufactured.

Next, referring to FIG. 10 (d1) and FIG. 10 (d2), the mother substrate 40 (or the cathode body 40) is lifted up to the outside of the plating liquid (not shown), and then the plating film 100 is separated from the mother board 40. The step of removing the insulating portion 50 may be performed by separating the plating film 100 from the mother substrate 40. When the plating film 100 is separated from the mother substrate 40 outside the plating solution, the portion where the plating film 100 is formed may constitute the mask 100 (or the mask body), and the portion where the plating film 100 is not formed may constitute the mask pattern. (PP).

Fig. 9 is an electron micrograph showing the form of an insulating portion according to various embodiments of the present invention.

Fig. 9(a) shows a mother board 40'' which includes a general inverted cone-shaped insulating portion 50 which does not form a tunnel space (TR), and Fig. 9(b) shows a mother board 40, the mother board The plate 40 overlaps the upper portion of the insulating portion 50 along a line and forms a tunnel space (TR) at the lower portion.

Further, in FIGS. 9(c) and 9(d), the mask pattern (PP) is represented only by the side of the BB' side of FIG. 5 or the form of FIG. 6(b), so that all the insulating portions 50 are provided. The upper part overlaps (OR). At this time, the mask 100 is formed only by forming a plating film in the tunnel space (TR), and the side cross-sectional shape may have a triangular shape in all portions of the mask 100. That is, when the mother board 40 is used for electroforming plating, the mask 100 does not have the tapered center portion 111, and all of the masks 100 have a shape like the connecting portion 115. With such a mother board, an ultra-high quality OLED can be further realized.

As described above, the present invention has an effect of performing electroforming plating in the lower space (TR) between the insulating portions 50 to form the mask pattern (PP) finely. Thereby, there is an effect of an ultra-high quality OLED which can be realized in an existing method.

As described above, the present invention has been described with reference to the preferred embodiments. However, the present invention is not limited thereto, and various modifications and changes can be made without departing from the spirit and scope of the invention. It is to be understood that such modifications and variations are within the scope of the invention and the scope of the appended claims.

Industrial Applicability The present invention can be applied to a field related to a mask, a method of manufacturing the same, and a mother board.

10‧‧‧Substrate

13, 13’, 13’’‧‧‧ shadow masks

15‧‧‧Source supply mechanism

17‧‧‧ source

18,700‧‧‧ pixels

40, 40’, 40’’‧‧‧ Motherboard

41‧‧‧Electrically conductive substrate

50, 50', 51, 51', 52, 52' ‧ ‧ insulation

51a, 52a‧‧‧ upper

51b, 52b‧‧‧ lower

100‧‧‧Mask, shadow mask, FMM

110‧‧‧Shielding unit

111‧‧‧ Central Department

115‧‧‧Connection, frame, ridge

200‧‧‧OLED pixel evaporation device

300‧‧‧ magnetic board

310‧‧‧ magnet

350‧‧‧Cooling water pipeline

500‧‧‧Decanting source supply department

600‧‧‧Organic source

800‧‧‧Frame

900‧‧‧Object substrate

DP‧‧‧ display pattern

F, PP, PP', PP1~PP4‧‧‧ pixel pattern, mask pattern

OR, OR’‧‧‧Insulation upper overlap area

P, P’, P’’‧‧‧ interval

R1, R2‧‧‧ width

S‧‧‧ cone shape

Thickness of the central part of T1‧‧

Thickness of T2‧‧‧ joints

TR, TR’‧‧‧low space, tunnel space, void space

FIG. 1 is a schematic diagram showing a conventional pixel forming step. Fig. 2 is a schematic view showing a conventional high-resolution shadow mask 13' for OLED formation. 3 is a schematic view showing an OLED pixel evaporation apparatus using an FMM. Figure 4 is a schematic view showing a mask. Fig. 5 is an enlarged view of a mask according to an embodiment of the present invention. Fig. 6 is a side cross-sectional view taken along line A-A', B-B', and C-C' of Fig. 5. Fig. 7 is an electron micrograph of a mask according to an embodiment of the present invention. Figure 8 is a perspective view of a motherboard in accordance with various embodiments of the present invention. Fig. 9 is an electron micrograph showing the form of an insulating portion according to various embodiments of the present invention. Figure 10 is a schematic view showing a manufacturing process of a mask in accordance with an embodiment of the present invention.

Claims (17)

A mask is manufactured by electroforming plating, and further comprises a mask body and a plurality of mask patterns, the mask body includes a plurality of shielding units, and a thickness of a central portion of the shielding unit is larger than a shielding unit frame portion The thickness is thick. The mask of claim 1, wherein the space between the predetermined mask pattern and the mask pattern adjacent to the mask pattern is formed, and the shielding unit is integrally coupled to the adjacent shielding unit through the connecting portion. The mask of claim 2, wherein the joint portion is the thinnest portion formed in the mask body. The mask of claim 2, wherein the side cross-sectional shape of the connecting portion is a triangle, or at least one of the side and the rib is a circular arc shape. The mask of claim 1, wherein the shielding unit is formed in a space between the predetermined mask pattern and the mask pattern adjacent to the second adjacent one. The mask of claim 5, wherein the central portion of the shielding unit is the thickest portion of the mask body. The mask of claim 1, wherein the mask is made of constant steel or super constant steel. A method for manufacturing a mask, which is a method for manufacturing a mask by electroforming plating, comprising the steps of: (a) providing a cathode body comprising a conductive substrate and a surface of the substrate Forming a plurality of insulating portions having a pattern thereon; (b) immersing at least a portion of the cathode body and the anode body disposed apart from the cathode body in the plating solution, and applying an electric field between the cathode body and the anode body; And the step (c), forming a plating film on the surface of the cathode body to form a mask body including a plurality of shielding units, and forming a plurality of mask patterns on the surface of the insulating portion to prevent formation of a plating film; At least a part of the frame portion of the unit is plated in the tunnel space of the insulating portion, and is formed to have a thickness thinner than a central portion of the shielding unit. A method of manufacturing a mask according to claim 8, wherein the tunnel space is formed by overlapping a predetermined insulating portion with at least an upper portion of the insulating portion adjacent thereto. A method of manufacturing a mask according to claim 9, wherein the plating film formed in the tunnel space integrally connects the joint portion between the shielding units. A method of manufacturing a mask according to claim 8, wherein in the step (c), after the plating film has been formed in the tunnel space, plating is further performed to form a shielding unit. The method of manufacturing a mask according to claim 8, wherein the predetermined insulating portion is disposed apart from the second insulating portion adjacent to the second insulating portion without overlapping, and the plating film formed in the partitioning space constitutes the shielding unit. A mother board is a mother board used for manufacturing a mask by electroforming plating, comprising: a conductive substrate; and a plurality of insulating portions disposed on one surface of the conductive substrate to form a pattern; The insulating portion has a shape in which the width gradually narrows from the upper portion toward the lower portion, and the predetermined insulating portion and at least an upper portion of the insulating portion adjacent thereto are coupled. The motherboard of claim 13 wherein at least a lower portion of the predetermined insulating portion and the insulating portion adjacent thereto are not joined to form a tunnel space. The mother board of claim 13 wherein the insulating portion and the upper portion of the insulating portion adjacent thereto are partially overlapped, or the apex portion of the upper portion is partially overlapped. The mother board of claim 13, wherein the conductive substrate is a doped single crystal germanium material. The mother board of claim 13, wherein the mother board is used as a cathode body in electroforming plating.