TW201904072A - Semiconductor device, display device, and sputtering target which has good reliability even with copper wiring - Google Patents

Abstract

A semiconductor device according to the present invention includes a substrate, a conductive wiring line provided on one surface of the substrate, and a thin film transistor electrically connected to the conductive wiring line. The conductive wiring line has a three-layer structure in which a copper layer or a copper alloy layer is sandwiched between a first conductive metal oxide layer and a second conductive metal oxide layer. The first conductive metal oxide layer and the second conductive metal oxide layer include indium oxide. The thin film transistor has a channel layer composed of an oxide semiconductor. The oxide semiconductor is made of composite oxide containing indium oxide, antimony oxide, and cerium oxide in an amount that is smaller than the respective amounts of indium oxide and antimony oxide. In the oxide semiconductor, the respective amounts of indium and antimony in the oxide semiconductor are 40 at% or more if the total amount of the constituent elements excluding oxygen is taken as 100 at%.

Description

 Semiconductor device, display device, and sputtering target  

The present invention relates to a semiconductor device, a display device, and a sputtering target.

A thin film transistor using an oxide semiconductor as a channel layer has a leakage current of two digits as compared with a germanium semiconductor, and has attracted attention as a power saving device. Further, since such a thin film transistor is resistant to high voltage, it has also been attracting attention for use in power semiconductor devices.

Further, in a circuit configuration using a germanium semiconductor or a circuit configuration using an oxide semiconductor, a conductive wiring having a low resistance is preferable in terms of a conductive wiring electrically connecting the circuit constituent elements in the above-described device. Since the resistivity (specific resistance) of aluminum is 2.7 μΩcm and the resistivity of copper is 1.7 μΩcm, it is attempted to change from aluminum wiring to copper wiring as a low-resistance conductive wiring. In recent years, copper wiring having better conductivity has been desired.

For example, Patent Document 1 provides a metal wiring including a copper layer sandwiched between oxide layers containing indium and zinc. The content of zinc oxide is set to 10% by weight or more and less than 35% by weight. In paragraph [0050] of Patent Document 1, it is referred to as zinc oxide (ZnO), indium oxide (InO), or the like. In the claim 1 of Patent Document 1, there is no specific description about the indium of the metal element contained in the oxide, and the definition of the metal element is not shown, so the atomic ratio (at%) of the metal element is not clear. In the case of indium oxide (InO), the atomic ratio of the oxide layer is about 15 at% under the condition that the lower limit of the content of zinc oxide is 10% by weight. When the amount of the zinc element exceeds 10 at% with respect to the total of the indium element and the zinc element, the alkali resistance becomes large, and it is difficult to obtain an ohmic contact. The more the amount of zinc, the more pronounced this tendency. In addition, when the amount of the zinc element exceeds 10 at%, the surface resistance of the composite oxide containing zinc oxide and indium oxide is lowered, which may hinder the step of electrically attaching such a metal wiring to a substrate or the like. Patent Document 1 does not disclose such a problem. Further, Patent Document 1 does not disclose any problem regarding migration or diffusion of copper.

On the other hand, in the technique for improving the adhesion of copper to a glass substrate or a tantalum substrate, Patent Document 2 and Patent Document 3 disclose zinc (Zn), calcium (Ca), magnesium (Mg), and manganese (Mn). A method of adding copper as an alloying element. However, in Patent Document 2 and Patent Document 3, since the copper alloy is directly in contact with the semiconductor layer constituting the glass substrate or the thin film transistor, the copper element to the copper layer (copper alloy layer) cannot be completely suppressed. The problem of diffusion of the substrate (base layer, glass substrate or semiconductor layer). Further, in Patent Document 2 and Patent Document 3, of course, a three-layer structure in which a copper alloy layer is sandwiched by a conductive metal oxide layer is not disclosed.

In the conductive wiring which is formed directly on the substrate by using a copper alloy, for example, when the conductive wiring is formed to have a line width (thin line) having a width of 10 μm or less, the conductive wiring may be peeled off from the substrate in the manufacturing step. For example, in the conductive wiring formed in the wet etching step, there may be partial peeling due to electrostatic breakdown in the developing step such as the cleaning step or the semiconductor pattern step performed after the wet etching step (the shortage of the conductive wiring or Broken line). The finer the line width of the conductive wiring, the more pronounced the tendency of the conductive wiring to peel off. The subject of such a manufacturing step is not disclosed in Patent Document 1, Patent Document 2, and Patent Document 3.

Patent Document 4 discloses an element such as In, Ga, Zn, Sn, or Sb as an oxide semiconductor film. However, in the disclosure of paragraph [0030], the oxide semiconductor composition is not described in detail except for the In-Zn system and the Sn-In-Zn system, and for example, the effect or efficacy when using cerium oxide or cerium oxide is not described. .

Prior technical literature Patent literature

Patent Document 1 Japanese Patent Laid-Open Publication No. 2014-78700

Patent Document 2 Japanese Patent Laid-Open Publication No. 2011-91364

Patent Document 3 Japanese Patent No. 5099504

Patent Document 4 Japanese Patent Laid-Open Publication No. 2007-73704

Aluminum wiring is low-resistance wiring and has practical reliability due to aluminum passivation. Therefore, aluminum wiring is often used for the conductive wiring used for the functional device. However, it is easy to generate hillocks (hemispherical) on the surface of the aluminum wiring due to the heat history in the manufacturing process of the functional device having high purity and excellent electrical conductivity, or long-term storage. When the protrusions are equal to each other, reliability such as insulation failure is likely to be lowered. In order to solve the problem of occurrence of hillocks, an aluminum alloy to which a metal such as a small amount of Nd (钕) or Ta (钽) is added is generally used.

The high-purity aluminum has a resistivity of 2.7 μΩcm, and the increase in the resistivity caused by adding Nd or Ta to aluminum is 3.7 μΩcm/at% and 8.6 μΩcm/at%, respectively. In other words, by adding 1 at% of Nd to aluminum, the electrical resistivity of the aluminum alloy (Al-Nd-based alloy) is calculated to be 6.4 μΩcm, and the electrical resistivity is deteriorated compared with the high-purity aluminum. Further, in general, the target resistivity in the aluminum alloy wiring is set to 6 μΩcm or less.

Copper alloy wiring is superior to aluminum alloy wiring from the viewpoint of alkali resistance. Even from the viewpoint of such chemical resistance, it is required to use copper alloy wiring as a conductive wiring for use in a functional device. Furthermore, aluminum or aluminum alloys cannot obtain ohmic contact to transparent electrodes such as ITO. Therefore, even from the viewpoint of ohmic contact, it is expected to use copper or a copper alloy as the conductive wiring used for the functional device.

Compared to aluminum, high-purity copper has a resistivity of 1.7 μΩcm, and copper wiring is expected as a conductive wiring instead of aluminum alloy wiring. However, the copper wiring has a disadvantage that copper is easily diffused to cause a decrease in reliability, and the surface of copper is not passivated, copper oxide is formed over time, and the amount of copper oxide is increased. When the film thickness of the copper oxide formed on the surface of copper increases, the surface resistance becomes high, and a problem arises in the step of electrically attaching the copper wiring to the substrate or the like. The formation of the copper oxide in the copper wiring not only increases the surface resistance of the copper wiring, but also the threshold voltage (Vth) of the thin film transistor varies (deviation) due to variations in contact resistance, which is less desirable. In the electrical mounting of the copper wiring or the copper alloy wiring for the electrode or the like, in order to remove the copper oxide on the wiring surface, it is necessary to perform a pretreatment such as chelation cleaning.

In the electronic device, in order to suppress the diffusion of copper which is a fundamental problem due to the characteristics of copper, a three-layer structure in which copper is sandwiched by a high melting point metal such as titanium (Ti), molybdenum (Mo) or tungsten (W) is often used. Or two layers. However, such high melting point metals are difficult to pattern (form a pattern) together with copper (using a one-component etchant, once). A pattern of Ti or Mo or the like is often formed by an etching liquid different from the etching liquid phase used for patterning copper, or patterned by dry etching. For example, in a liquid crystal display device, a wiring having a two-layer structure of titanium/copper may be formed on an insulating layer such as ruthenium oxide.

Furthermore, in the step of forming a circuit or the step of forming a matrix of thin film transistors constituting the display device, between the connection point (pad or the like) of the circuit element or the thin film transistor, and the wiring located at the upper portion of the connection point, Electrical contact is taken through the through holes. At this time, since a copper oxide layer is formed on the surface of the above-mentioned high melting point metal or the surface of copper, a high contact resistance is often generated. In other words, in the conventional copper wiring, it is difficult to obtain an ohmic contact required for electrical mounting. Further, the copper film exposed to the air grows abnormally during heat treatment, and is liable to be degraded on the surface of the film, which tends to deteriorate the electrical resistivity.

Further, a channel layer (oxide semiconductor layer) formed of a composite oxide containing indium oxide and gallium oxide and zinc oxide called IGZO has a reliability of crystallization, so that it is 400 to 700. The temperature range of °C is mostly heat treated. In the manufacturing process of a liquid crystal display device or the like, in the heat treatment, titanium and copper are mutually diffused, and the electrical conductivity of the copper wiring is greatly deteriorated. In the case where the heat treatment is not performed, the variation of the threshold voltage (Vth) due to the change with time in the channel layer formed of IGZO is not practical. With respect to the variation of the threshold voltage (Vth) caused by the change in time, the change in the impurity level of the oxygen defect or the like in the oxide semiconductor layer is considered to be hydrogen occluded in the oxide semiconductor layer. influences. Titanium or titanium nitride easily absorbs hydrogen, and changes in the characteristics of the transistor due to hydrogen contained in the metal electrode or the metal wiring are also expected. Further, when the source electrode or the gate electrode is formed of titanium or copper, a metal such as titanium which is in contact with the channel layer reduces an oxide semiconductor which forms a channel layer (oxide semiconductor layer), and causes transistor characteristics. Reduce the situation. In the manufacturing process of a thin film transistor having a channel layer formed of IGZO or the like, a low-temperature process that does not cause deterioration in conductivity of the copper wiring is required.

Further, in the case of indium oxide or ruthenium oxide, in the vacuum film formation such as sputtering, oxygen deficiency may occur, and it is difficult to obtain sufficient semiconductor characteristics. Further, the channel layer formed of an oxide semiconductor containing indium oxide or ruthenium oxide is easily subjected to etching damage in the step of forming a source electrode or the like using a manufacturing process such as wet etching. There is a need for an oxide semiconductor that is hardly affected by an etchant used for wet etching.

The present invention has been made in view of the above problems, and it is an object of the invention to provide a semiconductor device, a display device, and a sputtering target which can be easily manufactured even if copper wiring is used.

A semiconductor device according to a first aspect of the present invention includes: a substrate; a conductive wiring provided on one surface of the substrate; and a thin film transistor electrically connected to the conductive wiring; wherein the conductive wiring has a copper layer or a copper alloy layer a three-layer structure in which a conductive metal oxide layer and a second conductive metal oxide layer are sandwiched; the first conductive metal oxide layer and the second conductive metal oxide layer include indium oxide; and the film The transistor has a channel layer composed of an oxide semiconductor; the oxide semiconductor-based composite oxide, the composite oxide comprising indium oxide, antimony oxide, and having a quantity more than each of the indium oxide and the foregoing antimony oxide In the oxide semiconductor, when the total of the elements of the uncounted oxygen is 100 at%, the amount of each of indium and antimony is 40 at% or more.

In the semiconductor device according to the first aspect of the present invention, in the oxide semiconductor, when the total amount of uncounted oxygen indium, antimony, and antimony is 100 at%, the amount of each of indium and antimony may be 45 at. In the range of % or more and 49.8 at% or less, the amount of ruthenium may be in the range of 10 at% or less and 0.4 at% or more.

In the semiconductor device according to the first aspect of the present invention, the thin film transistor may have an insulating film in which the channel layer contacts and contains at least yttrium oxide.

In the semiconductor device according to the first aspect of the present invention, the copper alloy layer may include a first element which is solid-solubilized in copper, and a second element having a lower electrical property than copper and the first element; and the first element and The second element is an element having a specific resistance increase rate of 1 μΩcm/at% or less when added to copper, and the specific resistance of the copper alloy layer is in a range of 1.9 μΩcm to 6 μΩcm.

In the semiconductor device according to the first aspect of the invention, in the copper alloy layer, the first element is zinc, the second element is calcium, and when the total of copper, zinc, and calcium is 100 at%, the copper is The alloy layer may contain the first element in a range of 0.2 at% or more and 5.0 at% or less, and may contain the second element in a range of 0.2 at% or more and 5.0 at% or less, and may contain copper as a remaining portion.

In the semiconductor device according to the first aspect of the present invention, the first conductive metal oxide layer and the second conductive metal oxide layer contain indium oxide as a main conductive metal oxide and are selected from the group consisting of oxidation. One or more types of conductive metal oxides of the group consisting of ruthenium, zinc oxide, and gallium oxide.

A display device according to a second aspect of the present invention includes the semiconductor device of the first aspect.

A display device according to a second aspect of the present invention includes an antenna formed of a conductive wiring having a copper layer or copper sandwiched between the first conductive metal oxide layer and the second conductive metal oxide layer The alloy layer has a three-layer structure; the first conductive metal oxide layer and the second conductive metal oxide layer may further include indium oxide.

A sputtering target according to a third aspect of the present invention is a sputtering target used in the manufacture of a semiconductor device according to a first aspect, comprising indium oxide and antimony oxide as a main material, and containing cerium oxide as a stabilizer. In the composite oxide, when the total of indium, antimony, and antimony of uncounted oxygen is 100 at%, the amount of each of indium and antimony is in the range of 45 at% or more and 49.8 at% or less. The amount of ruthenium is in the range of 10 at% or less and 0.4 at% or more.

A sputtering target according to a fourth aspect of the present invention is a sputtering target used for forming a copper alloy layer of a semiconductor device of a first aspect, which contains a first element which is solid-dissolved in copper, and an electro-optic property. The second element is less than copper and the first element; the first element is zinc, and the second element is calcium; and when the total of copper, zinc, and calcium is 100 at%, the content of the first element is 0.2. In the range of at or more than 5.0 at% or less, the content of the second element is in the range of 0.2 at% or more and 5.0 at% or less, and the remainder other than the first element and the second element contains copper.

According to the aspect of the invention described above, it is possible to provide a semiconductor device and a display device which can be formed by a low-temperature process using conductive wiring having high conductivity and which have a thin film transistor having stable characteristics.

1‧‧‧1st substrate

2‧‧‧2nd substrate

3‧‧‧Semiconductor device

4‧‧‧Liquid layer

8‧‧‧Transparent electrode

9‧‧‧ pixel electrodes

11‧‧‧1st conductive metal oxide layer

12‧‧‧2nd conductive metal oxide layer

13‧‧‧ copper alloy layer

14‧‧‧ pixel opening

15‧‧‧Power Receiving Department

16‧‧‧Power Control Department

17‧‧‧Touch Drive Control Department

18‧‧‧Touch drive switching circuit

19‧‧‧Touch detection switching circuit

20‧‧‧Touch Signal Transceiver Control Department

21‧‧‧1st conductive wiring

22‧‧‧2nd conductive wiring

23‧‧‧3rd conductive wiring

24‧‧‧4th conductive wiring

25A, 25B‧‧‧ conductor pattern

26‧‧‧Source signal switching circuit

27‧‧‧ gate signal switching circuit

28‧‧‧Power Power Transmission Department

29‧‧‧Signal transmission and reception department

30‧‧‧Semiconductor interface

31‧‧‧Source wiring

35, 135‧‧‧ channel layer

36, 136‧‧‧ source electrode

37, 137‧‧‧汲electrode

38, 138‧‧ ‧ gate electrode

39‧‧‧Thin film transistor

41‧‧‧1st insulation layer

42‧‧‧2nd insulation layer

43‧‧‧3rd insulation layer

45, 93‧‧‧ contact holes

50‧‧‧through holes

51‧‧‧1st overlap

52‧‧‧2nd overlap

55‧‧‧5th conductive wiring

56‧‧‧6th conductive wiring

60, 61‧‧‧1st connection pad

62, 63‧‧‧2nd connection pad

67‧‧‧Source wiring

69‧‧‧ gate wiring

71‧‧‧effective display area

72‧‧‧Border area

81‧‧‧1st antenna unit (antenna unit)

82‧‧‧2nd antenna unit (antenna unit)

83‧‧‧3rd antenna unit (antenna unit)

84‧‧‧4th antenna unit (antenna unit)

87‧‧‧Upper electrode

88‧‧‧lower electrode

89‧‧‧Switching transistor (thin film transistor)

91‧‧‧ hole injection layer (organic EL layer)

92‧‧‧Lighting layer (organic EL layer)

94‧‧‧ dam

96‧‧‧flattening layer

97‧‧‧Transparent resin layer

100‧‧‧ display device substrate

109‧‧‧ Sealing layer

110‧‧‧Display Department

116‧‧‧ center line

120‧‧‧Control Department

121‧‧‧Image Signal Control Department

122‧‧‧Touch Sensing Control Department

123‧‧‧System Control Department

130‧‧‧Detection, AD conversion department

139‧‧‧Drive transistor (thin film transistor)

140‧‧‧Power cord

141‧‧‧lower insulation

142‧‧‧Intermediate insulation

143‧‧‧Upper insulation

164, 165‧‧ ‧ loop antenna

200‧‧‧ Sputtering device

201‧‧‧vacuum chamber

202‧‧‧ Keeper

203‧‧‧vacuum pump

204‧‧‧Sputter gas supply department

205‧‧‧Power supply

206‧‧‧Backing board

207‧‧‧Splating target

208‧‧‧Substrate

300‧‧‧Array substrate

R‧‧‧Red Picture

G‧‧‧Green pixels

B‧‧‧Blue pixels

BM‧‧‧ Black Matrix

OB‧‧‧ Observer

OC‧‧‧ outer cover

DSP1, DSP2‧‧‧ display device

Fig. 1 is a cross-sectional view partially showing a display device including a semiconductor device according to a first embodiment of the present invention.

Fig. 2 is a plan view partially showing a display device including the semiconductor device according to the first embodiment of the present invention.

Fig. 3 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention.

Fig. 4 is a cross-sectional view showing a part of the conductive wiring constituting the components of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a schematic configuration diagram of a sputtering apparatus provided with a sputtering target used in the manufacture of the semiconductor device according to the first embodiment of the present invention.

6 is a block diagram showing a control unit (a video signal control unit, a system control unit, and a touch sensing control unit) and a display unit that constitute a display device including the semiconductor device according to the second embodiment of the present invention.

Fig. 7 is a cross-sectional view partially showing a display device including a semiconductor device according to a second embodiment of the present invention.

8 is a cross-sectional view showing an array substrate (first substrate) constituting a display device according to a second embodiment of the present invention, and is a view showing a light-emitting layer of a driving transistor and an organic EL formed on the array substrate.

FIG. 9 is a view showing a display device according to a second embodiment of the present invention, showing a first conductive wiring, a second conductive wiring, a first antenna unit, and a second antenna formed on a display device substrate (second substrate). A plan view of a circuit of a unit, a control unit, or the like.

10 is a view showing a third antenna unit, a fourth antenna unit, a source signal switching circuit, a gate signal switching circuit, and an organic driving unit formed on an array substrate (first substrate) constituting the display device according to the second embodiment of the present invention. A plan view of a circuit such as an EL driving transistor.

11 is a partial plan view showing an enlarged view of a first antenna unit formed on a display device substrate constituting a display device including a semiconductor device according to a second embodiment of the present invention.

Fig. 12 is a view showing a first antenna unit formed on a display device substrate constituting a display device including a semiconductor device according to a second embodiment of the present invention, and is a cross-sectional view taken along line A-A' shown in Fig. 11;

FIG. 13 is a perspective view showing the superposition of a first antenna unit formed on a display device substrate including a display device including the semiconductor device according to the second embodiment of the present invention, and a third antenna unit formed on the array substrate.

Form for implementing the invention

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

In the embodiment of the present invention, a semiconductor device using a thin film transistor using an oxide semiconductor as a channel layer, and a semiconductor device having a copper alloy wiring having a low resistance (specific resistance) and a low contact resistance are used. A display device of a semiconductor device will be described. Further, a novel sputtering target used for the manufacture of the above semiconductor device will be described.

In the following description, functions and components that are the same or substantially the same are denoted by the same reference numerals, and the description thereof will be omitted or simplified, or only necessary. In each of the drawings, in order to set each component as a size that can be recognized on the drawing, the size and ratio of each component are appropriately different from those of the actual one. Further, if necessary, elements that are difficult to be illustrated are omitted, for example, an insulating layer constituting a display device, a buffer layer, a plurality of layers of a channel layer forming a semiconductor, a number of thin film transistors, and a plurality of layers forming a conductive layer, An alignment film, a polarizing film, an optical film such as a retardation film, a cover glass for protection, a backlight, and the like are provided to the liquid crystal layer.

As a substrate which can be applied to the semiconductor device according to the embodiment of the present invention, a semiconductor substrate such as tantalum, niobium carbide or tantalum, a glass substrate such as an alkali-free glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or a polyimide can be used. Or a plastic substrate such as polyamide. On the substrate suitable for the semiconductor device, an insulating film such as hafnium oxide or hafnium oxynitride may be formed before the formation of the thin film transistor or the conductive metal oxide layer. In the case where the semiconductor device is applied to a reflective display device, a thin film of a silver alloy may be formed on the substrate. In the following description, the substrate may be referred to as a first substrate or a second substrate.

Ordinal numbers such as "1st" or "2nd" used in the first substrate or the second substrate, and the first conductive wiring, the second conductive wiring, and the third conductive wiring are attached to avoid confusion of constituent elements. Unlimited number. The first conductive wiring, the second conductive wiring, and the third conductive wiring may be simply referred to as conductive wirings in the following description.

The first conductive metal oxide layer and the second conductive metal oxide layer may be roughly referred to as a conductive metal oxide layer in the following description. The display device according to the embodiment of the present invention may have a touch sensing function using an electrostatic capacitance method. As will be described later, the conductive wiring such as the first conductive wiring or the third conductive wiring can be used as a detection wiring or a driving wiring for touch sensing. In the following description, the conductive wiring, the electrodes, and the signals related to the touch sensing may be simply referred to as touch wiring, touch driving wiring, touch detection wiring, touch electrodes, and touch driving signals. The voltage applied to the touch sensing wiring for driving the touch sensing is referred to as a touch driving voltage, and a voltage applied between the common electrode and the pixel electrode for driving the display function layer, that is, the liquid crystal layer is referred to as LCD drive voltage. The voltage that drives the organic EL layer is referred to as an organic EL driving voltage. The conductive wiring connected to the common electrode is sometimes referred to as a common wiring.

The "plan view" described below means a plane viewed by the observer (symbol OB described later) in the direction in which the display surface (plane of the display device substrate) of the display device is viewed. The display unit shape of the display device according to the embodiment of the present invention, or the shape of the pixel opening portion defining the pixel, and the number of pixels constituting the display device are not limited. In the embodiment described below in detail, the short side direction of the pixel opening portion is limited to the X direction, the longitudinal direction (longitudinal direction) is limited to the Y direction, and the thickness direction of the substrate is limited. The display device will be described in the Z direction. In the following embodiments, the display device may be configured by exchanging the X direction and the Y direction defined above.

 (First embodiment)    (Configuration of display device DSP1)  

Fig. 1 is a cross-sectional view showing a display device DSP1 including a semiconductor device according to a first embodiment of the present invention. Fig. 2 is a plan view partially showing a display device including the semiconductor device according to the first embodiment of the present invention.

The display device DSP1 includes a liquid crystal display device including a first substrate 1 and a second substrate 2 and a liquid crystal layer 4 sandwiched between the first substrate 1 and the second substrate 2.

The first insulating layer 41, the second insulating layer 42, and the third insulating layer 43 are laminated on the first substrate 1. As will be described later, a thin film transistor 39 (semiconductor device 3) is provided between the first insulating layer 41 and the second insulating layer 42. A pixel electrode 9 is formed on the third insulating layer 43, and the pixel electrode 9 is electrically connected to the thin film transistor 39 via a contact hole 45 (refer to FIG. 3) provided in the third insulating layer 43. The pixel electrode 9 is, for example, a transparent conductive film called ITO or the like. In the case of an organic EL device or a reflective display device, the pixel electrode 9 can be a light reflective reflective electrode such as a silver alloy or aluminum. The pixel electrode 9 is provided at a position corresponding to the pixel opening portion 14 to be described later. The pixel electrode 9 and the thin film transistor 39 are formed in a matrix shape in plan view (for example, see FIG. 10).

A plurality of pixel openings 14 are defined on the surface of the second substrate 2 facing the first substrate 1. Red pixel R, green pixel G, and blue pixel B are provided in each of the plurality of pixel openings 14.

Between the pixels adjacent to each other, that is, in the example shown in FIG. 1, between the red pixel R and the green pixel G, a black matrix BM is disposed between the blue pixel B and the red pixel R. Further, as shown in FIG. 2, the red pixel R, the green pixel G, and the blue pixel B are divided into a lattice shape by the black matrix BM to constitute a color filter. On the color filter, a transparent resin overcoat layer OC is laminated. On the overcoat layer OC, a transparent electrode 8 of ITO is formed.

The liquid crystal layer 4 is interposed between the first substrate 1 and the second substrate 2. By switching driving by the thin film transistor 39, a voltage is applied between the transparent electrode 8 and the pixel electrode 9, and the liquid crystal layer 4 is driven by applying a voltage thereto.

The display device DSP1 shown in FIG. 1 is driven by a longitudinal electric field (voltage applied between the pixel electrode 9 and the transparent electrode 8), but may be a lateral electric field type liquid crystal display device such as IPS or FFS.

 (semiconductor device)  

Fig. 3 is a cross-sectional view showing the semiconductor device 3 according to the first embodiment of the present invention.

The semiconductor device 3 includes a first substrate 1 , a conductive wiring provided on the first substrate 1 (on one surface of the substrate), and a thin film transistor 39 electrically connected to the conductive wiring. Specifically, in the semiconductor device 3, the first insulating layer 41 made of yttrium oxynitride is formed on the first substrate 1, and the gate electrode 38 (conductive wiring) is formed on the first insulating layer 41. Further, a second insulating layer 42 which is a gate insulating film is formed on the first insulating layer 41 so as to cover the gate electrode 38. A channel layer 35 belonging to the oxide semiconductor, a drain electrode 37 (conductive wiring), and a source electrode 36 (conductive wiring) are formed on the second insulating layer 42. Further, a third insulating layer 43 is formed on the second insulating layer 42 so as to cover the channel layer 35, the drain electrode 37, and the source electrode 36. The gate electrode 38, the second insulating layer 42, the channel layer 35, the drain electrode 37, and the source electrode 36 constitute a thin film transistor 39.

The source electrode 36 is electrically connected to the source wiring 31 (conductive wiring) extending in the vertical direction (Y direction) from the plane of FIG. 3 . The gate electrode 38 is electrically connected to a gate wiring (conductive wiring) located on the back side in the plane of FIG. The distance between the end of the drain electrode 37 facing each other and the end of the source electrode 36 is the channel length L. By setting the channel length L to be short, the rise in the switching operation by the thin film transistor 39 can be sharpened. The gate electrode 37 constituting the thin film transistor 39 is electrically connected to the pixel electrode 9 formed on the third insulating layer 43 via the contact hole 45.

Fig. 4 is a cross-sectional view showing a gate electrode 38 constituting the semiconductor device according to the first embodiment of the present invention.

In the first insulating layer 41, the gate electrode 38 has a three-layer structure in which the copper alloy layer 13 is sandwiched between the first conductive metal oxide layer 11 and the second conductive metal oxide layer 12. Although the wiring structure of the gate electrode 38 is shown in FIG. 4, the structure of the three-layered conductive wiring can also be applied to the gate wiring, the source wiring 31, the drain electrode 37, and the source electrode 36.

In addition, the conductive wiring including the first conductive metal oxide layer 11 and the copper alloy layer 13 and the second conductive metal oxide layer 12 is applied to the wiring or electrode constituting the thin film transistor 39. It is suitable for wiring formed on the first substrate 1 or on the second substrate 2. For example, the conductive wiring can be used for wiring that constitutes an electronic circuit (a driving circuit or the like) formed on the substrate, a wiring that extends from the electronic circuit toward the thin film transistor 39, a touch sensing wiring, an antenna wiring, a light shielding pattern, and the like. .

Since the conductive wiring can easily obtain an ohmic contact which is indispensable for mounting, it can be applied to a multilayer wiring using a through hole. The film thickness of the conductive metal oxide layer can be selected from, for example, a range of 10 nm to 100 nm. The film thickness of the copper alloy layer may be selected from, for example, a range of 50 nm to 500 nm. The film formation of the conductive metal oxide layer or the copper alloy layer 13 is preferably performed by vacuum deposition such as sputtering. In order to perform electrical mounting, plating may be performed on a portion of the copper alloy layer 13 of the terminal portion.

 (copper alloy layer)  

Hereinafter, the copper alloy layer will be specifically described.

The copper alloy layer 13 includes a first element which is solid-solubilized in copper and a second element which is less than the copper and the first element. The first element and the second element are elements in which the specific resistance increase rate when added to copper is 1 μΩcm/at% or less. The resistivity of the copper alloy layer 13 is in the range of 1.9 μΩcm to 6 μΩcm.

In the embodiment of the present invention, the element which is solid-dissolved with copper, for example, includes copper which is stably used in a temperature range suitable for use in an in-vehicle electronic device, that is, - (minus) 40 ° C to + (positive) 80 ° C. Substituted solid solution element.

In the range of the above-mentioned temperature range (the range of use of the electronic device) and the amount of the element added to the copper alloy, the element which can replace the position of the copper atom in the crystal structure of copper is judged as "the element which acquires the solid solution of the substitution type". Further, the amount of copper added to the element (may be plural) may be within a range of not more than 6 μΩcm in terms of the resistivity (synonymous with specific resistance) of the copper alloy. When the matrix base material is copper, the metal system having a wide solid solution region for copper can be exemplified by gold (Au), nickel (Ni), zinc (Zn), gallium (Ga), palladium (Pd), and manganese (Mn). ). Although aluminum (Al) is not wide, it has a solid solution region for copper.

As an element added to the copper alloy, an additive element (a copper alloy element) having a small specific resistance is palladium (Pd), magnesium (Mg), bismuth (Be), gold (Au), calcium (Ca), or cadmium. (Cd), zinc (Zn), silver (Ag). When these elements add 1 at% to pure copper, the increase in the resistivity is approximately 1 μΩcm or less. Since the increase in the electrical resistivity of calcium (Ca), cadmium (Cd), zinc (Zn), and silver (Ag) is 0.4 μΩcm/at% or less, it is preferable as an alloy element. When considering economic and environmental loads, it is preferred to use zinc and calcium as alloying elements. Zinc and calcium can be added to 5 at% as an alloying element for copper, respectively.

It is also possible to increase or decrease the amount of zinc and calcium added by increasing the amount of calcium added or reducing the amount of zinc added depending on the range of the above-mentioned addition amount. Regarding the effect by the addition of zinc and calcium to copper, a remarkable effect can be obtained under the addition amount of 0.2 at% or more.

The resistivity of the copper alloy in which 0.4 at% of zinc and calcium were added to pure copper was about 1.9 μΩcm. Therefore, the lower limit of the resistivity of the copper alloy layer 13 of the embodiment of the present invention is 1.9 μΩcm. Further, in the case where calcium (Ca), cadmium (Cd), zinc (Zn), and silver (Ag) are used as the alloying elements, when the amount of addition is more than 5 at% with respect to the total number of elements of copper and alloying elements, copper The electrical resistivity of the alloy will increase significantly. Therefore, the amount added is preferably at least less than 5 at%.

Calcium has a property that it is difficult to dissolve in copper. The resistivity of the present invention means a value in which the composition of the copper alloy layer 13 is sandwiched by a conductive metal oxide. As will be described later, the copper alloy layer 13 which is not sandwiched by the conductive metal oxide is likely to deteriorate in electrical resistivity due to heat treatment or the like. For example, when two layers of titanium and pure copper are laminated on a substrate such as glass (the outermost surface is pure copper), the initial copper wiring has a resistivity of about 2 μΩcm, and then, when heat treatment is performed at 400 ° C to 500 ° C, There is a case where the resistivity is deteriorated to the extent of 4 μΩcm to 5 μΩcm. Thus, it is considered that the reason why the resistivity is deteriorated is that copper and titanium are mutually diffused and copper is oxidized by heat treatment at a high temperature.

The negative electrical system is the relative measure of the strength at which atoms (elements) attract electrons. The smaller the value, the easier it becomes to become a cation. The cathode of copper is 1.9. The anion of oxygen is 3.5. Examples of the element having a small anion property include an alkaline earth element, a titanium group element, and a chromium group element. The alkalinity of the alkali element is also small, but when there is an alkali element or moisture in the vicinity of copper, the diffusion of copper increases. Therefore, an alkali element such as sodium or potassium cannot be used as an alloying element of copper.

The anion of calcium is a small value of 1.0. When calcium is used as an alloying element of copper, calcium is oxidized earlier than copper to form calcium oxide during heat treatment, and the diffusion of copper can be suppressed. In the conductive wiring according to the embodiment of the present invention, calcium oxide can be selectively formed at the interface between the exposed surface of the copper alloy layer not covered by the conductive metal oxide layer, the copper alloy layer, and the conductive metal oxide layer. . In particular, the formation of calcium oxide on the exposed surface of the copper alloy layer not covered by the conductive metal oxide layer contributes to suppression of copper diffusion and improvement in reliability. The electrical conductivity of the conductive wiring or the copper alloy layer according to the embodiment of the present invention is improved by annealing such as heat treatment. The above-mentioned negative electrical properties are expressed by the value of Pauling's negative electrical properties. In the conductive wiring according to the embodiment of the present invention, it is preferable that the second element is oxidized to form an oxide before the copper element and the first element by a heat treatment step of the conductive wiring or the like. Further, it is preferable to prevent hydrogen or oxygen from being mixed into copper or a copper alloy.

Further, in the embodiment of the present invention, the "first element" may have a lower electrical property than copper. The "second element" may also have a solid solution region for copper. In the case of using two or more elements having two properties of less than copper and having a solid solution region for copper, an element having a small anion property among two or more elements is referred to as a "second element".

For example, the first element is zinc and the second element is calcium.

Specifically, when the total of copper, zinc, and calcium is 100 at%, the copper alloy layer 13 contains the first element in a range of 0.2 at% or more and 5.0 at% or less, and the composition of the copper alloy layer 13 is The second element is contained in a range of 0.2 at% or more and 5.0 at% or less, and the remainder contains copper.

In the present embodiment, for example, the copper alloy layer 13 is a copper alloy in which calcium is 2 at%, zinc is 0.5 at%, and the balance is copper and unavoidable impurities. The resistivity of the copper alloy layer 13 having such a composition condition is 2.7 μΩcm.

The resistivity of the copper alloy layer 13 may vary by about ±30% due to the film formation method or annealing condition of the copper alloy layer 13. For example, in a configuration in which a copper alloy layer is directly formed on a glass substrate or the like, the copper alloy layer is oxidized (formation of CuO or copper oxide) due to heat treatment at the time of film formation or heat treatment after film formation, and the resistance value is deteriorated. The situation. Further, in the case where the alloying element constituting the copper alloy layer is a copper alloy which is added at a low concentration, that is, a diluted alloy, copper oxide is formed, and crystal grains of the copper alloy become too large. Therefore, a coarse grain boundary (crystal grain boundary) having a gap is formed, and the surface of the copper alloy layer becomes thick, and the resistance value is deteriorated.

In the embodiment of the present invention, the copper alloy layer 13 is sandwiched between the first conductive metal oxide layer 11 and the second conductive metal oxide layer 12. In this constitution, there are many cases in which the resistivity is improved by heat treatment (annealing). In other words, in the embodiment of the present invention, the copper alloy layer 13 is covered with the conductive metal oxide layer, whereby the surface oxidation of the copper alloy layer 13 can be suppressed. Further, by the restriction (anchoring) generated by the conductive metal oxide layer formed on the front surface and the back surface of the copper alloy layer 13, the copper alloy layer is not extremely coarsened, and the copper alloy layer is not coarsened. The surface of 13 will not become thicker. Even if the alloying element constituting the copper alloy layer 13 is a copper alloy layer 13 which is added at a low concentration (for example, about 0.2 at%), crystal grains (grain) are hard to be enlarged, and the grain boundary can be suppressed. Carrier scattering (deterioration of resistivity). The dense copper alloy layer 13 can be obtained by adding the first element and the second element to the copper alloy under the condition of being 0.4 at% or more.

The effect of suppressing the deterioration of the resistivity is particularly the case where the specific resistance increase rate of the alloy element added to copper is 1 μΩcm/at% or less, and the copper alloy layer 13 is the first conductive metal oxide layer. When the structure of the 11 and the second conductive metal oxide layer 12 is sandwiched, it is easy to obtain a remarkable effect.

By the heat treatment, the interface between the copper alloy layer 13 and the first conductive metal oxide layer 11 and the interface between the copper alloy layer 13 and the second conductive metal oxide layer 12 are again in the absence of the conductive metal oxide. The exposed surface (side surface) of the copper alloy layer 13 covered by the layer forms calcium oxide. Since the calcium oxide is formed on the surface of the copper alloy layer 13 or the interface with the oxide layer, the diffusion of copper can be suppressed, contributing to an improvement in reliability.

Further, in the copper alloy layer 13 of the embodiment of the present invention, it is not necessary to intentionally contain oxygen (O). The oxygen-containing copper alloy layer, for example, may cause voids in the copper alloy layer due to the presence of water or alkali, which may reduce the reliability of the copper alloy layer.

Then, the three layers of the first conductive metal oxide layer 11 and the copper alloy layer 13 and the second conductive metal oxide layer 12 are continuously formed, for example, at a substrate temperature of 180 ° C or lower. The substrate temperature can also be set at room temperature (25 ° C), and further set to a temperature below room temperature. Further, in the subsequent step after the pattern of the channel layer is formed, for example, a low temperature annealing of 180 ° C to 340 ° C is applied. This low-temperature annealing can also be performed before the step of forming the conductive wiring such as the source wiring or the drain electrode. The electrical properties including the resistivity can be improved by low temperature annealing.

The semiconductor device according to the embodiment of the present invention can be formed by a low temperature process of 340 ° C or lower as described above. In addition, in the organic EL (electroluminescence) display device or the liquid crystal display device using a resin substrate or a glass having a thickness of 0.4 mm or less as a substrate material, the semiconductor device of the present embodiment is applied, which is particularly effective.

As the copper alloy used for the copper alloy layer 13, the above materials can be used. In the copper alloy according to the first embodiment, the content of zinc is 0.5 at%, the content of calcium is 2.0 at%, and the balance is copper and unavoidable impurities. The film thickness of the copper alloy is not specified. In the first embodiment, the thickness of the copper alloy layer 13 is 280 nm. The resistivity of the copper alloy layer 13 was 2.7 μΩcm after annealing (heat treatment) to be described later.

Further, in the present embodiment, the copper alloy layer 13 sandwiched between the first conductive metal oxide layer 11 and the second conductive metal oxide layer 12 can be suppressed to be extremely small in the range of about 1.9 μΩcm to 6 μΩcm. Resistance coefficient.

 (conductive metal oxide layer)  

The conductive metal oxide layer contains indium oxide as a main conductive metal oxide, and contains one or more kinds of conductive metal oxides selected from the group consisting of cerium oxide, zinc oxide, and gallium oxide. The amount of indium (In) contained in the conductive metal oxide layer must be more than 80 at%. The amount of indium (In) is preferably more than 80 at%. The amount of indium (In) is more preferably more than 90 at%. When the amount of indium (In) is less than 80 at%, the specific resistance of the formed conductive metal oxide layer becomes large, which is less preferable. When the amount of zinc (Zn) exceeds 20 at%, the alkali resistance of the conductive metal oxide (mixed oxide) is lowered, which is less desirable. In the above-mentioned conductive metal oxide layer, the atomic percentage of the element in the mixed oxide is used (the oxygen element is not counted and only the element is counted). Oxide is less likely to form a solid solution region of the metal ruthenium and copper, and suppresses the diffusion of copper in the buildup structure, so that it can be added to the above-mentioned conductive metal oxide layer. In the mixed oxide, other elements such as titanium, zirconium, magnesium, aluminum, and antimony may be added in a small amount.

In general, the copper layer or the copper alloy layer has low adhesion to a transparent resin or a glass substrate (suitable for the first substrate and the second substrate). Therefore, when the copper layer or the copper alloy layer is applied as it is to a display device or a semiconductor device as it is, it is difficult to realize a practical display device or semiconductor device. However, the above-mentioned composite oxide sufficiently has adhesion to a black matrix, a transparent resin, a glass substrate, or the like, and is also sufficient for adhesion to a copper layer or a copper alloy layer. Therefore, when a copper layer or a copper alloy layer using the above composite oxide is applied to a display device or a semiconductor device, a practical display device or semiconductor device can be realized.

Copper, copper alloy, silver, silver alloy, or oxides and nitrides thereof generally do not have sufficient adhesion to a transparent substrate such as glass or resin or a black matrix. Therefore, when the conductive metal oxide layer is not provided, peeling may occur at the interface between the conductive wiring and the transparent substrate such as glass, or at the interface between the conductive wiring and the black matrix or the insulating layer formed of SiO ₂ or the like. In the case where copper or a copper alloy is used as the conductive wiring having a fine wiring pattern, in the display device substrate in which the conductive metal oxide layer is not formed as the underlying layer of the conductive wiring, in addition to the defect due to the peeling, There is a problem that electrostatic breakdown occurs in the conductive wiring in the middle of the manufacturing process of the display device substrate, and it is not practical. Such electrostatic breakdown is a step of laminating a color filter on a substrate, a step of bonding a display device substrate (for example, corresponding to the second substrate 2), and an array substrate (for example, corresponding to the first substrate 1). In the relationship of the cleaning step or the like, static electricity is stored in the wiring pattern, and a phenomenon such as lack of pattern or disconnection due to the relationship of electrostatic breakdown occurs.

Further, on the surface of the copper layer or the copper alloy layer, copper oxide having no conductivity is formed thereon over time, and it becomes difficult to make electrical contact. On the other hand, a composite oxide layer such as indium oxide, zinc oxide, antimony oxide, gallium oxide or tin oxide can achieve stable ohmic contact, and in the case of using such a composite oxide, it can be easily transferred via conduction ( Transfer) or contact holes for electrical installation. In the description of the embodiment, the "contact hole" is synonymous with the "through hole".

In the present embodiment, in the thin film transistor using the copper wiring, as described above, the copper oxide having no conductivity on the surface of the copper layer or the copper alloy layer is formed over time, and is easily connected in the contact hole. The resistance produces a deviation. The variation in the connection resistance directly becomes a deviation of the threshold voltage (Vth) in the characteristics of the thin film transistor 39, which hinders the driving of the organic EL layer or the liquid crystal layer. In the embodiment of the present invention, a conductive metal oxide layer is formed between the conductive wiring and the surface electrically connected to the conductive wiring. Thereby, ohmic contact can be performed. With this configuration, a thin film transistor having a small variation in the threshold voltage (Vth) can be provided.

As the material constituting the conductive metal oxide used for the first conductive metal oxide layer 11 and the second conductive metal oxide layer 12, the above materials can be used. In the first embodiment, indium oxide, zinc oxide, and tin oxide are used in an amount of not counting oxygen (when the total amount of elements not counting oxygen is 100 at%), and the amount of indium (In) is 90 at%. Zinc (Zn) is 8 at% and tin (Sn) is 2 at%. The film thicknesses of the first conductive metal oxide layer 11 and the second conductive metal oxide layer 12 are not defined. In the first embodiment, the thickness of the first conductive metal oxide layer 11 is 30 nm, and the thickness of the second conductive metal oxide layer 12 is 50 nm.

 (sputtering device)  

FIG. 5 is a schematic configuration diagram of a sputtering apparatus provided with a sputtering target used for manufacturing the semiconductor device according to the first embodiment of the present invention.

As shown in FIG. 5, the sputtering apparatus 200 includes a vacuum chamber 201, a holder 202, a vacuum pump 203, a sputtering gas supply unit 204, a power source 205, a backing plate 206, and a sputtering target 207. The substrate 208 (the first substrate 1 and the second substrate 2) to be film-formed is placed on the holder 202. A sputtering target 207 is bonded to the backing plate 206, and in the vacuum chamber 201, the sputtering target 207 is disposed to face the holder 202 (substrate 208).

As the vacuum chamber 201, the holder 202, the vacuum pump 203, the sputtering gas supply unit 204, and the power source 205, a well-known configuration or material is used.

In the sputtering apparatus 200, sputtering is performed in a state where the substrate 208 is placed on the holder 202. Specifically, the vacuum chamber 201 is depressurized to maintain the pressure of the vacuum chamber 201 at a predetermined pressure so as to be in a vacuum state required for sputtering by driving the vacuum pump 203. In this state, the sputtering gas supply unit 204 supplies a sputtering gas such as argon to the vacuum chamber 201, and the power source 205 supplies a voltage to the sputtering target 207, whereby the sputtering target 207 is sputtered to form a sputtering. The metal of the target 207 is scattered from the sputter target 207 and deposited on the substrate 208.

Next, a case where a copper alloy sputtering target is used as the sputtering target 207 will be described.

The copper alloy sputtering target is used for the formation of the copper alloy layer 13, and includes a first element which is solid-solubilized in copper and a second element which is smaller than the copper and the first element, and the first element is zinc. 2 elements are calcium. Here, when the total of copper, zinc, and calcium is 100 at%, the content of the first element is in the range of 0.2 at% or more and 5.0 at% or less, and the content of the second element is 0.2 at% or more and 5.0 at%. In the following range, the remaining portion of the first element and the second element is removed to contain copper.

 (copper alloy sputtering target)  

The method for producing the copper alloy sputtering target is not particularly limited.

In the following description, "copper alloy" means a copper alloy of a sputtering target, and "copper alloy film" or "copper alloy layer" means copper which is vacuum-formed on the substrate 208 by using the sputtering apparatus 200 described above. Alloy film. "Copper" means copper having a purity of 99.99% or more and an unavoidable impurity of less than 0.01%.

In the method for producing a copper alloy sputtering target, for example, oxygen-free copper (purity: 99.99% by mass), zinc (purity: 99.99% by mass), and calcium (purity: 99.9% by mass) are used as a raw material of the sputtering target 207. . The amount of oxygen-free copper, zinc and calcium is adjusted to the above content. The raw material adjusted as described above was dissolved in a high-purity graphite crucible at a high frequency, and then cast into a cooled carbon mold. The ingot obtained by such casting is subjected to hot rolling as needed, for example, by grinding to a thickness of about 5 mm.

Next, a low melting point metal such as metal indium can be used as the bonding metal, and the ingot can be bonded to the copper backing plate 206 to obtain the sputtering target 207.

The average grain size of the crystal grains (crystal grains) of the copper alloy observed on the surface of the sputtering target 207 is preferably from 10 μm to 80 μm. When a sputtering target having an average grain size of the crystal grains of more than 80 μm is used, abnormal discharge is likely to occur during sputtering in vacuum film formation, which tends to cause product defects. The average grain size of the crystal grains may be 10 μm or less. However, in this case, it is necessary to rapidly cool the ingot which is melted in the production of the sputtering target 207 or to increase the amount of zinc added. Since increasing the amount of zinc added causes an increase in the electrical resistivity of the copper alloy film, it is less desirable. Rapid cooling tends to strain the sputter target.

Therefore, it is preferable to exclude oxygen in a gas atmosphere in which the raw material of the sputtering target 207 (oxygen-free copper, zinc, and calcium) is dissolved, and in a gas atmosphere in which the molten raw material is cast into a carbon mold.

When the total amount of copper, zinc, and calcium is 100 at%, when the calcium content exceeds 5 at%, the castability of the sputtering target 207 is deteriorated, so that the content of calcium is preferably 5 at% or less. On the other hand, when calcium is less than 0.2 at%, the protective effect between the first conductive metal oxide layer 11 and the second conductive metal oxide layer 12 and exposed on the surface of the copper alloy layer 13 at the end thereof Will decrease. In this case, the conductive wiring formed by the three-layer structure in which the copper alloy layer 13 is sandwiched between the first conductive metal oxide layer 11 and the second conductive metal oxide layer 12 cannot be reliable. Fully secured.

When the total of copper, zinc, and calcium is 100 at%, when the amount of zinc exceeds 5 at%, the electrical conductivity of the copper alloy layer 13 is lowered, so that it is preferably 5 at% or less. On the other hand, when the zinc is less than 0.2 at%, the copper alloy layer 13 is sandwiched between the first conductive metal oxide layer 11 and the second conductive metal oxide layer 12, and the diffusion of copper cannot be suppressed. Sexual assurance is not sufficient.

In the sputtering apparatus 200 shown in FIG. 5, a sputtering target 207 is disposed in one vacuum chamber 201. On the other hand, a configuration in which a plurality of sputtering targets of different types are disposed in one vacuum chamber 201 may be employed. Further, a plurality of vacuum chambers may be connected via a gate valve, and the types of the films formed on the substrate in each of the plurality of vacuum chambers may be different. That is, in this case, a plurality of films of different kinds can be continuously formed on the substrate while maintaining a vacuum state.

By using a sputtering apparatus having such a device, the first conductive metal oxide layer, the copper alloy layer, and the second conductive metal oxide layer can be continuously formed on the substrate while maintaining a vacuum state. . In such a sputtering film formation, a copper alloy sputtering target having the above composition and a conductive metal oxide target having the above composition are used. The three-layer film of the first conductive metal oxide layer, the copper alloy layer, and the second conductive metal oxide layer formed in this manner can be patterned once by a well-known photolithography method using an acidic etchant. And a conductive wiring is formed.

 (channel layer)  

Next, returning to Fig. 3, a channel layer constituting the thin film transistor 39 of the semiconductor device will be described.

In the first embodiment, the oxide semiconductor composite oxide constituting the channel layer 35 contains indium oxide and cerium oxide, and has a smaller amount than each of indium oxide and cerium oxide. Amount of cerium oxide. In the oxide semiconductor, when the total of the elements of the uncounted oxygen is 100 at%, the amount of each of indium and antimony is 40 at% or more.

Specifically, in the present embodiment, when the total of the elements of the uncounted oxygen in the oxide semiconductor is 100 at%, the amount of each of indium and antimony is about 48 at%, and the amount of antimony is about 4 at. %.

Further, cerium oxide or lanthanum oxide is different from gallium oxide or indium oxide, and since it can be obtained inexpensively, it has high industrial value.

In order to adjust the electrical characteristics or mobility of the oxide semiconductor, it is also possible to change the indium oxide concentration or the concentration of cerium oxide in the thickness direction of the channel layer 35, for example. Alternatively, the channel layer 35 may be formed using a plurality of layers having different concentrations of cerium oxide. Alternatively, in order to increase the wet etching processability of the source electrode or the like, the acid resistance of the channel layer 35 can be improved by enriching the composition of the surface layer of the channel layer 35 with cerium oxide. Although the etching stopper layer may be laminated on the channel layer 35, the composite oxide film containing cerium oxide becomes a film having high acid resistance after annealing at 180 ° C or higher, so that active insertion of the etching stopper layer is not required. This acid resistance can also be obtained by increasing the concentration of cerium oxide in the composite oxide film.

In the semiconductor device shown in FIG. 3, the channel layer of the oxide semiconductor is stabilized in the heat treatment at 260 ° C for 1 hour, and the first conductive metal oxide layer 11 and the copper alloy layer 13 and the second layer are provided. The conductive wiring composed of three layers of the conductive metal oxide layer 12 has a low resistance.

Further, in the contact hole 45 shown in FIG. 3, the pixel electrode 9 which is an ITO is formed in contact with the gate electrode 37 (conductive wiring) which is the upper layer of the second conductive metal oxide layer 12. The ITO and the second conductive metal oxide layer forming the pixel electrode 9 are made of a similar conductive metal oxide, and can be ohmically contacted. In the configuration shown in FIG. 3, when the surface in contact with the pixel electrode 9 in the contact hole 45 is an oxidized copper surface or aluminum, it is difficult to perform ohmic contact. The physical adhesion between ITO and aluminum is also insufficient. The novel configuration employed in the semiconductor device of the embodiment of the present invention can provide a wiring structure in which ohmic contact is performed in this manner.

In the configuration of the thin film transistor 39 shown in FIG. 3, the semiconductor interface 30 in which the channel layer 35 is in contact with the source electrode 36 and the semiconductor interface 30 in which the channel layer 35 is in contact with the drain electrode 37 are formed. In particular, in such a semiconductor interface 30, a conductive metal oxide having a low contact resistance and a high mobility is formed substantially on the electrode side (the source electrode side and the drain electrode side) of the channel layer 35. As a result, the transistor characteristics can be improved. In FIG. 3, the first conductive metal oxide layer 11 functions as a semiconductor layer having low resistance and high mobility. In the second embodiment to be described later, the second conductive metal oxide layer 12 functions as a semiconductor layer having low resistance and high mobility.

 (oxide semiconductor)  

The oxide semiconductor is a composite oxide containing indium oxide and cerium oxide as a main material. The oxide semiconductor may be formed only by the composition of indium oxide and antimony oxide. However, in an oxide semiconductor having such a composition, oxygen deficiency is likely to occur. In order to reduce oxygen deficiency of the oxide semiconductor, zirconia, yttria, yttria, yttria, yttria, yttria, yttria, yttria, and gallium oxide are further added to the oxide semiconductor as a stabilizer in an oxidized state. Preferably. Cerium oxide is particularly preferred for the reasons described below.

An example of the oxide semiconductor according to the embodiment of the present invention is a case where cerium oxide is used as the oxidation stabilizer.

The oxide semiconductor according to the embodiment of the present invention contains indium oxide and cerium oxide as a main material, and contains cerium oxide as an oxidation stabilizer. When the total of the elements of the uncounted oxygen in the oxide semiconductor is 100 at%, for example, the content of each of indium and antimony is in the range of 45 at% or more and 49.8 at% or less, and the content of cerium is 10 at% or less. Within the range of 0.4at% or more.

In the embodiment of the present invention, the term "main material" means indium oxide and antimony oxide, and when the total of the elements of the oxide semiconductor in which oxygen is not counted is 100 at%, the content of indium and antimony is 40 at% or more. Composite oxide.

On the other hand, for example, when gallium is used as the oxidation stabilizer, when the content of gallium is less than 0.4 at%, the oxygen deficiency of the oxide semiconductor cannot be sufficiently compensated. Moreover, when the content exceeds 10 at%, the conductivity of the composite oxide target as a raw material becomes low, and it is difficult to form a film by DC (direct current) sputtering.

The oxide semiconductor according to the embodiment of the present invention can be crystallized under low-temperature annealing at 180 ° C to 340 ° C which improves the electrical resistivity of the copper alloy layer described above. In other words, in the embodiment of the present invention, a composite oxide having a low crystallization temperature can be provided. In order to confirm the presence or absence of crystallization of the oxide semiconductor, it is only necessary to observe crystal grains of at least 3 nm by observation by TEM or the like after low-temperature annealing. However, since the thickness of the channel layer used for the thin film transistor is selected from the range of 3 nm to 80 nm which is extremely thin, it is difficult to confirm the crystallization. In the oxide semiconductor according to the embodiment of the present invention in which indium oxide and antimony oxide are used as the main material, it is not possible to confirm the crystallization after the low-temperature annealing, and it is also possible to provide a practical and stable semiconductor film by low-temperature annealing. Transistor. An etch stop layer may also be formed on the surface of the channel layer corresponding to the channel length L shown in FIG. Low temperature annealing is preferably carried out in an atmosphere or an oxygen-containing gas atmosphere.

In general, an oxide semiconductor called indium oxide, gallium oxide or zinc oxide of IGZO is required to be subjected to high-temperature annealing at 400 ° C to 700 ° C in order to carry out crystallization.

However, annealing exceeding 350 ° C has a tendency to increase the diffusion of copper and deteriorate the characteristics of the oxide semiconductor depending on the situation. In a conventional configuration in which the copper wiring is Mo/Cu or Ti/Cu, in the heat treatment exceeding 400 ° C, mutual diffusion of copper and titanium may occur, and the electrical resistance of the copper wiring may be deteriorated. The melting point of indium oxide is set to 1910 ° C, the melting point of gallium oxide is set to 1740 ° C, and the melting point of zinc oxide is set to 1980 ° C. In either case, the melting point is in a high temperature region of 1700 ° C or higher. Therefore, it can be inferred that the crystallization temperature of the composite oxide is also high. The melting point of cerium oxide is 656 ° C compared to such a high melting point oxide. The crystallization temperature of the inorganic oxide is empirically set to 1/2 or 2/3 of the melting point of its oxide. However, the crystallization temperature of the ITO film (a transparent conductive film formed of a composite oxide of indium oxide and tin oxide) or an indium oxide film containing about 10 Wt% of tin oxide is about 200 °C. Therefore, by forming a composite oxide (oxide semiconductor) containing cerium oxide and indium oxide having a low melting point at the same time, the crystallization temperature of the composite oxide can be lowered. Further, regarding the melting point of the above oxide, the description of the rock wave chemistry dictionary fourth edition (Iwanami Shoten) is used.

In the composition of the oxide semiconductor according to the embodiment of the present invention, indium oxide and cerium oxide can be set to a ratio of about 1:1. The ratio of indium oxide to antimony oxide may also vary by 20%, but as an oxide semiconductor, it is preferably a ratio close to 1:1. The lanthanum oxide is easily sublimed by vacuum film formation (sputtering) using a composite oxide target containing cerium oxide. Therefore, in the composition of the composite oxide target belonging to the original material, the ratio of indium oxide to ruthenium oxide can be made close to 1:1 by forming a film containing the ruthenium oxide as the composite film of the vacuum film formation.

It is also possible to form an oxide semiconductor only by the composition of indium oxide and yttrium oxide, but oxygen deficiency is likely to occur in an oxide semiconductor having such a composition. In order to reduce the oxygen deficiency of the oxide semiconductor, it is preferred to add cerium oxide as a stabilizer in an oxidized state. The oxide semiconductor according to the embodiment of the present invention contains indium oxide and cerium oxide as a main material, and contains cerium oxide as an oxidation stabilizer. When the total of the elements of the uncounted oxygen is 100 at% in the oxide semiconductor, the content of each of indium and antimony is in the range of 45 at% or more and 49.8 at% or less, and the content of cerium is 10 at% or less. Within the range of 0.4at% or more. In the case where the content of cerium is less than 0.4 at%, the oxygen deficiency cannot be sufficiently compensated. When the content of cerium exceeds 10 at%, it is difficult to crystallize at an annealing temperature of 340 ° C or lower. Alternatively, the conductivity of the composite oxide target having a niobium content of more than 10 at% is greatly lowered, and it is difficult to perform DC sputtering.

In the composite oxide target used for forming the channel layer composed of the above oxide semiconductor, tin oxide having a valence different from that of indium oxide and ruthenium oxide may be further added as a carrier dopant (carrier dopant) ), and use a highly conductive sputtering target.

Regarding cerium (Ce), it is a feature that facilitates the conversion between the 4f1-Ce(III) oxidation state and the 4f0-Ce(IV) oxidation state, and the cerium oxide (CeO ₂ ) system is used as a treatment for automotive exhaust gas. Media use. In other words, the difference in the oxidation-reduction potential of Ce ⁴⁺ and Ce ³⁺ of CeO ₂ is small, and the redox reaction is easily reversible. For example, it is easy to pick up oxygen in an oxidizing gas environment, and it is easy to release oxygen in a reducing gas atmosphere. This mutual conversion mode is, for example, CeO ₂ <=>CeO _2-x + "Ox"

To present. "Ox" can also be referred to as a superoxide oxidizing superoxide.

Also, in terms of behavior in the composite oxide, it is expected that CeO ₂ can capture an excessive amount of electrons (carriers). Therefore, it is easy to prevent an excessive concentration of electrons of the oxide semiconductor film. In the embodiment described later, an n-type semiconductor having an electron concentration of 9 × 10 ¹⁷ cm ^-3 or less can be obtained.

An oxide semiconductor-based indium oxide and a composite oxide of cerium oxide and cerium oxide according to an embodiment of the present invention. For example, when a sputtering vacuum film forming using a target composed of such a composite oxide is performed, by introducing a certain amount of oxygen into an argon base gas, oxidation with less oxygen deficiency can be obtained. Semiconductor film. For example, by performing annealing in the range of 180 ° C to 340 ° C in the atmosphere, oxygen deficiency can be further reduced, and an oxide semiconductor film having high acid resistance can be obtained. In the vacuum film formation, annealing may be performed after the substrate temperature is set to room temperature (for example, 25 ° C), and a pattern of the oxide semiconductor film serving as the channel layer is formed.

The above oxide semiconductor can be formed as the channel layer 35 of the thin film transistor as described above. In order to exhibit the function of the insulating layer which functions as the gate insulating film (the second insulating layer 42) in contact with the channel layer 35, a mixed bismuth citrate (HfSiOx), cerium oxide, aluminum oxide, or nitriding may be used. An insulating layer obtained by cerium, cerium oxynitride, aluminum oxynitride, titanium oxide, zirconium oxide, gallium oxide, zinc oxide, cerium oxide, cerium oxide, cerium oxide, cerium oxide, or the like.

The lanthanum oxide system has a high dielectric constant and is strongly bonded to the oxygen atom. Therefore, it is preferable to use a composite oxide containing cerium oxide as the gate insulating layer. In the case where cerium oxide is used as one of the oxides constituting the composite oxide, it is easy to maintain a high dielectric constant even in an amorphous state. Cerium oxide has an oxidizing power. The lanthanum oxide system can store and release oxygen. Therefore, by using a structure in which an oxide semiconductor (channel layer) and a yttrium oxide (gate insulating film) are in contact with each other, oxygen can be supplied from the yttrium oxide to the oxide semiconductor, oxygen deficiency of the oxide semiconductor can be avoided, and stable oxidation can be realized. Semiconductor (channel layer). In the configuration in which a nitride such as SiN is used for the gate insulating layer, it is difficult to find the above-described effects. Further, the material of the gate insulating layer (second insulating layer 42) may contain a lanthanide metal silicate represented by cerium oxide (CeSiOx). Alternatively, it may contain a cerium composite oxide, a ceric acid salt, and a cerium oxynitride or a cerium oxide.

As the structure of the gate insulating layer, a single layer film, a mixed film or a multilayer film can also be used. When a mixed film or a multilayer film is used, a mixed film or a multilayer film can be formed by selecting a material from the above insulating layer material. The film thickness of the gate insulating layer is, for example, a film thickness which can be selected from the range of 2 nm or more and 300 nm or less. In the case where the channel layer is formed of an oxide semiconductor, the interface of the gate insulating film in contact with the channel layer 35 can be formed in a state containing a large amount of oxygen (film forming gas atmosphere), and the oxide semiconductor layer can be reduced (channel) Layer 35) is deficient in oxygen.

In order to obtain an effect of flattening the upper surface of the insulating layer (third insulating layer 43) covering the thin film transistor 39, an acrylic resin, a polyimide resin, a benzocyclobutene resin, a polyamide resin, and a polyfluorene may be used. An imide resin or the like is used as a part of the insulating layer. Low dielectric constant materials (low-k materials) can also be used.

 (composite oxide sputtering target)  

The composite oxide sputtering target is used by, for example, bonding to the backing plate 206 in the apparatus configuration of the sputtering apparatus 200 shown in FIG. In the sputtering target 207 shown in FIG. 5, a composite oxide can be formed on the substrate 208 by using a composite oxide sputtering target for film formation of an oxide semiconductor (first substrate 1, first) 2 substrate 2).

Hereinafter, a composite oxide sputtering target will be described.

Further, the description of the method for producing a sputtering target below can also be applied to a composite oxide sputtering target used for the first conductive metal oxide layer 11 and the second conductive metal oxide layer 12.

The composite oxide sputtering target according to the embodiment of the present invention contains indium oxide (In ₂ O ₃ ) and bismuth oxide (Sb ₂ O ₃ ) as a main material, and contains cerium oxide (CeO ₂ ) as a composite oxide which is hard to be produced. An oxygen stabilizer that is deficient in oxygen. Here, the "main material" means that each of indium oxide and antimony oxide is contained in a larger proportion than cerium oxide.

In the composite oxide sputtering target used for forming the oxide semiconductor of the present invention, when the total of the elements of the oxide semiconductor in which the oxygen is not counted is 100 at%, for example, the content of each of indium and antimony The content is in the range of 45 at% or more and 49.8 at% or less, and the cerium content is in the range of 10 at% or less and 0.4 at% or more.

When the composite oxide sputtering target contains indium and antimony as main materials and the total amount of elements which do not count oxygen is 100 at%, the content of each of indium and antimony is at least 40 at% or more. An oxide such as tin oxide (SnO ₂ ) or titanium oxide (TiO ₂ ) may be added to the composite oxide sputtering target as a carrier dopant. The conductivity of the sputtering target can be adjusted by adding, for example, 0.2 at% or more and 5 at% or less of tin oxide or titanium oxide.

In the method for producing a composite oxide sputtering target according to an embodiment of the present invention, a powder of indium oxide (purity: 99.99%), a powder of cerium oxide (purity of 99.9%), and a powder of cerium oxide (purity of 99.9%) can be used. The mixture is mixed and molded, and is produced by sintering. The present invention does not limit such a manufacturing method. The sintering system can be carried out, for example, in a normal pressure or oxygen-containing gas atmosphere at a temperature ranging from 800 ° C to 1600 ° C. Since cerium oxide is evaded at a high temperature exceeding 1600 ° C, it is preferably 1600 ° C or lower. When the temperature is less than 800 ° C, there is a case where the target cannot obtain a sufficient density.

The powder (a powder of indium oxide, a powder of cerium oxide, and a powder of cerium oxide) is dispersed into a slurry by a wet method together with pure water, granulated, molded, and rapidly dried. Then, pressurization (for example, cold equalization) is performed. Further, thereafter, it is sintered at the above-described sintering temperature for several tens of hours to obtain a sintered body.

This sintering system is ground by a surface grinder and further polished with a diamond grindstone or the like. The sintered body obtained by the polishing finishing is bonded to a copper backing plate with a low melting point metal such as metal indium as a bonding metal. Thereby, a composite oxide sputtering target can be obtained.

Such a composite oxide sputtering target is placed in the sputtering apparatus 200 and sputter-deposited to form an oxide semiconductor having the above composition. The film formation method using such a composite oxide sputtering target can also be applied to the second embodiment to be described later.

 (Formation of a circuit using a thin film transistor)  

The resistive element can be formed by patterning the above-described conductive metal oxide layer or oxide semiconductor film into a desired pattern. Further, for example, when a semiconductor device (thin film transistor) is formed on the second substrate 2 (for example, in the second embodiment to be described later), a plurality of thin film transistors (active elements) using a polyfluorene semiconductor are used. After forming a matrix as a channel layer, a matrix of a thin film transistor (active device) using an oxide semiconductor is laminated as a channel layer through a through hole formed in the insulating layer.

In a conventional technique using a resistive element or an n-type thin film transistor, an inverter circuit or an SRAM can be constructed. Similarly, a logic circuit such as a ROM circuit, a NAND circuit, a NOR circuit, a flip-flop, or a shift register can be constructed. Since the oxide semiconductor has extremely small leakage current, a circuit with low power consumption can be formed. Oxide semiconductors can be used as power semiconductors because of their high electrical withstand voltage. Further, since it has memory (voltage retention) which is not possessed by the germanium semiconductor, a good memory element can be provided. Alternatively, a matrix in which an active element using a polysilicon semiconductor as a channel layer is formed as a first layer on a different substrate, and a matrix using an active element of an oxide semiconductor as a channel layer is formed as a layer of a second layer. The above memory element or logic circuit can also be formed. The semiconductor device according to the embodiment of the present invention may be bonded to a circuit formed on a different substrate, or a plurality of layers may be stacked on the substrate.

As shown in the second embodiment to be described later, the display device according to the embodiment of the present invention can be provided with a touch sensing function. Alternatively, the second substrate 2 facing the first substrate 1 (array substrate) may be provided with a touch sensing function, and the first substrate 1 may include a thin film transistor that drives the liquid crystal layer or the organic electroluminescent layer. In other words, the second substrate 2 can be used as a touch panel, and a touch sensing control circuit for controlling touch sensing using the above-described resistive element or n-type thin film transistor can be formed on the second substrate 2.

The semiconductor device according to the embodiment of the present invention can be used, for example, as an active device for driving a liquid crystal (Liquid Crystal), a light emitting diode (LED), or an organic EL (OLED (Organic Light Emitting Diode). Furthermore, the semiconductor device according to the embodiment of the present invention can be applied to an active device that drives an EMS (Electro Mechanical System) device, a MEMS (Micro Electro Mechanical System) device, an IMOD (Interferometric Modulation) device, or an RFID (Radio Frequency Identification) device. Moreover, the semiconductor device according to the embodiment of the present invention can also be applied to a touch sensing control circuit for controlling touch sensing.

Since the active element is electrically connected by the conductive wiring having a low resistivity according to the embodiment of the present invention, the attenuation of the electrical signal is reduced, and a circuit with low power consumption can be formed. The attenuation of the electrical signal means the collapse or delay of the waveform of the input signal.

The semiconductor device according to the embodiment of the present invention can be combined with a pixel electrode (or a driver) in a contact hole exposed on the surface of the conductive metal oxide layer, for example, when a thin film transistor that drives the organic EL layer or the liquid crystal layer is formed. The ITO of the electrode) forms a substantially complete ohmic contact. This ohmic contact contributes to an improvement in semiconductor characteristics and a reduction in power consumption. In a general thin film transistor, a high melting point metal layer such as molybdenum or titanium is often used in contact with the ITO of the pixel electrode. Since such high melting point metals form metal oxides on the surface, electrical contact directions are difficult. In addition, ITO cannot form an ohmic contact with aluminum, and the adhesion between aluminum and ITO is also insufficient.

In addition, when a two-layered Cu/Ti layer structure of a conventional technique or a three-layered layer of Ti/Cu/Ti is used as a structure of a conductive wiring, hydrogen easily contained in the Ti layer easily adversely affects the oxide semiconductor. Specifically, the hydrogen released from the Ti layer changes the channel length of the thin film transistor, and the transistor characteristics can be changed. In the conductive wiring according to the embodiment of the present invention, since the copper alloy layer is sandwiched between the conductive metal oxide layers and the Ti layer is not used, the adverse effect due to hydrogen is extremely small.

Further, Ti or Mo is located on the metal wiring of the surface layer, and it is easy to form titanium oxide or molybdenum oxide on the surface thereof. When a Schottky barrier is formed in the electrical bonding in the contact hole, the threshold voltage (Vth) of the transistor may be adversely affected.

On the other hand, the conductive wiring according to the present embodiment does not cause such an adverse effect.

 (Second embodiment)  

Next, a second embodiment of the present invention will be described with reference to the drawings.

Hereinafter, a display device DSP2 according to a second embodiment of the present invention will be described with reference to Figs. 6 to 13 .

In the second embodiment, the description of the components of the general display device and the display device of the present embodiment will be omitted.

The display device DSP2 includes a switching transistor 89 having the same configuration as the above-described thin film transistor 39, a driving transistor 139 (thin film transistor) controlled by switching the transistor 89, and an organic EL layer driven by the driving transistor 139. . The display device DSP2 has a touch sensing function using an in-cell method. Here, the “in-cell method” means a display device in which a touch sensing function is built in a display device, or a display device in which a touch sensing function is integrated with a display device. As a technical term used in the present invention, "touch sensing" as an adjective may be simply referred to as "touch".

 (Functional configuration of display device DSP2)  

6 is a block diagram showing a control unit (a video signal control unit, a system control unit, and a touch sensing control unit) and a display unit that constitute a display device DSP2 including a semiconductor device according to a second embodiment of the present invention.

As shown in FIG. 6, the display device DSP2 of the present embodiment includes a display unit 110 and a control unit 120 for controlling the display unit 110 and a touch sensing function.

The control unit 120 has a well-known configuration, and includes a video signal control unit 121 (first control unit), a touch sensing control unit 122 (second control unit), and a system control unit 123 (third control unit). Antenna units 81 to 84 are provided between the touch sensing control unit 122 and the system control unit 123.

As will be described later, each of a plurality of pixels constituting the display unit 110 is provided with a switching transistor 89 (see FIG. 10), a driving transistor 139 (see FIGS. 8 and 10), and an organic EL layer.

The video signal control unit 121 sets the upper electrode (common electrode) provided on the array substrate 300 (first substrate 1) to a constant potential, and transmits the signal to the gate wiring (scanning line to be described later) provided on the array substrate 300. The source wiring (a signal line to be described later) supplies the driving voltage (electric power) for driving the organic EL layer to the power source line 140 (see FIGS. 8 and 10). The switching transistor 89 is selected by the video signal control unit 121, and the driving transistor 139 is driven. The driving voltage is applied from the driving transistor 139 to the organic EL layer, and the organic EL layer emits light on the array substrate 300, whereby an image is displayed on the array substrate 300.

The touch sensing control unit 122 applies a touch sensing driving voltage to the touch sensing driving wiring, and detects a change in electrostatic capacitance generated between the touch sensing driving wiring and the touch sensing detection wiring to perform touch. Control sensing. The touch sensing control unit 122 includes a power receiving unit 15 , a power control unit 16 , a touch driving control unit 17 , a touch driving switching circuit 18 , a touch detection switching circuit 19 , and a touch signal transmission and reception control unit 20 , which will be described later. And the detection and AD conversion unit 130.

The system control unit 123 can control the video signal control unit 121 and the touch sensing control unit 122 to alternately perform the detection of the change in the emission of the organic EL layer and the electrostatic capacitance, that is, in a time-sharing manner. Further, the system control unit 123 may have a function of causing the organic EL layer to emit light by making the organic EL layer emit light at a frequency different from the touch sensing drive frequency or a different voltage.

In the system control unit 123 having such a function, for example, the frequency of the noise received from the external environment received by the display device DSP2 can be detected, and the touch sensing driving frequency different from the noise frequency can be selected. This can reduce the impact of noise. Further, in the system control unit 123, a touch sensing drive frequency matching the scanning speed of an indicator such as a finger or a pen may be selected.

In the display device DSP2 having the configuration shown in FIG. 6, the control unit 120 has a function of applying a driving voltage for display to the lower electrode 88 to cause the organic EL layer to emit light, and detecting a touch sensing drive wiring and touch. A touch sensing function that controls the change in electrostatic capacitance generated between the sensing lines. Since the touch sensing wiring according to the embodiment of the present invention can be formed by a conductive wiring having a good electrical conductivity, the resistance value of the touch sensing wiring can be reduced to improve the touch sensitivity.

Preferably, the control unit 120 has a function of performing touch sensing driving during at least one stable period of the stable period of the image display and the black display stable period after the image display.

Fig. 7 is a cross-sectional view partially showing a display device DSP2 including a semiconductor device according to a second embodiment of the present invention.

8 is a cross-sectional view showing an array substrate (first substrate) constituting the display device DSP2 of the second embodiment of the present invention, and is a view showing an active element formed on the array substrate and a light-emitting layer of the organic EL.

As shown in FIG. 7 and FIG. 8 , the display device DSP2 is bonded to the organic substrate of the array substrate 300 (first substrate 1) and the display device substrate 100 (second substrate 2) through the transparent resin layer 97 of the adhesive layer. Hereinafter, it is called an organic EL) display device.

In the display device DSP2 according to the embodiment of the present invention, the display function layer is the light-emitting layer 92 (organic EL layer) and the hole injection layer 91. The switching transistor 89 and the driving transistor 139 are provided on the first substrate 1 (see FIGS. 8 and 10). The switching transistor 89 selected by the image signal control unit 121 supplies a switching signal to the driving transistor 139, whereby the driving transistor 139 drives the light-emitting layer 92.

The structure of the display device DSP2 in plan view is the same as that of the display device DSP1 of the first embodiment, and the shape and the like of the pixel opening portion 14 are substantially the same as those of the first embodiment. Similarly to the first embodiment, a color filter such as red pixel R, green pixel G, or blue pixel B may be disposed in the pixel opening portion 14.

Similarly to the first embodiment, the display device DSP2 includes a thin film transistor using an oxide semiconductor as a channel layer, that is, a switching transistor 89 and a driving transistor 139, and a copper alloy layer 13 as a conductive metal oxide layer. Clamped conductive wiring. The display device DSP2 shown in FIG. 7 has a display device substrate 100 having touch sensing wirings and has a touch sensing function.

 (The cross-sectional structure of the display device substrate)  

As shown in FIG. 7, on the second substrate 2 of the display device substrate 100, as will be described later, a black matrix BM having a rectangular effective display region 71 and a frame region 72 surrounding the effective display region 71 is provided.

The lower insulating layer 141 is provided on the black matrix BM, and the first conductive wiring 21 (the fifth conductive wiring 55) is provided on the lower insulating layer 141. An intermediate insulating layer 142 (gate insulating layer) is provided on the lower insulating layer 141 so as to cover the first conductive wiring 21. The second conductive wiring 22 (the sixth conductive wiring 56) is provided on the intermediate insulating layer 142. An upper insulating layer 143 is provided on the intermediate insulating layer 142 so as to cover the second conductive wiring 22. A transparent resin layer 97 is provided on the upper insulating layer 143, and the transparent resin layer 97 bonds the display device substrate 100 to the array substrate 300.

Further, in a part of the frame region 72, a black matrix BM is not formed, but a thin film transistor or the like is used, and a circuit such as the touch drive switching circuit 18 is formed on the lower insulating layer 141. The formation of such a circuit is the same as that of the first embodiment. The insulating layer formed on the second substrate 2 may be formed of a resin, or may be formed of ruthenium oxide, ruthenium oxynitride, tantalum nitride or the like as needed.

 (Sectional structure of the array substrate)  

As shown in FIG. 7 and FIG. 8, the first insulating layer 41, the second insulating layer 42, and the third insulating layer 43 are laminated on the first substrate 1. A driving transistor 139 is provided on the first insulating layer 41. The driving transistor 139 includes a channel layer 135, a source electrode 136, a drain electrode 137, and a gate electrode 138, and has a so-called top gate structure. The channel layer 135 has the same configuration as the channel layer 35 of the first embodiment, and is formed of an oxide semiconductor. Further, the source electrode 136, the drain electrode 137, and the gate electrode 138 are formed of a conductive wiring having a wiring structure similar to that of the source electrode 36, the gate electrode 37, and the gate electrode 38 of the first embodiment. Further, similarly to the first embodiment, the semiconductor interface 30 is formed at the interface between the channel layer 135 and the source electrode 136 and at the interface between the channel layer 135 and the gate electrode 137.

Although not shown in FIGS. 7 and 8, a switching transistor 89 (see FIG. 10) for supplying a switching signal to the driving transistor 139 is provided on the first substrate 1. This switching transistor 89 has the same configuration as that applied to the thin film transistor 39 of the first embodiment. The drain electrode of the switching transistor 89 is not connected to the pixel electrode, but is connected to the gate electrode 138 of the driving transistor 139.

The source electrode 136 of the driving transistor 139 is connected to the power source line 140. The power supply line 140 has a three-layer structure in which the copper alloy layer 13 is sandwiched between the first conductive metal oxide layer 11 and the second conductive metal oxide layer 12. The power supply line 140 and the source electrode 136 are of the same conductive wiring structure and are formed in the same layer.

The gate electrode 138 of the driving transistor 139 is connected to the gate electrode of the switching transistor 89. Therefore, the driving of the driving transistor 139 is controlled by the switching signal output from the gate electrode of the switching transistor 89.

Further, a holding capacitor (not shown) for maintaining the potential of the gate electrode 138 is provided on the gate electrode 138. This holding capacitance is formed between the gate electrode 138 and the power supply line 140.

The connection structure between the gate electrode of the switching transistor 89 and the gate electrode 138, and the electrode or wiring constituting the above-described storage capacitor are similarly applied to the conductive wiring having the three-layer structure described in the first embodiment. .

The first insulating layer 41 is provided with a source wiring 67 (third conductive wiring 23) connected to the source electrode 36 constituting the switching transistor 89, and a power source connected to the source electrode 136 constituting the driving transistor 139. Line 140. The second insulating layer 42 is formed on the first insulating layer 41 so as to cover the first insulating layer 41, the source wiring 67, the source electrode 136, the power source line 140, and the drain electrode 137. The second insulating layer 42 is provided with a gate wiring 69 (fourth conductive wiring 24) connected to the gate electrode 38 constituting the switching transistor 89, and a gate electrode 138 constituting the driving transistor 139. Further, in the array substrate 300, the gate electrode 138 is disposed to face the channel layer 135. The third insulating layer 43 is formed on the second insulating layer 42 so as to cover the second insulating layer 42, the gate wiring 69, and the gate electrode 138. A planarization layer 96 is formed on the third insulating layer 43. The channel layer 135 is formed of an oxide semiconductor. Further, the source wiring 67 and the third conductive wiring 23 have the same structure of the conductive wiring and are formed in the same layer. The gate wiring 69 and the fourth conductive wiring 24 have the same structure of the conductive wiring and are formed in the same layer.

In the planarization layer 96, a contact hole 93 is formed at a position corresponding to the gate electrode 137 constituting the drive transistor 139. Further, a bank 94 is formed on the planarization layer 96 at a position corresponding to the channel layer 135. The region between the adjacent dams 94 in the cross-sectional view, that is, the region surrounded by the dam 94 in plan view, is formed to cover the upper surface of the planarization layer 96, the inside of the contact hole 93, and the drain electrode 137. There is a lower electrode 88 (pixel electrode). Further, the lower electrode 88 may not be formed on the upper surface of the dam.

Further, a hole injection layer 91 is formed to cover the lower electrode 88, the bank 94, and the planarization layer 96. On the hole injection layer 91, a light-emitting layer 92, an upper electrode 87, and a sealing layer 109 are sequentially laminated. The lower electrode 88 has a configuration in which a silver or silver alloy layer is sandwiched by a conductive metal oxide layer.

As the material of the bank 94, an organic resin such as an acrylic resin, a polyimide resin, or a novolak phenol resin can be used. In the dam 94, inorganic materials such as cerium oxide and cerium oxynitride may be further laminated.

As a material of the planarization layer 96, an acrylic resin, a polyimide resin, a benzene ring-butyl resin, a polyamide resin, or the like can also be used. Low dielectric constant materials (low-k materials) can also be used.

Further, in order to improve visibility, either the planarization layer 96, the sealing layer 109, or the substrate may have a function of light scattering. Alternatively, a light scattering layer may be formed on the array substrate 300 on the viewing side of the observer OB.

 (planar structure of the display device substrate)  

FIG. 9 is a view showing a display device according to a second embodiment of the present invention viewed from an observer OB, showing a first conductive wiring, a second conductive wiring, a first antenna unit, and a first conductive wiring formed on a display device substrate (second substrate). 2 Plan view of circuits such as antenna unit and control unit. In addition, FIG. 9 is a plan view of the display device substrate 100 viewed from the observer OB, and the components of the display device substrate 100 are displayed so as to see through the black matrix BM having light blocking properties.

As shown in FIG. 9 , the first conductive wiring 21 , the second conductive wiring 22 , the first antenna unit 81 , and the first conductive wiring 21 , the second conductive wiring 22 , and the first antenna unit 81 are provided on the second substrate 2 of the display device substrate 100 (the surface facing the array substrate 300 ). 2 antenna unit 82, power receiving unit 15, power control unit 16, touch drive control unit 17, touch drive switching circuit 18, touch detection switching circuit 19, touch signal transmission and reception control unit 20, and detection and AD conversion unit 130. The wiring for electrically connecting the circuits of the first antenna unit 81, the second antenna unit 82, the touch drive switching circuit 18, and the touch detection switching circuit 19 is used, and a part of the first conductive wiring 21 and the second conductive are used. A portion of the wiring 22.

The black matrix BM includes a rectangular effective display area 71 and a frame area 72 surrounding the effective display area 71. The power receiving unit 15 , the power source control unit 16 , the touch driving control unit 17 , the touch driving switching circuit 18 , the touch detection switching circuit 19 , the touch signal transmission/reception control unit 20 , the detection, and the AD conversion unit 130 are illustrated in FIG. 9 . And the like means "the circuit for controlling touch sensing" of the present invention. Further, a part of the first conductive wiring 21, a part of the second conductive wiring 22, and the first active element constitute a circuit for controlling touch sensing. The power receiving unit 15 smoothes and equalizes the received voltage, and outputs it as a touch driving voltage to the power source control unit 16.

Further, the first conductive wiring 21, the second conductive wiring 22, the first antenna unit 81, the second antenna unit 82, the touch signal transmission/reception control unit 20, the touch drive switching circuit 18, the touch detection switching circuit 19, and the like are also It may not be arranged on the black matrix BM. In this case, for example, the first conductive wiring 21 and the second conductive wiring 22 may be formed as a touch-sensing wiring on the black matrix BM in the effective display region, and the glass having no black matrix BM formed on the outer side of the frame may be formed. A touch signal transmission/reception control unit 20, a touch drive switching circuit 18, a touch detection switching circuit 19, and the like are formed on the surface. Further, a part of the first conductive wiring 21 and the second conductive wiring 22 can be applied to the two-layer conductive wiring structure of the first antenna unit 81 or the second antenna unit 82 via the lower insulating layer 141. The first antenna unit 81 and the second antenna unit 82 include a loop antenna pair in which the winding directions are opposite to each other and the number of windings is two or more.

A plurality of first touch sensing wires (first conductive wires 21) extending in the X direction (first direction) and extending in the Y direction are provided on a surface of the second substrate 2 facing the first substrate 1 A plurality of second touch sensing wires (second conductive wires 22) in the (second direction). The first conductive wiring 21 and the second conductive wiring 22 have the above-described three-layer configuration.

An intermediate insulating layer 142 of a transparent resin is disposed between the first touch sensing wiring and the second touch sensing wiring. In the touch sensing wiring according to the embodiment of the present invention, the conductive wiring of the copper alloy layer is sandwiched between the conductive metal oxide layers.

These touch sensing wirings include a thin film transistor using an oxide semiconductor as a channel layer, and a fifth conductive wiring 55 and a sixth conductive wiring 56 as constituent elements of a circuit for controlling touch sensing. In addition, the fifth conductive wiring 55 and the first touch sensing wiring (first conductive wiring 21) have the same conductive wiring structure and are formed in the same layer. The sixth conductive wiring 56 and the second touch sensing wiring (second conductive wiring 22) have the same conductive wiring structure and are formed in the same layer.

 (planar structure of the array substrate)  

10 is a view showing a third antenna unit, a fourth antenna unit, a source signal switching circuit, and a gate signal switching circuit formed in an array substrate (first substrate) constituting a display device according to a second embodiment of the present invention; A plan view of a circuit of the organic EL-driven driving transistor 139, the switching transistor 89 that drives the transistor 139, and the like.

As shown in FIG. 10, on the first substrate 1 of the array substrate 300 (the surface facing the display device substrate 100), the third antenna unit 83, the fourth antenna unit 84, and the source signal switching circuit 26 are provided. A circuit such as a gate signal switching circuit 27, a power transmission unit 28, a signal transmission/reception unit 29, and an FPC. In the array substrate 300, a switching transistor 89 and a driving transistor 139 functioning as a thin film transistor are provided at positions corresponding to the pixel opening portion 14. The third antenna unit 83 and the fourth antenna unit 84 include a loop antenna pair in which the winding directions are the same as each other and the number of windings is two or more.

Circuits such as the source signal switching circuit 26, the gate signal switching circuit 27, the power transmitting unit 28, and the signal transmitting and receiving unit 29 are formed outside the effective display area of the first substrate 1. The power for driving these circuits is connected to a battery (not shown) via an FPC, or to an external power supply such as 100V via an adaptor.

When the display device substrate 100 and the array substrate 300 are bonded together, the first antenna unit 81 and the third antenna unit 83 are arranged to overlap each other in plan view (first overlapping portion 51). Further, the second antenna unit 82 and the fourth antenna unit 84 are arranged to overlap each other in plan view (second overlapping portion 52). The first superimposing unit 51 has a transmission/reception function of the touch sensing signal, and the second superimposing unit 52 has a function of receiving a power signal. The first antenna unit 81 and the third antenna unit 83 forming the first superimposing unit 51 and the second antenna unit 82 and the fourth antenna unit 84 forming the second overlapping unit 52 are disposed in the frame region 72.

In the example shown in FIG. 10, a power supply line 140 extending from the FPC toward the peripheral area of the display unit 110 is provided, and the power supply line 140 is an outer area (the upper side in FIG. 10) of the end portion of the display unit 110 in the Y direction. , extending in the X direction. Furthermore, the power supply lines 140 extending in the X direction are branched into a plurality of lines extending in the Y direction. The power supply line 140 extending in the Y direction is also connected to the source electrode 136 of the driving transistor 139 provided in a plurality of pixels arranged in the Y direction.

Further, in FIG. 10, one thin film transistor is displayed for each pixel, but the number of thin film transistors is not shown. As described above, the switching transistor 89 and the driving transistor 139 controlled by the switching transistor 89 are set. In one pixel.

When the video signal control unit 121 selects the switching transistor 89, the selected switching transistor 89 transmits a switching signal to the gate electrode 138 of the driving transistor 139, and the driving transistor 139 is driven. The driving voltage supplied from the power source line 140 (the source wiring of the driving transistor 139) is applied to the lower electrode 88 (pixel electrode) via the source electrode 136 and the gate electrode 137 by the driving of the driving transistor 139. . That is, the driving voltage is applied to the organic EL layer, and the organic EL layer emits light on the array substrate 300, whereby an image is displayed on the array substrate 300.

 (antenna unit)  

Next, a specific configuration of the antenna unit will be described with reference to Figs. 11 to 13 . Here, as shown in FIG. 11, the antenna unit means an antenna of one or more (in FIG. 11, a reverse-wound loop antenna pair). Also, the antenna is not limited to a loop antenna.

FIG. 11 is a partial plan view showing an enlarged view of a first antenna unit formed on a display device substrate 100 constituting a display device DSP2 including a semiconductor device according to a second embodiment of the present invention.

Fig. 12 is a cross-sectional view showing the first antenna unit formed on the display device substrate 100 of the display device DSP2 including the semiconductor device according to the second embodiment of the present invention, taken along line A-A' of Fig. 11.

FIG. 13 is a perspective view showing the superposition of the first antenna unit formed on the display device substrate 100 of the display device DSP2 including the semiconductor device according to the second embodiment of the present invention, and the third antenna unit formed on the array substrate 300.

In the following description, in the first antenna unit 81, the second antenna unit 82, the third antenna unit 83, and the fourth antenna unit 84, the structure of the first antenna unit 81 will be described as a representative. The antenna unit can also adopt the same configuration. In addition, in the following description, there is a case where it is simply called "antenna unit".

The "antenna unit" of the present invention means a configuration in which one or more antennas are arranged on a substrate for the purpose of transmitting and receiving a touch sensing signal, receiving power and supplying power, and the like. In the case of an antenna having a ring shape (a coil formed in the same plane or a spiral pattern), the antenna unit is configured such that two antennas wound in opposite directions are adjacent to each other. It is preferable from the viewpoint of ensuring the stability of communication. Alternatively, two or more antennas that are wound in opposite directions may be alternately adjacent to each other, and one of the antennas may be selected for use.

Further, in the second embodiment, the loop antenna may have a function of communicating with an external antenna of the display device DSP2, for example, an antenna prepared in an IC card.

As shown in FIG. 13, the first antenna unit 81 of the display device substrate 100 and the third antenna unit 83 of the array substrate 300 have the same loop antenna shape in plan view, and are positioned and overlapped (the first overlapping portion 51). Similarly, the second antenna unit 82 of the display device substrate 100 and the fourth antenna unit 84 of the array substrate 300 have the same loop antenna shape in plan view, and are positioned and overlapped (the second overlapping portion 52).

In the first overlapping portion 51 and the second overlapping portion 52, the line width of the conductive wiring forming the antenna is, for example, a fine line width of 1 μm to 20 μm, and the case where the antenna unit must be housed in the narrow frame region 72 is considered. The positional accuracy of the antenna is preferably within ±3 μm. When the accuracy of the position matching becomes high, the transmission or reception of the signal can be performed efficiently. By connecting two or more loop antennas in parallel, it is possible to reduce the size of the antenna and increase the speed of non-contact data transmission. In addition, in FIG. 11 to FIG. 13, a resonance circuit for forming each of the first antenna unit 81 and the second antenna unit 82 and each of the third antenna unit 83 and the fourth antenna unit 84 is omitted. An illustration of a capacitor or other part.

As the structure of the conductive wiring forming the antenna, a conductive wiring composed of three layers in which the above-described copper alloy layer is sandwiched by a conductive metal oxide layer can be used. For example, the first antenna unit 81 and the second antenna unit 82 can be formed in the same step as the first conductive wiring 21 (or the fifth conductive wiring 55). The third antenna unit 83 and the fourth antenna unit 84 can be formed in the same step as the third conductive wiring 23 (or the fourth conductive wiring 24).

As shown in FIG. 11, each of the first antenna unit 81, the second antenna unit 82, the third antenna unit 83, and the fourth antenna unit 84 is configured by a reversely wound loop antenna pair. Since the direction of the magnetic field generated by the reverse-wound loop antenna is reversed, noise can be generated to generate less stable transmission and reception. In other words, in the reverse-wound loop antenna, by forming magnetic fields in different directions, the shielding effect of the external magnetic field can be obtained, and the influence of external noise can be reduced. Further, the reverse winding means that, for example, the winding directions of the pair of loop antennas 164, 165 shown in FIG. 11 are line symmetrical with respect to the center line 116 in plan view.

The number of windings of the loop antenna is preferably 2 or more or 3 or more. When the outer shape of the antenna is a small size of 5 mm or less, the number of winding wires can be set to 3 or more and 20 or less. In the second embodiment, the number of windings of the first antenna unit 81, the second antenna unit 82, the third antenna unit 83, and the fourth antenna unit 84 is set to three. Here, the planar shape of the loop antenna having the number of windings of 2 or more is a curve which is close to the center with the convolution on the same plane. Arches of Archimedes which are substantially equally spaced between the lines can be typically exemplified.

In order to reduce the influence of noise from external (drive circuit, commercial power supply, general external power supply such as 100V, etc.), in the present embodiment, the plane of the substantially U-shaped conductor patterns 25A, 25B shown in Fig. 11 or Fig. 13 is used. The antenna elements 81, 82, 83, 84 are surrounded by the ground. The conductive wiring forming the antenna has a line width of 6 μm, and the positional accuracy (alignment accuracy) is set within ±2 μm. The structure of the conductive wiring is a three-layer structure in which a copper alloy layer is sandwiched between conductive metal oxide layers, as in the first embodiment.

The first superimposing unit 51 in which the first antenna unit 81 and the third antenna unit 83 overlap each other receives, for example, a touch driving signal from the CPU, or the touch detection switching circuit 19 transmits and receives the control unit 20 via the touch signal. The output of the touch detection signal is output. The touch drive signal is driven by the touch drive control unit 17 via the touch drive control unit 17 .

In the overlapping portion (second overlapping portion 52) of the second antenna unit 82 and the fourth antenna unit 84, for example, power generated by the fourth antenna unit 84 due to the generation of electromagnetic waves at the resonance frequency is used by the second antenna unit 82. receive. The power receiving unit 15 smoothes and voltages the received voltage, and outputs it to the power source control unit 16 as a touch driving voltage.

As shown in FIG. 12, a black matrix BM is formed on the second substrate 2, a lower insulating layer 141 is formed on the black matrix BM, and a first antenna unit 81 and a second antenna unit 82 are formed on the lower insulating layer 141. Further, as shown in Figs. 7 and 9, the first conductive wiring 21, the fifth conductive wiring 55, the first antenna unit 81, and the second antenna unit 82 are formed on the lower insulating layer 141. In other words, the first conductive wiring 21, the fifth conductive wiring 55, the first antenna unit 81, and the second antenna unit 82 are located in the same layer. Further, the conductor pattern 25A is also formed on the lower insulating layer 141.

More specifically, the first conductive metal oxide layer 11, the copper alloy layer 13 (or copper layer), and the second conductive metal oxide layer 12 are formed on the lower insulating layer 141 (conductivity of three layers) After the layer), the conductive layer having three layers is patterned by a well-known photolithography method to form the first conductive wiring 21, the fifth conductive wiring 55, the first antenna unit 81, the second antenna unit 82, and the conductor. The pattern of each of the patterns 25A. In other words, the "same layer" of the present invention means that after forming a three-layer conductive layer on a substrate, each wiring layer (conductive wiring, antenna unit, etc.) is patterned by the patterning, and wiring is performed. The antenna or the like is formed of the same layer and the same material, and is disposed on the same layer.

As described above, each of the first antenna unit 81 and the second antenna unit 82 formed of the conductive wiring (the first conductive wiring 21) having the same layer is transmitted through the first connection provided inside the antenna. The through holes 50 in the pads 60 and 61 are electrically connected to different conductive wirings (second conductive wirings 22). An intermediate insulating layer 142 is interposed between the first conductive wiring 21 and the second conductive wiring 22.

In the same manner, each of the third antenna unit 83 and the fourth antenna unit 84 formed of the conductive wiring (the third conductive wiring 23) having the same layer is transmitted through the second connection provided inside the antenna. The through holes in the pads 62 and 63 are electrically connected to different conductive wirings (fourth conductive wirings 24). The second insulating layer 42 is interposed between the third conductive wiring 23 and the fourth conductive wiring 24.

Each of the first conductive wiring 21 (the fifth conductive wiring 55), the second conductive wiring 22 (the sixth conductive wiring 56), the third conductive wiring 23, and the fourth conductive wiring 24 has a first conductive metal oxide layer and a first conductive layer 2 The conductive metal oxide layer is sandwiched between three layers of a copper alloy layer.

In the second embodiment, the oxide semiconductor used in the channel layer 35 is subjected to low-temperature annealing at 280 ° C using a composite oxide of an element ratio of In:Sb:Ce=1:1:0.06 to form a channel layer. In the copper alloy layer of the second embodiment, a copper alloy having an element ratio of Cu:Ca:Zn=97:2.5:0.8 is used. After the low temperature annealing described above, the copper alloy layer of the second embodiment has a resistivity of 3.1 μΩcm.

In the display device DSP2 of the second embodiment, an organic EL layer is used as the light-emitting layer. The present invention is not limited to the structure shown in the second embodiment. Instead of the organic EL layer, an LED display device including an LED chip can be formed. For example, in the case of the LED chip, an electrode formed of n-type GaN and an LED-reflecting electrode arranged on the same surface side are referred to as horizontal type LED chips. Further, instead of forming a layer associated with the organic EL such as the hole injection layer 91 or the light-emitting layer 92 between the banks 94 shown in FIG. 8, the LED wafer may be directly placed on the lower electrode 88 of the reflective electrode. A conductor may be formed on the back or side of the LED chip, and the LED chip and the upper electrode 87 may be electrically connected. In this case, the conductive system is electrically connected to the electrode made of n-type GaN. In the method of mounting an LED wafer on a substrate, for example, an LED wafer having an n-type GaN/light-emitting layer/p-type GaN/LED reflective electrode (a film of an Ag alloy or the like) laminated in this order is faced. The face down method can be placed on a substrate such as sapphire or GaN. At this time, the LED reflective electrode and the lower electrode 88 are electrically joined. These LED chips can be arranged in three types of pixel openings, such as red light emission, green light emission, and blue light emission, in the pixel opening portion between the banks 94. Alternatively, the blue light-emitting LED chips may be placed on the pixel openings located between the banks 94, and the wavelength conversion layers such as the content sub-points may be directly or indirectly disposed on the pixel openings. The wavelength conversion layer converts, for example, blue light-emitting light into green light-emitting light or blue light-emitting light into red light-emitting light. Further, in addition to the blue light-emitting LED, a red light-emitting LED or an infrared light-emitting LED may be additionally mounted.

According to the above-described embodiment, the conductive wiring having the three-layer structure in which the copper alloy layer 13 is sandwiched between the first conductive metal oxide layer 11 and the second conductive metal oxide layer 12 and having high conductivity can be formed. Further, a semiconductor device including a thin film transistor electrically connected to the conductive wiring can be realized. Further, a semiconductor device including a minute loop antenna or a touch sensing wiring, and a display device including such a semiconductor device can be provided.

For example, the semiconductor device or the display device of the above embodiment can be used in various applications. Examples of the electronic device to which the display device according to the above embodiment can be applied include a mobile phone, a mobile game machine, a mobile information terminal, a personal computer, an electronic book, an image sensor, a video camera, a digital camera, a head mounted display, Navigation system, audio reproduction device (car audio, digital audio player, etc.), copier, fax machine, printer, composite printer, vending machine, automatic teller machine (ATM), personal authentication equipment, optical communication equipment, etc. . Each of the above embodiments can be used in combination.

The preferred embodiments of the present invention have been described above, but it should be understood that these aspects are exemplary embodiments of the present invention and should not be considered as limiting. Additions, omissions, substitutions, and other modifications can be made without departing from the scope of the invention. Accordingly, the invention is not to be limited by the foregoing description, but is limited by the scope of the claims.

Further, in the display device DSP1 of the first embodiment, the antenna unit (loop antenna) and the touch sensing wiring described in the second embodiment can be formed on the second substrate 2. These antenna elements or touch sensing wiring lines can be formed by three layers in which a copper alloy layer is sandwiched between a first conductive metal oxide layer and a second conductive metal oxide layer.

Claims (10)

 A semiconductor device comprising: a substrate; a conductive wiring provided on one surface of the substrate; and a thin film transistor electrically connected to the conductive wiring; wherein the conductive wiring has a first conductive metal oxide layer and a second conductivity a metal oxide layer having a three-layer structure in which a copper layer or a copper alloy layer is sandwiched; the first conductive metal oxide layer and the second conductive metal oxide layer include indium oxide; and the thin film transistor has an oxide a channel layer formed of a semiconductor; the oxide semiconductor composite oxide comprising: indium oxide, cerium oxide, and an amount of oxidation less than an amount of each of the indium oxide and the cerium oxide In the oxide semiconductor, when the total of the elements of the uncounted oxygen is 100 at%, the amount of each of indium and antimony is 40 at% or more.    The semiconductor device according to claim 1, wherein, in the oxide semiconductor, when the total of indium, bismuth and antimony of uncounted oxygen is 100 at%, the amount of each of indium and antimony is 45 at% or more and 49.8 at In the range of % or less, the amount of niobium is in the range of 10 at% or less and 0.4 at% or more.    A semiconductor device according to claim 1, wherein said thin film electromorphic system has an insulating film which is in contact with said channel layer and contains at least cerium oxide.    The semiconductor device according to claim 1, wherein the copper alloy layer comprises: a first element which is solid-solubilized in copper, and a second element having a lower electrical property than copper and the first element; and the first element and the second element The element having a specific resistance increase rate when added to copper is 1 μΩcm/at% or less; and the specific resistance of the copper alloy layer is in the range of 1.9 μΩcm to 6 μΩcm.    The semiconductor device according to claim 4, wherein in the copper alloy layer, the first element is zinc, the second element is calcium, and when the total of copper, zinc, and calcium is 100 at%, the copper alloy layer The first element is contained in a range of 0.2 at% or more and 5.0 at% or less, and the second element is contained in a range of 0.2 at% or more and 5.0 at% or less, and copper is contained as a remainder.    The semiconductor device according to claim 1, wherein the first conductive metal oxide layer and the second conductive metal oxide layer contain indium oxide as a main conductive metal oxide and are selected from the group consisting of ruthenium oxide and oxidation. One or more types of conductive metal oxides of the group consisting of zinc and gallium oxide.    A display device comprising the semiconductor device of claim 1.    The display device according to claim 7, comprising: an antenna formed of a conductive wiring having a copper layer or a copper alloy layer sandwiched between the first conductive metal oxide layer and the second conductive metal oxide layer; The three-layer structure is formed; the first conductive metal oxide layer and the second conductive metal oxide layer contain indium oxide.    A sputtering target for use in a sputtering target for manufacturing a semiconductor device according to claim 1, comprising indium oxide and antimony oxide as a main material, and containing a composite oxide having cerium oxide as a stabilizer; In the composite oxide, when the total of indium, antimony, and antimony of uncounted oxygen is 100 at%, the amount of each of indium and antimony is in the range of 45 at% or more and 49.8 at% or less, and the amount of ruthenium is 10 at% or less in the range of 0.4 at% or more.    A sputtering target for use in a sputtering target for forming a copper alloy layer of the semiconductor device of claim 1, comprising a first element which is solid-solubilized in copper, and a cathode which is less than copper and the first element The second element; the first element is zinc, and the second element is calcium; and when the total of copper, zinc, and calcium is 100 at%, the content of the first element is 0.2 at% or more and 5.0 at% or less In the range, the content of the second element is in the range of 0.2 at% or more and 5.0 at% or less, and the remainder other than the first element and the second element contains copper.