TW201904011A - Electronic package and method of manufacture thereof - Google Patents

Abstract

An electronic package and a method for manufacturing the same, wherein an electronic component and a plurality of conductive pillars and supporting members of different heights are disposed on the first circuit structure, and then the block body is disposed on the support member, and then the electronic component, the block body is formed, The cover of the support member and the conductive post is such that the periphery of the electronic component is covered with the block and the support member to prevent the electronic component from being subjected to external electromagnetic interference when the electronic package is operated.

Description

 Electronic package and its manufacturing method  

The invention relates to a packaging technology, in particular to a semiconductor package for avoiding electromagnetic interference and a method for manufacturing the same.

With the rapid development of the electronics industry, electronic products are gradually moving towards multi-functional and high-performance trends. In order to meet the demand for electronic products and miniaturization of electronic packages disposed therein, a technology for developing a chip scale package (CSP) is characterized in that the wafer size package has only a wafer and a wafer. Dimensions of equal or slightly larger size.

1A to 1E are schematic cross-sectional views showing a method of manufacturing a conventional wafer size package 1.

As shown in FIG. 1A, a thermal release tape 100 is formed on a carrier 10.

Next, a plurality of semiconductor elements 11 are disposed on the thermal release layer 100, and the semiconductor elements 11 have opposing surfaces 11a and 11b, each of which has a plurality of electrode pads 110, and Each of the active surfaces 11a is adhered to the heated release layer 100.

As shown in Fig. 1B, an encapsulant 14 is formed on the thermal release adhesive layer 100 to coat the semiconductor element 11.

As shown in FIG. 1C, the encapsulant 14 is baked to harden the thermal release layer 100 and the decarburized layer 100 and the carrier 10 are removed, and the active surface 11a of the semiconductor element 11 is exposed. .

As shown in FIG. 1D, a wiring structure 16 is formed on the encapsulating body 14 and the active surface 11a of the semiconductor component 11, so that the wiring structure 16 is electrically connected to the electrode pad 110. Next, an insulating protective layer 18 is formed on the wiring structure 16, and the insulating protective layer 18 exposes a portion of the surface of the wiring structure 16 for bonding the conductive elements 17 such as solder balls.

As shown in FIG. 1E, a singulation process is performed along the dicing path L as shown in FIG. 1D to obtain a plurality of wafer-sized packages 1.

However, in the conventional wafer-sized package 1, it is only possible to place the semiconductor element 11 in a single layer, so that the application of the terminal product is greatly limited. Accordingly, the industry has developed a three-dimensional Wafer Level System in Package (WLSiP) structure to meet the needs of today's terminal product applications.

2A to 2E are schematic cross-sectional views showing a manufacturing method of a conventional WLSiP type electronic package 2.

As shown in FIG. 2A, a first circuit structure 20 is bonded to a carrier board 9 having a release layer 90 and a bonding layer 91. The first circuit structure 20 has a first side 20a and a second side 20b. The second side 20b is bonded to the bonding layer 91, and the first circuit structure 20 includes a first insulating layer 200 and a first redistribution layer (redistribution layer) disposed on the first insulating layer 200. RDL) 201.

Then, a plurality of conductive pillars 23 electrically connected to the first line structure 20 are formed on the first side 20a, and the first electronic component 21 is disposed on the first side 20a of the first line structure 20. The first electronic component 21 has an opposite active surface 21a and an inactive surface 21b. The first electronic component 21 is adhered to the first side of the first circuit structure 20 by a bonding layer 214. 20a, the active surface 21a has a plurality of electrode pads 210, and a conductive body 212 is formed thereon, and an insulating layer 211 is formed on the active surface 21a to cover the electrode pads 210 and the insulating layer 211. Conductor 212.

As shown in FIG. 2B, a cladding layer 25 is formed on the first side 20a of the first circuit structure 20 to cover the first electronic component 21 and the conductive pillars 23, and the cladding layer 25 is formed. The surface of the insulating layer 211 is flush with the surface of the insulating layer 211 and the end surface of the conductive body 212, so that the surface of the insulating layer 211, the end surface of the conductive pillar 23 and the end surface of the conductive body 212 are exposed. Cover 25.

As shown in FIG. 2C, a second line structure 26 is formed on the cladding layer 25, and the second line structure 26 is electrically connected to the conductive pillars 23 and the conductor 212. The second line is electrically connected. The structure 26 includes a plurality of second insulating layers 260, 260' and a plurality of second line redistribution layers (RDL) 261, 261' disposed on the second insulating layer 260, 260'.

As shown in Fig. 2D, the carrier sheet 9 and the release layer 90 thereon are removed. Then, an insulating protective layer 28 is formed on the bonding layer 91, and a plurality of openings are formed in the insulating protective layer 28 and the bonding layer 91 to expose a part of the surface of the first circuit redistribution layer 201. An opening is provided for bonding a plurality of conductive elements 27 such as solder balls to the second side 20b of the first line structure 20 to receive the second electronic component 22.

As shown in FIG. 2E, an encapsulation layer 24 is formed on the second side 20b of the first line structure 20 to encapsulate the second electronic components 22. Next, an under bump metallurgy (UBM) 270 is formed on the outermost second line redistribution layer 261' to form a plurality of conductive elements 27' such as solder balls. Electronic devices such as structures or wafers (not shown).

However, when the conventional electronic package 2 is in operation, the first electronic component 21 located between the first and second circuit structures 20, 26 is very sensitive to external electromagnetic waves, which not only makes the first electronic component 21 impossible to perform normally. It operates, and external electromagnetic waves may also damage the first electronic component 21.

Therefore, how to overcome the various problems of the above-mentioned prior art has become a problem that is currently being solved.

In view of the above-mentioned deficiencies of the prior art, the present invention provides an electronic package comprising: a first line structure having opposite first and second sides; and a plurality of conductive posts disposed on the first side and electrically The first line structure is connected to the first line structure; the plurality of support members are disposed on the first side of the first line structure; the electronic component is coupled and electrically connected to the first side of the first line structure; The cover member is disposed on the support member to cover the electronic component; the cladding layer is formed on the first side of the first circuit structure to cover the electronic component, the block body, the support member and the conductive pillar; The two-line structure is formed on the cladding layer and electrically connected to the conductive pillar.

The invention also provides a method for manufacturing an electronic package, comprising: providing a first line structure having opposite first and second sides, and forming a plurality of conductive columns and a plurality of support members on the first side, and Locating at least one electronic component; providing a block on the support member to cover the electronic component; forming a cladding layer on the first side of the first circuit structure to allow the cladding layer to be wrapped And covering the electronic component, the block, the support member and the conductive pillar; and forming a second circuit structure on the cladding layer, and electrically connecting the second circuit structure to the conductive pillar.

In the above method, the process of providing the block includes: bonding a conductive cover member to the conductive post and the support member, wherein the conductive cover member comprises the block disposed on the support member and by the plurality A bracket is coupled to the frame of the block, and the frame is disposed on the conductive post; and after the cover layer is formed, the frame is removed. Further, the stent may be removed after the coating layer is formed.

In the above electronic package and method of manufacturing the same, the electronic component is provided on the first line structure in a flip chip manner.

In the above electronic package and method of manufacturing the same, the height of the support relative to the first side is less than the height of the conductive post relative to the first side.

In the foregoing electronic package and method of manufacturing the same, the support member is located between the electronic component and the conductive post.

In the foregoing electronic package and method of manufacturing the same, the support is used for grounding.

In the above electronic package and the method of manufacturing the same, the material forming the support and the block is a conductive material.

In the above electronic package and the method of manufacturing the same, the top surface of the block exposes the cladding layer.

In the foregoing electronic package and method of manufacturing the same, the second line structure is connected to the block.

In the foregoing electronic package and method of manufacturing the same, the method further includes forming a plurality of conductive elements on the second side of the first line structure.

In the foregoing electronic package and method of manufacturing the same, the method further comprises forming a plurality of conductive elements on the second line structure.

It can be seen from the above that the electronic package of the present invention and the manufacturing method thereof are mainly provided by the design of the block and the support member, so that the periphery of the electronic component is covered with a shielding structure, so that when the electronic package is operated, the electronic component does not Subject to electromagnetic interference from the outside world.

Furthermore, the present invention utilizes a metal frame as a block for shielding, so that it is not necessary to form a metal shield layer by electroplating or splashing, which not only reduces the process cost, but also maintains the consistency of the electronic product.

1‧‧‧ Wafer size package

10‧‧‧ Carrier

100‧‧‧heating release layer

11‧‧‧Semiconductor components

11a, 21a, 31a‧‧‧ action surface

11b, 21b, 31b‧‧‧ non-active surface

110,210,310‧‧‧electrode pads

14‧‧‧Package colloid

16‧‧‧Line structure

17,27,27’,37,37’‧‧‧Conductive components

18,28,38‧‧‧Insulating protective layer

2,3‧‧‧Electronic package

20,30‧‧‧First line structure

20a, 30a‧‧‧ first side

20b, 30b‧‧‧ second side

200,300‧‧‧first insulation

201,301‧‧‧First line redistribution

21‧‧‧First electronic components

211,311‧‧‧Insulation

212,312‧‧‧Electrical conductor

214,91‧‧‧bonding layer

22‧‧‧Second electronic components

23,33‧‧‧conductive pillar

24‧‧‧Encapsulation layer

25,35‧‧" cladding

26, 36‧‧‧Second line structure

260,260',360,360'‧‧‧second insulation

261,261’,361,361’‧‧‧Second line redistribution

270,370‧‧‧Metal under the bump

31‧‧‧Electronic components

311‧‧‧ solder bumps

311a‧‧‧brass

32‧‧‧Electrical cover

320‧‧‧ Block

321‧‧‧Frame

321’‧‧‧ bracket

34‧‧‧Support

4‧‧‧Electronic devices

40‧‧‧ wafer

9‧‧‧Loading board

90‧‧‧ release layer

L, S‧‧‧ cutting path

H, h‧‧‧ height

1A to 1E are schematic cross-sectional views showing a conventional method for fabricating a wafer-sized package; FIGS. 2A to 2E are schematic cross-sectional views showing a method of manufacturing a conventional WLSiP type electronic package; and FIGS. 3A to 3G are diagrams showing the electron of the present invention; A schematic cross-sectional view of a method of fabricating a package; a 3C' view is a partial top plan view corresponding to FIG. 3C; and a 3D' view is a cross-sectional view of another embodiment corresponding to the 3D view.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "first", "second" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.

3A to 3G are schematic cross-sectional views showing the manufacturing method of the electronic package 3 of the present invention.

As shown in FIG. 3A, a first line structure 30 having a first side 30a and a second side 30b opposite to each other is formed on a carrier board 9, and a plurality of conductive pillars 33 and a plurality of support members are formed on the first side 30a. 34, and the second side 30b is coupled to the carrier plate 9.

In this embodiment, the carrier board 9 is a circular plate body made of a semiconductor material such as glass, and a release layer 90 and a bonding layer 91 are sequentially formed on the substrate for coating, for example, for the first line. Structure 30 is provided on the bonding layer 91.

Furthermore, the first circuit structure 30 includes at least one first insulating layer 300 and a first redistribution layer (RDL) 301 disposed on the first insulating layer 300. Specifically, the material forming the first circuit redistribution layer 301 is, for example, copper, and the material forming the first insulating layer 300 is a dielectric material, such as polybenzoxazole (PBO), polyphthalate. Polyimide (PI), Prepreg (PP).

Moreover, the conductive pillar 33 is disposed on the first circuit redistribution layer 301 to electrically connect the first circuit redistribution layer 301, and the material of the conductive pillar 33 is made of a metal material such as copper or a solder material.

In addition, the support member 34 is disposed on the first circuit redistribution layer 301 for grounding, and the material forming the support member 34 is a metal material such as copper or a solder material, and the conductive pillars 33 are surrounded. On the periphery of the support members 34, the height h of the support member 34 relative to the first side 30a is smaller than the height H of the conductive post 33 relative to the first side 30a.

Specifically, in the embodiment, the support member 34 is columnar (also in the form of a sheet), which can be fabricated together with the conductive post 33, for example, a Double image process. In detail, the conductive post 33 can be separately formed from the support member 34. For example, the photoresist of the support member 34 can be directly formed without removing the photoresist formed by the conductive post 33 to form a high and low column, and then removed. The two layers of photoresist; or, first form a low pillar (the support member 34) and remove the photoresist used thereby, form a high pillar (the conductive pillar 33) and remove the photoresist used; or remove the fabrication The photoresist of the conductive pillar 33 is further provided with another photoresist to form the support member 34. Therefore, the conductive post 33 and the support member 34 are manufactured in a wide variety of ways, and are not limited to the foregoing.

As shown in FIG. 3B, at least one electronic component 31 is coupled to the first side 30a of the first circuit structure 30, and the electronic component 31 is electrically connected to the first circuit structure 30, and the support members 34 are Surrounding the periphery of the electronic component 31, the support member 34 is positioned between the electronic component 31 and the conductive pillar 33.

In the present embodiment, the electronic component 31 is a semiconductor component that is an active component, a passive component, or a combination thereof, and the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. For example, the electronic component 31 is a semiconductor wafer having an opposite active surface 31a and a non-active surface 31b. The active surface 31a has a plurality of electrode pads 310, and the electronic component 31 is in a flip chip manner (eg, by a plurality of copper) The solder bump 311) of the block 311a is electrically connected to the first circuit redistribution layer 301 and the electrode pad 310.

As shown in FIG. 3C, a conductive cover member 32 is coupled to the conductive post 33 and the support member 34 such that the conductive cover member 32 covers the electronic component 30.

In this embodiment, the conductive cover member 32 is a metal body, and includes a frame 321 and a block 320. The frame 321 is connected to the block 320 by a plurality of brackets 321', as shown in FIG. 3C', and The frame 321 is connected to the conductive post 33, and the block 320 is connected to the support member 34 to cover the electronic component 30.

As shown in FIG. 3D, a cladding layer 35 is formed on the first side 30a of the first circuit structure 30, so that the cladding layer 35 covers the electronic component 31, the conductive cover member 32, and the conductive layers. The pillars 33 and the support members 34 are further subjected to a leveling process to expose the end faces of the conductive pillars 33 and the bulk body 320 to the cladding layer 35.

In this embodiment, the cladding layer 35 is an insulating material, such as an epoxy encapsulant, which may be formed on the first circuit structure 30 by lamination or molding. On the first side 30a.

Furthermore, the leveling process removes a portion of the material of the conductive post 33, the frame 321 of the conductive cover member 32 (including the bracket 321'), and a portion of the material of the cladding layer 35 by grinding, so that the conductive material is electrically conductive. The end face of the post 33 is flush with the top surface of the block 320 to the surface of the cover layer 35.

Moreover, the block 320 may not be exposed on the surface of the cladding layer 35. As shown in FIG. 3D', the frame 321 can be pressed against the block 320 by bending the bracket 321' to make the frame 321 and the block 320 stand out high, so when the package is formed After the cladding layer 35 is on the first side 30a of the first circuit structure 30, the frame 321 is protruded from the cladding layer 35, and the frame 321 is removed by the leveling process to make the bracket 321' The block 320 is embedded in the cladding layer 35.

As shown in FIG. 3E, a second wiring structure 36 is formed on the cladding layer 35, and the second wiring structure 36 is electrically connected to the conductive pillars 33 and the bulk 320.

In this embodiment, the second circuit structure 36 includes a plurality of second insulating layers 360, a plurality of second circuit redistribution layers 361 disposed on the second insulating layer 360, and a second insulating layer 360 of the outermost layer. 'Can be used as a solder resist layer to expose the outermost second line redistribution layer 361' to the solder resist layer. Alternatively, the second line structure 36 may also include only a single second insulating layer 360 and a single second line redistribution layer 361.

Furthermore, the material of the second circuit redistribution layer 361, 361' is made of copper, and the material of the second insulating layer 360, 360' is formed, for example, poly-p-oxazobenzene (PBO), polyimine (Polyimide, abbreviation PI), prepreg (PP) dielectric material.

As shown in FIG. 3F, the carrier sheet 9 and the release layer 90 thereon are removed. Next, an insulating protective layer 38 such as a solder resist layer is formed on the bonding layer 91 on the second side 30b of the first wiring structure 30.

As shown in Fig. 3G, a singulation process is performed along the dicing path S as shown in Fig. 3F to complete the electronic package 3 of the present invention.

In this embodiment, a bump under metal layer (UBM) 370 may be formed on the outermost second line redistribution layer 361' to combine a plurality of conductive elements such as solder balls on the outermost layer of the second line. On the layer 361', the cymbal is used to connect other electronic structures (such as another package, or a wafer such as the conventional second electronic component 22).

In addition, a plurality of openings may be formed on the insulating protective layer 38 and the bonding layer 91 to expose the first circuit redistribution layer 301 to the openings, for forming a plurality of conductive elements 37' of solder balls. The second side 30b of the first line structure 30 is connected to an electronic device 4 such as a package structure containing a wafer 40 or other electronic structure such as another package or wafer.

Therefore, the electronic package 3 of the present invention is formed by using the block 320 of the conductive cover member 32 as a shielding structure to block external electromagnetic waves from the electronic component 31 between the first and second line structures 30, 36. The interference allows the electronic component 31 of the present invention to operate normally, and the external electromagnetic wave can be prevented from damaging the electronic component 31.

Furthermore, the manufacturing method of the present invention uses the metal block 320 on the simple metal frame 321 as a shielding structure, so that it is not necessary to form a metal shielding layer by electroplating or splashing, so that the process cost can be reduced.

Moreover, the method of the present invention makes the appearance of the electronic package 3 substantially unchanged, thereby maintaining the consistency of the electronic product.

The invention also provides an electronic package 3 comprising: a first line structure 30, a plurality of conductive columns 33, an electronic component 31, a block 320, a plurality of supports 34, a cladding layer 35 and a second circuit structure 36.

The first line structure 30 has opposite first side 30a and second side 30b.

The conductive pillars 33 are disposed on the first side 30a and electrically connected to the first line structure 30.

The support member 34 is disposed on the first side 30a of the first line structure 30.

The first electronic component 31 is coupled and electrically connected to the first line structure 30.

The block 320 is disposed on the support member 34 and covers the first electronic component 31.

The cladding layer 35 is formed on the first side 30a of the first circuit structure 30 to cover the electronic component 31, the block 320, the support member 34 and the conductive pillars 33, and the conductive pillars are The end face of 33 is exposed to the cladding layer 35.

The second line structure 36 is formed on the cladding layer 35 and electrically connected to the conductive pillars 33.

In one embodiment, the electronic component 31 is provided on the first side 30a of the first line structure 30 in a flip chip manner.

In one embodiment, the height h of the support member 34 relative to the first side 30a is smaller than the height H of the conductive post 33 relative to the first side 30a.

In an embodiment, the support member 34 is located between the electronic component 31 and the conductive pillar 33.

In an embodiment, the support member 34 is a conductive material.

In one embodiment, the block 320 is a conductive material.

In an embodiment, the block 320 is exposed to the cladding layer 35.

In an embodiment, the second line structure 36 is connected to the block 320.

In one embodiment, the electronic package 3 includes a plurality of conductive elements 37' formed on the second side 30b of the first line structure 30.

In one embodiment, the electronic package 3 includes a plurality of conductive elements 37 formed on the second line structure 36.

In summary, the electronic package of the present invention and the method for manufacturing the same are used as the shielding structure of the electronic component by the block and the support member, thereby preventing the electronic component from being subjected to external electromagnetic interference and making the electrical property of the electronic package. The function is working properly.

Furthermore, the present invention utilizes a block on a simple metal frame as a shield structure, so that it is not necessary to form a metal shield layer by electroplating or sputtering, which not only reduces process cost but also maintains the consistency of electronic products.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

Claims (22)

 An electronic package includes: a first circuit structure having opposite first and second sides; a plurality of conductive posts disposed on the first side and electrically connected to the first circuit structure; And being disposed on the first side of the first circuit structure; the electronic component is coupled and electrically connected to the first side of the first circuit structure; the block is disposed on the support member to cover the electronic component a cladding layer formed on a first side of the first wiring structure to cover the electronic component, the block, the support member, and the conductive pillar; and a second wiring structure formed on the cladding layer The conductive pillar is electrically connected to and electrically connected.    The electronic package of claim 1, wherein the electronic component is provided on the first circuit structure in a flip chip manner.    The electronic package of claim 1, wherein the height of the support relative to the first side is less than the height of the conductive post relative to the first side.    The electronic package of claim 1, wherein the support member is located between the electronic component and the conductive post.    The electronic package of claim 1, wherein the material forming the support and the block is a conductive material.    The electronic package of claim 1, wherein the support member is used for grounding.    The electronic package of claim 1, wherein the top surface of the block exposes the cladding layer.    The electronic package of claim 1, wherein the second line structure is connected to the block.    The electronic package of claim 1, further comprising a plurality of conductive elements formed on the second side of the first line structure.    The electronic package of claim 1, further comprising a plurality of conductive elements formed on the second line structure.    An electronic package manufacturing method includes: providing a first line structure having opposite first and second sides, and forming a plurality of conductive columns and a plurality of support members on the first side and at least one of the plurality of support members An electronic component; a block body is disposed on the support member to cover the electronic component; and a cladding layer is formed on the first side of the first circuit structure, so that the cladding layer covers the electronic component, The block, the support member and the conductive post; and a second line structure formed on the cover layer, and the second line structure is electrically connected to the conductive post.    The method of manufacturing an electronic package according to claim 11, wherein the electronic component is provided on the first circuit structure in a flip chip manner.    The method of manufacturing the electronic package of claim 11, wherein the height of the support member relative to the first side is less than the height of the conductive post relative to the first side.    The method of manufacturing an electronic package according to claim 11, wherein the support member is located between the electronic component and the conductive post.    The method of manufacturing an electronic package according to claim 11, wherein the material forming the support member and the block is a conductive material.    The method of manufacturing an electronic package according to claim 11, wherein the support member is used for grounding.    The method of manufacturing an electronic package according to claim 11, wherein the top surface of the block exposes the cladding layer.    The method of manufacturing an electronic package according to claim 11, wherein the second circuit structure is connected to the block.    The method of manufacturing an electronic package according to claim 11, further comprising forming a plurality of conductive elements on the second side of the first line structure.    The method of manufacturing an electronic package according to claim 11, further comprising forming a plurality of conductive elements on the second line structure.    The method of manufacturing the electronic package of claim 11, wherein the process of installing the block comprises: bonding a conductive cover member to the conductive post and the support member, wherein the conductive cover member comprises The block on the support member and the frame of the block are connected by a plurality of brackets, and the frame is disposed on the conductive post; and after the cover layer is formed, the frame is removed.    The method for manufacturing an electronic package according to claim 21, wherein the method comprises: after forming the cladding layer, removing the bracket.