TW201841353A - Method for manufacturing three-dimensional flash memory device - Google Patents

Abstract

The present invention relates to three-dimensional fast filling of a dielectric filler having a very large aspect ratio three-dimensional flash memory device by using a supercritical vapor deposition step or a high-pressure densification step by using a high-pressure supercritical oxide composition ratio optimization technology. The manufacturing method of the flash memory device can fill the dielectric filler for filling the dielectric material by low-temperature and high-pressure heat treatment, thereby improving the characteristics and reliability of the three-dimensional flash memory device.

Description

   Manufacturing method of three-dimensional flash memory device   

The present invention relates to a method for manufacturing a three-dimensional flash memory device that fills a void-free dielectric gap under high aspect ratio conditions, and more particularly, by using a high-pressure supercritical-based oxide Manufacturing of a three-dimensional flash memory device using a composition ratio optimization technique to form a dielectric filler of a three-dimensional flash memory device with a very large aspect ratio in a supercritical evaporation step or a high-pressure densification step. method.

Generally, a flash memory device is classified into a NAND type and a NOR type according to a unit structure and operation.

In addition, the memory device is classified into a floating gate type memory device, a metal oxide nitride semiconductor (Metal Oxide Nitride Oxide Semiconductor; MONOS) structure, or a nitride according to the type of the material used in the charge storage layer (charge storage film) of the unit cell. A memory device with a Silicon Oxide Nitride Oxide Semiconductor (SONOS) structure.

A floating gate type memory device is a device that uses a potential well to achieve memory characteristics. A metal oxide nitride semiconductor or a silicon nitride semiconductor type uses a volume of a silicon nitride film as a dielectric film. A floating gate existing in a bulk or a floating gate existing at an interface between the dielectric film and the dielectric film, etc., to realize the memory characteristics. The aforementioned metal oxide nitride semiconductor refers to a case where the control gate is formed of a metal, and a silicon nitride semiconductor refers to a case where the control gate is formed of polycrystalline silicon.

In particular, compared with a flash memory of a floating gate type, a silicon nitride semiconductor or a metal oxide nitride semiconductor type has advantages in that it has relatively easy scaling and improved endurance and Uniform threshold voltage distribution. However, when the thicknesses of the tunnel insulating film and the blocking insulating film are reduced for high integration, characteristics are degraded in terms of record retention and durability.

Recently, flash memory devices have achieved large-capacity based on continuous expansion. As a result, they have been used as storage memory in various fields, and mass production of 20nm-class 128Gbit products has been realized. It is expected to use floating gate technology ( floating gate technology) to scale below 10nm.

In addition, in order to achieve high integration of flash memory devices, from two-dimensional structure to three-dimensional structure, NAND flash memory devices can eliminate the need to form contacts in each storage cell. In the case of), the storage units are connected in a string form, so that a variety of three-dimensional structures in the vertical direction can be realized.

This three-dimensional and non-flash memory is formed in a configuration in which an N + junction diffusion layer is arranged in a Si volume and used as a common source line. This structure has advantages, but since the resistance of the diffusion layer is large, a phenomenon that the characteristics of the memory cell are deteriorated occurs.

On the other hand, technical development is also being made to reduce the size of the isolation area for electrically isolating the devices of the storage unit. In the step of local oxidation of silicon (LOCOS) in which a magnetic field oxide film is formed in the isolation region, a bird's beak of the active area in which the magnetic field oxide film penetrates into the active region is reduced. problem. In order to improve the problem of local oxidation of silicon, a shallow trench isolation (STI) step is proposed. In the above shallow trench isolation step, as the design rule is reduced, the width of the channel becomes smaller, but the depth of the channel is almost constant, thus causing the aspect ratio of the channel to gradually increase. Therefore, it becomes difficult to completely fill the space in the channel with an insulator.

An example of this technique is disclosed in the following documents and the like.

For example, in the following Patent Document 1, a shallow trench isolation method is disclosed, which includes forming a shallow trench by a conventional photoetching step after laminating a multilayer insulating film on the surface of a semiconductor substrate. A step of forming an oxide film on the bottom surface and an inner side surface of the shallow trench; a step of forming a predetermined film having no underlying dependency on the surface of the oxide film; and filling the shallow trench in which the predetermined film is formed A method of laminating a predetermined insulating film in a predetermined thickness.

In addition, Patent Document 2 below discloses a method for processing a semiconductor substrate, that is, including a step (a) as a step of providing a substrate including a feature portion having one or more features. The features are substrates each having a feature opening; step (b), in order to partially fill a plurality of the above features, the substrate is exposed to a cobalt-containing precursor; step (c), the substrate is exposed to a nitrogen-containing gas and a plasma; step ( d) selectively repeating the above steps (b) and (c); and step (e), according to the differential suppression configuration, cobalt is vapor-deposited within the above characteristics, and the semiconductor is performed at a temperature of less than about 400 ° C Processing method of substrate.

In addition, Patent Document 3 below discloses a three-dimensional flash memory device including a device-forming substrate formed with through holes penetrating through an upper surface and a lower surface, and a conductive body with a gap filled in the through holes. A vertical channel formed in the through hole and formed in a shape extending long along the upper direction of the device forming substrate; and a common source line electrically connected to the conductor and formed of a conductive substance.

In addition, in the following Patent Document 4, a covering step of a high aspect ratio feature is disclosed, that is, after the semiconductor substrate including the patterned feature is wet-cleaned, the second step is performed without the drying step. A step of vaporizing a film solution on the patterned semiconductor substrate; and heating at least one of a solvent and an unreacted solution of a film formed from the film solution by heating the substrate at a firing temperature A step of applying the above-mentioned film solution to the patterned features using a spin-on method, in which a step for performing heating, thermal annealing, ultraviolet (UV) curing, plasma curing, or Chemically reactive cured spin-on dielectric.

In addition, Non-Patent Document 1 below discloses a technique for oxidizing Si ₃ N ₄ which is difficult to oxidize by a common procedure under a H ₂ O supercritical condition at a low temperature of 400 ° C. to 500 ° C.

[Prior technical literature]

[Patent Literature]

Patent Document 1: Korean Published Patent Gazette No. 1999-0058163 (published on July 15, 1999).

Patent Document 2: Korean Published Patent Gazette No. 2016-0024351 (published on March 4, 2016).

Patent Document 3: Korean Granted Patent Gazette No. 10-1040154 (registered on June 02, 2011).

Patent Document 4: Korean Published Patent Gazette No. 2016-0019391 (published on February 19, 2016).

[Non-patent literature]

Non-Patent Document 1: Low-Temperature Oxidation of siliconnitride by water in supercritical condition, Journal of the European Ceramic Society, Vol. 16, no. 10, 1996, p. 1111.

However, in the prior art as described above, when a dielectric material is filled in a flash memory device based on a Macaroni Si channel, voids or seams are generated due to a high aspect ratio. )The problem.

That is, in the three-dimensional flash memory device of the prior art, a structure having a very large aspect ratio is formed. In a structure in which a dielectric filler is filled in a central portion of a silicon channel having a hollow structure, an oxide having a composition ratio that fully matches Filling is performed to ensure stable operating characteristics of the device.

The present invention has been made in order to solve the problems as described above, and an object of the present invention is to provide a low-temperature and high-pressure treatment of a dielectric filler of a three-dimensional flash memory device with a very large aspect ratio during charging of the dielectric filler. Manufacturing method of three-dimensional flash memory device without forming voids and seams.

Another object of the present invention is to provide a method for manufacturing a three-dimensional flash memory device that can maximize the device characteristics and reliability of the three-dimensional flash memory device.

To achieve the above object, the present invention provides a method for manufacturing a three-dimensional flash memory device for manufacturing a three-dimensional flash memory for filling a gap having a high aspect ratio as a void-free dielectric substance. The manufacturing method of a bulk device is characterized in that a dielectric filler for filling the above-mentioned dielectric is filled by a low-temperature and high-pressure heat treatment.

The present invention is also characterized in that, in the method for manufacturing a three-dimensional flash memory device of the present invention, the dielectric filler is an oxide film.

Furthermore, the present invention is characterized in that, in the method for manufacturing the three-dimensional flash memory device of the present invention, the low-temperature and high-pressure heat treatment is performed under a pressure condition of 1 to 20 and a temperature condition of 100 to 500 ° C.

Furthermore, the present invention is characterized in that, in the method for manufacturing a three-dimensional flash memory device of the present invention, the low-temperature and high-pressure heat treatment is performed for 30 minutes by using water (H ₂ O).

In addition, the present invention is characterized in that the method for manufacturing the three-dimensional flash memory device of the present invention includes the following steps: (a) step of laminating an interlayer insulating film and a sacrificial layer for controlling the gate on the substrate in a multilayer manner; Forming a molded structure; step (b) forming a gap by etching the molded structure; step (c), forming a gate insulating film on the inner wall of the interlayer insulating film and the sacrificial layer; step (d), in A channel is formed on the inner wall of the gate insulating film; in step (e), a dielectric filler is filled into the inside of the channel through a supercritical evaporation step or a high-pressure densification step; and in step (f), the sacrificial layer is removed.

In addition, the present invention is characterized in that, in the method for manufacturing a three-dimensional flash memory device of the present invention, the step (e) includes the step (e1), using a polysilazane solution to coat the inside of the channel with a spinner. Coating a glass insulating film; step (e2), in order to remove the solvent component of the insulating film, pre-firing at a predetermined temperature; and step (e3), performing a heat treatment as a wet heat treatment under a high pressure state.

Furthermore, the present invention is characterized in that, in the method for manufacturing a three-dimensional flash memory device of the present invention, the step (e2) is performed in a range of 50 to 350 ° C. for 20 minutes to 40 minutes.

As described above, according to the method for manufacturing a three-dimensional flash memory device of the present invention, by minimizing a void in a three-dimensional flash memory device having a hollow structure and a high aspect ratio, it has improved device characteristics and reliability Sexual effect.

In addition, the method for manufacturing a three-dimensional flash memory device according to the present invention has the effect of forming a dielectric filler of the three-dimensional flash memory device by performing a supercritical evaporation or high-pressure densification step by performing a low temperature and high pressure heat treatment.

In addition, according to the manufacturing method of the three-dimensional flash memory device of the present invention, when a shallow trench isolation step is adopted for a new device such as Ge or III-V, the oxide film with good quality is densified at a very low temperature. , Which has the effect of thermal budget.

10‧‧‧ semiconductor substrate

11‧‧‧bit line

12‧‧‧ cell string

13‧‧‧Lower selection gate

14‧‧‧ Upper selection grid

15‧‧‧Control gate

16‧‧‧channel

20‧‧‧Gate insulation film

21‧‧‧ insulator

100‧‧‧Flash memory device

200‧‧‧ sacrificial layer

300‧‧‧ Clearance

FIG. 1 is a perspective view showing a unit area of a NAND flash memory device as a three-dimensional flash memory device to which the present invention is applied.

FIG. 2 is a perspective view showing an example of a unit transistor constituting the unit region in FIG. 1.

FIG. 3 is a perspective view showing still another example of a unit transistor constituting the unit region in FIG. 1.

4 to 8 are cross-sectional views for explaining a process of sequentially forming a gate insulating film, a channel, and an insulator in a control gate.

FIG. 9 is a scanning electron microscope (SEM) image showing a cross section of an insulator formed according to an embodiment of the present invention.

The objects and novel features of the present invention as described above will be more clearly understood from the techniques and drawings in this specification.

The structure of the present invention will be described below with reference to the drawings.

FIG. 1 is a perspective view showing a unit region of a three-dimensional flash memory device and a non-type flash memory device suitable for the present invention. FIG. 2 is a diagram showing an example of a unit transistor constituting the unit region in FIG. 1. A perspective view. FIG. 3 is a perspective view showing another example of the unit transistor constituting the unit region in FIG. 1.

As a three-dimensional flash memory device adopted in the present invention, the vertical NAND-type flash memory device 100 includes: a unit area including a plurality of storage units; and a peripheral area including a storage unit Working peripheral circuits. That is, the vertical NAND flash memory device 100 includes a row control circuit, a page buffer circuit, a common source line control circuit, a memory cell array, and a column gate circuit. Such a vertical and non-type flash memory device has a gate-all-round (GAA) structure of a fully depleted channel. Therefore, program inhibition during program inhibition The characteristics are excellent.

In the following description, a storage cell array as a cell region is described, but it is not limited to this, and it can also be applied to the peripheral field as described above.

For example, the above-mentioned unit region includes: a plurality of control gates 15 formed in a plate shape, and vertically stacked along the Z direction on the semiconductor substrate 10 to form an XY plane; and a lower selection gate 13 provided below the plurality of control gates 15. A plurality of upper selection gates 14 provided on the upper side of the plurality of control gates 15; a plurality of bit lines 11 stacked on the upper side of the upper selection gate 14 and extending along the Y direction; and a plurality of channels in the The semiconductor substrate 10 extends vertically along the Z direction.

The plurality of channels 16 are formed so as to extend from the semiconductor substrate 10 to the bit line 11 and penetrate the upper selection gate 14, the lower selection gate 13, and the control gate 15. In addition, the semiconductor substrate 10 is a P-type silicon substrate, but is not limited to this. The channel 16 is made of the same or similar material as the semiconductor substrate 10 and may be of the same conductivity type. The semiconductor substrate 10 may include an N-type source.

As shown in FIG. 1, in the three-dimensional flash memory device suitable for the present invention, the channel 16 and the control gate 15 constitute a storage transistor, and the channel 16 and the lower selection gate 13 may constitute a lower selection transistor. The upper selection gate 14 may constitute an upper selection transistor.

As described above, as shown in FIG. 1, a vertical NAND flash memory device 100 suitable for the present invention is configured by connecting a plurality of storage transistors formed in one channel 16 with an upper transistor and a lower transistor in series. One cell string 12.

Moreover, in the structure shown in FIG. 1, one unit string 12 is composed of four storage transistors, but the number of storage transistors of one unit string 12 is not limited to this, and any number can be selected according to the storage capacity, for example 8, 16, 32, etc. Further, although the passage 16 is formed in a cylindrical shape in the structure shown in FIG. 1, it is not limited to this, and a quadrangular pillar shape may be adopted.

As described above, the storage transistor, the upper selection transistor, and the lower selection transistor are formed in the channel 16 as a depletion type transistor having no source and drain, but the storage transistor and the upper portion are not limited thereto. The selection transistor and the lower selection transistor may be composed of an enhancement transistor having a source and a drain in the channel 16.

The plurality of channels 16 pass through the plurality of control gates 15 in the Z direction. Therefore, the intersections between the plurality of control gates 15 and the plurality of channels 16 are three-dimensionally distributed. The storage transistors of the present invention are respectively formed at a plurality of intersection points of the three-dimensional distribution as described above.

As shown in FIG. 2, the storage transistor suitable for the vertical and non-type flash memory device 100 of the present invention may have a gate insulating film 20 having a charge storage film provided between the channel 16 and the control gate 15. The charge storage film may include an insulating film capable of floating charges. For example, the gate insulating film 20 is a so-called oxide-nitride-oxide (ONO) formed by stacking a silicon oxide film, a silicon nitride film (or a silicon oxide nitride film), and a silicon oxide film. In the case of a film), the charge can be floated and maintained by the silicon nitride film (or silicon oxide nitride film). The charge storage film may include a floating gate made of a conductive material.

Also, in the vertical and non-type flash memory device 100 applicable to the present invention, as shown in FIG. 3, the storage transistor may be formed in a so-called hollow form having an insulator 21 as a dielectric filler inside the channel 16. The insulator 21 is formed in a pillar shape so as to correspond to the shape of the channel 16. Since the insulator 21 occupies the inside of the channel 16, the channel 16 may have a thinner thickness than the structure in FIG. 2, which may reduce the floating gate of the carrier.

Moreover, in FIG. 1, the upper selection transistor 14 and the lower selection transistor 13 may have the same or similar structures as those shown in FIG. 2 or 3. The gate insulating film 20 of the upper selection transistor and the lower selection transistor may be made of a silicon oxide film or a silicon nitride film.

Next, a method of filling the gap 300 provided in the channel 16 with a void-free dielectric during the formation of the insulator 21 in the three-dimensional flash memory device having a high aspect ratio according to the present invention will be described with reference to FIGS. 4 to 9.

4 to 8 are cross-sectional views for explaining a process of sequentially forming a gate insulating film, a channel, and an insulator in a control gate, and FIG. 9 is a scanning electron showing a cross-section of an insulator formed according to an embodiment of the present invention. Microscope image.

In addition, in the following description, a three-dimensional flash memory device having a hollow structure as shown in FIG. 3 is taken as an example for description, but it is not limited to this, and can also be applied to the structure shown in FIG. 2. In addition, for convenience of explanation, a description is given of a string structure in which the control gate 15 is stacked on the semiconductor substrate 10, but the present invention is not limited to this, and is applicable to the case where the lower selection gate 13 and the lower selection gate 13 are provided on the semiconductor substrate 10 as shown in FIG. The structure of the upper selection gate 14.

First, as shown in FIG. 4, an interlayer insulating film for controlling the gate 15 and a sacrificial layer 200 are laminated on the semiconductor substrate 10 to form a molded structure. The semiconductor substrate 10 may be a semiconductor substance, for example, it may be a silicon single crystal substrate, a germanium single crystal substrate, a silicon-germanium single crystal substrate, or a semiconductor on insulator (SOI) substrate. For example, the semiconductor substrate 10 may include a semiconductor layer (for example, a silicon layer, a silicon-germanium layer, or a germanium layer) disposed on an insulating layer for protecting a plurality of transistors on the semiconductor substrate.

The sacrificial layer 200 is a substance having an etching selectivity with respect to the interlayer insulating film. Preferably, the sacrificial layer 200 has a higher etching selection ratio in a wet etching step using a chemical solution than the interlayer insulating film. For example, the interlayer insulating film may be a silicon oxide film or a silicon nitride film, and the sacrificial layer 200 may be selected from a silicon oxide film, a silicon nitride film, silicon carbide, silicon, and silicon germanium, and may have an etching selection ratio with respect to the interlayer insulating film. The substance. For example, the interlayer insulating film may be made of metal nitride, and the sacrificial layer 200 may be made of silicon oxide. Such an interlayer insulating film and the sacrificial layer 200 can be formed by using thermal chemical vapor deposition (Thermal CVD), plasma enhanced chemical vapor deposition (Plasma enhanced CVD), or atomic layer deposition (ALD) technology.

In addition, for convenience of explanation, the structure for four control gates 15 is shown in FIG. 4, but it is not limited to this, and it can also be applied to a string structure including eight, twelve, and the like.

Next, as shown in FIG. 5, the molded structure is etched to form a gap 300 having a substantially cylindrical shape. The gap 300 forms a mask pattern on the molded structure, and uses the mask pattern as an etching mask to form the molded structure by anisotropic etching. The gap 300 can increase the aspect ratio according to the increase in the capacity of the three-dimensional flash memory device, for example, it can be increased to 50 or more.

Next, as shown in FIGS. 3 and 6, a gate insulating film 20 is formed inside the control gate 15 and the sacrificial layer 200 as an interlayer insulating film. Such a gate insulating film 20 may include a charge storage film that can float the charge from the channel. For example, in the case where the flash memory is a metal oxide nitride semiconductor type or a silicon nitride semiconductor type, the charge may be made of silicon nitrogen. The film (or silicon nitride oxide film) floats and is maintained. In addition, the gate insulating film 20 may include a blocking insulating film, a charge storage film, and a tunnel insulating film. For example, the blocking insulating film, the charge storage film, and the tunnel insulating film are sequentially formed from the control gate 15 and the inner walls of the sacrificial layer 200.

Next, as shown in FIG. 7, a channel 16 is formed on the inner wall of the gate insulating film 20. The above-mentioned channel 16 can be formed of Poly-Si which can easily control the sub-critical characteristics.

Next, as shown in FIG. 8, a dielectric filler is filled into the inside of the channel 16 in a supercritical vapor deposition or high-pressure densification step, a channel (not shown) is formed in the molded structure, and the exposed sacrificial layer is removed in the channel. 200. By forming an opening region between the interlayer insulating films for the control gate 15, a plurality of control gates 15 are arranged by the channel 16 to be spaced apart, thereby forming a structure as shown in FIG. In terms of removing the sacrificial layer 200, for example, the sacrificial layer 200 is a silicon nitride film, and when the interlayer insulating film is a silicon oxide film, an etching solution containing phosphoric acid is used to uniformly etch the sacrificial layer 200, thereby Open areas can be formed.

Next, the process of filling the via 16 with the insulator 21 as a dielectric filler while preventing the generation of voids or joints will be described.

A hole having an aspect ratio of 50 or more is provided in the channel 16.

A spin-on-glass (SOG) insulating film is coated on the surface of the uppermost control gate 15 provided on the semiconductor substrate 10 with a polysilazane solution. That is, in order to form the insulator 21 by filling a dielectric filler with holes having a high aspect ratio, for example, the polysilazane solution is spin-coated at 1500 rpm for 30 seconds in an air atmosphere, thereby filling. In the above description, the spin coating method was described as being performed at a speed of 1500 rpm for 30 seconds, but it is not limited to this, and can be changed according to the value of the aspect ratio. The polysilazane is a substance that can be expressed as-(SixNyHz)-, and uses a solvent that can be dissolved in xylene or dibutyl ether (dibuthyl ether) to have a solution having a predetermined weight ratio. In addition, high-density plasma chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), and liquid-phase chemical vapor deposition ( LPCVD) and the like to form an Al ₂ O ₃ buffer layer.

Thereafter, in order to remove the solvent component of the insulator 21, pre-firing is performed in a temperature range of 50 ° C to 350 ° C. In the pre-baking, the substrate is heated at the same temperature or stepwise from the normal temperature on the base of the heating equipment, and the substrate is heated in a range of 50 to 350 ° C. for a predetermined time (for example, 30 minutes). Through this process, most of the solvent components will be removed. The above-mentioned temperature and time can be adjusted according to the formation conditions of the three-dimensional flash memory device.

After that, the insulator 21 is heat-treated. In the present invention, the heat treatment is performed as a wet heat treatment in a low temperature and high pressure state.

That is, after the pre-baking, a low-pressure wet heat treatment is performed under a pressure of 1 to 20 and a temperature of 100 to 500 ° C. For example, an amount sufficient to react with spin-coated polysilazane (for example, 20 ml) of water to perform a low-pressure wet heat treatment for 30 minutes.

In the heat treatment process as described above, the spin-coated polysilazane reacts with H ₂ O to generate the SiO ₂ insulator 21.

FIG. 9 shows a state in which the insulator 21 as a dielectric filler is filled in the channel 16 as a result of performing the heat treatment as described above.

FIG. 9 is a scanning electron microscope image showing a cross section of the insulator 21 formed under the 10-pressure condition as in the example of the present invention, and it can be seen that the gaps and joints are not uniform in the upper and lower portions.地 fill the insulator 21. This is because, by the high-pressure heat treatment, water and polysilazane can be sufficiently reacted even in the deep part of the channel 16.

As described above, according to the present invention, the dielectric of a three-dimensional flash memory device having a very large aspect ratio is formed in a supercritical vapor deposition or high-pressure densification step by using a high-pressure supercritical-based oxide composition ratio optimization technique. Quality fillers to minimize voids and seams.

The invention made by the present inventors has been specifically described based on the above embodiments, but the invention is not limited to the above embodiments, and various changes can be made without departing from the gist of the invention.

[Industrial availability]

By using the manufacturing method of the three-dimensional flash memory device of the present invention, the voids can be minimized in the three-dimensional flash memory device, so that the characteristics and reliability of the device can be improved.

Claims (7)

    A method for manufacturing a three-dimensional flash memory device, for manufacturing a three-dimensional flash memory device that fills a gap with a high aspect ratio as a void-free dielectric, wherein a dielectric filler for filling the foregoing dielectric is used. Filling is performed by low-temperature and high-pressure heat treatment.         The method for manufacturing a three-dimensional flash memory device according to claim 1, wherein the dielectric filler is an oxide film.         The method for manufacturing a three-dimensional flash memory device according to claim 1, wherein the low-temperature and high-pressure heat treatment is performed under a condition of 1 to 20 atmospheres and a temperature condition of 100 to 500 ° C.         The method for manufacturing a three-dimensional flash memory device according to claim 3, wherein the low-temperature and high-pressure heat treatment is performed for 30 minutes by using water.         The method for manufacturing a three-dimensional flash memory device according to claim 1, including the following steps: step (a), by laminating an interlayer insulating film and a sacrificial layer for controlling the gate in a multilayer manner on a substrate Forming a molded structure; step (b) forming a gap by etching the molded structure; step (c), forming a gate insulating film on the inner wall of the interlayer insulating film and the sacrificial layer; step (d), in A channel is formed on the inner wall of the gate insulating film; step (e) fills the inside of the channel with a dielectric filler through a supercritical evaporation step or a high-pressure densification step; and step (f) removes the sacrificial layer.         The method for manufacturing a three-dimensional flash memory device according to claim 5, wherein the aforementioned step (e) includes the following steps: Step (e1), using a polysilazane solution to apply spin-coated glass inside the aforementioned channel An insulating film; step (e2), in order to remove a solvent component of the insulating film, pre-baking at a predetermined temperature; and step (e3), performing a heat treatment as a wet heat treatment under a high pressure state.         The method for manufacturing a three-dimensional flash memory device according to claim 6, wherein the step (e2) is performed in a range of 50 ° C to 350 ° C for 20 minutes to 40 minutes.