TW201837989A - Method and manufacturing equipment for epitaxial wafer - Google Patents

Abstract

According to an embodiment, a method for fabricating an epitaxial wafer by forming an epitaxial layer on a wafer mounted on a susceptor includes pre-determining an epitaxial process condition of the epitaxial layer for each thickness pattern of the wafer, an epitaxial layer A configuration-matched thickness profile capable of compensating for a total thickness variation of the wafer, determining a thickness pattern of the wafer using a first thickness variation in a central region of the wafer loaded on the susceptor and a second thickness variation in the edge region And forming a epitaxial layer on the wafer under the epitaxial process conditions corresponding to the determined thickness pattern in the predetermined epitaxial process conditions. These epitaxial process conditions include at least one of a supply amount of the carrier gas, a supply amount of the source gas, an opening/closing degree of the gas supply valve, a rotation speed of the susceptor, or a height of the susceptor.

Description

Method and manufacturing equipment for epitaxial wafer

The present invention relates to a method and apparatus for manufacturing an epitaxial wafer.

Generally, germanium wafers are used as materials for fabricating semiconductor devices and are manufactured in the form of polished wafers through various processes. These processes include a slicing process, a lapping process, an etching process, and a polishing process. In the cutting process, the single crystal block is cut into a wafer shape. In the polishing process, the flatness of the wafer is improved and ground to a desired thickness. The etch process is used to remove damaged layers within the wafer. The polishing process is used to polish the surface of the wafer to a mirrored surface and to improve the flatness of the wafer. In addition, the germanium wafer is fabricated in the form of an annealed wafer by additionally performing heat treatment to adjust its defect density, or is fabricated in the form of an epitaxial wafer to be more suitable for formation of a semiconductor device.

According to a general manufacturing method for a germanium epitaxial wafer, a germanium-polished wafer (not shown) as a substrate is loaded onto a susceptor (not shown), and a gas such as a source gas and a doping gas is supplied to the polishing. Wafer. Through the heater (not shown) of the epitaxial wafer fabrication equipment, the gas is decomposed and thus reactive, thereby depositing a germanium epitaxial layer (not shown) on the polished wafer, thereby fabricating germanium epitaxial Wafer.

Through this manufacturing method, a germanium epitaxial layer having a specific film thickness or resistivity is formed on the tantalum polished wafer. Therefore, germanium epitaxial wafers are used to fabricate high performance semiconductor devices. Typically, such germanium epitaxial wafers comprise a germanium epitaxial layer having a thickness ranging from a few micrometers (μm) to tens of micrometers.

Meanwhile, in the manufacturing process of the semiconductor device, the geometry of the wafer such as its shape, thickness, flatness, and the like has a great influence on the yield of the semiconductor wafer. Therefore, the geometry of the wafer must be strictly maintained. In particular, with the development of highly integrated semiconductor devices, the geometry of wafers has become extremely important in semiconductor device fabrication processes. That is, as the line width of the recently developed semiconductor device is reduced and the degree of integration is increased, the flatness of the wafer greatly affects the productivity and yield of the semiconductor manufacturing process. In particular, high flatness wafers are required to alleviate problems such as focusing on the exposure apparatus in the lithography process. As the line width of the circuit becomes finer, line distortion caused by flatness defects of the wafer in the semiconductor manufacturing process further deteriorates the yield of the device. Therefore, there is a need to develop high quality epitaxial wafers with excellent flatness.

However, according to the general manufacturing method of enamel polishing wafer, since the epitaxial layer is deposited on the polished wafer having poor flatness after the polishing process is completed, the epitaxial wafer also has poor flatness, and thus needs to be improved. .

The embodiment of the present invention provides a method and a manufacturing apparatus for an epitaxial wafer having improved flatness.

According to one embodiment, a method of fabricating an epitaxial wafer that forms an epitaxial layer on a wafer mounted on a susceptor comprises (a) pre-determining a plurality of epitaxial layers of the epitaxial layer for each thickness pattern of the wafer The process conditions, the epitaxial layer has a configuration matching thickness profile capable of compensating for the total thickness variation of the wafer, and (b) the first thickness variation in the central region of the wafer loaded on the susceptor and the edge region a thickness variation, determining a thickness pattern of the wafer, and (c) forming an epitaxial layer on the wafer under the epitaxial process conditions corresponding to the determined thickness pattern in the predetermined epitaxial process conditions, wherein The epitaxial process conditions include at least one of a supply amount of the carrier gas, a supply amount of the source gas, an opening/closing degree of the gas supply valve, a rotation speed of the susceptor, or a height of the susceptor.

For example, the supply amount of the carrier gas includes at least one of a first supply amount of carrier gas to be supplied to a region above the wafer or a second supply amount of carrier gas to be supplied to a region below the wafer.

For example, the central area of the wafer is defined as the area from the center of the wafer to the first point, and the edge area of the wafer is defined as the area from the second point to the third point of the wafer, and the second The point is located further or the same distance from the center than the position of the first point, and the third point is located further from the center than the position of the second point.

For example, the first point is located 80 mm to 100 mm from the center, the second point is located 80 mm to 100 mm from the center, and the third point is located 140 mm to 148 mm from the center.

For example, the value of the first thickness variation is obtained by subtracting the second thickness of the first point from the first thickness of the center, and the second thickness is obtained by subtracting the fourth thickness of the third point from the third thickness of the second point. The value of the thickness variation.

For example, step (b) includes obtaining a first thickness variation and a second thickness variation, and comparing the first thickness variation with the first reference thickness value to obtain a first comparison value by comparing the second thickness variation with the second reference thickness The value, the second comparison value is obtained, and the thickness pattern of the wafer is determined using the first comparison value and the second comparison value.

For example, the first reference thickness value is 15 nanometers or 30 nanometers, and the second reference thickness value is zero.

For example, in the step (a), the relative supply ratio of the supply amount of the carrier gas, the supply amount of the source gas, the opening/closing degree of the air supply valve, the rotation speed of the susceptor, and the height of the susceptor is set to be for the wafer. The thickness pattern corresponds to one of the epitaxial process conditions.

For example, the wafer is a double-sided polished wafer.

According to another embodiment, a manufacturing apparatus for forming an epitaxial wafer by forming an epitaxial layer on a wafer includes a gas supply unit for supplying a carrier gas and a source gas, supporting a susceptor of the wafer loaded thereon, and supporting the pedestal The driving shaft, the driving unit for adjusting the upward/downward movement and the rotating speed of the driving shaft, supplying the carrier gas and the source gas from the air supply unit to the air supply valve of the wafer, and storing a plurality of epitaxial processes of the epitaxial layer a storage unit for a condition, the thickness layer of the epitaxial layer matching the configuration capable of compensating for the total thickness variation of the wafer for each thickness pattern of the wafer, and the pattern thickness pattern determining unit for determining the thickness of the wafer loaded on the susceptor And a controller for reading an epitaxial process condition corresponding to the thickness pattern determined by the thickness pattern determining unit from the storage unit, and controlling at least one of the air supply unit, the air supply valve or the driving unit to respond to the read epitaxial Process conditions for adjusting the supply of carrier gas, the supply of source gas, the opening/closing degree of the gas supply valve, the rotational speed of the susceptor, or the height of the pedestal, at least .

For example, the controller controls the gas supply amount of the doping gas as the epitaxial process condition.

According to the method and apparatus for manufacturing an epitaxial wafer according to an embodiment, even when the wafer exhibits a total thickness variation, an epitaxial layer is formed on the wafer by a combination of factors for adjusting the conditions of the epitaxial process, and the total wafer can be compensated. A thickness profile with varying thicknesses enables the fabrication of epitaxial wafers with improved GBIR and improved SBIR and thus increased throughput.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail in conjunction with the drawings. However, the disclosure is embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and will be

Hereinafter, a method of manufacturing an epitaxial wafer 100 and a manufacturing apparatus 200 of an embodiment will be described with reference to the accompanying drawings. For convenience of description, the epitaxial wafer fabrication apparatus 200 will be described using a Cartesian coordinate system (x-axis, y-axis, z-axis). However, the disclosure is not limited thereto. That is, other different coordinate systems can be used.

1 is a flow chart for explaining an epitaxial wafer fabrication method 100 of an embodiment.

2 is a schematic cross-sectional view of the epitaxial wafer fabrication apparatus 200 of the embodiment, and FIG. 3 is a plan view of the supply valve 240A of the embodiment of the air supply valve 240 shown in FIG. 2.

For a better understanding of the disclosure, the epitaxial wafer fabrication apparatus 100 illustrated in FIG. 1 will be described using the epitaxial wafer fabrication apparatus 200 illustrated in FIG. 2; however, the disclosure is not limited thereto. That is, the epitaxial wafer fabrication method 100 shown in FIG. 1 can be completed using an epitaxial wafer fabrication apparatus having a different configuration than the epitaxial wafer fabrication apparatus 200 shown in FIG. 2.

Before describing the epitaxial wafer fabrication method 100 shown in FIG. 1, the epitaxial wafer fabrication apparatus 200 shown in FIG. 2 will be briefly described below.

The epitaxial wafer fabrication apparatus 200 shown in FIG. 2 includes a chamber 210, an upper chamber frame 212, a lower chamber frame 214, a gas supply unit 230, a gas supply valve 240, a drive unit 260, a storage unit 270, and a controller 280. And a thickness pattern determining unit 290.

The chamber 210 serves as a space for completing the heat treatment, thereby forming a layer such as an epi-layer on the surface of the wafer W, and may be formed of quartz glass. For example, the wafer W is a polished wafer; however, the disclosure is not limited thereto. The chamber 210 includes an upper chamber frame 212 and a lower chamber frame 214, and an intake port IN1 and an outlet port OUT are placed between the upper chamber frame 212 and the lower chamber frame 214. The carrier gas and the source gas (or the material gas or the reaction gas) are required to grow the epitaxial layer E on the wafer W in the chamber 210, and the carrier gas and the source gas (or the source gas or the reaction gas) pass through the intake port 埠IN1. It is introduced into the chamber 210 to form an epitaxial layer E on the wafer W. After the epitaxial layer E is formed, the gas for the reaction is discharged through the gas enthalpy OUT. Therefore, the intake port IN1 and the outlet port OUT are formed opposite to each other, and the laminar flow of the source gas introduced through the intake port IN1 is induced along the surface of the wafer W.

The chamber 210 includes a base 220, a lift arm 250, a support unit 252, a driving shaft (or support shaft) 254, and a support pin 256.

Through the carrier unit (not shown), the wafers W are introduced into or removed from the chamber 210 in a single wafer process, that is, one by one; however, the present disclosure is not limited to the wafer W that is transferred once. Number.

While the epitaxial layer is formed on the wafer W (or substrate), the susceptor 220 is used to provide a space on which the wafer W is loaded and to support the wafer W. The susceptor 220 is formed of a graphite material covering a silicon carbide, and has a planar disk shape. Further, the base 220 has a variety of cross-sectional shapes. After the wafer W is loaded onto the susceptor 220, the wafer W undergoes rapid heat treatment or the epitaxial layer E is grown on the main surface of the wafer W.

The support unit 252 is used to support the base 220. The material of the supporting unit 252 may be quartz, tantalum, tantalum carbide, or quartz coated with tantalum or tantalum carbide.

The lift arm 250 is placed between the drive shaft 254 and the support pin 256 and extends radially from the drive shaft 254 to connect the support pins 256. The lift arm 250 is used to move the support pin 256 up or down when the drive shaft 254 completes the upward/downward movement.

The support pin 256 extends perpendicularly from the distal end of the lift arm 250, penetrates the base 220, and connects the lift arm 250 to move up or down as the lift arm 250 moves up/down. Therefore, the susceptor 220 has a through hole (not shown) therein, and the support pin 256 is inserted through the through hole.

The drive shaft 254 connects the support unit 252 to support the base 220, and connects the lift arm 250 to support the support pin 256. The drive shaft 254 performs a rotational motion or an upward/downward motion through the drive unit 260. That is, the upward/downward movement or the rotational movement of the drive shaft 254 is determined by the drive unit 260. When the driving shaft 254 is rotated by the driving unit 260, the susceptor 220 rotates together with the supporting unit 252, thereby rotating the wafer W. For example, when the epitaxial layer E is formed on the wafer W, the wafer W can be rotated at a high speed, so that the thickness of the epitaxial layer E becomes uniform.

Further, the driving unit 260 is used to move the support pin 256 upward or downward by the lift arm 250, and to move the base 220 up or down by the support unit 252. The driving unit 260 can adjust at least one of the upward/downward movement or the rotational movement of the driving shaft 254 in response to the third control signal C3 generated by the controller 280. For example, when the drive shaft 254 is moved up or down by the drive unit 260, the height of the base 220 may rise or fall.

The gas supply unit 230 is for supplying a carrier gas, a source gas, and a doping gas to the gas supply valve 240. At this time, in response to the first control signal C1 generated by the controller 280, the air supply unit 230 adjusts each of the amount of the carrier gas supplied to the air supply valve 240, the amount of the source gas, and the amount of the doping gas.

An air supply valve 240 (accuset) (or an automatic metering valve (AMV)) for injecting a carrier gas, a source gas and a doping gas, a carrier gas, a source gas, and a doping gas from the air supply unit 230 through the intake air埠IN1 is supplied into the chamber 210 such that these gases are supplied to the wafer W. At this time, the degree of opening/closing of the air supply valve 240 can be adjusted in response to the second control signal C2 generated by the controller 280.

Referring to FIG. 3, the air supply valve 240A includes a central nozzle and a peripheral nozzle. The central nozzle ejects in the direction of the central portion IN2 of the wafer W, and the peripheral nozzles eject in the direction of the edge portions OUT1 and OUT2 of the wafer W. A nozzle having such a configuration is also referred to as a multiport injector (MPI).

The manufacturing process of the epitaxial wafer using the epitaxial wafer fabrication apparatus 200 of the above configuration will now be briefly described.

After the wafer W is loaded onto the susceptor 220, the wafer W is maintained at a temperature range, for example, from 1100 ° C to 1200 ° C, and heated in a hydrogen atmosphere for about 10 minutes to remove carbon-based impurities or Natural oxide layer.

Next, source gas such as silane-trichlorophenyl SiHCl ₃ (Trichlorosilane; TCS) or dichloro Silane SiH ₂ Cl _2, and a carrier gas such as hydrogen gas H ₂ (hydrogen) is supplied to the chamber 210. When depositing the epitaxial layer E, in order to impart conductivity to the epitaxial layer E, a doping gas such as diborane (B ₂ H ₆ ) or phosphine (PH ₃ ) is supplied to the chamber together with the carrier gas and the source gas. 210.

The carrier gas, source gas, and dopant gas are supplied into the chamber 210 in the direction of arrow 310. In addition, the carrier gas is also supplied in the direction of arrow 320. Through the heaters (not shown) of the epitaxial wafer fabrication apparatus 200, these gases are decomposed and thereby reactive, thereby depositing an epitaxial layer E on the wafer W, thus fabricating an epitaxial wafer EP.

The epitaxial wafer fabrication method 100 of the embodiment will now be described in conjunction with FIGS. 1 through 3.

For each different thickness pattern of the wafer W, the epitaxial process conditions of the epitaxial layer E are predetermined, and the epitaxial layer E has a thickness profile matched with a configuration capable of compensating for the total thickness variation of the wafer W ( Step 110). For example, various different epitaxial process conditions for a predetermined epitaxial layer for each thickness pattern of the wafer W are stored in the memory cell 270.

In the epitaxial wafer fabrication method 100 shown in FIG. 1, the process of etching and double-side polishing (DSP) is performed by cutting a predetermined block into a wafer-shaped process, and the diced wafer is subjected to a process of polishing and double-side polishing (DSP). The process and the polishing process prepare the wafer W on which the epitaxial layer E is to be formed. Next, the wafer W is subjected to final polishing (FP) using an alkaline aqueous solution such as a mixed liquid of ammonia and hydrogen peroxide and/or an acidic aqueous solution such as hydrofluoric acid ( The fluoric acid is washed and then loaded onto the susceptor 220.

Further, the wafer W may be a germanium wafer and, for example, have a diameter of 300 mm; however, the present disclosure is not limited to such material or diameter of the wafer W.

4A to 4C are schematic views for explaining the principle of the epitaxial layer E compensating for the thickness variation of the wafer W. In each of the figures, the horizontal axis represents the position in the y-axis direction (ie, the radial direction of the wafer W), and the vertical axis represents the position in the z-axis direction (for example, the normalized THK of the wafer) .

In particular, FIG. 4A shows a thickness profile of the wafer W, FIG. 4B shows a thickness profile of the epitaxial layer E capable of compensating for variations in the thickness of the wafer W, and FIG. 4C shows a variation in thickness of the wafer W by the epitaxial layer E. The thickness profile of the compensated epitaxial wafer EW.

For example, as representatively shown in FIG. 4A, it is assumed that the central area CA of the wafer W is formed into a plane, so there is no thickness variation, but the edge area EA of the wafer W is formed to be curved upward, and thus has a thickness variation. In this case, when the epitaxial layer E having the thickness profile shown in FIG. 4B is formed on the wafer W, as shown in FIG. 4C, the wafer W on which the epitaxial layer E is formed (referred to as epitaxial crystal) The change in the total thickness of the wafer EW) is eliminated. This is because the epitaxial layer E compensates for variations in the total thickness of the wafer W. For example, the epitaxial layer E shown in FIG. 4B is implemented in accordance with the epitaxial process conditions.

As described above, the epitaxial layer E has a thickness profile that matches the configuration of the thickness variation of the wafer W, and the epitaxial process conditions for forming the epitaxial layer E include the supply amount of the carrier gas and the supply of the source gas. The amount, the opening/closing degree of the air supply valves 240 and 240A, the rotational speed of the base 220, or the height of the base 220 are at least one. Here, since the wafer W rotates while the susceptor 220 rotates, the rotational speed of the susceptor 220 is also regarded as the rotational speed of the wafer W.

The supply amount of the carrier gas includes at least one of the first supply amount or the second supply amount. For example, the first supply amount refers to the amount of carrier gas supplied to the region above the wafer W as indicated by an arrow 310 in FIG. Further, for example, the second supply amount refers to the amount of carrier gas supplied to the region below the wafer W as indicated by an arrow 320 in FIG.

In addition, the epitaxial process conditions further include the supply amount of the doping gas; however, the disclosure is not limited thereto. The dopant gas is supplied into the chamber 210 along with the source gas, as indicated by arrow 310 of FIG.

Further, according to the embodiment, each of the different epitaxial processing conditions predetermined for each thickness pattern of the wafer W refers to the supply amount of the carrier gas, the supply amount of the source gas, the opening/closing degree of the air supply valves 240 and 240A, and the base. The relative speed of the rotational speed of the seat 220 and the height of the base 220. Representative epitaxial process conditions are explained below in conjunction with Table 1.

Referring again to FIG. 1, after step 110, the first thickness variation ΔT1 in the central region CA of the wafer W loaded on the susceptor and the second thickness variation ΔT2 in the edge region EA of the wafer W are determined to be determined. A thickness pattern of the wafer W forming the epitaxial layer E is formed (step 120). For example, step 120 is completed by the thickness pattern determining unit 290 shown in FIG. That is, the thickness pattern determining unit 290 determines the thickness pattern of the wafer W loaded on the susceptor 220, and outputs the determined thickness pattern to the controller 280.

FIG. 5 is a flow chart for explaining an embodiment 120A of step 120 shown in FIG. 1.

Figure 6 shows the cross-sectional shape of the wafer W to explain the central area CA and the edge area EA of the wafer W.

Before describing step 120A shown in FIG. 5, the central area CA and the edge area EA of the wafer W will now be described in conjunction with FIG.

The central area CA of the wafer W is defined as an area from the center P0 of the wafer W to the first point ± P1. In addition, the edge region EA of the wafer W is defined as a region from the second point ±P2 to the third point ±P3 of the wafer W. The second point ±P2 is located farther from the center P0 than the first point ±P1, or at the same position as the first point ±P1. The third point ± P3 is located farther from the center P0 than the second point ± P2.

If the wafer W is a double-sided polished wafer having a diameter of 300 mm, the first point P1 is located at a distance of P080 mm to 100 mm, for example, 90 mm from the center, and the second point P2 is located at a distance of P080 mm to 100 mm from the center, for example, 100 The position of the millimeter, and the third point P3 are located at a distance from the center P0140 mm to 148 mm, for example 144 mm; however, the disclosure is not limited thereto.

Further, the value obtained by subtracting the second thickness T2 at the first point P1 from the first thickness T1 of the center P0 is the first thickness variation ΔT1, and subtracting the third point P3 from the third thickness T3 at the second point P2. The value obtained by the fourth thickness T4 is the second thickness variation ΔT2; however, the disclosure is not limited thereto.

Referring to FIG. 5, after step 110, the first thickness variation ΔT1 and the second thickness variation ΔT2 of the wafer W loaded on the susceptor 220 are obtained (step 121).

After the step 121, the first comparison value is obtained by comparing the first thickness variation ΔT1 with the first reference thickness value RT1, the second comparison value is obtained by comparing the second thickness variation ΔT2 with the second reference thickness value RT2, and the first comparison value is used. The thickness pattern of the wafer W is determined in comparison with the second comparison value (steps 122 to 128).

For example, it is determined whether the first thickness variation ΔT1 is smaller than the first reference thickness value RT1 (step 122). Based on the determination that the first thickness variation ΔT1 is smaller than the first reference thickness value RT1, it is determined whether the second thickness variation ΔT2 is greater than the second reference thickness value RT2 (step 123). However, based on the determination result that the first thickness variation ΔT1 is not smaller than the first reference thickness value RT1, it is determined whether the second thickness variation ΔT2 is greater than the second reference thickness value RT2 (step 124). For example, the first reference thickness value RT1 is 15 nm or 30 nm, and the second reference thickness value RT2 is 0; however, the disclosure is not limited thereto.

The thickness pattern of the wafer W loaded on the susceptor 220 is determined as the first pattern TP1 according to the determination that the first thickness variation ΔT1 is smaller than the first reference thickness value RT1 and the second thickness variation ΔT2 is greater than the second reference thickness value RT2 (step 125).

Further, the thickness pattern of the wafer W loaded on the susceptor 220 is determined to be the second pattern according to the determination that the first thickness variation ΔT1 is smaller than the first reference thickness value RT1 and the second thickness variation ΔT2 is not greater than the second reference thickness value RT2. TP2 (step 126).

Further, the thickness pattern of the wafer W loaded on the susceptor 220 is determined to be the third pattern according to the determination that the first thickness variation ΔT1 is not less than the first reference thickness value RT1 and the second thickness variation ΔT2 is greater than the second reference thickness value RT2. TP3 (step 127).

Further, the thickness pattern of the wafer W loaded on the susceptor 220 is determined to be fourth according to the determination that the first thickness variation ΔT1 is not less than the first reference thickness value RT1 and the second thickness variation ΔT2 is not greater than the second reference thickness value RT2. Pattern TP4 (step 128).

In FIG. 5, when the first thickness variation ΔT1 is equal to the first reference thickness value RT1, the routine proceeds to step 124; however, the present disclosure is not limited thereto. That is, according to another embodiment, when it is determined in step 122 that the first thickness variation ΔT1 is equal to the first reference thickness value RT1, the program may move to step 123 instead of step 124.

Similarly to the above, when it is determined in step 123 that the second thickness variation ΔT2 is equal to the second reference thickness value RT2, the routine proceeds to step 126; however, the present disclosure is not limited thereto. That is, according to another embodiment, when it is determined in step 123 that the second thickness variation ΔT2 is equal to the second reference thickness value RT2, the program may proceed to step 125 instead of step 126.

Further, when it is determined in step 124 that the second thickness variation ΔT2 is equal to the second reference thickness value RT2, the routine proceeds to step 128; however, the present disclosure is not limited thereto. That is, according to another embodiment, when it is determined in step 124 that the second thickness variation ΔT2 is equal to the second reference thickness value RT2, the program may move to step 127 instead of step 128.

The step 120A shown in Fig. 5 is completed by the thickness pattern determining unit 290 shown in Fig. 3.

After step 120 or step 120A, an epitaxial layer is formed on the wafer W under the epitaxial process conditions corresponding to the thickness pattern determined in step 120 or step 120A in a predetermined epitaxial process condition (step 130).

In order to complete step 130, the controller 280 reads the epitaxial process conditions corresponding to the thickness pattern of the wafer W determined by the thickness pattern determining unit 290 from the storage unit 270, and generates the first to third control signals C1 to C3 in response to the reading. The epitaxial process conditions are taken to control the gas supply unit 230, the gas supply valve 240, and the drive unit 260. That is, the controller 280 generates the first control signal C1 to control the air supply unit 230, thereby adjusting the supply amount of the carrier gas, the supply amount of the source gas, and the supply amount of the doping gas. Further, the controller 280 controls the second control signal C2 to adjust the opening/closing degree of the air supply valve 240. In addition, the controller 280 generates a third control signal C3 to control the upward/downward movement and the rotation speed of the driving shaft 254 through the driving unit 260, thereby adjusting the rotation speed of the base 220 or the height of the base 220.

Hereinafter, in order to better understand the epitaxial wafer fabrication method 100 and the epitaxial wafer fabrication apparatus 200 of the above embodiments, the epitaxial process conditions changed according to the thickness pattern of the wafer W will be described with reference to the accompanying drawings. An example in which the epitaxial layer E is formed on the wafer W. This example of forming the epitaxial layer E on the wafer W is completed based on the assumption that the first point P1, the second point P2, and the third point P3 are 90 mm, 90 mm, and 148 mm from the center, respectively, and the first reference thickness value The RT1 is 15 nm or 30 nm, and the second reference thickness value RT2 is 0 nm.

7A to 7D are diagrams showing first to fourth patterns TP1 to TP4 of the wafer when the first reference thickness value RT1 is 15 nm. In each of the figures, the horizontal axis represents the radial position of the wafer W, and the vertical axis represents the thickness of the wafer W.

As shown in FIG. 7A, when the first thickness variation ΔT1 is less than the first reference thickness value RT1 of 15 nm, and the second thickness variation ΔT2 is greater than the second reference thickness value RT2 of 0 nm, the crystal loaded on the susceptor 220 The thickness pattern of the circle W is determined as the first pattern TP1.

Alternatively, as shown in FIG. 7B, when the first thickness variation ΔT1 is less than the first reference thickness value RT1 of 15 nm, and the second thickness variation ΔT2 is not greater than the second reference thickness value RT2 of 0 nm, the susceptor 220 is The thickness pattern of the loaded wafer W is determined as the second pattern TP2.

Alternatively, as shown in FIG. 7C, when the first thickness variation ΔT1 is not less than the first reference thickness value RT1 of 15 nm, and the second thickness variation ΔT2 is greater than the second reference thickness value RT2 of 0 nm, the susceptor 220 is The thickness pattern of the loaded wafer W is determined as the third pattern TP3.

Alternatively, as shown in FIG. 7D, when the first thickness variation ΔT1 is not less than the first reference thickness value RT1 of 15 nm, and the second thickness variation ΔT2 is not greater than the second reference thickness value RT2 of 0 nm, the susceptor 220 The thickness pattern of the wafer W loaded thereon is determined as the fourth pattern TP4.

8A to 8D are diagrams showing first to fourth patterns TP1 to TP4 of the wafer W when the first reference thickness RT1 is 30 nm. In each of the figures, the horizontal axis represents the radial position of the wafer W, and the vertical axis represents the thickness of the wafer W.

As shown in FIG. 8A, when the first thickness variation ΔT1 is less than the first reference thickness value RT1 of 30 nm, and the second thickness variation ΔT2 is greater than the second reference thickness value RT2 of 0 nm, the crystal loaded on the susceptor 220 The thickness pattern of the circle W is determined as the first pattern TP1.

Alternatively, as shown in FIG. 8B, when the first thickness variation ΔT1 is less than the first reference thickness value RT1 of 30 nm, and the second thickness variation ΔT2 is not greater than the second reference thickness value RT2 of 0 nm, the susceptor 220 is The thickness pattern of the loaded wafer W is determined as the second pattern TP2.

Alternatively, as shown in FIG. 8C, when the first thickness variation ΔT1 is not less than the first reference thickness value RT1 of 30 nm, and the second thickness variation ΔT2 is greater than the second reference thickness value RT2 of 0 nm, the susceptor 220 is The thickness pattern of the loaded wafer W is determined as the third pattern TP3.

Alternatively, as shown in FIG. 8D, when the first thickness variation ΔT1 is not less than the first reference thickness value RT1 of 30 nm, and the second thickness variation ΔT2 is not greater than the second reference thickness value RT2 of 0 nm, the susceptor 220 The thickness pattern of the wafer W loaded thereon is determined as the fourth pattern TP4.

As described above, when the thickness pattern of the wafer W loaded on the susceptor 220 is determined, the epitaxial layer E is formed on the wafer W under the epitaxial process conditions corresponding to the determined thickness pattern, as in Table 1 below. Show. [Table 1]

Here, "H" indicates hydrogen gas as carrier gas H ₂ , "H ₂ Main" indicates the first supply amount of hydrogen as a carrier gas, and "H ₂ Slit" indicates a second supply amount of hydrogen as a carrier gas, "TCS" The source gas, "Accuset (In/Out)" indicates the opening/closing degree of the air supply valves 240 and 240A, "HT" indicates the height of the base 220, and "RPM" indicates the rotation speed of the base 220.

Table 1 above shows the epitaxial process conditions predetermined for the respective thickness patterns TP1 to TP4 of the wafer W in step 110. As can be seen from Table 1, the relative proportions of the factors of the thickness pattern TP1 to TP4 of the wafer W corresponding to each of the epitaxial process conditions of one of them are different from the relative proportions of the factors of the other epitaxial process conditions. For example, Table 1 can be stored in the storage unit 270 shown in FIG. 3 in the form of a look-up table (LUT).

Referring to Table 1, when the thickness pattern of the wafer W is determined as the first pattern TP1 in step 120 or step 120A, the relative proportions of the factors corresponding to the epitaxial process conditions are as follows: total 100%, H ₂ Main 40 %, H ₂ Slit accounted for 30%, TCS accounted for 10%, Accuset (In/Out) accounted for 10%, HT accounted for 7%, and RPM accounted for 3%.

However, when the thickness pattern of the wafer W is determined as the second pattern TP2, the relative proportions of the factors corresponding to the epitaxial process conditions are as follows: total 100%, H ₂ Main 42%, H ₂ Slit 31%, TCS accounted for 6%, Accuset (In/Out) accounted for 10%, HT accounted for 10%, and RPM accounted for 1%.

However, when the thickness pattern of the wafer W is determined as the third pattern TP3, the relative proportions of the factors corresponding to the epitaxial process conditions are as follows: total 100%, H ₂ Main 42%, H ₂ Slit 30%, TCS accounted for 8%, Accuset (In/Out) accounted for 10%, HT accounted for 7%, and RPM accounted for 3%.

However, when the thickness pattern of the wafer W is determined as the fourth pattern TP4, the relative proportions of the factors corresponding to the epitaxial process conditions are as follows: total 100%, H ₂ Main 42%, H ₂ Slit 31%, TCS accounted for 6%, Accuset (In/Out) accounted for 10%, HT accounted for 10%, and RPM accounted for 1%.

As shown in Table 1 above, depending on the thickness pattern of the wafer W, the degree of use of each factor of the epitaxial process conditions changes.

The thickness variation of the wafer W is compensated by the epitaxial layer E. For example, the thickness of the edge region EA of the wafer W shown in FIGS. 7A, 7C, 8A or 8C falls from the second point P2 to the third point P3. At this time, if the epitaxial layer E is formed such that its thickness increases from the second point P2 to the third point P3, the epitaxial layer E compensates for the thickness variation of the wafer W. Therefore, the thickness variation in the edge region EA of the finally fabricated epitaxial wafer EW is minimized.

In addition, the epitaxial wafer fabrication method 100 and the epitaxial wafer fabrication apparatus 200 of the embodiment are used to classify a plurality of wafers on which an epitaxial layer is to be formed according to a thickness pattern to have a thickness of a maximum number of wafer features. An epitaxial layer is formed on the patterned wafer W, and then an epitaxial layer is formed on the wafer W having the thickness pattern of the second largest number of wafer features by changing the epitaxial process conditions. That is, this configuration preferably forms the epitaxial layer E on the wafer W having the thickness pattern of the largest number of wafer features; however, the present disclosure is not limited thereto.

Generally, the Global Backside Ideal Range (GBIR) or the Site Backside Ideal Range (SBIR) is used as a measurement index to evaluate the thickness variation, that is, the flatness of the wafer W or the epitaxial wafer EW.

Fig. 9A is a schematic diagram for explaining GBIR, and Fig. 9B is a schematic diagram for explaining SBIR.

Referring to FIG. 9A, GBIR is the difference between the maximum thickness Tmax and the minimum thickness Tmin of the wafer W based on the ideal back reference plane 400, and the unit thereof is micrometer/wafer (or nano/wafer or simply micron) Or nano). GBIR is represented by Equation 1 below. [Equation 1]

Referring to FIG. 9B, the SBIR is the difference between the maximum thickness STmax and the minimum thickness STmin of the wafer site WS based on the ideal back reference plane 410, and the unit is micrometer/wafer (or nano/wafer). Or simply referred to as micron or nano). The SBIR is represented by the following Equation 2. [Equation 2]

Here, the wafer position WS means that each small piece into which the wafer W is divided is, for example, a rectangle.

10A to 10C are schematic views for explaining an example of a manufacturing process of an epitaxial wafer in which the change in the total thickness of the wafer W is compensated using the epitaxial layer E, so that the variation in the total thickness is improved.

In particular, FIG. 10A shows a three-dimensional map of the wafer W, FIG. 10B shows a three-dimensional map of the epitaxial layer E having a thickness profile capable of compensating for the thickness variation of the wafer W, and FIG. 10C shows that the crystal is compensated by the epitaxial layer E. A three-dimensional map of the epitaxial wafer EW with varying thickness of the circle W.

When the wafer W shown in FIG. 10A has a GBIR of 94.6 nm and an SBIR of 51.3 nm, if the epitaxial layer E having the shape shown in FIG. 10B is formed through the epitaxial wafer fabrication method 100 of the embodiment, it is formed in FIG. 10A. On the wafer W shown, an epitaxial wafer with an improved SBIR of 89.4 nm with improved GBIR and 35.2 nm can be fabricated, as shown in Figure 10C.

Hereinafter, a comparison between the flatness of the epitaxial wafer manufactured by the conventional epitaxial wafer manufacturing method M1 and the flatness of the epitaxial wafer fabricated by the epitaxial wafer manufacturing method M2 of the embodiment will be described with reference to the accompanying drawings. The conventional epitaxial wafer fabrication method M1 does not consider the thickness variation of the wafer W, and the epitaxial wafer fabrication method M2 of the embodiment considers the thickness variation of the wafer W.

11A shows the GBIR of the epitaxial wafer manufactured by the conventional method and the GBIR of the epitaxial wafer manufactured by the method of the embodiment, and FIG. 11B shows the SBIR of the epitaxial wafer manufactured by the conventional method and the method of the embodiment. SBIR of epitaxial wafers.

As can be seen from FIG. 11A, GBIR M2 of a plurality of epitaxial wafers having an epitaxial layer E having a thickness profile capable of compensating for the thickness variation of the wafer W is formed on the wafer W by the method of the embodiment, less than The conventional method does not consider the thickness variation of the quantum circle W to form GBIR M1 of a plurality of epitaxial wafers of the epitaxial layer E on the wafer W.

As can be seen from FIG. 11B, SBIR M2 of a plurality of epitaxial wafers having an epitaxial layer E having a thickness profile capable of compensating for the thickness variation of the wafer W is formed on the wafer W by the method of the embodiment, less than The SBIR M1 of a plurality of epitaxial wafers on which the epitaxial layer E is formed on the wafer W is not considered by conventional methods. The points shown in Fig. 11B indicate the maximum value of the SBIR of each epitaxial wafer.

12A is a histogram showing GBIR of a plurality of epitaxial wafers manufactured by a conventional method and GBIR of a plurality of epitaxial wafers manufactured by the method of the embodiment, and FIG. 12B is a view showing a plurality of epitaxial wafers manufactured by a conventional method. A histogram of the SBIR of several epitaxial wafers fabricated by SBIR and the method of the examples.

Referring to FIG. 12A, when comparing the number of occurrences of epitaxial wafers having low GBIR M1 on which the epitaxial layer E is formed on the wafer W without considering the flatness of the wafer W by a conventional method, and considering the wafer W Flatness When the number of occurrences of an epitaxial wafer having a low GBIR M2 having an epitaxial layer E capable of compensating for a thickness profile of the variation of the thickness of the wafer W is formed on the wafer W according to the method of the embodiment, it can be seen that the phase The number of epitaxial wafers having a low GBIR is large when manufactured according to the method M2 of the embodiment when manufactured according to the conventional method M1.

Referring to FIG. 12B, when comparing the number of occurrences of the epitaxial wafer having the low SBIR M1 in which the epitaxial layer E is formed on the wafer W by the flatness of the conventional method without considering the flatness of the wafer W, and considering the wafer W It can be seen that the number of occurrences of the epitaxial wafer having the low SBIR M2 of the epitaxial layer E having the thickness profile capable of compensating for the thickness variation of the wafer W is formed on the wafer W according to the method of the embodiment. The number of epitaxial wafers having a low SBIR is large when manufactured according to the method M2 of the embodiment when manufactured according to the conventional method M1.

According to the epitaxial wafer fabrication method 100 and the epitaxial wafer fabrication apparatus 200 of the above embodiment, even when the wafer W exhibits a total thickness variation, the factor of the epitaxial process condition is adjusted by combination (H ₂ Main, H ₂ Slit , TCS, Accuset (In/Out), HT, RPM), forming an epitaxial layer E on the wafer W, having a thickness profile capable of compensating for the total thickness variation of the wafer W, thereby improving the final fabricated epitaxial wafer EW GBIR and SBIR and increase production.

While the invention has been described above in terms of the foregoing embodiments, it should be understood that various other modifications and applications of those skilled in the art will fall within the essential aspects of the embodiments. For example, various variations and modifications are possible in the specific components of the embodiments. In addition, it is to be understood that variations and modifications may be made within the spirit and scope of the disclosure as defined by the appended claims.

100‧‧‧Manufacture method

110, 120, 130‧ ‧ steps

200‧‧‧Manufacture equipment

210‧‧‧ chamber

212‧‧‧Upper chamber frame

214‧‧‧ lower chamber frame

220‧‧‧Base

230‧‧‧ gas supply unit

240, 240A‧‧‧ gas supply valve

250‧‧‧ lifting arm

252‧‧‧Support unit

254‧‧‧Active shaft

256‧‧‧Support pins

260‧‧‧ drive unit

270‧‧‧ storage unit

280‧‧‧ Controller

290‧‧‧thickness pattern determining unit

310, 320‧‧‧ arrows

IN1‧‧‧ intake 埠

OUT‧‧‧Exhaust 埠

IN2‧‧‧Central Department

OUT1, OUT2‧‧‧ edge

C1‧‧‧First control signal

C2‧‧‧second control signal

C3‧‧‧ third control signal

W‧‧‧ wafer

E‧‧‧ epitaxial layer

CA‧‧‧Central Area

EA‧‧ marginal area

EW‧‧‧ epitaxial wafer

ΔT1‧‧‧First thickness change

ΔT2‧‧‧second thickness variation

RT1‧‧‧ first reference thickness value

RT2‧‧‧ second reference thickness value

P0‧‧ Center

P1‧‧‧ first point

P2‧‧‧ second point

P3‧‧‧ third point

Tmax‧‧‧max thickness

Tmin‧‧‧min thickness

400‧‧‧Ideal back reference plane

410‧‧‧Ideal back reference plane

STmax‧‧‧Maximum thickness

STmin‧‧‧minimum thickness

WS‧‧‧ wafer location

M1‧‧‧ traditional method

Method of the M2‧‧‧ embodiment

1 is a flow chart for explaining a method of manufacturing an epitaxial wafer of an embodiment. 2 is a schematic view showing the cross-sectional shape of the epitaxial wafer manufacturing apparatus of the embodiment. Figure 3 is a plan view showing an embodiment of the air supply valve shown in Figure 2. 4A to 4C are schematic views for explaining the principle of the thickness change of the epitaxial layer compensation wafer. FIG. 5 is a flow chart for explaining an embodiment of step 120 shown in FIG. 1. Figure 6 shows the cross-sectional shape of the wafer to explain the central and edge regions of the wafer. 7A to 7D are schematic views showing first to fourth patterns of the wafer when the first reference thickness value is 15 nm. 8A to 8D are schematic views showing first to fourth patterns of a wafer when the first reference thickness value is 30 nm. Fig. 9A is a schematic diagram for explaining GBIR. Fig. 9B is a schematic diagram for explaining SBIR. 10A to 10C are schematic views for explaining an example of a manufacturing process of an epitaxial wafer in which a change in the total thickness of the wafer is compensated using the epitaxial layer to thereby improve the variation in the total thickness. Fig. 11A shows the GBIR of the epitaxial wafer manufactured by the conventional method of the epitaxial wafer and the GBIR of the epitaxial wafer manufactured by the method of the embodiment. Figure 11B shows the SBIR of the epitaxial wafer fabricated by the conventional method and the SBIR of the epitaxial wafer fabricated by the method of the embodiment. Figure 12A is a histogram showing the GBIR of a number of epitaxial wafers produced by the method of the GBIR of a plurality of epitaxial wafers manufactured by the conventional method and the method of the embodiment. Figure 12B is a histogram showing the SBIR of several epitaxial wafers fabricated by conventional methods and the SBIR of several epitaxial wafers fabricated by the method of the embodiment.

Claims (12)

A method for fabricating an epitaxial wafer, forming an epitaxial layer on a wafer mounted on a susceptor, the method comprising: (a) predetermining a plurality of epitaxial layers for each thickness pattern of the wafer An epitaxial process condition, the epitaxial layer having a configuration matching a thickness profile capable of compensating for a total thickness variation of the wafer; (b) using one of the central regions of the wafer loaded on the susceptor a first thickness variation and a second thickness variation in an edge region to determine a thickness pattern of the wafer; and (c) in the predetermined epitaxial process conditions, the determined thickness pattern corresponds to Forming the epitaxial layer on the wafer under an epitaxial process condition, wherein the epitaxial process conditions include a supply amount of the carrier gas, a supply amount of the source gas, an opening/closing degree of the gas supply valve, and a susceptor of the susceptor The speed of rotation or the height of the base is at least one. The method of manufacturing an epitaxial wafer according to claim 1, wherein the supply amount of the carrier gas includes a first supply amount of the carrier gas to be supplied to the upper region of the wafer or is to be supplied to the lower region of the wafer. A second supply of carrier gas is at least one of them. The method of fabricating an epitaxial wafer according to claim 1, wherein the central region of the wafer is defined as a region from a center of the wafer to a first point, and the edge region of the wafer is defined as An area from a second point to a third point of the wafer, and wherein the second point is located further or the same distance from the center than the first point, and the third point is located The position of the two points is further away from the center. The method of manufacturing an epitaxial wafer according to claim 3, wherein the first point is located 80 mm to 100 mm from the center, the second point is located 80 mm to 100 mm from the center, and the The third point is located 140 mm to 148 mm from the center. The method of manufacturing an epitaxial wafer according to claim 3, wherein the first thickness variation is obtained by subtracting a second thickness of the first point from a first thickness of the center, and The third thickness of one of the two points is subtracted from the fourth thickness of the third point to obtain the value of the second thickness variation. The method for manufacturing an epitaxial wafer according to claim 5, wherein the step (b) comprises: obtaining the first thickness variation and the second thickness variation; and comparing the first thickness variation with a first reference thickness value, Obtaining a first comparison value; obtaining a second comparison value by comparing the second thickness variation with a second reference thickness value; and determining a thickness of the wafer by using the first comparison value and the second comparison value pattern. The method of fabricating an epitaxial wafer according to claim 6, wherein the first reference thickness value is 15 nm or 30 nm, and the second reference thickness value is 0. The method for manufacturing an epitaxial wafer according to claim 1, wherein in the step (a), the supply amount of the carrier gas, the supply amount of the source gas, the opening/closing degree of the gas supply valve, and the rotation speed of the susceptor are The relative proportion of the heights of the pedestals is set to the epitaxial process conditions for one of the respective thickness patterns of the wafer. The method of fabricating an epitaxial wafer according to claim 4, wherein the wafer is a double-sided polished wafer. The method for manufacturing an epitaxial wafer according to claim 1, wherein the epitaxial process condition further comprises a supply amount of the doping gas. An apparatus for manufacturing an epitaxial wafer, forming an epitaxial layer on a wafer, the apparatus comprising: a gas supply unit for supplying a carrier gas and a source gas; and a susceptor supporting the wafer loaded thereon; a driving shaft supporting the base; a driving unit for adjusting an upward/downward movement of the driving shaft and a rotation speed; a gas supply valve for supplying the carrier gas and the source gas from the gas supply unit to the wafer a memory cell storing a plurality of epitaxial process conditions of the epitaxial layer, wherein the epitaxial layer has a thickness profile for each thickness pattern of the wafer, the thickness profile and a total thickness variation capable of compensating for the wafer a configuration matching; a thickness pattern determining unit determining a thickness pattern of the wafer loaded on the susceptor; and a controller for reading the thickness pattern determined by the thickness pattern determining unit from the memory unit Corresponding an epitaxial process condition, and controlling the gas supply unit, the gas supply valve or the driving unit to adjust the supply of the carrier gas in response to at least one of the epitaxial process conditions read , The height of the source of gas supply, opening / closing of the supply valve, the rotational speed of the base or the at least one base. The apparatus for manufacturing an epitaxial wafer according to claim 11, wherein the controller further controls a gas supply amount of the doping gas as the epitaxial process condition.