TW201836127A - Memory device and method for fabricating the same - Google Patents

Abstract

A memory device includes memory includes a multi-layers stack includes a plurality of insulating layers and a plurality conductive layers alternatively stacked on a semiconductor device, a plurality of memory cells formed on the conductive layers, a contact plug passing through the insulating layers and the conductive layers, and a dielectric layer including a plurality of extending parts each of which is inserted between each adjacent two ones of the insulating layers to isolate the conductive layer from the contact plug. Wherein any one of the extending parts that has a shorter distance departed from the semiconductor substrate has a size substantially greater than a size of the others that has a longer distance departed from the semiconductor substrate.

Description

Memory element and manufacturing method thereof

The present disclosure relates to a memory component and a method of fabricating the same. In particular, there is a non-volatile memory (NVM) and a method for fabricating the same.

Non-volatile memory components, such as flash memory, have the property of not losing information stored in the memory unit when the power source is removed. It has been widely used in solid-state mass storage applications for portable music players, mobile phones, digital cameras, and the like. Three-dimensional non-volatile memory components, such as Vertical-Channel (VC) three-dimensional flash memory components, have many layer stack structures for higher storage capacity and superior electronic characteristics, such as good The data is stored for reliability and speed of operation.

A method of forming a typical three-dimensional non-volatile memory component includes the steps of first comprising a multi-layers stack of a plurality of insulating layers and conductive layers stacked one on another. And forming at least one trench in the multi-layer structure by an etching process, and dividing the multi-layer structure into a plurality of ridge-shaped stacks, so that each ridge-shaped multilayer stack comprises a plurality of patterns by patterning a conductive strip formed by the conductive layer. Forming a memory material layer and a channel layer on the sidewall of the trench, and then defining a plurality of memory cells at a position where each of the conductive strips overlaps the memory material layer and the channel layer, and the channel layer is vertically stringed Connected to form a memory cell string.

However, in view of the nature of the etching process, the trenches used to define the ridge multilayer stack typically have an upper width and a lower profile, which would result in conduction as a gate of the memory cell in the ridge multilayer stack. The strip exhibits a phenomenon that the width of the lower layer is smaller than the width of the upper layer, resulting in a difference in the gate resistance of the memory cells of different levels in the same memory cell string, thereby affecting the operation of the memory element.

Therefore, there is a need to provide an advanced memory component and its fabrication method to solve the problems faced by the prior art.

An embodiment of the present specification discloses a memory device including a semiconductor substrate, a multi-layers stack, a plurality of memory cells, a contact plug, and a dielectric layer. The multilayer stack structure includes a plurality of conductor layers and a plurality of insulating layers staggered on a semiconductor substrate. Memory cells are formed on these conductor layers. The contact plug passes through the conductor layer and the insulating layer. The dielectric layer is located in the multilayer stack structure and includes a plurality of extensions extending between adjacent ones of the insulating layers to isolate the contact plugs and the conductor layers, and the extensions are away from the semiconductor substrate One of the dimensions is smaller than the size of the other adjacent to the semiconductor substrate.

Another embodiment of the present specification discloses a method of fabricating a memory device, comprising the steps of: first forming a multilayer stack structure on a semiconductor substrate, the multilayer stack structure comprising a plurality of conductor layers and a plurality of insulating layers stacked in a staggered manner . At the same time, a plurality of memory cells are formed on the conductor layers. A dielectric layer is then formed in the multilayer stack structure to include a plurality of extensions extending between adjacent ones of the insulating layers. Wherein the dimension of the extension away from one of the semiconductor substrates is smaller than the size of the other of the semiconductor substrate. Subsequently, a contact plug is formed through the conductor layer and the insulating layer and electrically isolated from the conductor layers by a dielectric layer.

According to the above embodiment, the present specification is to provide a memory element and a method of fabricating the same. A multilayer stack structure having a plurality of staggered stacked conductor layers and insulating layers is formed on the semiconductor substrate while forming a plurality of memory cells in the multilayer stack structure. Thereafter, a first etching back process is performed through a through opening through the multilayer stack structure, and a portion of the conductor layer is removed to form an alcove between the two adjacent insulating layers, respectively. A protective layer is then formed in the recess, and then a second etch back process is performed to remove a portion of the conductor layer and a portion of the protective layer. Subsequently, a dielectric layer is formed to be filled in the recess, and the through opening is filled with a conductive material to form a contact plug, and the contact plug is electrically isolated from the conductor layer by the dielectric layer.

By adjusting the size of the protective layer formed in the recess and the length of time of the second etching, the remaining dimensions of the conductor layer and the length of the dielectric layer extending into the recess can be simultaneously adjusted. So that the layers of the conductor layers used as the memory cell gates in the multi-layer stack structure have substantially the same size, thereby causing the resistance variation value between the memory cell gates located in the same vertical memory cell string to fall. Within the difference. At the same time, it can ensure the contact between the plug and the conductor layer, because of the isolation of the dielectric layer, there is sufficient bridge margin (Bridge Window, BR window) to prevent memory cell leakage, so as to improve the reliability and operational efficiency of the memory component.

In order to better understand the above and other aspects of the present specification, the following specific embodiments are described in detail below with reference to the accompanying drawings:

This specification provides a method for defining the critical dimensions of a memory component, which can improve the reliability and operational performance of the memory component. The above described embodiments and other objects, features and advantages of the present invention will become more apparent and understood.

However, it must be noted that these specific embodiments and methods are not intended to limit the invention. The invention may be practiced with other features, elements, methods and parameters. The preferred embodiments are merely illustrative of the technical features of the present invention and are not intended to limit the scope of the invention. Equivalent modifications and variations will be made without departing from the spirit and scope of the invention. In the different embodiments and the drawings, the same elements will be denoted by the same reference numerals.

Referring to FIGS. 1A to 1I , FIGS. 1A to 1I are schematic cross-sectional views showing a process structure for fabricating a memory device 100 according to an embodiment of the present specification. In the present embodiment, memory component 100 can be, but is not limited to, a NAND memory component having vertical channels. The method of fabricating the memory device 100 includes the following steps: First, a semiconductor substrate 101 is provided. In some embodiments of the present specification, the semiconductor layer substrate 101 may be composed of, for example, p-type doped, n-type doped or undoped polysilicon, germanium or other suitable semiconductor material.

Thereafter, a conductor layer 102 is formed on the semiconductor substrate 101; and a multilayer stack structure 110 is formed on the conductor layer 102. In some embodiments of the present specification, the conductor layer 102 may be a poly-silicon layer or a doped semiconductor located in the semiconductor substrate 101. The multilayer stack structure 110 includes a plurality of sacrificial layers 111-115 and a plurality of insulating layers 121-126 that are staggered stacked. Here, the sacrificial layers 111-115 and the insulating layers 121-126 are parallel to each other, and are alternately stacked on the conductor layer 102 along the Z-axis direction. The insulating layer 126 is located on the top layer of the multilayer stack structure 110, and the insulating layer 121 is located at the bottommost layer of the multilayer stack structure 110 and is in direct contact with the conductor layer 102 (as shown in FIG. 1A).

In some embodiments of the present specification, the sacrificial layers 111-115 and the insulating layers 121-126 may be fabricated by, for example, a Low Pressure Chemical Vapor Deposition (LPCVD) process. Moreover, the materials of the sacrificial layers 111-115 and the insulating layers 121-126 must be different. For example, the sacrificial layers 111-115 may be composed of a niobium-containing nitride such as tantalum nitride (SiN), hafnium oxynitride (SiON), niobium oxynitride (SiCN), or any combination thereof. The insulating layers 121-126 may be composed of a dielectric material different from the sacrificial layers 111-115, such as tantalum oxide, silicon carbide, niobate, or any combination thereof. In the present embodiment, the sacrificial layers 111-115 are composed of tantalum nitride having a thickness of substantially 520 angstroms. The insulating layers 121-126 are composed of cerium oxide (SiO ₂ ) having a thickness of substantially 280 Å.

Next, the multilayer stack structure 110 is etched to form a plurality of first through openings 110a through the multilayer stack structure 110, thereby exposing a portion of the conductor layer 102 to the outside. In some embodiments of the present specification, an etching process for forming the first through opening 110a includes patterning a hard mask layer (not shown) as an etching mask by an anisotropic etching process, The multilayer stack structure 110 is etched, for example, by a reactive ion etch (RIE) process. A plurality of through holes extending downward in the Z-axis direction are formed in the multilayer stack structure 110, and a portion of the conductor layer 102 located on the bottom surface of the first through opening 110a and the sidewalls of the first through opening 110a are used. A portion of the insulating layers 121-126 and the sacrificial layers 111-115 are exposed. Among them, the first through opening 110a has a sectional appearance which is gradually decreased in size (upper width and lower width) along the Z axis.

Thereafter, the memory layer 104 and the channel layer 105 are sequentially formed on the sidewall of the first through opening 110a, and the memory layer 104 is sandwiched between the channel layer 105 and a portion of the sacrificial layer 111-115 exposed through the first through opening 110a. between. In some implementations of the present specification, the memory layer 104 includes, for example, Oxide-Nitride-Oxide (ONO), yttrium oxide-tantalum nitride-yttria-yttrium nitride-yttrium oxide ( Oxide-Nitride-Oxide-Nitride-Oxide, ONONO) or Oxide-Nitride-Nitride-Oxide-Nitride-Oxide-Nitride-Oxide , ONONONO) structure (but not limited to this). The channel layer 105 can be composed of an undoped polysilicon material.

Thereafter, the first through opening 110a is filled with an insulating material 103, such as ceria or other suitable dielectric material. After etch back the insulating material 103, pads 106 are formed over the insulating material 103, and a cap layer 107 is formed to cover the multilayer stack structure 110 and the pads 106 (as depicted in FIG. 1B). In an embodiment of the present specification, the insulating material 103 may be tantalum oxide, tantalum carbide, niobium or any combination of the above. The cover layer 107 includes tantalum oxide.

Thereafter, another etching process is performed to form at least one second through opening 108 extending in the Z-axis direction extending through the multi-layer stacked structure 110 in the multilayer stacked structure 110, and the insulating layers 121-126 and the sacrificial layer 111- 115 and conductor layer 102 are partially exposed (as depicted in Figure 1C). In some embodiments of the present specification, the second through opening 108 is formed by a plurality of slits that extend through the multilayer stack structure 110. And the second through opening 108 has a cross-sectional appearance that decreases in size along the Z-axis (upper width and lower width).

Subsequently, the remaining sacrificial layers 111-115 are removed. In the present embodiment, the remaining sacrificial layers 111-115 are removed through the second through opening 108 using a phosphoric acid (H ₃ PO ₄ ) solution, thereby forming a plurality of spaces 109 between the insulating layers 121-126 and A portion of the memory layer 104 is exposed to the outside. Thereafter, a dielectric liner layer 120 is formed on the sidewalls of the memory layer 104 and the insulating layers 121-126 that define a portion of the space 109 by a deposition process, such as a low pressure chemical vapor deposition process. In some embodiments of the present specification, the dielectric liner layer 120 may be a high dielectric gate oxide layer of aluminum oxide (Al ₂ O ₃ ).

After forming the dielectric liner layer 120, a plurality of conductor layers 127 are formed to fill the original positions of the remaining remaining sacrificial layers 111-115 by another deposition process, such as a low pressure chemical vapor deposition process (space 109). And forming a memory cell 128a in a region where each of the conductive layer 105, the dielectric liner layer 120, the memory layer 104, and the channel layer 105 overlap, and forming at least one memory cell having a vertical channel in the multilayer stack structure 110 The serial array 128 (as shown in FIG. 1D) further constitutes a memory array (not shown). In some embodiments of the present specification, the conductor layer 127 may be composed of polysilicon, metal, or other conductive material. In the present embodiment, the conductor layer 127 may be a tungsten (W) metal layer.

Next, a first etch back process 129 is performed, and a portion of the conductor layer 127 is removed through the second through opening 108 to form between each of the remaining conductive layers 127 and the corresponding adjacent two insulating layers 121-126. An alcove. For example, in the present embodiment, the recess 130a is formed between the lowermost conductor layer 127 and the adjacent two insulating layers 121 and 122; the recess 130b is formed in the second conductor layer 127 and the adjacent two insulating layers 122 and 123. The recess 130c is formed between the third layer conductor layer 127 and the adjacent two insulating layers 123 and 124; the recess 130d is formed between the fourth layer conductor layer 127 and the adjacent two insulating layers 124 and 125; The chamber 130e is formed between the highest conductor layer 127 and the adjacent insulating layers 125 and 126. And due to the characteristics of the etching process, the lateral dimensions of the higher-level recesses (eg, the highest-level recesses 130e) formed in the multilayer stack structure 110 may be larger than the lower-level recesses (eg, the recesses 130a-130c). The lateral dimensions. In other words, the recesses 130a-130c are respectively extended outward by the second through opening 108, and the combined structure of the recesses 130a-130c has a central axis L of the second through opening 108, and the dimension is gradually increased along the Z axis. The cross-sectional appearance (as shown in Figure 1E).

A protective layer 131 is further formed, at least partially filled in the recesses 130a-130e. In some embodiments of the present specification, the protective layer 131 is formed by a deposition process, such as a low-pressure chemical vapor deposition process, using methyl fluoride (CH ₃ F) as a reactive gas, and the polymer layer formed includes a plurality of layers. The filling portions 131a-131e are filled in the recesses 130a-130e, respectively. It should be noted that the material constituting the protective layer 131 is not limited thereto. Any material having a different etching selectivity from the conductor layer 127 may be used to form the protective layer 131.

In some embodiments of the present specification, the filling portions 131a-131e of the protective layer 131 do not completely fill the recesses 130a-130e. Since the protective layer 131 is formed by the deposition process in the second through opening 108 which is narrow in the upper width and the lower, the lateral dimension of the higher-level filling portion (for example, the highest layer filling portion 131e) located in the multilayer stacked structure 110 is larger than the lower portion thereof. The lateral dimension of the fill portion of the hierarchy (e.g., fill portions 131a-c) (as depicted in Figure 1F).

Then, a second etch back process 132 is performed to remove a portion of the conductor layer 127 and the protective layer 131 via the second through opening 108. The lateral dimension of the filling portion (for example, the highest layer filling portion 131e) located at the higher level is larger than the lateral dimension of the filling portion (for example, the filling portions 131a-c) of the lower layer. Therefore, when the second etchback process 132 removes the higher-level filling portion (for example, the highest layer filling portion 131e), in addition to removing the filling portion (for example, the filling portions 131a-131c) of the lower layer, and shifting A portion of the conductor layer 127 (as depicted in FIG. 1G) other than the recesses (e.g., recesses 130a-130c) in the lower level of the hierarchy. In other words, the portion of the conductor layer 127 that is at the higher level is removed, and the portion of the conductor layer 127 that is at the lower level is removed. In some embodiments of the present specification, the second etch back process 132 may completely remove the filling portion 131e located in the highest layer recess 130e, and remove a portion of the conductor layer 127 located in the highest layer recess 130e, or may only A portion of the protective layer 131 located in the highest layer recess 130e is removed without removing the conductor layer 127 located in the highest layer recess 130e.

In some embodiments of the present specification, another protective layer may be repeatedly formed, and the step of the subsequent etch back process may be repeated a plurality of times. For example, in the present embodiment, the protective layer 133 including the filling portions 133a-133e (as shown in FIG. 1H) may be formed in the recesses 130a-130e, and the first and second etching processes 132 may be performed. The etchback process 134 is performed three times to remove a portion of the second conductor layer 127 and the fill portions 133a-133e (as depicted in FIG. 1I). In addition, after the first etch back process 129, the protective layer may not be formed first, and the fourth etch back process 135 may be directly performed to remove a portion of the conductor layer 127 (as shown in FIG. 1J).

Subsequently, a dielectric layer 136 is formed in the second through opening 108. In some embodiments of the present specification, the step of forming the dielectric layer 136 includes first depositing an epitaxial germanium in the recesses 130a-130c and the second through opening 108 by a deposition process, and then performing a low temperature tantalum oxidation process ( Low Temperature Oxidation (LTO), passing the reaction gas at a low temperature of 300 ° C to 450 ° C, thereby forming a tantalum oxide layer on the sidewalls and the bottom of the second through opening 108, and filling the recesses 130a-130c. In the present embodiment, the dielectric layer 136 has at least one vertical wall 136a and a plurality of extensions 136b-131f. Wherein at least one vertical wall 136a is blanketed over the sidewall of the second through opening 108. The extensions 136b-131f extend into the recesses 130a-130c, respectively. And the dimension of the extension 136b away from one of the semiconductor substrates 101 (eg, the extension 136f at the highest level) is substantially smaller than the other of the semiconductor substrate (eg, the extensions 136b, 136c, 136d at the highest level or 136e) size. In other words, the dielectric layer 136 has a cross-sectional appearance that rises along the Z-axis and is gradually reduced in size (as shown in FIG. 1K).

After removing a portion of the dielectric layer 136 at the bottom of the second through opening 108, the second through opening 108 is filled with a conductive material, such as a metal telluride or a metal, by a deposition process, such as a low pressure chemical vapor deposition process. For example, titanium (Ti), tungsten, aluminum (Al), copper (Cu), gold (Au), silver (Ag) or alloys thereof, metal oxides (for example, titanium nitride (TiN)) or other suitable The conductive material is formed to form a contact plug 137 in the second through opening 108 and electrically contact with the conductor layer 102, and is electrically isolated from the conductor layer 127 in each layer of the multilayer stack structure 110 by the dielectric layer 136. . Subsequently, the preparation of the memory component 100 (as shown in FIG. 1K) is completed via a series of back-end processes (not shown).

By controlling the number of fillings of the filling portions 131a-131eC and 133a-133e in the recesses 130a-130e, and the first etching process 129, the second etching process 132, the third etching process 134, and the fourth etching process At time 135, the amount of the removed portion of the conductor layer 127 in each level of the multilayer stack structure 110 can be adjusted to control the lateral dimension of the conductor layer 127 in each level. In the present embodiment, the conductor layers 127 located in the respective layers have substantially the same lateral dimension. The memory cells 128a located in the same memory cell string 128 can be gated with the same resistance. Moreover, the dielectric layer 136 extending portion 136a formed in the recesses 130a-130c can have sufficient bridging margin to prevent the memory cell 128a from leaking, thereby greatly improving the reliability and operational efficiency of the memory device 100.

According to the above embodiment, the present specification is to provide a memory element and a method of fabricating the same. A multilayer stack structure having a plurality of staggered stacked conductor layers and insulating layers is formed on the semiconductor substrate while forming a plurality of memory cells in the multilayer stack structure. Thereafter, an etch back process is performed through a through opening through the multilayer stack structure, and a portion of the conductor layer is removed to form an alcove between the two adjacent insulating layers, respectively. A protective layer is then formed in the recess, and then a second etch back process is performed to remove a portion of the conductor layer and a portion of the protective layer. Subsequently, a dielectric layer is formed to be filled in the recess, and the through opening is filled with a conductive material to form a contact plug, and the contact plug is electrically isolated from the conductor layer by the dielectric layer.

The remaining dimensions of the conductor layer in the recess are adjusted by the protection of the protective layer and in conjunction with the regulation of the etch back time. Therefore, the layers of the conductor layers used as the memory cell gates in the multi-layer stack structure have substantially the same size, so that the resistance variation value between the memory cell gates located in the same vertical memory cell string falls on Within the tolerance range, it is ensured that there is sufficient bridging margin between the contact plug and the conductor layer formed in the through opening to prevent memory cell leakage, thereby improving the reliability and operational efficiency of the memory component.

While the invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and it is to be understood by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧ memory components

101‧‧‧Semiconductor substrate

102, 127‧‧‧ conductor layer

103‧‧‧Insulation materials

104‧‧‧ memory layer

105‧‧‧Channel layer

106‧‧‧ solder pads

107‧‧‧ Coverage

108‧‧‧second through opening

109‧‧‧ Space

110‧‧‧Multilayer stacking structure

110a‧‧‧first through opening

111-115‧‧‧ Sacrifice layer

120‧‧‧Dielectric lining

121-126‧‧‧Insulation

127‧‧‧ conductor layer

128‧‧‧Memory cell series

128a‧‧‧ memory cells

129‧‧‧First etchback process

130a-130e‧‧‧ alcove

131, 133‧‧ ‧ protective layer

131a-131e, 133a-133e‧‧‧Filling

132‧‧‧Second eclipse process

134‧‧‧ Third etchback process

135‧‧‧ Fourth eclipse process

136‧‧‧ dielectric layer

136a‧‧‧立立

136b-131f‧‧‧Extension

137‧‧‧Contact plug

Z‧‧‧ axis

L‧‧‧The central axis of the second through opening

X‧‧‧ axis

1A to 1K are schematic cross-sectional views showing a process structure for fabricating a semiconductor device according to an embodiment of the present specification.

no.

Claims (10)

A memory device comprising: a semiconductor substrate; a multi-layers stack comprising a plurality of first conductor layers and a plurality of insulating layers staggered on the semiconductor substrate; a plurality of memory cells Formed on the first conductor layers; a contact plug passing through the first conductor layers and the insulating layers; and a dielectric layer located in the multilayer stack structure and including a plurality of extensions And extending between the adjacent ones of the insulating layers to isolate the contact plugs and the first conductive layers, and the one of the extensions away from the semiconductor substrate has a smaller than One size of the other of the semiconductor substrates. The memory device of claim 1, further comprising: a channel layer on at least one side wall and a bottom surface of a first through opening, wherein the first through opening passes through the insulating layers and The first conductor layer; and a memory layer on the channel layer, thereby forming the memory cells at a plurality of intersection points of the first conductor layer, the memory layer and the channel layer. The memory device of claim 1, wherein the contact plug is located in a second through opening through the first conductor layer and the insulating layers; each of the first conductor layers And an adjacent two of the insulating layers define an recess communicating with the second through opening; each of the extending portions respectively extending into the corresponding one of the recesses. The memory device of claim 3, wherein the first through opening and the second opening respectively have a cross-sectional profile that is gradually widened away from the semiconductor substrate; and the first The conductor layers have substantially the same size. The memory device of claim 1, further comprising a dielectric liner layer between each of the first conductor layers and the adjacent two of the insulating layers. The memory device of claim 1, further comprising a second conductor layer between the semiconductor substrate and the multilayer stack structure, electrically contacting the contact plug, and the first The conductor layer is electrically isolated. A method of fabricating a memory device, comprising: providing a semiconductor substrate; forming a multilayer stack structure on the semiconductor substrate, comprising a plurality of first conductor layers and a plurality of insulating layers stacked in a staggered manner; Forming a plurality of memory cells on the layer; forming a dielectric layer in the multilayer stack structure to include a plurality of extensions extending between adjacent ones of the plurality of insulating layers, wherein the extensions a dimension away from the semiconductor substrate, having a size smaller than the other of the semiconductor substrate; forming a contact plug, passing through the first conductor layer and the insulating layers, and The electrical layer is electrically isolated from the first conductor layers. The method of fabricating the memory device of claim 7, wherein the forming the memory cell step comprises: forming a plurality of sacrificial layers on the semiconductor substrate and stacking the insulating layers in a staggered manner; forming a first a through-opening, through the sacrificial layer and the insulating layer; forming a channel layer on at least one sidewall of the first through opening; forming a second through opening, passing through the sacrificial layer and the insulating layer; Removing the sacrificial layers through the second through opening; and forming the first conductor layers on the original positions of the sacrificial layers, thereby forming a plurality of the first conductor layers, the memory layer and the channel layer The overlapping regions form the memory cells. The method of fabricating the memory device of claim 8, wherein the forming the dielectric layer comprises: forming a second through opening, passing through the first conductive layer and the insulating layers; Determining one of the plurality of recesses between the first conductive layer and the adjacent two of the insulating layers, such that one of the recesses away from the semiconductor substrate has a larger than the semiconductor substrate A size of the other; a dielectric material is deposited in the recesses to form the extensions. The method of fabricating the memory device of claim 9 , before depositing the dielectric material, further comprising: performing a first etch back process, removing a portion of the first conductors through the second through opening a layer to form the recesses; forming a protective layer in the recesses; and performing a second etch back process, removing a portion of the first conductor layers via the second through openings and the recesses, and Part of the protective layer.