TW201834218A - Semiconductor device and manufacturing method thereof capable of reducing the distance from the sidewall portion contacting the source layer within the semiconductor body to the gate layer disposed on the source layer - Google Patents

Abstract

Embodiments of the present invention provide a semiconductor device capable of shortening a distance from a side wall portion in contact with a source layer in a semiconductor body to a gate layer above the source layer, and a manufacturing method thereof. The gate layer 80 of the semiconductor device according to the embodiment is provided between the source layer SL and the laminated body 100, and is thicker than one layer of the electrode layer 70. The semiconductor body 20 extends in the laminated direction of the laminated body 100 in the laminated body 100, the gate layer 80 and the semiconductor layer 13, and has a side wall portion 20 a that is in contact with the semiconductor layer 13. The semiconductor body 20 is not in contact with the electrode layer 70 and the gate layer 80.

Description

Semiconductor device and manufacturing method thereof

Embodiments relate to a semiconductor device and a method of manufacturing the same.

The industry has proposed a three-dimensional memory having a structure in which a side wall of a channel body penetrating a multilayer body including a plurality of electrode layers is in contact with a source layer disposed below the multilayer body.

Embodiments provide a semiconductor device capable of shortening a distance from a side wall portion in contact with a source layer in a semiconductor body to a gate layer above the source layer, and a manufacturing method thereof. A semiconductor device according to an embodiment includes a source layer, a multilayer body, a gate layer, a semiconductor body, and a charge storage portion. The source layer includes a semiconductor layer containing impurities. The laminated body is disposed on the source layer, and has a plurality of electrode layers laminated with a dielectric insulator. The gate layer is disposed between the source layer and the laminated body, and is thicker than one layer of the electrode layer. The semiconductor body extends in the laminated direction of the laminated body in the laminated body, in the gate layer, and in the semiconductor layer, and has a side wall portion in contact with the semiconductor layer. The semiconductor body is not in contact with the electrode layer and the gate layer. The charge storage section is provided between the semiconductor body and the electrode layer.

Hereinafter, embodiments will be described with reference to the drawings. In the drawings, the same elements are denoted by the same symbols. In the embodiment, as a semiconductor device, for example, a semiconductor memory device having a three-dimensional memory cell array will be described. FIG. 1 is a schematic perspective view of a memory cell array 1 according to an embodiment. FIG. 2 is a schematic sectional view of the memory cell array 1. FIG. In FIG. 1, two directions that are parallel to and orthogonal to the main surface of the substrate 10 are set as the X direction and the Y direction, and the directions that are orthogonal to the two X and Y directions are set. Z direction (lamination direction). The Y and Z directions in FIG. 2 correspond to the Y and Z directions in FIG. 1, respectively. The memory cell array 1 has a source layer SL, a multilayer body 100 disposed on the source layer SL, a gate layer 80 disposed between the source layer SL and the multilayer body 100, a plurality of columnar portions CL, and a plurality of separation The portion 160 and a plurality of bit lines BL provided above the laminated body 100. The source layer SL is disposed on the substrate 10 through the edge layer 41. The substrate 10 is, for example, a silicon substrate. The columnar portion CL is formed in a substantially cylindrical shape extending in the laminated direction (Z direction) within the laminated body 100. The columnar portion CL further penetrates the gate layer 80 below the laminated body 100 and reaches the source layer SL. The plurality of columnar portions CL are aligned, for example, in an offset manner. Alternatively, the plurality of columnar portions CL may be arranged in a square grid along the X direction and the Y direction. The separation unit 160 separates the laminated body 100 and the gate layer 80 into a plurality of blocks (or claw portions) in the Y direction. The separation section 160 has a structure in which an insulating film 163 is embedded in the slit ST as shown in FIG. 17 described below. The plurality of bit lines BL are, for example, metal films extending in the Y direction. The plurality of bit lines BL are separated from each other in the X direction. The upper end of the below-mentioned semiconductor body 20 of the columnar portion CL is connected to the bit line BL via a contact Cb and a contact V1 shown in FIG. 1. As shown in FIG. 2, the source layer SL includes a layer 11 including a metal and semiconductor layers 12 to 14. The metal-containing layer 11 is disposed on the insulating layer 41. The metal-containing layer 11 is, for example, a tungsten layer or a tungsten-silicon alloy layer. A semiconductor layer 12 is provided on the metal-containing layer 11, a semiconductor layer 13 is provided on the semiconductor layer 12, and a semiconductor layer 14 is provided on the semiconductor layer 13. The semiconductor layers 12 to 14 are polycrystalline silicon layers containing impurities and having conductivity. The semiconductor layers 12 to 14 are, for example, n-type polycrystalline silicon layers doped with phosphorus. The semiconductor layer 14 may also be an undoped polycrystalline silicon layer that is not intentionally doped with impurities. The thickness of the semiconductor layer 14 is thinner than the thickness of the semiconductor layer 12 and the thickness of the semiconductor layer 13. An insulating layer 44 is provided on the semiconductor layer 14, and a gate layer 80 is provided on the insulating layer 44. The gate layer 80 is a polycrystalline silicon layer containing impurities and having conductivity. The gate layer 80 is, for example, an n-type polycrystalline silicon layer doped with phosphorus. The thickness of the gate layer 80 is thicker than the thickness of the semiconductor layer 14. A laminated body 100 is provided on the gate layer 80. The laminated body 100 includes a plurality of electrode layers 70 laminated in a direction (Z direction) perpendicular to the main surface of the substrate 10. An insulating layer (insulator) 72 is provided between the upper and lower adjacent electrode layers 70. An insulating layer 72 is provided between the lowermost electrode layer 70 and the gate layer 80. An insulating layer 45 is provided on the uppermost electrode layer 70. The electrode layer 70 is a metal layer. The electrode layer 70 is, for example, a tungsten layer containing tungsten as a main component or a molybdenum layer containing molybdenum as a main component. The insulating layer 72 is a silicon oxide layer containing silicon oxide as a main component. At least the uppermost electrode layer 70 of the plurality of electrode layers 70 is the drain-side selection transistor SGD of the drain-side selection transistor STD (FIG. 1), and at least the lowermost electrode layer 70 is the source-side selection transistor STS. (Figure 1) The source side selects the gate SGS. For example, a plurality of layers (for example, three layers) including the lower layer of the electrode layer 70 (eg, three layers) of the electrode layer 70 is the source-side selection gate SGS. The drain-side selection gate SGD may be provided with a plurality of layers. A plurality of electrode layers 70 are provided between the drain-side selection gate SGD and the source-side selection gate SGD as the cell gate CG. The gate layer 80 is thicker than the thickness of one layer of the electrode layer 70 and the thickness of one layer of the insulating layer 72. Therefore, the gate layer 80 is thicker than the thickness of one layer of the gate-side selection gate SGD, the source-side selection of the gate SGS, and the cell-gate CG. The plurality of columnar portions CL extend in the laminated body 100 in the laminated direction thereof, and further penetrate the gate layer 80, the insulating layer 44, the semiconductor layer 14, and the semiconductor layer 13 and reach the semiconductor layer 12. FIG. 3 is an enlarged sectional view of part A in FIG. 2. The columnar portion CL includes a memory film 30, a semiconductor body 20, and an insulating core film 50. The memory film 30 is a laminated film of an insulating film including a tunnel insulating film 31, a charge accumulation film (charge accumulation portion) 32, and a barrier insulating film 33. As shown in FIG. 2, the semiconductor body 20 is formed in a tubular shape that continuously extends in the Z direction in the laminated body 100 and in the gate layer 80 and reaches the source layer SL. The core film 50 is disposed inside the tubular semiconductor body 20. The upper end portion of the semiconductor body 20 is connected to the bit line BL via a contact point Cb and a contact point V1 shown in FIG. 1. The side wall portion 20 a on the lower end side of the semiconductor body 20 is in contact with the semiconductor layer 13 of the source layer SL. The memory film 30 is provided between the laminated body 100 and the semiconductor body 20 and between the gate layer 80 and the semiconductor body 20, and surrounds the semiconductor body 20 from the outer peripheral side. The memory film 30 continuously extends in the Z direction in the laminated body 100 and the gate layer 80. The side wall portion (source contact portion) 20 a of the semiconductor body 20 that is in contact with the semiconductor layer 13 is not provided with the memory film 30. The side wall portion 20 a is not covered by the memory film 30. Furthermore, a memory film 30 may be arranged between the semiconductor body 20 and the semiconductor layer 13 on a part of the outer periphery of the semiconductor body 20. The lower end portion of the semiconductor body 20 is continuous with the side wall portion 20 a, is located below the side wall portion 20 a, and is located in the semiconductor layer 12. A memory film 30 is provided between the lower end portion of the semiconductor body 20 and the semiconductor layer 12. Therefore, on the one hand, the memory film 30 is divided in the Z direction at the position of the side wall portion 20a of the semiconductor body 20, and on the other hand, it is arranged below the semiconductor body 20 at a position surrounding the outer periphery of the lower end of the semiconductor body 20 and the semiconductor body 20 Underneath. As shown in FIG. 3, the tunnel insulating film 31 is provided between the semiconductor body 20 and the charge accumulation film 32, and is in contact with the semiconductor body 20. The charge accumulation film 32 is provided between the tunnel insulating film 31 and the barrier insulating film 33. The barrier insulating film 33 is provided between the charge accumulation film 32 and the electrode layer 70. The semiconductor body 20, the memory film 30, and the electrode layer 70 (cell gate CG) constitute a memory cell MC. The memory cell MC has a vertical transistor structure with an electrode layer 70 (cell gate CG) surrounding the semiconductor body 20 through the memory film 30. In the memory cell MC of this vertical transistor structure, the semiconductor body 20 is, for example, a channel body of silicon, and the electrode layer 70 (cell gate CG) functions as a control gate. The charge accumulation film 32 functions as a data memory layer that accumulates charges injected from the semiconductor body 20. The semiconductor memory device according to the embodiment is a nonvolatile semiconductor memory device capable of electrically erasing and writing data freely and storing the memory contents even when the power is turned off. The memory cell MC is, for example, a charge-trapping memory cell. The charge accumulation film 32 is a film having a plurality of capture sites for trapping charges in an insulating film, and includes, for example, a silicon nitride film. Alternatively, the charge accumulation film 32 may be a conductive floating gate surrounded by an insulator. The tunnel insulating film 31 becomes a potential barrier when a charge is injected from the semiconductor body 20 into the charge accumulation film 32 or when the charge accumulated in the charge accumulation film 32 is released to the semiconductor body 20. The tunnel insulating film 31 includes, for example, a silicon oxide film. The blocking insulating film 33 prevents the charges accumulated in the charge accumulation film 32 from being released to the electrode layer 70. The blocking insulating film 33 prevents back tunneling of electric charges from the electrode layer 70 to the columnar portion CL. The barrier insulating film 33 includes, for example, a silicon oxide film. Alternatively, the barrier insulating film 33 may have a laminated structure of a silicon oxide film and a metal oxide film. In this case, a silicon oxide film may be provided between the charge accumulation film 32 and the metal oxide film, and the metal oxide film may be provided between the silicon oxide film and the electrode layer 70. The metal oxide film is, for example, an aluminum oxide film. As shown in FIG. 1, a drain-side selection transistor STD is provided on an upper layer portion of the multilayer body 100. A source-side selection transistor STS is provided at a lower layer portion of the multilayer body 100. The drain-side selection transistor STD has the above-mentioned drain-side selection gate SGD (Figure 2) as a vertical transistor that controls the gate, and the source-side selection transistor STS has the above-mentioned source-side selection gate SGS (Figure 2) A vertical transistor as a control gate. The portion of the semiconductor body 20 opposite to the drain-side selection gate SGD functions as a channel, and the memory film 30 between the channel and the drain-side selection gate SGD functions as a gate of the drain-side selection transistor STD. Function as an insulating film. The portion of the semiconductor body 20 facing the source-side selection gate SGS functions as a channel, and the memory film 30 between the channel and the source-side selection gate SGS functions as a source-side selection transistor STS. The gate insulating film functions. A plurality of drain-side selection transistors STD connected in series through the semiconductor body 20 may be provided, and a plurality of source-side selection transistors STS connected in series through the semiconductor body 20 may be provided. The same gate potential is assigned to the plurality of drain-side selection transistors STD of the plurality of drain-side selection transistors STD, and the same source is selected to the plurality of source-side selection gates SGS of the plurality of source-side selection transistors STS. Gate potential. A plurality of memory cells MC are provided between the drain-side selection transistor STD and the source-side selection transistor STS. The plurality of memory cells MC, the drain-side selection transistor STD, and the source-side selection transistor STS are connected in series through the semiconductor body 20 of the columnar portion CL to form a memory string. The memory strings are arranged, for example, in a plane direction parallel to the XY plane, and a plurality of memory cells MC are three-dimensionally arranged in the X direction, the Y direction, and the Z direction. The side wall portion 20a of the semiconductor body 20 is in contact with the semiconductor layer 13 doped with impurities (for example, phosphorus), and the side wall portion 20a also contains impurities (for example, phosphorus). The impurity concentration of the side wall portion 20 a is higher than the impurity concentration of the portion of the semiconductor body 20 that faces the laminated body 100. The impurity concentration of the side wall portion 20a is higher than the impurity concentration of the channel of the memory cell MC, the impurity concentration of the channel of the source-side selection transistor STS, and the impurity concentration of the drain-side selection gate STD. In addition, by the following heat treatment, impurities (for example, phosphorus) are diffused from the side wall portion 20 a to the portion 20 b of the semiconductor body 20 facing the gate layer 80. A portion (a portion corresponding to the insulating layer 44) between the side wall portion 20 a and the portion 20 b in the semiconductor body 20 also contains impurities (for example, phosphorus). The impurities do not diffuse throughout the entire area of the portion 20b of the semiconductor body 20, and the impurity concentration of the area on the side of the laminate 100 in the portion 20b is lower than that on the side of the side wall portion 20a in the portion 20b. The portion 20b has a gradient in which the impurity concentration decreases from the side of the side wall portion 20a toward the side of the laminated body 100. The impurity concentration of the region on the side of the side wall portion 20a of the portion 20b is higher than the impurity concentration of the portion of the semiconductor body 20 that faces the laminated body 100. During the read operation, electrons are supplied from the source layer SL to the channel of the memory cell MC through the side wall portion 20 a of the semiconductor body 20. At this time, by applying an appropriate potential to the gate layer 80, a channel (n-channel) can be induced in the entire region of the portion 20b of the semiconductor body 20. The memory film 30 between the portion 20b of the semiconductor body 20 and the gate layer 80 functions as a gate insulating film. Since the portion 20b of the semiconductor body 20 contains impurities as described above, there may be cases where it is difficult to turn off the portion 20b by controlling the potential of the gate layer 80, but the function of the cutoff is assumed by the source-side selection transistor STS. The above impurities are not diffused to the channel of the source-side selection transistor STS. The distance between the side wall portion 20 a and the portion 20 b of the semiconductor body 20 is smaller than the thickness of the gate layer 80. The distance between the side wall portion 20a and the portion 20b of the semiconductor body 20 substantially corresponds to the total thickness of the thickness of the semiconductor layer 14 and the thickness of the insulating layer 44. As an etch stop layer when the slit ST is formed as described below, a thicker gate layer 80 is used. Therefore, the semiconductor layer 14 can be made thin. The thickness of the gate layer 80 is, for example, about 200 nm, and the thickness of the semiconductor layer 14 is, for example, about 30 nm. Therefore, it is possible to shorten the distance from which the impurities diffuse from the side wall portion 20 a to the portion facing the insulating layer 44 in the semiconductor body 20, and it is easy to control the diffusion of the impurities to a region where it is difficult to induce a channel by the gate layer 80. In addition, since the portion 20b facing the gate layer 80 in the semiconductor body 20 contains impurities, the gate layer 80 can be used as a GIDL (gate induced drain leakage) generator during the erasing operation. Function. An erase potential (for example, several volts) is applied to the gate layer 80, and a hole generated by applying a high electric field to the portion 20b of the semiconductor body 20 is supplied to a channel of the memory cell MC to increase the channel potential. Then, the potential of the cell gate CG is set to, for example, a ground potential (0 V), and a hole is injected into the charge accumulation film 32 by using a potential difference between the semiconductor body 20 and the cell gate CG to perform a data erasing operation. Next, a method for manufacturing a semiconductor device according to an embodiment will be described with reference to FIGS. 4 to 17. The cross sections of FIGS. 4 to 17 correspond to the cross section of FIG. 2. As shown in FIG. 4, an insulating layer 41 is formed on the substrate 10. A metal-containing layer 11 is formed on the insulating layer 41. The metal-containing layer 11 is, for example, a tungsten layer or a tungsten-silicon alloy layer. A semiconductor layer (first semiconductor layer) 12 is formed on the metal-containing layer 11. The semiconductor layer 12 is, for example, a polycrystalline silicon layer doped with phosphorus. The thickness of the semiconductor layer 12 is, for example, about 200 nm. A protective film 42 is formed on the semiconductor layer 12. The protective film 42 is, for example, a silicon oxide film. A sacrificial layer 91 is formed on the protective film 42. The sacrificial layer 91 is, for example, an undoped polycrystalline silicon layer. The thickness of the sacrificial layer 91 is, for example, about 30 nm. A protective film 43 is formed on the sacrificial layer 91. The protective film 43 is, for example, a silicon oxide film. A semiconductor layer (second semiconductor layer) 14 is formed on the protective film 43. The semiconductor layer 14 is, for example, a polycrystalline silicon layer that is undoped or doped with phosphorus. The thickness of the semiconductor layer 14 is, for example, about 30 nm. An insulating layer 44 is formed on the semiconductor layer 14. The insulating layer 44 is, for example, a silicon oxide layer. A gate layer 80 is formed on the insulating layer 44. The gate layer 80 is, for example, a polycrystalline silicon layer doped with phosphorus. The thickness of the gate layer 80 is thicker than the thickness of the semiconductor layer 14 and the thickness of the insulating layer 44, and is, for example, about 200 nm. As shown in FIG. 5, a laminated body 100 is formed on the gate layer 80. The insulating layer (second layer) 72 and the sacrificial layer (first layer) 71 are alternately laminated on the gate layer 80. The step of alternately stacking the insulating layers 72 and the sacrificial layers 71 is repeated to form a plurality of sacrificial layers 71 and a plurality of insulating layers 72 on the gate layer 80. An insulating layer 45 is formed on the uppermost sacrificial layer 71. For example, the sacrificial layer 71 is a silicon nitride layer, and the insulating layer 72 is a silicon oxide layer. The thickness of the gate layer 80 is thicker than the thickness of one layer of the sacrificial layer 71 and the thickness of one layer of the insulating layer 72. As shown in FIG. 6, a plurality of memory holes MH are formed in a layer above the semiconductor layer 12. The memory hole MH is formed by a reactive ion etching (RIE) method using a mask layer (not shown). The memory hole MH penetrates the laminated body 100, the gate layer 80, the insulating layer 44, the semiconductor layer 14, the protective film 43, the sacrificial layer 91, and the protective film 42, and reaches the semiconductor layer 12. The bottom of the memory hole MH is located in the semiconductor layer 12. The plurality of sacrificial layers (silicon nitride layers) 71 and the plurality of insulating layers (silicon oxide layers) 72 are continuously etched without using the same gas (for example, CF-based gas). At this time, the gate layer (polycrystalline silicon layer) 80 functions as an etch stop layer, and the etching is temporarily stopped at the position of the gate layer 80. The thicker gate layer 80 absorbs uneven etching rates among the plurality of memory holes MH, and reduces unevenness of the bottom positions among the plurality of memory holes MH. Thereafter, each layer is etched by switching the type of gas. That is, the remaining portion of the gate layer 80 is etched using the insulating layer 44 as the stop layer, the insulating layer 44 is etched using the semiconductor layer 14 as the stop layer, and the semiconductor layer 14 is etched using the protective film 43 as the stop layer. The protective film 43 is etched by the sacrificial layer 91 as a stop layer, the sacrificial layer 91 is etched by using the protective film 42 as a stop layer, and the protective film 42 is etched by using the semiconductor layer 12 as a stop layer. Then, the etching is stopped in the middle of the thicker semiconductor layer 12. With the thicker gate layer 80, it becomes easy to control the etching stop position of the hole processing of the laminated body 100 having a relatively high aspect ratio. As shown in FIG. 7, a columnar portion CL is formed in the memory hole MH. A memory film 30 is conformally formed along the side and bottom of the memory hole MH, a semiconductor body 20 is conformally formed along the memory film 30 inside the memory film 30, and a core film 50 is formed inside the semiconductor body 20. Thereafter, as shown in FIG. 8, a plurality of slits ST are formed in the laminated body 100. The slit ST is formed by an RIE method using a mask layer (not shown). The slit ST penetrates the laminated body 100 and reaches the gate layer 80. Similar to the formation of the memory hole MH, the plurality of sacrificial layers 71 and the plurality of insulating layers 72 are continuously etched using the same gas (for example, CF-based gas) without switching the gas type. At this time, the gate layer 80 functions as an etch stop layer, and the slit processing etching is temporarily stopped at the position of the gate layer 80. The thicker gate layer 80 absorbs unevenness in the etching rate between the plurality of slits ST, and reduces unevenness in the position of the bottom between the plurality of slits ST. Thereafter, each layer is etched by switching the type of gas. That is, the remaining portion of the gate layer 80 is etched using the insulating layer 44 as a stop layer. As shown in FIG. 9, the insulating layer 44 is exposed at the bottom of the slit ST. After that, the insulating layer 44 is etched using the semiconductor layer 14 as a stop layer, and the semiconductor layer 14 is etched using the protective film 43 as a stop layer. As shown in FIG. 10, the sacrificial layer 91 is exposed at the bottom of the slit ST. With the thicker gate layer 80, it is easy to control the etching stop position for the slit processing of the laminated body 100 having a relatively high aspect ratio. Furthermore, in the subsequent step etching, the bottom position control of the slit ST can be performed with high accuracy and easily. The slit ST does not pass through the sacrificial layer 91, and the bottom of the slit ST stops inside the sacrificial layer 91. As shown in FIG. 11, a liner film 161 is conformally formed along the side and bottom of the slit ST along the side and bottom of the slit ST. The liner film 161 is, for example, a silicon nitride film. The liner film 161 formed on the bottom of the slit ST is removed by, for example, the RIE method. As shown in FIG. 12, the sacrificial layer 91 is exposed at the bottom of the slit ST. Then, the sacrificial layer 91 is removed by etching through the slit ST. For example, heat TMY (trimethyl-2hydroxyethylammonium hydroxide) is supplied through the slit ST to remove the sacrificial layer 91 as a polycrystalline silicon layer. The sacrificial layer 91 is removed. As shown in FIG. 13, a cavity 90 is formed between the semiconductor layer 12 and the semiconductor layer 14. For example, the protective films 42, 43 as silicon oxide films protect the semiconductors 12, 14 from thermal TMY etching. In addition, a liner film (for example, a silicon nitride film) 161 formed on the side surface of the slit ST prevents side erosion of the gate layer 80 and the semiconductor layer 14 from the slit ST side. In the cavity 90, a part of a side wall of the columnar portion CL is exposed. That is, a part of the memory film 30 is exposed. A portion of the memory film 30 exposed in the cavity 90 is removed by etching through the slit ST. For example, the memory film 30 is etched by a CDE (chemical dry etching) method. At this time, the same kinds of protective films 42 and 43 as those included in the memory film 30 are also removed. The backing film 161 formed on the side of the slit ST is a silicon nitride film of the same kind as the charge storage film 32 included in the memory film 30, but the film thickness of the backing film 161 is thicker than that of the charge storage film 32. The liner film 161 remains on the side of the slit ST. The liner film 161 prevents side etching of the sacrificial layer 71, the insulating layer 72, and the insulating layer 44 from the slit ST side when a part of the memory film 30 exposed in the cavity 90 is removed. In addition, since the lower surface of the insulating layer 44 is covered by the semiconductor layer 14, the etching of the insulating layer 44 from the lower surface side is also prevented. By removing a part of the memory film 30, the memory film 30 is divided up and down at a portion of the side wall portion 20a as shown in FIG. By controlling the etching time, the memory film (gate insulating film) 30 between the gate layer 80 and the semiconductor body 20 is not etched. In addition, by controlling the etching time, the memory film 30 remains between the semiconductor layer 12 and the semiconductor body 20 even under the side wall portion 20a. A state in which the lower end portion of the semiconductor body 20 below the sidewall portion 20 a is supported by the semiconductor layer 12 with the memory film 30 interposed therebetween is maintained. A part of the memory film 30 is removed. As shown in FIG. 14, a part of the semiconductor body 20 (side wall portion 20 a) is exposed in the cavity 90. As shown in FIG. 15, a semiconductor layer (third semiconductor layer) 13 is formed in the cavity 90. The semiconductor layer 13 is, for example, a polycrystalline silicon layer doped with phosphorus. The silicon-containing gas is supplied to the cavity 90 through the slit ST, and the semiconductor layer 13 is epitaxially grown from the upper surface of the semiconductor layer 12, the lower surface of the semiconductor layer 14, and the side wall portion 20a of the semiconductor body 20 exposed from the cavity 90. The cavity 90 is filled with the semiconductor layer 13. A semiconductor layer 14 as a polycrystalline silicon layer is also formed on the upper surface of the cavity 90. Therefore, the semiconductor layer 13 can also be epitaxially grown from the upper surface side of the cavity 90, thereby reducing the time required to form the semiconductor layer 13. The side wall portion 20 a of the semiconductor body 20 is in contact with the semiconductor layer 13. At the stage where the columnar portion CL is formed, the semiconductor body 20 does not substantially contain impurities from the upper end to the lower end. The semiconductor layer 13 is epitaxially grown under a high temperature heat treatment. At this time, the side wall portion 20 a of the semiconductor body 20 is also doped with impurities (for example, phosphorus). Furthermore, by the heat treatment during the epitaxial growth of the semiconductor layer 13 or the heat treatment in the subsequent steps, impurities (phosphorus) are thermally diffused from the side wall portion 20 a to the extending direction of the semiconductor body 20. The impurities diffuse into at least a portion of the semiconductor body 20 that opposes the insulating layer 44. That is, impurities are diffused to a region where it is difficult to induce a channel using the gate layer 80. As described above, the function of the absorption layer having a difference in etching rate when forming the memory hole MH or the slit ST is assumed by the gate layer 80. Therefore, the semiconductor layer 14 need not be thickened. Therefore, it is possible to shorten a distance for diffusing impurities from the side wall portion 20 a of the semiconductor body 20 to a portion facing the insulating layer 44. For example, the diffusion distance is about 50 nm, and impurities can be easily and surely diffused to a portion of the semiconductor body 20 facing the insulating layer 44. In addition, if impurities are diffused into the portion 20b of the semiconductor body 20 opposite to the gate layer 80, as described above, a hole of GIDL is generated in the portion 20b, and an erasing operation using the hole can be performed. Next, after the liner film 161 is removed, or in the same step as the liner film 161 is removed, the sacrificial layer 71 is removed by an etching solution or an etching gas supplied through the slit ST. For example, the sacrificial layer 71 as a silicon nitride layer is removed using an etching solution containing phosphoric acid. The sacrificial layer 71 is removed. As shown in FIG. 16, a gap 75 is formed between the upper and lower adjacent insulating layers 72. The gap 75 is also formed between the uppermost insulating layer 72 and the insulating layer 45. The plurality of insulating layers 72 are in contact with the side surfaces of the columnar portions CL so as to surround the side surfaces of the plurality of columnar portions CL. The plurality of insulating layers 72 are supported by this physical combination with the plurality of columnar portions CL, and the gaps 75 between the insulating layers 72 can be maintained. As shown in FIG. 17, an electrode layer 70 is formed in the gap 75. The electrode layer 70 is formed by, for example, a CVD (chemical vapor deposition) method. The source gas is supplied to the gap 75 through the slit ST. The electrode layer 70 formed on the side surface of the slit ST is removed. Thereafter, as shown in FIG. 2, an insulating film 163 is embedded in the slit ST. The sacrificial layer 91 is not limited to a polycrystalline silicon layer, and may be, for example, a silicon nitride layer. In the case of the combination of the semiconductor layers 12 and 14 as the polycrystalline silicon layer and the sacrificial layer 91 as the silicon nitride layer, the protective films 42 and 43 may not be provided. FIG. 18 is a schematic sectional view showing another example of the memory cell array according to the embodiment. The semiconductor layer 13 is provided along the upper surface of the semiconductor layer 12, the lower surface of the semiconductor layer 14, and the sidewall portion 20 a of the semiconductor body 20. The semiconductor layer 13 provided on the upper surface of the semiconductor layer 12 and the semiconductor layer 13 provided on the semiconductor layer 14. A cavity 90 is left between the semiconductor layers 13 on the lower surface. If the semiconductor layer 13 is embedded in the cavity 90 in an insufficient state, and pores are generated in the semiconductor layer 13, the pores may move in the subsequent high-temperature heat treatment step and the side wall portion 20 a of the semiconductor body 20 may be disconnected. As shown in FIG. 18, the semiconductor layer 13 is formed as a thin film along the upper surface of the semiconductor layer 12, the lower surface of the semiconductor layer 14, and the sidewall portion 20 a of the semiconductor body 20, and a cavity is left inside the semiconductor layer 13. 90, there are no pores such as moving. In the above embodiment, a silicon nitride layer is exemplified as the first layer 71, but a metal layer or a silicon layer doped with impurities may be used as the first layer 71. In this case, the first layer 71 directly becomes the electrode layer 70. Therefore, there is no need to replace the first layer 71 with the electrode layer. In addition, the second layer 72 may be removed by etching through the slit ST, so that a gap is formed between the electrode layers 70 adjacent to each other. Although some embodiments of the present invention have been described, these embodiments are proposed as examples and are not intended to limit the scope of the invention. The novel embodiments can be implemented in various other forms without departing from the invention. Various omissions, substitutions, and changes are made within the scope of the gist. These embodiments or variations thereof are included in the scope or gist of the invention, and are included in the invention described in the scope of the patent application and their equivalent scope. [Related Application] This application has priority based on Japanese Patent Application No. 2017-36973 (application date: February 28, 2017). This application contains the entire contents of the basic application by referring to the basic application.

1‧‧‧ memory cell array

10‧‧‧ substrate

11‧‧‧ layer containing metal

12‧‧‧ silicon layer

13‧‧‧ silicon layer

14‧‧‧ silicon layer

20‧‧‧ semiconductor body

20a‧‧‧ sidewall

20b‧‧‧part

30‧‧‧membrane

31‧‧‧Tunnel insulation film

32‧‧‧ Charge accumulation film (charge accumulation section)

33‧‧‧ barrier insulating film

41‧‧‧ Insulation

42‧‧‧ protective film

43‧‧‧ protective film

44‧‧‧ Insulation

45‧‧‧ Insulation

50‧‧‧ core membrane

70‧‧‧ electrode layer

71‧‧‧ sacrificial layer

72‧‧‧ Insulation

75‧‧‧Gap

80‧‧‧Gate layer

90‧‧‧ cavity

91‧‧‧ sacrificial layer

100‧‧‧Laminated body

160‧‧‧ Separation Department

161‧‧‧lining film

163‧‧‧Insulation film

BL‧‧‧bit line

Cb‧‧‧ contact

CG‧‧‧ Cell Gate

CL‧‧‧Columnar

MC‧‧‧Memory Cell

MH‧‧‧Memory hole

SGD‧‧‧ Select gate on drain side

SGS‧‧‧Source side selection gate

SL‧‧‧Source layer

ST‧‧‧Slit

STD‧‧‧Drain side selection transistor

STS‧‧‧Source side selection transistor

V1‧‧‧ contact

X‧‧‧ direction

Y‧‧‧ direction

Z‧‧‧ direction

FIG. 1 is a schematic perspective view of a semiconductor device according to an embodiment. FIG. 2 is a schematic cross-sectional view of a semiconductor device according to an embodiment. FIG. 3 is an enlarged sectional view of part A in FIG. 2. 4 to 17 are schematic sectional views showing a method for manufacturing a semiconductor device according to the embodiment. FIG. 18 is a schematic cross-sectional view of a semiconductor device according to an embodiment.

Claims (20)

A semiconductor device includes: a source layer having a semiconductor layer containing impurities; a laminated body provided on the source layer and having a plurality of electrode layers laminated with an insulating margin; a gate layer provided with Between the source layer and the laminated body, and thicker than the thickness of one layer of the electrode layer; a semiconductor body, which is laminated in the laminated body, in the gate layer, and in the semiconductor layer along the laminated body It extends in a direction, has a side wall portion that is in contact with the semiconductor layer, and does not contact the electrode layer and the gate layer; and a charge accumulation portion, which is provided between the semiconductor body and the electrode layer. The semiconductor device according to claim 1, wherein a distance between a portion of the semiconductor body facing the gate layer and the side wall portion is smaller than a thickness of the gate layer. The semiconductor device according to claim 1, wherein an impurity concentration of the side wall portion of the semiconductor body is higher than an impurity concentration of a portion of the semiconductor body facing the laminated body. The semiconductor device according to claim 1, wherein an impurity concentration of a portion of the semiconductor body facing the gate layer is higher than an impurity concentration of a portion of the semiconductor body facing the laminated body. The semiconductor device according to claim 1, wherein the electrode layer has: at least one drain-side selection gate, which is thinner than the gate layer; at least one source-side selection gate, which is disposed on the drain-side selection gate. Between the gate and the gate layer, and thinner than the gate layer; and a plurality of cell gates, which are disposed between the drain-side selection gate and the source-side selection gate and accumulate with the charge The parts are opposite to each other and are thinner than the above gate layers, respectively. The semiconductor device according to claim 1, wherein the gate layer is a silicon layer containing phosphorus. The semiconductor device according to claim 1, wherein the semiconductor layer is a silicon layer containing phosphorus. The semiconductor device according to claim 1, wherein the source layer further includes a metal-containing layer, and the semiconductor layer is provided between the metal-containing layer and the gate layer. The semiconductor device according to claim 1, wherein the charge accumulation portion is continuous between the laminated body and the semiconductor body in the laminated direction. The semiconductor device according to claim 9, wherein an insulating film including a film of the same type as the charge storage portion is provided between the gate layer and the semiconductor body. The semiconductor device according to claim 9, wherein an insulating film including a film of the same type as that of the charge accumulation portion is provided below the bottom surface of the semiconductor body. For example, in the semiconductor device of claim 1, during the erasing operation, a potential of GIDL (gate induced drain leakage) in a portion of the semiconductor body opposite to the gate layer is applied to the gate layer. The semiconductor device according to claim 1, wherein the semiconductor layer includes: a first semiconductor layer; a second semiconductor layer provided between the first semiconductor layer and the gate layer; and a third semiconductor layer, which is formed along the The upper surface of the first semiconductor layer, the lower surface of the second semiconductor layer, and the sidewall portion of the semiconductor body are provided; and the third semiconductor layer and the third semiconductor layer are provided on the upper surface of the first semiconductor layer. A cavity is formed between the third semiconductor layer on the lower surface of the second semiconductor layer. A method for manufacturing a semiconductor device includes the following steps: forming a sacrificial layer on a first semiconductor layer; forming a second semiconductor layer on the sacrificial layer; forming an insulating layer on the second semiconductor layer; and forming on the insulating layer A gate layer thicker than the second semiconductor layer; forming a laminated body having a plurality of first layers and a plurality of second layers including the first layer and the second layer that are alternately laminated on the gate layer; A semiconductor body is formed in the laminated body, the gate layer, the insulating layer, the second semiconductor layer, and the sacrifice layer; after the semiconductor body is formed, a through body is formed through the laminated body, the gate layer, and the insulation. Layer, and a slit of the second semiconductor layer and reaching the sacrificial layer; removing the sacrificial layer through the slit to form a cavity between the first semiconductor layer and the second semiconductor layer; A part is exposed in the cavity; and a third semiconductor layer containing impurities and in contact with the part of the semiconductor body is formed in the cavity. The method for manufacturing a semiconductor device according to claim 14, wherein the first semiconductor layer, the second semiconductor layer, the sacrificial layer, and the gate layer are silicon layers between the first semiconductor layer and the sacrificial layer. And a protective film having a material different from that of the silicon layer is formed between the sacrificial layer and the second semiconductor layer, and the sacrificial layer is removed in a state where a side surface of the slit is covered with a liner film different from the silicon layer. The method for manufacturing a semiconductor device according to claim 14, wherein the first semiconductor layer, the second semiconductor layer, and the gate layer are silicon layers, and the sacrificial layer is a silicon nitride layer. The method for manufacturing a semiconductor device according to claim 14, wherein an insulating film is formed on the side of the hole before the semiconductor body is formed, and after removing the sacrificial layer, a part of the insulating film exposed from the cavity is removed. The part of the semiconductor body is exposed in the cavity. The method for manufacturing a semiconductor device according to claim 14, wherein when the third semiconductor layer is formed, or after the third semiconductor layer is formed, the impurities are directed to the part of the semiconductor body and the insulating layer in the semiconductor body. The opposite part is thermally diffused. The method for manufacturing a semiconductor device according to claim 18, wherein the above-mentioned impurities are also diffused to a portion of the above-mentioned semiconductor body that is opposed to the above-mentioned gate layer. The method for manufacturing a semiconductor device according to claim 14, further comprising the step of replacing the first layer with an electrode layer through the slit.