TW201822466A - Phase-locked loop method for utility power parallel connection system for overcoming voltage distortion of input utility power and achieving precise synchronization - Google Patents

Abstract

The present invention provides a phase-locked loop method for utility power parallel connection system, which includes a conversion signal generation step, an error calculation step, a frequency correction signal obtaining step, an angle signal obtaining step, and a synchronous signal generation step, so as to calculate the value of error by means of detection of the utility power voltage and reduce or zero the value of error by means of proportional integral adjustment. Thus, with the aforementioned steps, the present invention may overcome the voltage distortion and frequency change of the input utility power and thus achieve a precise synchronization effect. Moreover, the present invention may achieve the advantage of fast response and may be provided with a very wide frequency range for tracking the power generation equipment, such as a diesel power generator, and expanding the application range of an inverter.

Description

Phase-locked loop method for mains parallel system

The present invention discloses a phase-locked loop method, and more particularly, relates to a phase-locked loop method for a parallel connection system of utility power.

In a city power parallel system, there is usually an inverter circuit that can be controlled digitally. The inverter circuit detects the city power voltage to generate a sinusoidal synchronization signal, which is used to provide the current in the inverter circuit The loop or AC voltage control loop enables the voltage, frequency, and phase of the inverter circuit to be the same as the voltage, frequency, and phase of the mains, thereby enabling power flow control between the two.

A conventional inverter circuit 1000 is shown in FIG. 1. It uses a comparator or an operational amplifier 1100 to detect the zero crossing point of the mains voltage V _S. The zero crossing signal S _{ZERO is} divided by a digital capture (Capture) 1200. In addition to calculating its frequency, this zero-crossing signal S _{ZERO is} also used to reset a preset sine table 1300 to generate the synchronous sine wave signal S _SIN required by the inverter circuit 1000.

However, when using the inverter circuit 1000 described above, it is easy to cause the reset signal to oscillate due to the mains voltage distortion, the zero crossing signal oscillation of the detection circuit, etc., and then cause the sine wave table to oscillate. In order to solve this problem, although a low-pass filter can be used to improve the detected mains voltage waveform, or a comparator with hysteresis can slow down the signal oscillation problem, however, this will cause a phase delay problem of the sine wave table, which is difficult to apply to voltage frequency changes Wider application.

One object of the present invention is to provide a phase-locked loop method, which can overcome the problems of input mains voltage distortion and frequency change, and accurately achieve synchronization, so that the inverter is not easily affected by mains disturbance and maintains normal operation.

Another object of the present invention is to provide a phase-locked loop method, which has the advantage of fast response and has a relatively wide frequency range, which can be used for tracking power generation equipment such as diesel generators to expand the application range of inverters.

To achieve the above and other objectives, the present invention provides a phase-locked loop method for a commercial power parallel system. The phase-locked loop method includes a conversion signal generation step, an error calculation step, a frequency correction signal acquisition step, and an angle. A signal obtaining step and a synchronous signal generating step.

The conversion signal generating step is to generate a first conversion signal and a second conversion signal by detecting a voltage of a utility power. The first conversion signal is a first function form, and the second conversion signal is a second function. Form; the error calculation step is to obtain an error value by calculating values of the first conversion signal, the second conversion signal, a first synchronization signal, and a second synchronization signal, and the first synchronization signal is the first A two-function form, the second synchronization signal is the first function form; the frequency correction signal obtaining step is to input an error signal having the error value to a proportional integrator to obtain a frequency correction signal; the angle signal obtaining step It first obtains an adjusted frequency by adding the frequency correction signal to the original frequency, and then integrates the adjusted frequency to obtain an angle signal; and the synchronization signal generation step refers to a first function table and a second function respectively Table to obtain the value corresponding to the angle value of the angle signal, and the value corresponding to the angle value of the angle signal in the first function table is used as the first same Value signal, the value of the angle signal of the angle value based on the second function table corresponding to the second value as the synchronization signal.

In an embodiment of the phase-locked loop method of the present invention, the first function table is a sine table, the second function table is a cosine table, and the phase of the first synchronization signal and the phase The phase difference of the phase of the second synchronization signal is 90 degrees.

In an embodiment of the phase-locked loop method of the present invention, the error calculation step includes a first product obtaining step, a second product obtaining step, and an error value obtaining step. The first product obtaining step is to convert the first conversion Multiplying the value of the signal and the first synchronization signal to obtain a first product; the step of obtaining the second product is to multiply the value of the second conversion signal by the value of the second synchronization signal to obtain a second product; And the error value obtaining step is to subtract the second product from the first product to obtain the error value.

In an embodiment of the phase-locked loop method of the present invention, an angle limiting step is further included between the angle signal obtaining step and the synchronization signal generating step. The angle value of the angle signal is first limited by a range limiter. Within a range.

In an embodiment of the phase-locked loop method of the present invention, the mains has a three-phase voltage. In the step of generating the conversion signal, the first conversion signal and the second are generated by detecting the three-phase voltage of the mains. Conversion signal.

In an embodiment of the phase-locked loop method of the present invention, the mains has a single-phase voltage. In the conversion signal generating step, the first conversion signal and the second are generated by detecting the single-phase voltage of the mains. Conversion signal.

In an embodiment of the phase-locked loop method of the present invention, the conversion signal generating step further includes a sampling step, which generates the first conversion signal by sampling the detected mains voltage.

In an embodiment of the phase-locked loop method of the present invention, the conversion signal generating step further includes a delaying step. The second conversion signal is generated by delaying the first conversion signal.

With this, the phase-locked loop method of the present invention can achieve the effect of accurately synchronizing over the input mains voltage distortion and frequency change through the above steps. In addition, it can achieve the advantages of fast response and a wide frequency range. Efficiency, used to track diesel generators and other power generation equipment, to expand the scope of application of inverters.

In order to fully understand the purpose, features and effects of the present invention, the following specific embodiments are used in conjunction with the accompanying drawings to make a detailed description of the present invention, which will be described later:

Please refer to FIG. 2. FIG. 2 is a system block diagram of an embodiment of a parallel connection system 100 for commercial power using the phase locked loop method of the present invention. As shown in FIG. 2, the mains parallel system 100 includes a phase-locked loop 110, an isolation protection element 120, a voltage controller 130, a current controller 140, a sinusoidal PWM driver 150 and a The inverter 160 includes a DC bus 161, a MOSFET module 162, and an LC filter 163, and the LC filter 163 is connected to a mains power grid.

The phase-locked loop 110 detects the mains voltage V _S and gradually reduces the error (such as a phase difference) between the output signal (for example, a sine wave signal) and the mains voltage V _S through an internal tracking adjustment mechanism, thereby enabling The voltage, frequency, and phase of the inverter 160 are made the same as the voltage, frequency, and phase of the mains to perform power flow control between the two.

It is worth noting that the mains parallel system 100 of FIG. 2 is just one example of many parallel mains systems. The scope of application of the phase locked loop method of the present invention is not limited to the mains parallel system 100 of FIG. 2. The phase locked loop of the present invention The method is applicable to various types of parallel power systems, including at least a grid-connected renewable energy power generation system and a UPS (Uninterruptible Power Supply).

Next, please refer to FIG. 3, which is a flowchart of a phase locked loop method according to the present invention. As shown in FIG. 3, the phase-locked loop method includes a conversion signal generation step S110, an error calculation step S120, a frequency correction signal acquisition step S130, an angle signal acquisition step S140, and a synchronization signal generation step S150.

The conversion signal generating step S110 generates a first conversion signal S1 and a second conversion signal S2 by detecting the mains voltage V _S. In an embodiment, the value of the first conversion signal S1 is V _m sin ( wt), the first conversion signal S1 is in the form of a sine function, so the sine function is called a first function, and the first conversion signal S1 is in a first function form; the value of the second conversion signal S2 is V _m cos (wt) Since the second conversion signal S2 is in the form of a cosine function, the cosine function is called a second function, and the second conversion signal S2 is in the form of a second function. In addition, V _m represents the rms voltage of the mains, w represents the original frequency, and t represents time.

It is worth noting that although the first function and the second function are sine function and cosine function respectively in this embodiment, they are not limited thereto. For example, in other possible embodiments, the first function may be It is in the form of a cosine function and the second function corresponds to the form of a sine function.

The error calculation step S120 is to obtain an error value e by calculating the values of the first conversion signal S1, the second conversion signal S2, a first synchronization signal S3, and a second synchronization signal S4. In an embodiment, The value of the first synchronization signal S3 is cos (w ₁ t), the first synchronization signal S3 is in the form of a cosine function, so the first synchronization signal S3 is in the form of a second function, and the value of the second synchronization signal S4 Is sin (w ₁ t), the second synchronization signal S4 is in the form of a sine function, so the second synchronization signal S4 is in the form of a first function. In addition, w ₁ represents the adjusted frequency after frequency correction.

For example, the error value e can be calculated using the following formula: e = V _m {sin (wt) cos (w ₁ t)-cos (wt) sin (w ₁ t)}.

Among them, V _m sin (wt) cos (w ₁ t) is called a first product, and the first product is equal to the result of multiplying the values of the first conversion signal S1 and the first synchronization signal S3; V _m cos ( wt) sin (w ₁ t) is called a second product, and the second product is equal to the result of multiplying the value of the second conversion signal S2 and the second synchronization signal S4; the error value e is equal to the first product minus Go to that second product.

The frequency correction signal obtaining step S130 is to input an error signal having the error value e into a proportional integrator to obtain a frequency correction signal S5, and the value of the frequency correction signal S5 is Δw.

The angle signal obtaining step S140 is to first obtain the adjustment frequency w ₁ by adding the frequency correction signal Δw and the original frequency w, and then integrate the adjustment frequency w ₁ to obtain an angle signal q, that is, w ₁ = w + △ w, q is obtained by integrating w ₁ .

The synchronization signal generating step S150 refers to a first function table T1 and a second function table T2 to obtain the values corresponding to the angle value of the angle signal q. In this embodiment, the first function table T1 is a cosine. Cosine table. The second function table T2 is a sine table. The phase difference between the phase of the first synchronization signal S3 and the phase of the second synchronization signal S4 is 90 degrees. Therefore, if , Then after consulting the first function table T1, After consulting the second function table T2, we can get .

Further, as shown in FIG. 4, an angle limiting step S160 is further included between the angle signal obtaining step S140 and the synchronization signal generating step S150. The angle limiting step S160 first uses a range limiter to limit the angle signal. The angle value of q is limited to a range, for example, within the range of 0 to 2π. With the angle limitation step S160, it can be confirmed that the angle value of the angle signal q must fall within a predetermined range after conversion, and let The sizes of the first function table T1 and the second function table T2 are appropriately controlled, for example, there is no need to consider , The problem of the corresponding values of the first function table T1 and the second function table T2, because after conversion, q must fall within the range of 0 ~ 2π, and after conversion, the calculated sinq and cosq values will still be the same. .

The corresponding value of the angle value of the angle signal q in the first function table T1 is taken as the value of the first synchronization signal S3, that is, the value of the first synchronization signal S3 is cos (w ₁ t), the angle The corresponding value of the angle value of the signal q in the second function table T2 is taken as the value of the second synchronization signal S4, that is, the value of the second synchronization signal S4 is sin (w ₁ t). For example, if , Then the value of the first synchronization signal S3 is , The value of the first synchronization signal S4 is .

Through the above steps, the error e can be gradually changed to zero through proportional integral adjustment, so as to achieve the phase-locking purpose, that is, w ₁ = w, Δw = 0. Even if the mains voltage signal is distorted or the frequency is oscillating, the calculation of the phase-locked control loop can also use the feedback control of the control loop to attenuate the error caused by the distortion or frequency oscillating, thereby avoiding the problem of phase-locked signal oscillation.

In addition, compared with the conventional technique of using a detection circuit with a comparator or an operational amplifier, the phase-locked loop method of the present invention directly converts the mains voltage V _S into a first function form or a second function form. The method is helpful to speed up the response speed, and also helps to expand the applicable frequency range, so it can be used to track diesel generators and other power generation equipment.

With different types of commercial power, the phase-locked loop method of the present invention can also be correspondingly changed or adjusted. Hereinafter, please refer to FIGS. 5 to 7 and 8 to 10, and FIGS. 5 to 7 respectively show when the mains has three phases. A schematic diagram, an analog circuit diagram, and a simulation result diagram of an embodiment when voltage is applied. FIG. 8 to FIG. 10 are schematic diagrams, analog circuit diagrams, and simulation result diagrams of an embodiment when the mains has a single-phase voltage.

As shown in FIG. 5, the three-phase voltages of the mains are V _sa , V _sb, and V _{sc respectively} . After the abc- ab axis conversion, the value of the first conversion signal S1 can be obtained as V _m sin (wt) and the first The value of the second conversion signal S2 is V _m cos (wt). The first conversion signal S1 and the second conversion signal S2 are multiplied by the first synchronization signal S3 and the second synchronization signal S4, respectively, and then subtracted. The error value e is calculated, and a frequency correction signal Δw is obtained after passing through a proportional integrator PI.

Next, please refer to the analog circuit diagrams and simulation results of the simulation verification shown in Figure 6 and Figure 7. When setting the initial value of the voltage, the phase A phase of the three-phase input voltage is intentionally different from the Sine Table by 100 degrees. , Its error (Verr) is getting smaller and smaller, so that the input voltage (Vin_sin) can be in phase with the Sine Table (Vsin), and the frequency (Freq) is also locked to the same 60Hz as the mains voltage.

As shown in FIG. 8, the mains has a single-phase voltage. After a sampling step S111 and a delay step S112, the value of the first conversion signal S1 can be obtained as V _m sin (wt) and the value of the second conversion signal S2. Is V _m cos (wt), the first conversion signal S1 and the second conversion signal S2 are multiplied by the first synchronization signal S3 and the second synchronization signal S4, respectively, and then the error value e can be calculated. After the error value e passes a proportional integrator PI, a frequency correction signal Δw is obtained.

Next, please refer to the analog circuit diagrams and simulation results of the simulation verification shown in Figures 9 and 10. When setting the initial voltage value, the phase of the single-phase input voltage is intentionally different from the Sine Table by 100 degrees. The error (Verr) is getting smaller and smaller, so that the input voltage (Vin_sin) can be in phase with the Sine Table (Vsin), and the frequency (Freq) is also locked at 60Hz, which is the same as the mains voltage V _S.

In summary, the phase-locked loop method of the present invention can achieve the effect of accurately synchronizing over the input mains voltage distortion and frequency change through the above steps. In addition, it can achieve the advantages of fast response and a fairly wide frequency. The range of effectiveness is used to track diesel generators and other power generation equipment, and expand the scope of application of inverters.

The present invention has been disclosed in the foregoing with a preferred embodiment, but those skilled in the art should understand that this embodiment is only for describing the present invention, and should not be interpreted as limiting the scope of the present invention. It should be noted that all changes and substitutions equivalent to this embodiment should be included in the scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the scope of the patent application.

Vsa, Vsb, Vsc‧‧‧three-phase mains voltage

100‧‧‧ city electricity parallel system

110‧‧‧Phase Locked Loop

120‧‧‧Isolated protection element

130‧‧‧Voltage Controller

140‧‧‧Current Controller

150‧‧‧ sinusoidal pulse width modulation driver

160‧‧‧ Inverter

161‧‧‧DC bus

162‧‧‧MOSFET Module

163‧‧‧LC filter

1000‧‧‧ inverter circuit

1100‧‧‧ Operational Amplifier

1200‧‧‧Digital Capture

1300‧‧‧ sine wave table

S _ZERO ‧‧‧Zero crossing signal

S _SIN ‧‧‧Sine wave signal

T1‧‧‧first function table

T2‧‧‧Second function table

V _sa , V _sb , V _sc Three-phase voltage

V _S ‧‧‧ city voltage

S110 ~ S160‧‧‧step

S1‧‧‧First conversion signal

S2‧‧‧Second conversion signal

S3‧‧‧First sync signal

S4‧‧‧Second sync signal

S5‧‧‧ Frequency correction signal

[Fig. 1] is a schematic diagram of a conventional inverter circuit. [FIG. 2] A system block diagram of one embodiment of a parallel connection system of a commercial power system using the phase locked loop method of the present invention. 3 is a flowchart of an embodiment of a phase-locked loop method according to the present invention. 4 is a flowchart of another embodiment of a phase-locked loop method according to the present invention. [FIG. 5] A schematic diagram of an embodiment of the present invention when the mains has a three-phase voltage. 6 is an analog circuit diagram of an embodiment of the present invention when the mains has a three-phase voltage. FIG. 7 is a simulation result diagram of an embodiment of the present invention when the mains has a three-phase voltage. [FIG. 8] A schematic diagram of an embodiment of the present invention when the mains has a single-phase voltage. [FIG. 9] An analog circuit diagram of an embodiment of the present invention when the mains has a single-phase voltage. FIG. 10 is a simulation result diagram of an embodiment of the present invention when the mains has a single-phase voltage.

Claims (8)

A phase-locked loop method for a utility power parallel system includes: a conversion signal generating step, which detects a voltage of a utility power to generate a first conversion signal and a second conversion signal, the first conversion signal is a A first function form, the second conversion signal is a second function form; an error calculation step is performed by using the values of the first conversion signal, the second conversion signal, a first synchronization signal, and a second synchronization signal Operation to obtain an error value, the first synchronization signal is the second function form, and the second synchronization signal is the first function form; a frequency correction signal obtaining step is to input an error signal having the error value A proportional integrator to obtain a frequency correction signal; an angle signal acquisition step is to first obtain an adjusted frequency by adding the frequency correction signal to the original frequency, and then integrate the adjusted frequency to obtain an angle signal; and The step of generating the synchronization signal is to consult a first function table and a second function table to obtain the value corresponding to the angle value of the angle signal. The corresponding value of the angle value of the signal in the first function table is used as the value of the first synchronization signal, and the corresponding value of the angle value of the angle signal in the second function table is used as the value of the second synchronization signal. value. The phase-locked loop method according to claim 1, wherein the first function table is a sine table, the second function table is a cosine table, and the phase of the first synchronization signal and the phase The phase difference of the phase of the second synchronization signal is 90 degrees. The phase-locked loop method according to claim 1, wherein the error calculation step includes: a first product obtaining step of multiplying the first conversion signal and the value of the first synchronization signal to obtain a first product A second product obtaining step that multiplies the value of the second conversion signal and the second synchronization signal to obtain a second product; and an error value obtaining step that subtracts the first product from the first product Product of two to get the error value. The phase-locked loop method according to claim 1, wherein an angle limiting step is further included between the step of obtaining the angle signal and the step of generating the synchronization signal. The angle value of the angle signal is first obtained by a range limiter. Limited to a range. The phase-locked loop method according to claim 1, wherein the mains has a three-phase voltage, and in the step of generating the conversion signal, the first conversion signal and the second are generated by detecting the three-phase voltage of the mains Conversion signal. The phase-locked loop method according to claim 1, wherein the mains has a single-phase voltage, and in the conversion signal generating step, the first conversion signal and the second are generated by detecting the single-phase voltage of the mains Conversion signal. The phase-locked loop method according to claim 6, wherein the conversion signal generating step further includes a sampling step to generate the first conversion signal by sampling the detected mains voltage. The phase-locked loop method according to claim 7, wherein the conversion signal generating step further includes a delaying step for generating the second conversion signal by delaying the first conversion signal.