TW201822298A - Semiconductor structure - Google Patents

Abstract

The present invention relates to a semiconductor device and a method for forming the same, and more particularly, to a semiconductor device with reduced trench load effect. The present invention provides a novel multilayer cover film that employs one or more oxygen layers to reduce trench loading effects in semiconductor devices. The multilayer cover film may be composed of a hard metal mask and one or more oxygen layers. The metal hard mask may be formed of titanium nitride. The oxygen layer may be formed of tetraethoxysilane.

Description

   Semiconductor structure   

The embodiments of the present invention relate to the manufacturing process of the semiconductor structure, and more particularly, to a method for reducing a trench load effect.

The semiconductor integrated circuit industry has experienced exponential growth. The technical progress of integrated circuit materials and design makes each generation of integrated circuits have smaller and more complex circuits than the previous generation of integrated circuits. In the evolution of integrated circuits, the functional density (such as the number of interconnect devices per unit chip area) usually increases with decreasing geometric dimensions (such as the smallest component or circuit that can be produced by the process). The downsizing process usually helps to increase capacity and reduce related costs.

A semiconductor structure provided by an embodiment of the present invention includes: a dielectric layer formed on a substrate; a patterned oxygen layer formed on the dielectric layer; and a first trench and a second trench formed in the dielectric layer. It uses a patterned oxygen layer as a mask, wherein the width of the second trench is greater than the width of the first trench, and the depth of the second trench is substantially the same as the depth of the first trench.

D _M , D _N , D _X , D _Y ‧‧‧ Etching depth

W _M , W _N , W _X , W _Y ‧‧‧Width

100‧‧‧Semiconductor Structure

102‧‧‧ substrate

104‧‧‧Etch stop layer

106‧‧‧ Dielectric layer

201‧‧‧Multi-layer cover film

202‧‧‧oxy layer

204‧‧‧metal hard mask

206‧‧‧ District 1

207 _A , 207 _B , 207 _C , 209 _A , 209 _B , 607 _A , 607 _B , 607 _C , 609 _A , 609 _B

208‧‧‧Second District

406‧‧‧First depression

408‧‧‧Second depression

606‧‧‧ District 3

608‧‧‧Fourth District

706‧‧‧Third depression

708‧‧‧Fourth depression

900‧‧‧ Method

902, 904, 906, 908, 910‧‧‧ steps

FIG. 1 is a cross-sectional view of a semiconductor structure in some embodiments.

FIG. 2 is a cross-sectional view of a semiconductor structure after a multilayer cover film is deposited in some embodiments.

3A and 3B are cross-sectional views of a semiconductor structure after patterning a multilayer cover film in some embodiments.

FIG. 4 is a cross-sectional view of a semiconductor structure after using a multilayer cover film as an etching mask and etching a dielectric layer in some embodiments.

FIG. 5 is a cross-sectional view of the semiconductor structure after the multilayer cover film is removed in some embodiments.

6A and 6B are cross-sectional views of a semiconductor structure after patterning a multilayer cover film in some embodiments.

FIG. 7 is a cross-sectional view of a semiconductor structure after using a multilayer cover film as an etching mask and etching a dielectric layer in some embodiments.

8A and 8B are respectively a cross-sectional view and an isometric view of the semiconductor structure after the multilayer cover film is removed in some embodiments.

FIG. 9 is a flowchart of a method for reducing a trench effect in a semiconductor structure in some embodiments.

The different embodiments or examples provided below can implement different structures of the present invention. Examples of specific components and arrangements are provided to simplify the invention but not limit the invention. For example, the description of forming the first structure on the second structure includes direct contact between the two, or there are other additional structures between the two rather than direct contact. In addition, in various examples of the present invention, reference numerals may be repeated, but these repetitions are only for simplification and clear description, and do not represent that the units with the same reference numerals in different embodiments and / or settings have the same correspondence relationship.

In addition, spatial relative terms such as "below", "below", "below", "above", "above", or similar terms can be used to simplify the description of one component and another component in the illustration. Relative relationship. Spatial relative terms can be extended to components used in other directions, not limited to the illustrated directions. The element can also be rotated 90 ° or other angles, so the directional term is used to describe the direction in the illustration.

The term "nominal" as used herein refers to the expected value or target value of the characteristics or parameters of the component or process during the design phase of the product or process, and the range above and / or below the expected value . The range of values usually comes from small variables or tolerances in the process.

The term "substantially" as used herein means ± 5% of a given value.

The term "about" as used herein refers to ± 10% of a given value.

As technology evolves, integrated circuits are distinguished by smaller size requirements than previous generations of devices. However, the implementation of the above structures and processes faces challenges. As the gate length and device spacing decrease, the trench loading effect of the entire device will be exacerbated, especially when the devices have different key sizes or pattern densities. The above-mentioned trench loading effect may cause different etching depths.

The trench loading effect comes from the difference in the etching rate of the entire semiconductor device, because the semiconductor device has different patterns (such as pattern density, structure aspect ratio, and / or structure composition and reflectance).

Various embodiments of the present invention provide a method for forming a multilayer cover film, which consists of a metal hard mask and one or more oxygen layers. For example, a metal hard mask may be formed from titanium nitride. For example, the oxygen layer may be formed of tetraethoxysilane.

Multilayer cover film with oxygen layer can reduce etch rate variation. For example, a multilayer cover film during a plasma etching process can release oxygen ions. Oxygen ions can change the etch rate of the dielectric material in different pattern areas to reduce the trench loading effect. Oxygen ions diffused from the oxygen layer can increase the rate at which the plasma etches the dielectric material.

Figures 1 to 8 are various diagrams of the semiconductor device manufacturing process. This process can reduce the trench load effect. The above process can integrate multiple cover films of an oxygen-containing layer. The processes provided here are for example only, and other processes that can be implemented by the present invention are not shown.

FIG. 1 is a cross-sectional view of a semiconductor structure 100 in some embodiments of the present invention.

The semiconductor structure 100 includes a substrate 102, an etch stop layer 104, and a dielectric layer 106. In some embodiments, the substrate 102 may be a silicon substrate. In some embodiments, the substrate 102 may be (i) another semiconductor such as germanium; (ii) a semiconductor compound such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, gallium phosphorus arsenide, arsenic Aluminum indium, aluminum gallium arsenide, indium gallium arsenide, indium gallium phosphide, indium gallium arsenide, and / or indium antimonide; (iii) semiconductor alloys such as silicon germanium; or (iv) combinations thereof. In some embodiments, the substrate 102 may be a semiconductor on an insulating layer. In some embodiments, the substrate 102 may be an epitaxial material.

In some embodiments, the etch stop layer 104 is formed on the substrate 102 and can be used to avoid etching the substrate 102. The composition of the etch stop layer 104 may be silicon nitride, and other exemplary compositions include silicon oxynitride, titanium nitride, and / or other suitable materials. The deposition method of the etch stop layer 104 may be any suitable process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, molecular beam epitaxy, high-density plasma chemical vapor deposition, organic metal chemical vapor deposition, remote End-plasma chemical vapor deposition, plasma enhanced chemical vapor deposition, electroplating, other suitable methods, and / or combinations thereof.

The composition of the dielectric layer 106 is a dielectric material, and may be made of silicon oxide, spin-on glass, silicon nitride, silicon oxynitride, fluorine-doped silicate glass, low dielectric constant dielectric material, and / or other Formed from a suitable insulating material. In some embodiments, the thickness of the dielectric layer 106 may be between about 500 Å and about 700 Å. In some embodiments, the thickness of the dielectric layer 106 is greater than about 700Å. The deposition method of the dielectric layer 106 can be any suitable process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, molecular beam epitaxy, high-density plasma chemical vapor deposition, organic metal chemical vapor deposition, remote End-plasma chemical vapor deposition, plasma enhanced chemical vapor deposition, other suitable methods, and / or combinations thereof. In some embodiments, the semiconductor structure 100 may include a cap layer, other etch stop layers, and / or other suitable materials. In some embodiments, the semiconductor structure 100 may also include an integrated circuit wafer after processing, which may include a plurality of transistors configured as complementary metal-oxide-semiconductor circuits. These circuits can include logic, analog, and RF parts, which are composed of various transistors, capacitors, resistors, and interconnects, and are not shown in Figure 1 to simplify the diagram. In some embodiments, the semiconductor structure includes raised structures such as fins. The manufacturing method of the fins may adopt a suitable process, which includes photolithography and etching processes.

FIG. 2 is a cross-sectional view of a semiconductor structure after a multilayer cover film is deposited in some embodiments of the present invention. The multilayer cover film may include an oxygen layer 202 and a metal hard mask 204. In some embodiments, the multilayer cover film may also include other layers, which are not shown in FIG. 2 for the purpose of simplicity. An exemplary composition of the oxy layer 202 may include tetraethoxysilane. The formation method of the oxygen layer 202 may adopt a suitable deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, molecular beam epitaxy, high-density plasma chemical vapor deposition, organic metal chemical vapor deposition, remote Plasma chemical vapor deposition, plasma enhanced chemical vapor deposition, other suitable methods, and / or combinations thereof. In some embodiments, the thickness of the oxygen layer 202 is between about 25Å to about 250Å. In some embodiments, the thickness of the oxygen layer 202 is between about 225 Å and about 275 Å. An exemplary composition of the metal hard mask 204 may include titanium nitride. The formation method of the metal hard mask 204 can adopt a suitable deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, molecular beam epitaxy, high-density plasma chemical vapor deposition, and organic metal chemical vapor deposition , Remote plasma chemical vapor deposition, plasma enhanced chemical vapor deposition, other suitable methods, and / or combinations thereof. In some embodiments, the thickness of the metal hard mask 204 is between about 250 Å and about 350 Å.

3A to 5 are various diagrams of a semiconductor device manufacturing process in some embodiments of the present invention. This process can reduce the effect of trench loading in semiconductor structures containing different pattern densities.

3A to 3B are cross-sectional views of the semiconductor structure 100 after patterning the multilayer cover film 201 in some embodiments of the present invention. The method for etching the multilayer cover film 201 may include depositing a photoresist material on the metal hard mask 204, exposing and patterning the photoresist layer to expose a part of the metal hard mask 204, and etching the exposed part of the metal hard mask 204 and the Lower oxygen layer 202.

In some embodiments as shown in FIG. 3A, a portion of the metal hard mask 204 that is not protected (ie, exposed) by the photoresist layer is removed by etching, and a portion of the lower oxygen layer 202 is removed by etching. By over-etching the metal hard mask 204, a portion of the oxygen layer 202 can be etched. In some embodiments shown in FIG. 3B, a part of the metal hard mask 204 and the oxygen layer 202 underneath the photoresist are not protected (that is, exposed) are removed. The process of etching the metal hard mask 204 and the oxygen layer 202 may include any suitable etching technique, such as dry etching, wet etching, reactive ion etching, and / or other etching methods. In addition, multiple steps of a suitable process can also be used to remove the oxygen layer 202 and the metal hard mask 204 respectively.

In some embodiments, removing a part of the multilayer cover film 201 may form a first region 206 and a second region 208 in the remaining multilayer cover film 201. The first region 206 and the second region 208 include different pattern densities across the semiconductor structure 100. In some embodiments, the first region 206 may include dense regions (such as higher pattern density), and the second region 208 may include sparse regions (such as lower pattern density). It should be noted, however, that any relative comparison between "dense" and "sparse" is within the scope of the present invention.

In some embodiments, the first region 206 may include an area of one or more structures of the substrate separated by a minimum space allowed by design rules (such as the critical dimension of the photolithography process used). For example, the adjacent trenches 207 _A , 207 _B , and the multilayer cover film 201 at a distance from 207 _{C in} the first region 206 have a width W _{M of} less than about 10 nm. In some embodiments, the distance between adjacent trenches 207 _A , 207 _B , and 207 _{C of the} first region 206 may be between about 10 nm and about 20 nm. It should be noted that the distance between the trenches in the remaining multilayer cover film is for example only, and it can be selected according to product requirements.

In some embodiments, the second region 208 may include regions where one or more structures of the substrate are spaced apart by multiples of a minimum or approximately minimum space allowed by design rules (such as multiples of a critical dimension). For example, there is a reserved multilayer cover film 201 between adjacent trenches 209 _A and 209 _{B in} the second region 208, and the width W _N is about 60 nm. In some embodiments, the distance between adjacent trenches 209 _A and 209 _{B of the} second region 208 may be between about 40 nm and about 70 nm. It should be noted that the distance between the trenches in the remaining multilayer cover film is for example only, and it can be selected according to product requirements.

FIG. 4 is a cross-sectional view of the semiconductor structure 100 after the dielectric layer is etched using the multilayer cover film 201 as an etching mask in some embodiments of the present invention. In some embodiments, the unprotected portion of the dielectric layer 106 of the metal hard mask 204 and the oxygen layer 202 is etched to form a first recess 406 in the first region 206 and a second recess 408 in the second region 208 in. In this way, the etching process can transfer the pattern formed by the remaining multilayer cover film 201 to the dielectric layer 106 and form a first recess 406 and a second recess 408. Since the adjacent trenches 207 _A , 207 _B , and 207 _C have a width W _M , the first recesses 406 formed are also separated by the same width W _M. Similarly, the interval between the second recesses 408 has a width W _N , which is the width between the adjacent trenches 209 _A and 209 _B. The above-mentioned etching process may be a plasma etching process, such as a reactive ion etching process using an oxygen plasma. In some embodiments, the reactive ion etching process may include other etchant gases, such as nitrogen, carbon tetrafluoride, and / or other suitable gases. In addition, various other suitable methods may be used to form the recesses in the dielectric layer 106.

The use of an oxygen layer can increase the etch rate of the dielectric material. For example, in a reactive ion etching process using oxygen as an etchant gas, the oxygen layer 202 can release oxygen ions into the depression to enhance the plasma etching process, that is, to increase the etching rate of the dielectric layer 106. In dense areas such as the first area 206 having a higher pattern density, the etching rate can be increased more effectively. If the oxygen-free layer 202 is used, the oxygen ion supply of the etched surface is insufficient, and the reaction efficiency of reactive ion etching in the dense region cannot be maximized. This is because the average number of etching gas ions in the depressions in the dense area is statistically lower than the average number of etching gas ions in the depressions in the sparse area. As a result, the ion density and plasma flow of the etching gas ions in the recess in the dense area are lower. The use of the oxygen layer 202 can release oxygen ions into the first recess 406 during the etching process, so as to increase the supply of oxygen ions in the dense region, thereby increasing the etching rate of the dielectric layer 106 in the first recess 406 of the first region 206. . In FIG. 4, the first recess 406 formed by the etching process may have an etching depth D _M , which is between about 435Å and about 485Å. In some embodiments, the etch depth D _{M is} greater than about 400Å. In some embodiments, the etch depth D _{M is} less than about 400Å. It should be noted that the numerical range described here is only an example, and the etching depth D _M of the first depression 406 depends on the device specifications and can be determined by the etching conditions (such as etching time, chamber pressure, gas flow rate, and plasma power). , Bias, and / or other suitable parameters).

On the other hand, the use of the oxygen layer 202 can also affect the etch rate of the dielectric material in the sparse regions (such as the second region 208 with a lower pattern density). The etching rate can be increased, decreased, or maintained depending on the structure density and the etching conditions. In some embodiments, the structure in the second region 208 is dense. If the oxygen-free layer 202 is absent, oxygen ions are insufficient during etching. The use of the oxygen layer 202 in this example can increase the etching rate of the dielectric layer 106. In contrast, the structure in the second region 208 of some embodiments is relatively sparse, and even if the oxygen layer 202 is not used, it can have sufficient oxygen ions during etching. The use of the oxygen layer 202 in this example can reduce the etching rate of the dielectric layer 106 because the supply of oxygen ions is excessive. In addition, in some embodiments, the structure density is between the aforementioned dense and dense structure densities. Using the oxygen layer 202 does not have a significant effect on the etching rate of the dielectric layer.

In FIG. 4, the second recess 408 formed by the etching process has an etching depth D _N between about 450 Å and about 500 Å. In some embodiments, the etch depth D _{N is} greater than about 400Å. In some embodiments, the etch depth D _{N is} less than about 400Å. It should be noted that the above numerical range is for example only, and the etching depth D _N of the second recess 408 depends on the device specifications and can be determined by the etching conditions (such as etching time, chamber pressure, gas flow rate, plasma power, bias voltage, And / or other suitable parameters).

As described above, the use of the oxygen layer 202 can affect the etch rate of the dielectric material in the dense and sparse areas of the dielectric layer 106 on the semiconductor structure 100. More specifically, the etching rate of the dielectric layer 106 in the dense region (such as the first region 206) can be increased, and the etching rate of the dielectric layer 106 in the dense region (such as the second region 208) can be similar or the same. . As such, in some embodiments, the etching depth D _M of the first recess 406 and the etching depth D _{N of the} second recess 408 may be substantially the same. In some embodiments, the difference between the etch depth D _{M of the} first recess 406 and the etch depth D _{N of the} second recess 408 may be less than or equal to about 40Å. In some embodiments, the above differences may be less than about 20Å. In some embodiments, the aspect ratio (such as the ratio of depth to width) of the depression may be greater than about one. In some embodiments, the aspect ratio may be about 10 or about 20. The above numerical range is only used as an example, and the oxygen layer 202 allows the dielectric material in the sparse area and the dense area to have similar etch rates to reduce the trench load effect in the semiconductor structure 100.

FIG. 5 is a cross-sectional view of the semiconductor structure 100 after the multilayer cover film 201 is removed in some embodiments of the present invention. The removal method of the oxygen layer 202 and the metal hard mask 206 of the multilayer cover film 201 may adopt a suitable process such as dry etching, wet etching, reactive ion etching, and / or other etching methods. The above-mentioned etching method may be replaced with any other suitable method such as a chemical mechanical polishing process, which may also planarize the surface of the remaining dielectric layer 106.

6A to 8 are various diagrams of a semiconductor device manufacturing process in some embodiments of the present invention. This process can reduce the trench load effect in semiconductor structures containing different structure sizes.

6A and 6B are cross-sectional views of a semiconductor structure 100 (see FIG. 2) after patterning a multilayer cover film 201 in some embodiments of the present invention. The etching method of the multilayer cover film 201 may include depositing a photoresist material on the metal hard mask 204, exposing and patterning the photoresist to expose a portion of the metal hard mask 204, and then etching the exposed portion of the metal hard mask 204 and The lower oxygen layer 202.

In some embodiments as shown in FIG. 6A, a portion of the metal hard mask 204 that is not protected (that is, exposed) by the photoresist layer is removed by etching, and a portion of the lower oxygen layer 202 is removed by etching. By over-etching the metal hard mask 204, a portion of the oxygen layer 202 can be etched. In some embodiments shown in FIG. 6B, a part of the metal hard mask 204 and the oxygen layer 202 under the photoresist are not protected (that is, exposed) are removed. The process of etching the metal hard mask 204 and the oxygen layer 202 may include any suitable etching technique, such as dry etching, wet etching, reactive ion etching, and / or other etching methods. In addition, multiple steps of a suitable process can also be used to remove the oxygen layer 202 and the metal hard mask 204 respectively.

In some embodiments, removing a part of the multilayer cover film 201 may form a third region 606 and a fourth region 608 in the remaining multilayer cover film 201. The third region 606 and the fourth region 608 include different structure sizes across the semiconductor structure 100. In some embodiments, the third region 606 may include a smaller structure size (such as a structure with a smaller width or length), and the fourth region 608 may include a larger structure size (such as a structure with a larger width or length) . It should be noted, however, that any relative comparison between "smaller" and "larger" is within the scope of the present invention.

In some embodiments, the third region 606 may be a region of one or more semiconductor structures, and the width or length of the semiconductor structure is substantially equal to the minimum space allowed by the design rules (such as the critical size of the photolithography process used) . For example, the trenches 607 _A , 607 _B , and 607 _C formed in the remaining multilayer cover film 201 in the third region 606 may have a width W _{X of} less than about 10 nm. In some embodiments, the widths W _X of the trenches 607 _A , 607 _B , and 607 _{C of} the third region 606 may be between about 10 nm and about 20 nm. It should be noted that the groove width in the reserved multilayer cover film is for example only, and it can be selected according to product requirements.

In some embodiments, the fourth region 608 may include an area of the substrate, and the width or length of the structure in the area is almost equal to the multiple of the minimum or approximate minimum space allowed by the design rules (such as the multiple of the critical size of the photolithography process used) ). For example, the width W _Y of the trenches 609 _A and 609 _B formed in the remaining multilayer cover film 201 in the fourth region 608 may be about 60 nm. In some embodiments, the width W _Y of the trenches 609 _A and 609 _B in the fourth region 608 may be between about 40 nm and about 70 nm. In some embodiments, the trenches 607 _A, 607 _B, and the difference between the widths W _X and W _Y width of the trench 609 _A 609 _B 607 _C of greater than 40nm. It should be noted that the range of the groove width in the reserved multilayer cover film is for example only, and it can be selected according to product requirements.

FIG. 7 is a cross-sectional view of a semiconductor structure 100 after using a multilayer cover film 201 as an etching mask and etching a dielectric layer in some embodiments of the present invention. In some embodiments, the unprotected portion of the dielectric layer 106 of the metal hard mask 204 and the oxygen layer 202 is etched to form a third recess 706 in the third region 606 and a fourth recess 708 in the fourth region 608 in. In this way, the etching process can transfer the pattern formed by the remaining multilayer cover film 201 to the dielectric layer 106 and form a third recess 706 and a fourth recess 708. Since the adjacent trenches 607 _A , 607 _B , and 607 _C have a width W _X , the third recess 706 formed also has the same width W _X. Similarly, the fourth recess 708 has a width W _Y , which is the width of the trenches 609 _A and 609 _B. The above-mentioned etching process may be a plasma etching process, such as a reactive ion etching process using an oxygen plasma. In some embodiments, the reactive ion etching process may include other etchant gases, such as nitrogen, carbon tetrafluoride, and / or other suitable gases. In addition, various other suitable methods may be used to form the recesses in the dielectric layer 106.

In some embodiments, the use of an oxygen layer can increase the etch rate of the dielectric material. For example, in a reactive ion etching process using oxygen as an etchant gas, the oxygen layer 202 can release oxygen ions into the depression to enhance the plasma etching process, that is, to increase the etching rate of the dielectric layer 106. In areas of small structure size, such as the third area 606, that is, areas where the width or length of the structure is substantially equal to the minimum or approximately minimum space allowed by the design rules, the etch rate can be increased more effectively. If the oxygen-free layer 202 is used, the oxygen ion supply of the etched surface is insufficient, and the reaction efficiency of reactive ion etching in a region with a small structure size cannot be maximized. This is because statistically, structures with smaller structure sizes (such as trenches) have openings equal to the critical size, and the number of etching gas ions entering groove openings with smaller structure sizes is less than depressions with larger structure sizes. Number of. As a result, the ion density and plasma flow in structures with smaller structure sizes are lower, resulting in a lower etch rate of their dielectric materials. However, the oxygen ions released from the oxygen layer can increase the plasma etching of the dielectric material and improve the etching rate.

Taking the semiconductor structure 100 in FIG. 7 as an example, the use of the oxygen layer 202 can release oxygen ions into the recess during the etching process, so as to increase the structure of the oxygen ions in a region substantially equal to the minimum or approximately minimum space allowed by the design rules. The supply quantity further increases the etching rate of the dielectric layer 106 in the third recess 706 of the third region 606. In FIG. 7, the third recess 706 formed by the etching process may have an etching depth D _X , which is between about 435Å and about 485Å. In some embodiments, the etch depth D _{X is} greater than about 400Å. In some embodiments, the etch depth D _{X is} less than about 400Å. It should be noted that the numerical range described here is for example only, and the etching depth D _X of the third depression 706 depends on the device specifications and can be determined by the etching conditions (such as etching time, chamber pressure, gas flow rate, and plasma power) , Bias, and / or other suitable parameters).

On the other hand, the use of the oxygen layer 202 can also affect areas with larger structure sizes (such as the fourth area 608, where the width or length of the structure is substantially equal to several times the minimum or approximately minimum space allowed by the design rules). Etching rate of dielectric materials. The etching rate can be increased, decreased, or maintained depending on the structure size and the etching conditions. In some embodiments, the structure size in the fourth region 608 is relatively small. If the oxygen-free layer 202 is used, the oxygen ions are insufficient during etching. The use of the oxygen layer 202 in this example can increase the etching rate of the dielectric layer 106. Compared with this, the structure size in the fourth region 608 of some embodiments is larger, and even if the oxygen layer 202 is not used, it can have sufficient oxygen ions during etching. The use of the oxygen layer 202 in this example can reduce the etching rate of the dielectric layer 106 because the supply of oxygen ions is excessive. In addition, in some embodiments, the structure size is between the aforementioned structure sizes. The use of the oxygen layer 202 does not have a significant effect on the etching rate of the dielectric layer. In FIG. 7, the fourth recess 708 formed by the etching process has an etching depth D _Y between about 450 Å and about 500 Å. In some embodiments, the etch depth D _{Y is} greater than about 400Å. In some embodiments, the etch depth D _{Y is} less than about 400Å. In some embodiments, the aspect ratio of the depression may be greater than about 1. In some embodiments, the aspect ratio may be about 10 or about 20. It should be noted that the above numerical range is for example only, and the etching depth D _Y of the fourth depression 708 depends on the device specifications and can be determined by the etching conditions (such as etching time, chamber pressure, gas flow rate, plasma power, bias voltage, And / or other suitable parameters).

As described above, the use of the oxygen layer 202 can affect the etch rate of the dielectric material in the regions of different structural sizes of the dielectric layer 106 on the semiconductor structure 100. More specifically, the etch rate of the dielectric layer 106 in a region (such as the third region 606) may be increased, and may be similar or the same as that of the dielectric layer 106 in other regions (such as the fourth region 608). Thus, in some embodiments the etching depth of the third recess 706 D _X and D _Y etching depth in the recess 708 of the fourth embodiment may be substantially the same. In some embodiments, the difference between the third recess etching depth D _X 706 D _Y with an etching depth of the second recess 708 may be less than or equal to about 40Å. In some embodiments, the above differences may be less than about 20Å. The above numerical range is only used as an example, and the oxygen layer 202 allows the dielectric materials in regions with different structure sizes to have similar etch rates to reduce the trench load effect in the semiconductor structure 100.

8A and 8B are respectively a cross-sectional view and an isometric view of the semiconductor structure 100 after the multilayer cover film 201 of FIG. 7 is removed in some embodiments of the present invention. The removal method of the oxygen layer 202 and the metal hard mask 206 of the multilayer cover film 201 may adopt a suitable process such as dry etching, wet etching, reactive ion etching, and / or other etching methods. The above-mentioned etching method may be replaced with any other suitable method such as a chemical mechanical polishing process, which may also planarize the surface of the remaining dielectric layer 106.

FIG. 9 is a flowchart of a method 900 for reducing a trench load effect in a semiconductor structure in some embodiments of the present invention. Based on what is described herein, other steps may be performed in method 900. Further, the steps in method 900 may be changed and / or the steps in method 900 may be performed in a different order.

In some embodiments, step 902 forms structures and layers on and / or in the semiconductor structure. The semiconductor structure may include a substrate, one or more etch stop layers, and one or more dielectric layers. The semiconductor structure may also include other layers as required. In some embodiments, the substrate may be a silicon substrate. In some embodiments, the substrate may be (i) another semiconductor such as germanium; (ii) a semiconductor compound such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, gallium phosphorus arsenide, arsenide Aluminum indium, aluminum gallium arsenide, indium gallium arsenide, indium gallium phosphide, indium gallium arsenide, and / or indium antimonide; (iii) semiconductor alloys such as silicon germanium; or (iv) combinations thereof. In some embodiments, the substrate may be a semiconductor on an insulating layer. In some embodiments, the substrate may be an epitaxial material. In some embodiments, an etch stop layer is formed on the substrate and can be used to avoid etching the substrate. The composition of the etch stop layer may be silicon nitride, and other exemplary compositions include silicon oxynitride, titanium nitride, and / or other suitable materials. The etch stop layer may be deposited by any suitable process. The composition of the dielectric layer is a dielectric material, and can be made of silicon oxide, spin-on glass, silicon nitride, silicon oxynitride, fluorine-doped silicate glass, low dielectric constant dielectric material, and / or other suitable materials. Made of insulating material. The dielectric layer can be deposited by any suitable process. In some embodiments, the semiconductor structure may include a cap layer, other etch stop layers, and / or other suitable materials. In some embodiments, the semiconductor structure may also include an integrated circuit wafer after the process, which may include a plurality of transistors configured as complementary metal-oxide-semiconductor circuits. In some embodiments, active and passive devices such as transistors, diodes, capacitors, resistors, inductors, and the like may be formed on and / or in a semiconductor substrate. In some embodiments, the semiconductor structure includes raised structures such as fins. The manufacturing method of the fins may adopt a suitable process, which includes photolithography and etching processes.

In some embodiments, a step of depositing a multilayer cover film on the semiconductor structure is performed. The multilayer cover film may include an oxygen layer and a metal hard mask. In some embodiments, the multilayer cover film may also include other layers. An exemplary composition of the oxygen layer may include tetraethoxysilane. The formation method of the oxygen layer may adopt a suitable deposition process such as chemical vapor deposition. In some embodiments, the thickness of the oxygen layer is between about 25Å to about 250Å. An exemplary composition of a metal hard mask may include titanium nitride. The metal hard mask can be formed by a suitable deposition process, such as chemical vapor deposition. In some embodiments, the thickness of the metal hard mask is between about 250 Å and about 350 Å.

In some embodiments, step 906 patterns the multilayer cover film. The patterning process may include an etching process, which includes depositing a photoresist material on the metal hard mask, exposing and patterning the photoresist layer to expose a portion of the metal hard mask, and etching the exposed portion of the metal hard mask and the underlying Oxygen layer. In some embodiments, the unprotected (ie exposed) portion of the metal hard mask of the photoresist layer is removed by etching, and the underlying oxygen layer is removed by etching. In some embodiments, a portion of the metal hard mask that is not protected (ie exposed) by the photoresist and the underlying oxygen layer is removed. The etching process may include any suitable etching technique, such as dry etching, wet etching, reactive ion etching, and / or other etching methods. In addition, multiple steps of a suitable process can also be used to remove the oxygen layer and the metal hard mask separately.

In some embodiments, removing a part of the multilayer cover film may form a first region and a second region in the remaining multilayer cover film. The first and second regions contain different pattern densities across the semiconductor structure. In some embodiments, the first region may include a dense region and the second region 208 may include a sparse region. It should be noted that any relative comparison between "dense" and "sparse" is within the scope of the present invention.

In some embodiments, the first region may include a region of the semiconductor structure in which one or more structures are spaced apart by a minimum space allowed by design rules (such as a critical dimension of a photolithography process used). For example, there is a reserved multilayer cover film between adjacent trenches in the first region, and the width is less than about 10 nm. In some embodiments, the distance between adjacent trenches in the first region may be between about 10 nm and about 20 nm. An example of the first area is the first area 206 shown in FIG. 3A.

In some embodiments, the second region may include regions where one or more structures of the substrate are spaced apart by multiples of a minimum or approximately minimum space allowed by design rules (such as multiples of a critical dimension). For example, a multilayer cover film with a space between adjacent trenches in the second region has a width of about 60 nm. In some embodiments, the distance between adjacent trenches in the second region may be between about 40 nm and about 70 nm. It should be noted that the distance between the trenches in the remaining multilayer cover film is for example only, and it can be selected according to product requirements. An example of the second area is the second area 208 shown in FIG. 3A.

In some embodiments, the third layer and the fourth region may be formed in the remaining multilayer cover film by removing a part of the multilayer cover film. The third region and the fourth region include different structure sizes across the semiconductor structure. In some embodiments, the third region may include a smaller structural size and the fourth region may include a larger structural size. It should be noted, however, that any relative comparison between "smaller" and "larger" is within the scope of the present invention.

In some embodiments, the third region may be a region of a substrate, wherein a width or a length of one or more semiconductor structures is substantially equal to a minimum space allowed by design rules (such as a critical dimension of a photolithography process). For example, the width of the trench formed in the remaining multilayer cover film in the third region may be less than about 10 nm. In some embodiments, the trench width of the third region may be between about 10 nm and about 20 nm. An example of the third area is the third area 606 shown in FIG. 6A. It should be noted that the range of the groove width in the reserved multilayer cover film is for example only, and it can be selected according to product requirements.

In some embodiments, the fourth region may include a region of the substrate, and a structure width or length in the region is almost equal to a multiple of a minimum or approximately minimum space allowed by design rules (such as a multiple of a critical dimension). For example, the width of the trench formed in the remaining multilayer cover film in the fourth region may be about 60 nm. In some embodiments, the trench width in the fourth region may be between about 40 nm and about 70 nm. An example of the fourth area is the fourth area 608 shown in FIG. 6A. It should be noted that the range of the groove width in the reserved multilayer cover film is for example only, and it can be selected according to product requirements.

In some embodiments, step 908 uses a multilayer cover film as an etch mask and etches the dielectric layer. In some embodiments, an unprotected portion of the dielectric layer of the metal hard mask and the oxygen layer is etched to form a first recess in the first region, a second recess in the second region, and a third recess in In the third region, and a fourth depression is formed in the fourth region. In this way, the etching process can transfer the pattern formed by the remaining multilayer cover film to the dielectric layer. The width of the gap between the recesses may be the same as the width of the trenches in the first or second regions; or the width of the recess may be the same as the width of the trenches in the third or fourth regions. The etching process may be a plasma etching process, such as a reactive ion etching process using an oxygen plasma. In some embodiments, the reactive ion etching process may include other etchant gases, such as nitrogen, carbon tetrafluoride, and / or other suitable gases. In addition, various other suitable methods may be used to form the recesses in the dielectric layer.

The use of an oxygen layer can increase the etch rate of the dielectric material. For example, in a reactive ion etching process using oxygen as an etching gas, the oxygen layer can release oxygen ions into the depression to enhance the plasma etching process, that is, to increase the etching rate of the dielectric layer. In dense areas (e.g., the first area) or areas with smaller structure sizes (e.g., the third area), the etching rate can be increased more effectively. An example of the first region may include the first region 206 in FIG. 3A, and an example of the third region may include the third region 606 in FIG. 6A. The use of the oxygen layer can release oxygen ions into the depression during the etching process, so as to increase the supply of oxygen ions, and thereby increase the etching rate of the dielectric layer. The etching depth of the first recess and the third recess formed by the etching process may be between about 435Å and about 485Å. An example of the first depression may include the first depression 406 in FIG. 4, and an example of the third depression may include the third depression 706 in FIG. 7. The etching depth of the first recess and the third recess may depend on the device specifications, and may be adjusted by etching conditions (such as etching time, chamber pressure, gas flow rate, plasma power, bias voltage, and / or other suitable parameters).

The use of an oxygen layer can increase the etch rate of the dielectric material. For example, in a reactive ion etching process using oxygen as an etching gas, the oxygen layer can release oxygen ions into the depression to enhance the plasma etching process, that is, to increase the etching rate of the dielectric layer. In dense areas (such as the first area) or areas with smaller structural dimensions (such as the third area), the etching rate can be increased more effectively. An example of the first region may include the first region 206 in FIG. 3A, and an example of the third region may include the third region 606 in FIG. 6A. The use of the oxygen layer can release oxygen ions into the depression during the etching process, so as to increase the supply of oxygen ions, and thereby increase the etching rate of the dielectric layer. The etching depth of the first recess and the third recess formed by the etching process may be between about 435Å and about 485Å. An example of the first depression may include the first depression 406 in FIG. 4, and an example of the third depression may include the third depression 706 in FIG. 7. The etching depth of the first recess and the third recess may depend on the device specifications, and may be adjusted by etching conditions (such as etching time, chamber pressure, gas flow rate, plasma power, bias voltage, and / or other suitable parameters).

The use of the oxygen layer can also affect the etching rate of the dielectric material in the sparse area (such as the second area) or the area with a larger structural size (such as the fourth area). An example of the second region may include the second region 208 in FIG. 3A, and an example of the fourth region may include the fourth region 608 in FIG. 6A. The etching rate can be increased, decreased, or maintained depending on the structure density and the etching conditions. In some embodiments, the use of an oxygen layer can increase the etch rate of the dielectric layer. In contrast, the use of an oxygen layer can reduce the etching rate of the dielectric layer because the supply of oxygen ions is excessive. However, some embodiments employ an oxygen layer that does not have a significant effect on the etch rate of the dielectric layer. The etching depth of the second recess and the fourth recess formed by the etching process may be between about 450 Å and about 500 Å. An example of the second depression may include the second depression 408 in FIG. 4, and an example of the fourth depression may include the fourth depression 708 in FIG. 7. It should be noted that the above numerical range is only an example, and the etching depth of the second and fourth depressions depends on the device specifications and can be determined by the etching conditions (such as etching time, chamber pressure, gas flow rate, plasma power, and bias voltage). , And / or other suitable parameters).

In some embodiments, step 910 may remove the multilayer cover film. The method for removing the oxygen layer and the metal hard mask of the multilayer cover film may adopt a suitable process such as dry etching, wet etching, reactive ion etching, and / or other etching methods. The above-mentioned etching method can be replaced by any other suitable method such as a chemical mechanical polishing process, which can also planarize the surface of the remaining dielectric layer.

The methods provided by various embodiments of the present invention can reduce the trench load effect in a semiconductor structure. The use of the oxygen layer can affect the etch rate of the dielectric material in the dense area and the sparse area (or the area with a small structure size or a large structure size). More specifically, the etch rate of a dielectric layer in a dense region or a region having a smaller structure size can be increased. As the etching rate in the above-mentioned area increases, it may be similar to or the same as the etching rate in the sparse area or the area having a larger structure size. In some embodiments, the difference in etch depth in these regions can be less than about 20 Å, as low as 0. The separation distance of the structure in the dense area, or the size of the small structure can be as small as the minimum space allowed by the design rules (such as the critical size). The above numerical range is used as an example, and the use of the oxygen layer allows the dielectric material in the dense area and the sparse area (or the area with a smaller structure or a larger structure) to have a similar etching rate. In this way, the trench load effect in the semiconductor structure can be reduced.

In some embodiments, the semiconductor structure includes a dielectric layer formed on a substrate. A patterned oxygen layer is formed on the dielectric layer. The semiconductor structure may also include a first trench and a second trench formed in the dielectric layer, which uses a patterned oxygen layer as a mask. The width of the second trench may be greater than the width of the first trench, and the depth of the second trench may be substantially the same as the depth of the first trench.

In some embodiments, the patterned oxygen layer of the semiconductor structure includes tetraethoxysilane.

In some embodiments, the semiconductor structure further includes a metal hard mask on the patterned oxygen layer, wherein the metal hard mask includes titanium nitride.

In some embodiments, the first trench width of the semiconductor structure is between about 10 nm and about 20 nm.

In some embodiments, the first trench width of the semiconductor structure is less than about 10 nm.

In some embodiments, the second trench width of the semiconductor structure is between about 40 nm and about 70 nm.

In some embodiments, the thickness of the metal hard mask of the semiconductor structure is between about 250 Å and about 350 Å.

In some embodiments, the thickness of the dielectric layer of the semiconductor structure is between about 500 Å and about 700 Å.

In some embodiments, the dielectric layer of the semiconductor structure includes a low dielectric constant material.

In some embodiments, the thickness of the patterned oxygen layer of the semiconductor structure is between about 225 Å and about 275 Å.

In some embodiments, a method for fabricating a semiconductor structure includes: forming a dielectric layer on a substrate; and depositing a tetraethoxysilane layer on the dielectric layer. A metal hard mask can be deposited on the tetraethoxysilane layer. Patternable metal hard mask and tetraethoxysilane layer. This method also includes using a patterned metal hard mask and a tetraethoxysilane layer as a mask, and etching the dielectric layer to form a first trench and a second trench.

In some embodiments, the first trench of the above method has a first depth and the second trench has a second depth, and the gap between the first depth and the second depth is less than about 20Å.

In some embodiments, the first and second depths of the above method are greater than about 400Å.

In some embodiments, the first trench of the above method has an aspect ratio greater than about 1.

In some embodiments, the first trench of the above method has a first width and the second trench has a second width, and a gap between the first width and the second width is greater than about 40 nm.

In some embodiments, the semiconductor structure includes: a dielectric layer is formed on the substrate; and a tetraethoxysilane layer is formed on the dielectric layer. The first trench and the second trench may be formed in a dielectric layer, which uses a tetraethoxysilane layer as a mask. The width of the first trench may be substantially equal to a critical dimension of the photolithography process, and the width of the second trench may be larger than the width of the first trench.

In some embodiments, the thickness of the tetraethoxysilane layer of the semiconductor structure is between about 225Å and about 275Å.

In some embodiments, the first trench of the semiconductor structure has a first depth and the second trench has a second depth, and the first depth is substantially the same as the second depth.

In some embodiments, the first trench of the semiconductor structure has a first depth and the second trench has a second depth, and a gap between the first depth and the second depth is less than about 20Å.

In some embodiments, the first trench of the semiconductor structure has an aspect ratio greater than about 1.

It should be understood that the embodiments (non-abstract) are only used to illustrate the scope of patent application. The abstract proposes one or more embodiments, but not all of them, and is therefore not limited to the scope of related patent applications.

The features of the above embodiments are helpful for those with ordinary knowledge in the technical field to understand the embodiments of the present invention. Those of ordinary skill in the art should understand that the present invention can be used as a basis for designing and changing other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those with ordinary knowledge in the technical field should also understand that these equivalent replacements do not depart from the spirit and scope of the present invention, and can be changed, replaced, or changed without departing from the spirit and scope of the present invention.

Claims (1)

    A semiconductor structure includes: a dielectric layer formed on a substrate; a patterned oxygen layer formed on the dielectric layer; and a first trench and a second trench formed on the dielectric layer Wherein the patterned oxygen layer is used as a mask, wherein the width of the second trench is greater than the width of the first trench, and the depth of the second trench is substantially the same as the depth of the first trench .