TW201810219A - Display device and driving method thereof - Google Patents

Abstract

A display device includes a display panel and a controller. The display panel includes a plurality of sub pixels and a multiplexer. The multiplexer includes a plurality of output terminals electrically and respectively coupled to the sub pixels. The controller is configured to output a plurality of selecting signals to the multiplexer. The controller is further configured to independently adjust a length of an enable duration of one of the selecting signals in a scanning duration, such that the length of the enable duration is different from a plurality of lengths of a plurality of enable durations of other selecting signals in the scanning duration.

Description

Display device and driving method thereof

The present invention relates to a display technology, and more particularly, to a display device and a driving method thereof.

With the development of display technology, the demand for narrow bezels of display devices is increasing. In order to meet the requirements of narrow bezels, the traces in the display device will have more complicated designs. In this case, the lengths of the traces (for example: data lines) may be different, and the traces of different lengths have different resistance values. In this way, pixels or sub-pixels that are electrically coupled to a trace with a larger line resistance will have a problem of insufficient charging.

In view of this, the present disclosure proposes a display device and a driving method thereof to solve the problems mentioned in the prior art.

An embodiment of the present disclosure relates to a display device. The display device includes a display panel and a controller. The display panel includes a plurality of sub pixels and a multiplexer. The multiplexer includes a plurality of output terminals respectively electrically coupled to the sub-pixels. Controller used to output multiple selections Signal to multiplexer. The controller is further configured to independently adjust the length of the uniform enable period of one of the selection signals during a scanning period, so that the length of the enable period is different from the length of the plural enable periods of the other selection signals during the scan period.

One embodiment of the present disclosure relates to a driving method. The driving method is used to drive a display device. The driving method includes: independently adjusting the length of the uniform energy period of one of the plurality of selection signals in a scanning period by a controller in the display device, so that the length of the enabling period and the other selection signals are between The lengths of the plurality of enabling periods in the scanning period are different; and the controller outputs the selection signals to a multiplexer in the display device.

An embodiment of the present disclosure relates to a display device. The display device includes a display panel and a controller. The display panel includes a plurality of sub pixels and a multiplexer. The multiplexer includes a plurality of output terminals respectively electrically coupled to the sub-pixels. The controller is configured to output a plurality of selection signals to the multiplexer and output a bias current to the multiplexer according to a current control signal. The current control signal has a plurality of voltage conversion edges corresponding to a scanning period, and the voltage conversion edges respectively correspond to the selection signals. The controller is further configured to independently adjust the voltage conversion rate of one of the voltage conversion edges so that the voltage conversion rate of this voltage conversion edge is different from the voltage conversion rates of the other voltage conversion edges.

One embodiment of the present disclosure relates to a driving method. The driving method is used to drive a display device. The driving method includes: independently adjusting a complex in a current control signal by a controller in the display device. One of the voltage conversion edges has a voltage conversion rate such that the voltage conversion rate of this voltage conversion edge is different from the voltage conversion rates of other voltage conversion edges. The voltage conversion edges correspond to a scanning period and Corresponding to a plurality of selection signals respectively; and outputting the selection signals to a multiplexer in the display device by the controller, and outputting a bias current to the multiplexer according to the current control signal.

In summary, by applying the above embodiment, the controller can independently adjust the width of the enable period of one of the selection signals of the multiplexer, or independently adjust one of the voltage conversion rates of the current control signal of the bias current. To improve the problem of insufficient charging.

100‧‧‧ display device

110‧‧‧display panel

112‧‧‧ Multiplexer

120‧‧‧ Controller

122‧‧‧Sequence Controller

124‧‧‧Gate driver

126‧‧‧Source Driver

1262‧‧‧Control Unit

600, 700‧‧‧ Drive method

R1, R2, G1, G2, B1, B2 ‧‧‧ sub pixels

DL1, DL2, DL3‧‧‧ data line

SL1, SL2‧‧‧scan line

XSTB‧‧‧ Loading signal

S1, S2, S3 ‧‧‧ Select signal

CS‧‧‧Current control signal

BUF‧‧‧Buffer

Ibias‧‧‧ bias current

VG1, VG2‧‧‧‧scan signal

VGH, VGL, VP, VL, GND, AVEE, VCOM, AVDD‧‧‧Voltage levels

D1, D2 ‧‧‧ during scanning

P11, P21, P31, P12, P22, P32 ‧‧‧Enable period

d1, d2‧‧‧ interval

E1, E2, E3‧‧‧‧voltage conversion edge

E11, E21, E31, E12, E22, E32 ‧‧‧ Conversion stage

SR1, SR2, SR3 ‧‧‧ Voltage Slew Rate

S602, S604, S702, S704‧‧‧ steps

In order to make the above and other objects, features, advantages, and embodiments of the present disclosure more comprehensible, the description of the drawings is as follows: FIG. 1 is a schematic diagram of a display device according to an embodiment of the present disclosure; FIG. 2 is a timing diagram of some signals of the display device of FIG. 1 according to an embodiment of the disclosure; FIG. 3 is a part of signals of the display device of FIG. 1 according to an embodiment of the disclosure; FIG. 4 is a timing diagram of some signals of the display device of FIG. 1 according to an embodiment of the present disclosure; and FIG. 5 is a display of FIG. 1 according to an embodiment of the present disclosure. Timing diagram of some signals of the device; FIG. 6 is a flowchart of a driving method according to an embodiment of the present disclosure; and FIG. 7 is a flowchart of a driving method according to an embodiment of the present disclosure.

The following is a detailed description with examples and the accompanying drawings, but the examples provided are not intended to limit the scope covered by this disclosure, and the description of the structure operation is not used to limit the order of its implementation, and any recombination of components The structure and the devices with the same effect are all the scope covered by this disclosure. In addition, the drawings are for illustrative purposes only, and are not drawn to the original dimensions. In order to facilitate understanding, the same elements or similar elements in the following description will be described with the same symbols.

The terms used throughout the specification and the scope of patent applications, unless otherwise specified, usually have the ordinary meaning of each term used in this field, in the content disclosed here, and in special content.

Regarding the "first", "second", "third", etc. used in this article, they are not meant to specifically refer to the order or order, nor are they used to limit this disclosure. They are only used to distinguish the same technology. Elements or operations described by words.

About "about", "approximately" or "approximately" as used herein is generally an error or range of the index value within 20%, preferably within 10%, and more preferably Within five percent. Unless explicitly stated in the text, the mentioned values are regarded as approximate values. That is, the error or range indicated by "about", "about" or "approximately".

In addition, as used in this document, "coupling" or "connection" can mean that two or more components make direct physical or electrical contact with each other, or indirectly make physical or electrical contact with each other, and "coupling" It may also mean that two or more elements operate or act on each other.

FIG. 1 is a schematic diagram of a display device 100 according to an embodiment of the disclosure. As shown in FIG. 1, the display device 100 includes a display panel 110 and a controller 120. In some embodiments, the display device 100 may be, for example, a liquid crystal display panel or other various display panels. The display panel 110 includes a multiplexer 112 and a plurality of sub pixels. For simplicity and easy understanding, only six sub-pixels R1, R2, G1, G2, B1, B2, three data lines DL1-DL3, and two scanning lines SL1-SL2 are shown in Figure 1. Disclosures are not limited to these quantities.

As shown in FIG. 1, the multiplexer 112 includes three outputs. The multiplexer 112 is electrically coupled to the sub-pixels through the output terminals. In detail, the three output terminals of the multiplexer 112 are electrically coupled to the data lines DL1-DL3, respectively. Sub-pixel R1 and sub-pixel R2 are electrically coupled to data line DL1, sub-pixel G1 and sub-pixel G2 are electrically coupled to data line DL2, sub-pixel B1 and sub-pixel B2 are electrically coupled to data line DL3 . In addition, the sub-pixel R1, the sub-pixel G1, and the sub-pixel B1 are electrically coupled to the scan line SL1, and the sub-pixel R2, the sub-pixel G2, and the sub-pixel B2 are electrically coupled to the scan line SL2.

It is important to note that the arrangement of these sub-pixels in Figure 1 is for illustration purposes only. Other various sub-pixel configurations, such as stripe, delta arrangement, etc. Within the scope of this disclosure.

The controller 120 includes a timing controller 122, a gate driver 124, and a source driver 126. The timing controller 122 is electrically coupled to the gate driver 124 and the source driver 126 to control the operations of the gate driver 124 and the source driver 126.

In detail, the timing controller 122 is configured to output a clock signal to the gate driver 124 to control the gate driver 124 to output the scanning signal VG1 and the scanning signal VG2 to the scanning line SL1 and the scanning line SL2, respectively, so that the corresponding The pixel driving transistor is turned on. For example, during the enabling period of the scanning signal VG1, the driving transistors of the sub-pixel R1, the sub-pixel G1, and the sub-pixel B1 will be turned on. During the enabling period of the scanning signal VG2, the driving transistors of the sub-pixel R2, the sub-pixel G2, and the sub-pixel B2 will be turned on.

At the same time, the timing controller 122 is further configured to output the load signal XSTB to the source driver 126. The control unit 1262 of the source driver 126 generates a current control signal CS according to the loading signal XSTB. In some embodiments, the control unit 1262 may be, for example, a signal processing body. The buffer BUF outputs the corresponding bias current Ibias to the multiplexer 112 according to the current control signal CS. The bias current Ibias corresponds to data signals to be written into the data lines DL1-DL3.

At the same time, the timing controller 122 is further configured to output a plurality of selection signals S1-S3 to the multiplexer 112. In some embodiments, the multiplexer 112 includes three switching units. The three switch units are used to receive the selection signals S1-S3, respectively. The three switch units are electrically coupled to the data lines DL1-DL3, respectively. in In some embodiments, these switching units may be implemented by P-type transistors, N-type transistors, or other various switching elements. The selection signals S1-S3 are transmitted to the control terminals of the three switch units, respectively, to control the conduction states of the switch units, respectively.

For example, when the driving transistors of sub-pixel R1, sub-pixel G1, and sub-pixel B1 are on (the enabling period of the scanning signal VG1), the three switching units in the multiplexer 112 will be respectively Controlled by the selection signals S1-S3 and sequentially turned on. In this way, the multiplexer 112 can output the bias current Ibias when each switching unit is turned on to the corresponding data lines DL1-DL3, so that the liquid crystal capacitors of the sub-pixel R1, the sub-pixel G1, and the sub-pixel B1 can be The sequence is charged to the corresponding voltage level, and then the corresponding gray level is displayed.

Similarly, when the driving transistors of the sub-pixel R2, the sub-pixel G2, and the sub-pixel B2 are on (the enabling period of the scanning signal VG2), the three switching units in the multiplexer 112 will be affected separately. Select signals S1-S3 to control and turn on sequentially. In this way, the multiplexer 112 can respectively output the bias current Ibias when each switching unit is turned on to the corresponding data lines DL1-DL3, so that the liquid crystal capacitors of the sub-pixel R2, the sub-pixel G2, and the sub-pixel B2 can be The sequence is charged to the corresponding voltage level, and then the corresponding gray level is displayed.

It should be noted that the number of switch units included in the multiplexer 112 is not limited to the above examples.

FIG. 2 is a timing diagram of some signals of the display device 100 shown in FIG. 1 according to an embodiment of the disclosure. In detail, Figure 2 It is shown that the scanning signal VG1, the selection signals S1-S3, and the current control signal CS correspond to the voltage waveform in the scanning period D1.

As shown in FIG. 2, the scanning signal VG1 has a first voltage level VGH and a second voltage level VGL. In some embodiments, the first voltage level VGH is higher than the second voltage level VGL. For example, the voltage value of the first voltage level VGH is approximately 21 volts, and the voltage value of the second voltage level VGL is approximately -8 volts. The scanning signal VG1 is used to control the conducting state of the driving transistor of the first row of sub-pixels. The selection signals S1-S3 also have a first voltage level VGH and a second voltage level VGL, respectively. In the scanning period D1 of the scanning signal VG1, the selection signal S1 has an enabling period P1, the selection signal S2 has an enabling period P2, and the selection signal S3 has an enabling period P3. The interval period d1 is between the enabling period P1 and the enabling period P2, and the interval period d2 is between the enabling period P2 and the enabling period P3.

It should be noted that although the scanning period D1 corresponds to the first voltage level VGH, in other embodiments, the scanning period D1 may correspond to the second voltage level VGL. For example, if the driving transistor of the sub-pixel R1 is an N-type transistor, when the scanning signal VG1 is at the first voltage level VGH, the driving transistor of the sub-pixel R1 will be turned on. At this time, the scanning period D1 of the scanning signal VG1 corresponds to the first voltage level VGH. Conversely, if the driving transistor of the sub-pixel R1 is a P-type transistor, the scanning period D1 of the scanning signal VG1 corresponds to the second voltage level VGL. In short, the voltage level of D1 during the scanning period of the scanning signal VG1 can be adjusted according to the type of the driving transistor of the sub-pixel. Similarly, the voltage levels corresponding to the enabling periods P1-P3 can also be changed according to the type of the switching unit in the multiplexer 112.

As mentioned above, during the scanning period D1 of the scanning signal VG1, the three switching units in the multiplexer 112 will be controlled by the selection signals S1-S3 and sequentially turned on, so as to output the bias current Ibias when the switching units are turned on. Go to the corresponding data lines DL1-DL3.

In some embodiments, the controller 120 is used to independently adjust the length of one of the selection signals during the enabling period in the scanning period D1. Taking FIG. 2 as an example, the controller 120 independently adjusts the length of the enabling period P3 of the selection signal S3 so that the length of the enabling period P3 is different from the length of the enabling period P1 and also the length of the enabling period P2. Not the same. In other words, when the controller 120 adjusts the length of the enabling period P3 of the selection signal S3, it is not necessary to adjust the length of the enabling period P1 synchronously, and it is not necessary to adjust the length of the enabling period P2 synchronously. In some embodiments, the length of the enabling period P3 is adjusted to be longer than the length of the enabling period P1 or the enabling period P2. In some other embodiments, the length of the enabling period P3 may be adjusted to be shorter than the length of the enabling period P1 or the enabling period P2. In other words, the lengths of the enabling periods P1, P2, and P3 can be independently adjusted, and they can be different from each other.

Although the lengths of the data lines DL1-DL3 shown in FIG. 1 are equal lengths, in practice, in order to achieve the purpose of a narrow frame, the lengths of all the data lines may not be the same length. For example, the length of the data line DL3 between the multiplexer 112 and the sub-pixel B1 may be longer than the length of the data line DL1 between the multiplexer 112 and the sub-pixel R1. However, when the length of the data line DL3 from the multiplexer 112 to the sub-pixel B1 is long, it means that the line resistance of the data line DL3 between the multiplexer 112 and the sub-pixel B1 is large. In this kind of In this case, the sub-pixel B1 may have an insufficient charging problem.

Since the multiplexer 112 outputs the corresponding bias current Ibias to the data line DL3 according to the selection signal S3, if the controller 120 adjusts the length of the enabling period P3 of the selection signal S3 to be longer, it is electrically coupled The charging time to the sub-pixel B1 of the data line DL3 will be extended. In this way, the above-mentioned problem of insufficient charging can be solved.

It should be noted that in addition to controlling the length of the enabling period P1-P3, the controller 120 may also control the length of the interval period d1-d2 in some embodiments.

On the other hand, as shown in FIG. 2, the current control signal CS generated by the control unit 1262 has a first voltage level VP, a second voltage level VN, and a ground voltage level GND. Generally, the voltage value of the first voltage level VP is positive, and the voltage value of the second voltage level VN is negative.

In some embodiments, the current control signal CS has three voltage conversion edges E1, E2, and E3 during the scanning period D1 corresponding to the scanning signal VG1. The voltage conversion edges E1-E3 correspond to the enable period P1 of the selection signal S1, the enable period P2 of the selection signal S2, and the enable period P3 of the selection signal S3, respectively. The voltage conversion edges E1-E3 have voltage slew rates SR1-SR3, respectively.

For example, the voltage conversion edge E1 may be slightly earlier in timing than the enable period P1. The start time of the voltage conversion edge E2 is aligned with the start time of the enable period P2. The start time of the voltage conversion edge E3 is aligned with the start time of the enable period P3. In addition, the voltage conversion edge E1 includes a first conversion stage E11 and a second conversion stage E12. Voltage conversion edge E2 contains The first conversion stage E21 and the second conversion stage E22. The voltage conversion edge E3 includes a first conversion stage E31 and a second conversion stage E32. The conversion process of the second conversion stage E12 of the voltage conversion edge E1 corresponds to the voltage conversion rate SR1. The conversion process of the second conversion stage E22 of the voltage conversion edge E2 corresponds to the voltage conversion rate SR2. The conversion process of the second conversion stage E32 of the voltage conversion edge E3 corresponds to the voltage conversion rate SR3.

When the sub-pixel inversion is used in the display device 100, the polarities of the sub-pixel R1, the sub-pixel G1, and the sub-pixel B1 are staggered. For example, when the sub-pixel R1 has a positive polarity, the sub-pixel G1 has a negative polarity and the sub-pixel B1 has a positive polarity. In contrast, when the sub-pixel R1 has a negative polarity, the sub-pixel G1 has a positive polarity and the sub-pixel B1 has a negative polarity. In the following embodiments, the sub-pixel R1 and the sub-pixel B1 have a positive polarity and the sub-pixel G1 has a negative polarity as an example.

As shown in FIG. 2, since the sub-pixel R1 and the sub-pixel B1 have a positive polarity, the voltage conversion edge E1 and the voltage conversion edge E3 of the current control signal CS will change from the second voltage level VN (negative voltage) to The first voltage level is VP (positive voltage). Since the sub-pixel G1 has a negative polarity, the voltage conversion edge E2 of the current control signal CS will change from the first voltage level VP (positive voltage) to the second voltage level VN (negative voltage).

In detail, during the enable period P1 of the selection signal S1 or the precharge period before the enable period P1, the current control signal CS will be precharged from the second voltage level VN to the ground voltage level GND (first conversion Stage E11), and then charge from the ground voltage level GND to the first voltage level VP (second conversion stage E12), so as to be electrically coupled to the sub-connector of the data line DL1 Pixels (for example: sub-pixel R1) have positive polarity. The process of charging the voltage conversion edge E1 from the ground voltage level GND to the first voltage level VP corresponds to the voltage conversion rate SR1.

During the enabling period P2 of the selection signal S2, the current control signal CS will be pre-discharged from the first voltage level VP to the ground voltage level GND (first conversion stage E21), and then discharged from the ground voltage level GND to the first Two voltage levels VN (second conversion stage E22), so that the sub-pixels (eg, sub-pixel G1) electrically coupled to the data line DL2 have negative polarity. The process of discharging the voltage conversion edge E2 from the ground voltage level GND to the second voltage level VN corresponds to the voltage conversion rate SR2.

During the enabling period P3 of the selection signal S3, the current control signal CS will be precharged from the second voltage level VN to the ground voltage level GND (first conversion stage E31), and then charged from the ground voltage level GND to the third A voltage level VP (second conversion stage E32), so that the sub-pixels (eg, the sub-pixel B1) electrically coupled to the data line DL3 have a positive polarity. The process of charging the voltage conversion edge E3 from the ground voltage level GND to the first voltage level VP corresponds to the voltage conversion rate SR3.

In some embodiments, the controller 120 is used to independently adjust a voltage conversion rate of one of the voltage conversion edges of the control signal CS. Taking FIG. 2 as an example, the controller 120 independently adjusts the voltage conversion rate SR3 of the voltage conversion edge E3 so that the voltage conversion rate SR3 is different from the voltage conversion rate SR1, and is also different from the voltage conversion rate SR2. In other words, when the controller 120 adjusts the voltage slew rate SR3, it is not necessary to adjust the voltage slew rate SR1 synchronously, nor does it need to adjust the voltage slew rate synchronously. SR2. In some embodiments, the voltage slew rate SR3 is adjusted to be larger. That is, the current control signal CS has a larger voltage conversion rate during the enabling period P3 of the selection signal S3. In other words, the voltage conversion rates SR1, SR2, and SR3 can be independently adjusted, and they can all be different from each other.

As mentioned above, the buffer BUF of the source driver 126 generates a corresponding bias current Ibias according to the current control signal CS. In other words, the current control signal CS will determine the current value of the bias current Ibias, and then affect the charging process of the corresponding sub-pixel.

Therefore, when the voltage slew rate SR3 is adjusted to be large, the bias current Ibias output to the data line DL3 will increase rapidly, thereby making the charging effect of the sub-pixel B1 electrically coupled to the data line DL3 Promotion. In this way, the above-mentioned problem of insufficient charging can also be solved.

It should be particularly noted here that, although the above description is based on the example of sub-pixel inversion, a display panel using pixel inversion is also within the scope of the present disclosure. Since the display panel using pixel inversion has similar operation, it will not be described again.

FIG. 3 is a timing diagram of some signals of the display device 100 shown in FIG. 1 according to an embodiment of the disclosure. In detail, FIG. 3 illustrates the voltage waveforms of the scanning signal VG1 (hereinafter referred to as a first scanning signal), the scanning signal VG2 (hereinafter referred to as a second scanning signal), and the selection signals S1-S3.

It should be noted that, since the display device 100 in FIG. 1 only shows two scanning lines VG1-VG2, FIG. 3 also only shows the voltage waveforms of the scanning signals VG1-VG2 and the corresponding ones in the selection signals S1-S3. Information No. pulse. However, this disclosure is not limited to this.

As shown in FIG. 3, within a frame time, the first scanning signal VG1 and the second scanning signal VG2 have a scanning period D1 and a scanning period D2, respectively. During the scanning period D1, the driving transistors of the sub-pixel R1, the sub-pixel G1, and the sub-pixel B1 in the first column will be turned on. At the same time, the selection signals S1-S3 will be sequentially enabled to include the enable period P11, the enable period P21, and the enable period P31, respectively. The multiplexer 112 outputs the corresponding bias current Ibias to the sub-pixel R1, the sub-pixel G1, and the sub-pixel B1 according to the enabling period P11, the enabling period P21, and the enabling period P31, respectively. Similarly, during the scanning period D2, the driving transistors of the sub-pixel R2, the sub-pixel G2, and the sub-pixel B2 in the second column will be turned on. At the same time, the selection signals S1-S3 will be sequentially enabled to include the enabling period P12, the enabling period P22, and the enabling period P32, respectively. The multiplexer 112 outputs the corresponding bias current Ibias to the sub-pixel R2, the sub-pixel G2, and the sub-pixel B2 according to the enabling period P12, the enabling period P22, and the enabling period P32, respectively.

The high voltage level (voltage level VGH) and low voltage level (voltage level VGL) of the scan signals VG1-VG2 and the selection signals S1-S3 are shown in FIG. When these signals undergo a transient change in voltage (for example, a rising edge of a voltage rise or a falling edge of a voltage drop), a voltage load will be generated to generate panel noise.

In order to solve the above problem, in some embodiments, the controller 120 is configured to control the falling edge of one selection signal and the rising edge of another selection signal to be aligned in timing to cancel the voltage instants. Change, which in turn reduces noise.

Taking the example in FIG. 3, the controller 120 controls the falling edge of the enabling period P11 and the rising edge of the enabling period P21 to be aligned in timing. The controller 120 controls the falling edge of the enable period P21 and the rising edge of the enable period P31 to be aligned in timing. The controller 120 controls the falling edge of the enabling period P31 and the rising edge of the enabling period P12 to be aligned in timing. The controller 120 controls the falling edge of the enabling period P12 and the rising edge of the enabling period P22 to be aligned in timing. The controller 120 controls the falling edge of the enabling period P22 and the rising edge of the enabling period P32 to be aligned in timing. By aligning the rising edge of one selected signal with the falling edge of the other selected signal, the instantaneous voltage changes can be offset with each other, thereby reducing noise.

In addition, in some embodiments, the controller 120 is further configured to control that the falling edge of the scanning period D1 and the rising edge of the scanning period D2 are aligned in time. This can also cancel the instantaneous changes in voltage, thereby reducing noise.

FIG. 4 is a timing diagram of some signals of the display device 100 shown in FIG. 1 according to an embodiment of the disclosure. In detail, FIG. 4 illustrates voltage waveforms of the first scanning signal VG1, the second scanning signal VG2, and the selection signals S1-S3.

4 is different from FIG. 3 in that in FIG. 4, the scanning period D1 of the first scanning signal VG1 and the scanning period D2 of the second scanning signal VG2 partially overlap in timing. By partially overlapping the scanning period D1 and the scanning period D2 in time sequence, the problem of incorrect data filling can be avoided. In some embodiments, the controller 120 is configured to control a falling edge (rising edge) of one of the scanning signals and a rising edge (falling edge) of one of the selected signals. The edges are aligned in timing to offset the instantaneous changes in voltage, thereby reducing noise.

Taking the example in FIG. 4, the controller 120 controls the falling edge of the first scanning signal VG1 during the scanning period D1 and the rising edge of the selection signal S1 during the enabling period P12 to be aligned in time. The controller 120 controls the rising edge of the second scanning signal VG2 during the scanning period D2 and the falling edge of the selecting signal S3 during the enabling period P31 to be aligned in timing. This can also cancel the instantaneous voltage changes to each other, thereby solving the problem of poor touch.

FIG. 5 is a timing diagram of some signals of the display device 100 shown in FIG. 1 according to an embodiment of the disclosure. In detail, FIG. 5 illustrates voltage waveforms of the first scanning signal VG1, the second scanning signal VG2, and the selection signals S1-S3.

In some embodiments, the controller 120 utilizes a charge sharing mechanism to make the rising edge and / or the falling edge of the signal have three or more voltage levels to save power and solve the problem of poor touch.

As shown in FIG. 5, the controller 120 uses the charge sharing mechanism to control the rising edge and / or falling edge of the selection signal S1 to include six voltage levels VGL, AVEE, GND, VCOM, AVDD, and VGH. In detail, the selection signal S1 is sequentially charged from the voltage level VGL to the voltage level AVEE, the ground voltage level GND, the voltage level VCOM, the voltage level AVDD, and the voltage level VGH. Then, it sequentially discharges from the voltage level VGH to the voltage level AVDD, the voltage level VCOM, the ground voltage level GND, the voltage level AVEE, and the voltage level VGL.

For example, when the rising edge or falling edge of the selection signal S1 is divided into multiple segments, the voltage change in each segment can be effectively reduced. As a result, the power consumed by the selection signal S1 during the voltage conversion process will be greatly reduced, and the effect of power saving can be achieved. In addition, when the rising edge or falling edge of the selection signal S1 is divided into a plurality of segments, the voltage change of the rising edge or falling edge will become relatively gentle. This can also eliminate noise and solve the problem of poor touch.

In addition, the controller 120 uses a charge sharing mechanism to control the rising edge and / or the falling edge of the selection signal S2 to include five voltage levels VGL, AVEE, GND, AVDD, and VGH. In detail, the selection signal S2 is sequentially charged from the voltage level VGL to the voltage level AVEE, the ground voltage level GND, the voltage level AVDD, and the voltage level VGH. Then, it sequentially discharges from the voltage level VGH to the voltage level AVDD, the ground voltage level GND, the voltage level AVEE, and the voltage level VGL.

In addition, the controller 120 uses the charge sharing mechanism to control the rising edge of the selection signal S3 to include three voltage levels VGL, AVDD, and VGH, and the falling edge of the control selection signal S3 to include three voltage levels VGL, AVDD, VGH, and VGH, VGL / 2, VGL. In detail, the selection signal S3 is sequentially charged from the voltage level VGL to the voltage level AVDD and the voltage level VGH. Then, it sequentially discharges from the voltage level VGH to the voltage level VGH / 2 and the voltage level VGL.

In addition to the selection signal, the controller 120 uses a charge sharing mechanism to control the rising edge of the second scanning signal VG2 to include three voltage levels VGL, VGH / 2, and VGH.

In some embodiments, in addition to performing the charge sharing mechanism, the controller 120 can also align the rising edge of one of the signals with the falling edge of the other signal at the same time in order to achieve a better noise cancellation effect.

FIG. 6 is a flowchart of a driving method 600 according to an embodiment of the disclosure. In some embodiments, the driving method 600 is applied to the display device 100 of FIG. 1.

Please refer to Fig. 1, Fig. 2 and Fig. 6 together, and take Fig. 2 as an example below. However, this disclosure is not limited to this.

In step S602, the controller 120 in the display device 100 independently adjusts the length of one of the plurality of selection signals S1-S3 during the enabling period P3 in the scanning period D1 to enable the enabling period. The length of P3 is different from the lengths of the complex enable periods P1 and P2 of the other selection signals S1 and S2 in the scanning period D1.

In step S604, the controller 120 outputs the selection signals S1-S3 to the multiplexer 112 in the display device 100.

The details of the driving method 600 have been described in the foregoing descriptions of the embodiments, and will not be repeated here. In addition, within the spirit and scope of the embodiments of the present disclosure, these steps may be added, replaced, changed, and / or omitted as appropriate.

FIG. 7 is a flowchart of a driving method 700 according to an embodiment of the disclosure. In some embodiments, the driving method 700 is applied to the display device 100 of FIG. 1.

Please refer to Figure 1, Figure 2 and Figure 7 together, and The following will take Figure 2 as an example. However, this disclosure is not limited to this.

In step S702, the controller 120 in the display device 100 independently adjusts the voltage conversion rate SR3 of the voltage conversion edge E3 in the current control signal CS, so that the voltage conversion rate SR3 and the voltage conversion of other voltage conversion edges E1 and E2 are converted. The rates SR1 and SR2 are different. The voltage conversion edges E1-E3 correspond to the selection signals S1-S3, respectively.

In step S704, the controller 120 outputs the selection signals S1-S3 to the multiplexer 112 in the display device 100, and outputs the bias current Ibias to the multiplexer 112 according to the current control signal CS.

The details of the driving method 700 have been described in the foregoing descriptions of the embodiments, and are not repeated here. In addition, within the spirit and scope of the embodiments of the present disclosure, these steps may be added, replaced, changed, and / or omitted as appropriate.

In summary, by applying the above embodiment, the controller can independently adjust the width of the enable period of one of the selection signals of the multiplexer, or independently adjust one of the voltage conversion rates of the current control signal of the bias current. To improve the problem of insufficient charging.

Although this disclosure has been disclosed as above in the form of implementation, it is not intended to limit this disclosure. Any person with ordinary knowledge in the field can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, this disclosure The scope of protection shall be determined by the scope of the attached patent application.

100‧‧‧ display device

110‧‧‧display panel

112‧‧‧ Multiplexer

120‧‧‧ Controller

122‧‧‧Sequence Controller

124‧‧‧Gate driver

126‧‧‧Source Driver

1262‧‧‧Control Unit

R1, R2, G1, G2, B1, B2 ‧‧‧ sub pixels

DL1, DL2, DL3‧‧‧ data line

SL1, SL2‧‧‧scan line

XSTB‧‧‧ Loading signal

S1, S2, S3 ‧‧‧ Select signal

CS‧‧‧Current control signal

BUF‧‧‧Buffer

Ibias‧‧‧ bias current

VG1, VG2‧‧‧‧scan signal

Claims (10)

A display device includes: a display panel including a plurality of sub pixels and a multiplexer, the multiplexer including a plurality of output terminals, the output terminals are electrically coupled to the sub pixels, respectively; and a controller Is used to output a plurality of selection signals to the multiplexer; wherein the controller is further used to independently adjust the length of the uniform energy period of one of the selection signals in a scanning period, so that the length of the enable period and other The length of the plural enable periods of the selection signal in the scanning period is different. The display device according to item 1 of the patent application scope, wherein the controller is further configured to control a falling edge of one of the selection signals and a rising edge of another of the selection signals to be aligned in timing. . The display device according to item 1 of the scope of patent application, wherein the controller is further configured to output a scanning signal, and control a falling edge of the scanning signal and a rising edge of one of the selection signals to be aligned in timing, Alternatively, a rising edge of the scanning signal and a falling edge of one of the selection signals are controlled to be aligned in timing. The display device according to item 3 of the scope of patent application, wherein the controller is further configured to control the scan signal by using a charge sharing mechanism. Or one of the selected signals has at least three voltage levels. The display device according to item 1 of the scope of patent application, wherein the controller is further configured to output a first scanning signal and a second scanning signal, and control a falling edge of the first scanning signal and the second scanning signal. A rising edge of is aligned in timing. A driving method for driving a display device, the driving method comprising: independently adjusting a length of a uniform energy period of one of the plurality of selection signals during a scanning period by a controller in the display device; So that the length of the enabling period is different from the length of the multiple enabling periods of other selection signals in the scanning period; and the controller outputs the selection signals to a multiplexer in the display device. The driving method according to item 6 of the scope of patent application, further comprising: outputting a scanning signal by the controller; and controlling a falling edge of the scanning signal and a rising edge of one of the selection signals by the controller. The timing is aligned, or a rising edge of the scanning signal and a falling edge of one of the selection signals are aligned in timing. A display device includes: a display panel including a plurality of sub-pixels and a multiplexer, the multiplexer including a plurality of output terminals, each of which is electrically coupled to the sub-pixels; and a controller For outputting a plurality of selection signals to the multiplexer and outputting a bias current to the multiplexer according to a current control signal, the current control signal has a plurality of voltage conversion edges corresponding to a scanning period, and the The voltage conversion edges respectively correspond to the selection signals; wherein the controller is further configured to independently adjust the voltage conversion rate of one of the voltage conversion edges so that the voltage conversion rate of one of the voltage conversion edges and the voltage of the other voltage conversion edges are independent. The conversion rates are different. The display device according to item 8 of the scope of patent application, wherein the controller is further configured to output a scanning signal, and control a falling edge of the scanning signal and a rising edge of one of the selection signals to be aligned in timing, Alternatively, a rising edge of the scanning signal and a falling edge of one of the selection signals are controlled to be aligned in timing. A driving method for driving a display device. The driving method includes: independently adjusting a voltage conversion of one of a plurality of voltage conversion edges of a plurality of voltage conversion edges in a current control signal by a controller in the display device. Rate so that the voltage transition rate of one of the voltage transition edges is different from the voltage transition rate of the other voltage transition edges. The voltage conversion edge corresponds to a scanning period and each of a plurality of selection signals; and the controller outputs the selection signals to a multiplexer in the display device, and outputs a bias current according to the current control signal To the multiplexer.