TW201810019A - Floating-point divider and method for operating floating-point divider - Google Patents

Abstract

A floating-point divider operated based on first partial reminder, a divisor and a first quotient value to generate second partial reminder, and operated based on the second partial reminder, the divisor and second quotient value candidates to generate third partial reminder candidates. Based on a first quotient value look-up table, a second quotient value is obtained according to the second partial reminder and the divisor, and third quotient value candidates are obtained according to the third partial reminder candidates and the divisor. A first multiplexer outputs a third quotient value which is selected from the third quotient value candidates and corresponds to the second quotient value. The third quotient value is transformed to partial bits of the next-round quotient, or is output in this round of quotient calculation and used in prediction of the next-round quotient.

Description

Floating-point divider and floating-point divider operation method

This case is about floating-point dividers.

The floating-point divider needs to iterate repeatedly for multiple rounds of quotient calculation. However, in the face of large radix design requirements, the quotient calculated by each round of the floating-point divider has a considerable number of bits, and the logic circuit design is quite cumbersome.

This case proposes a floating-point divider that combines the short-bit quotient values obtained from multiple table lookups in one round of operation and outputs the combined quotient value of long-bit values, where each round of operations further includes prediction of the next round of operations The resulting bits of the combined quotient.

A floating-point divider implemented according to an embodiment of the present invention includes a round remainder generator, a remainder simulator, a first quotient table, and a first multiplexer. The current round partial remainder generator generates a second partial remainder according to a first partial remainder, a divisor and a first quotient. The partial remainder simulator generates a plurality of third partial remainder candidates according to the second partial remainder, the divisor, and a plurality of second quotient values to be measured. The first quotient table is queried to provide a second quotient corresponding to the second part of the remainder and the divisor. The first quotient table is further queried to provide a plurality of third quotient candidates corresponding to the third partial remainder candidates and the divisor. The first multiplexer is from the third quotient Check and select the output corresponding to the second quotient, as a third quotient. The third quotient value is used as a part of the combined quotient value of the next round of operation, or as a part of the combined quotient value of the current round, but is more used to predict the content required for the next round of operation.

A method for operating a floating-point divider implemented according to an embodiment of the present invention, for operating a floating-point divider including a first quotient table, includes: according to a first partial remainder, a divisor, and a first quotient , Generating a second partial remainder; generating a plurality of third partial remainder candidates according to the second partial remainder, the divisor, and a plurality of second quotient values to be measured; querying the first quotient table, the supply should correspond to the first A two-part remainder and a second quotient of the divisor; querying the first quotient table to supply the third-part remainder candidates and a plurality of third quotient candidates for the divisor; and providing a first multiple The worker selects the output corresponding to the second quotient from the third quotient candidates as a third quotient. The third quotient value is used as a part of the combined quotient value of the next round of operation, or as a part of the combined quotient value of the current round, but is more used to predict the content required for the next round of operation.

In this case, a round of operation of the floating-point divider does not only perform a query of the quotient table. The query results of the quotient table obtained multiple times can be combined, and the combined quotient value is output in one operation of the floating-point divider. The long-bit quotient value that a floating-point divider with a large radix should output in each round of operation can therefore be combined with multiple short-bit data obtained by looking up a table. In addition, the rounds of operations of the floating-point divider in this case further include prediction of the bits of the combined quotient value output by the next round of operations, which is far superior to the traditional floating-point divider architecture.

The embodiments are exemplified below, and the accompanying drawings are used to describe the content of the present invention in detail.

200‧‧‧ floating-point divider

202‧‧‧ Partial remainder generator

204‧‧‧Partial Residual Simulator

206‧‧‧First Quotient Form

207‧‧‧The first multiplexer

208‧‧‧Second quotient form and second multiplexer

210‧‧‧Quotient Converter

212‧‧‧Partial remainder generator for subsequent rounds

400‧‧‧ floating-point divider

410‧‧‧partial remainder simulator

420‧‧‧ First quotient form and first multiplexer

430‧‧‧Quotient Converter

440‧‧‧Partial remainder generator for subsequent rounds

d‧‧‧Divisor

Q‧‧‧Combined Quotient

q0 ... q3, q (i + 1), qa, qb, qc, qan‧‧‧quotient

qp1… qpN‧‧‧Second / third quotient value to be measured

S1 ... S3, S (i + 1), Sa, Sb, San‧‧‧partial remainder

S302 ... S314, S502 ... S518‧‧‧ steps

San1 ... SanN, Sc1 ... ScN, San11 ... San1N, ..., SanN1 ... SanNN‧‧‧Partial remainder candidates

qan1… qanN‧‧‧ third quotient candidate

w‧‧‧ dividend

w0… w2, w (i + 1) ‧‧‧ intermediate remainder

Fig. 1A illustrates each operand of division operation; Fig. 1B and Fig. 1C display a quotient table in two-dimensional coordinates; Fig. 2 illustrates a floating-point divider 200 according to an embodiment of the present case; and Fig. 3 is a flowchart 2 illustrates the operation method of the floating-point divider 200 in FIG. 2 to provide a division operation (w / d); FIG. 4 illustrates a floating-point divider 400 according to another embodiment of the present case; and FIGS. 5A and 5B are flowcharts. FIG. 4 illustrates the operation method of the floating-point divider 400 of FIG. 4 to provide a division operation (w / d).

The following description lists various embodiments of the present invention. The following description introduces the basic concepts of the present invention and is not intended to limit the present invention. The actual scope of the invention should be defined in accordance with the scope of the patent application.

FIG. 1A illustrates each operand of a division operation, including a dividend w and a divisor d. In the operation, quotient values q0, q1, q2, and q3 are sequentially obtained. It is worth noting that the four quotients q0 ~ q3 obtained by the operation here are just examples. The present invention is not limited to this. The number of quotients is determined by when the divisor w is divided by the divisor d or convergence, so the division operation is likely Obtain other quantities of quotient, not limited to four. In this embodiment, a radix 4 is adopted, that is, a quotient of 2 bits is generated every clock cycle. During the operation of the quotients q0, q1, q2, and q3, the decimal point of the intermediate remainder wi needs to be shifted to the right by 2 bits (that is, 4 × wi), and i is the number. In this case, both the value wi and 4 × wi are called partial remainders, and the label is S (i + 1). The quotient value q (i + 1) can be obtained by looking up the table according to the partial remainder S (i + 1) and the divisor d.

Figure 1B shows a quotient table in two-dimensional coordinates. A table lookup method is to use a partial remainder 4 × wi (that is, S (i + 1)) to look up the table, and compare the partial remainder 4 × wi (that is, S (i + 1)) with various multiples of the divisor d to obtain Corresponding quotient q (i + 1) lines. On the line of the quotient q (i + 1), the remainder 4 × wi, which is a certain multiple of the divisor d, has the same quotient q (i + 1) within a certain range, as shown in Figure 1B, as [- d, d] Partial remainder 4 × wi in the interval corresponds to the quotient q (i + 1) = 0. The following describes in detail how to query the quotient value table to obtain the corresponding quotient value in conjunction with FIG. 1A, for example, the partial remainder 4 × w0 = 1.110101B 1.75D (where B represents a binary number and D represents a decimal number), the divisor d = 1.101B 1.625D, the partial remainder 4 × w0 appears to be approximately 1.08 times the divisor d, so querying the quotient table in Figure 1B shows that the corresponding quotient q1 = 1. Partial remainder 4 × wi (ie S (i + 1)) axis can be designed with multiple critical values, so that the partial remainder 4 × wi corresponding to multiple quotients q (i + 1) lines can be correctly derived from these quotients The q (i + 1) line selects the correct counterpart. Figure 1C shows a quotient table with another two-dimensional coordinate, in which wi is used as the partial remainder, that is, the value on the S (i + 1) axis is the value of wi. Compared with various multiples of the divisor d, the corresponding quotient q (i + 1) lines can be obtained. The quotient table in FIG. 1B or 1C is used to obtain a quotient value q (i + 1) according to a lookup table based on the partial remainder S (i + 1) and the divisor d. The above quotient table concept can be used in various radix floating-point divider applications. In this embodiment, a radix 4 is used, that is, a two-bit quotient is generated every clock cycle. If the quotient table can only be queried once per clock cycle, the range of the quotient is {-2, -1, 0,1,2}. In the embodiment using other cardinality, for example, using a cardinality of 16, a quotient of 4 bits is generated per clock cycle. If the quotient table can only be queried once per clock cycle, the value range of the quotient is {-15 , -14, -13, -12, ...- 1,0,1, ... 12,13,14,15}, that is, [-15,15], but the present invention is not limited to this, and adopts different When the quotient value encoding method is used, the value range of the quotient value will be different. It is time-consuming to query the quotient value table in the floating-point division operation, and the more quotient bits are obtained each time the table is looked up, the greater the hardware overhead. Therefore, the present invention proposes a floating-point divider that performs multiple rounds of quotient table query in one round of operation. Even if a quotient table with less hardware overhead is used, for example, only 2 digit quotients can be obtained even with each table lookup. A table of values (for example, querying the quotient table in Figure 1B). You can also get a 4-bit quotient value in two rounds of query operations, that is, to implement a base 16, such as SRT-16, without having to use a quotient with a large hardware overhead. A table of quotients with a value range of [-15,15].

In this case, a round of operation of the floating-point divider does not only perform a query of the quotient table. The query results of the quotient table obtained multiple times can be combined, and the combined quotient value is output in one operation of the floating-point divider. The long-bit quotient value that a floating-point divider with a large radix should output in each round of operation can therefore be combined with the short-bit data obtained from the look-up table. In addition, the rounds of operations of the floating-point divider in this case further include prediction of the bits of the combined quotient value output by the next round of operations, which is far superior to the traditional floating-point divider architecture.

FIG. 2 illustrates a floating-point divider 200 according to an embodiment of the present case, including a round part remainder generator 202, a part remainder simulator 204, a first quotient table 206, a first multiplexer 207, a first Two quotient tables and a second multiplexer (combined with block 208), a quotient converter 210, and a subsequent round of partial residue generator 212.

The current partial remainder generator 202 generates a second partial remainder Sb according to a first partial remainder Sa, a divisor d, and a first quotient qa. The partial remainder simulator 204 is based on the second partial remainder Sb, the divisor d, and a plurality of The second quotient values qp1 ... qpN generate a plurality of third part remainder candidates San1 ... SanN. The measured values of the second quotient values qp1 ... qpN can be all possible values of the second quotient value qb. For example, the values of qp1 ... qpN are all possible quotient values in the quotient value table of FIG. 1B or FIG. The first quotient table 206 is queried to provide a second quotient qb corresponding to the second partial remainder Sb and the divisor d. The first quotient table 206 is further used for querying and supplying a plurality of third quotient candidates qan1 ... qanN corresponding to the third partial remainder candidates San1 ... SanN and the divisor d, and the multiplexer 207 sends The second quotient qb selects an output corresponding to the second quotient qb from the third quotient candidates qan1 ... qanN as a third quotient qan, that is, the second quotient qb (as a plurality of The third quotient candidate (one of qan1 ... qanN) corresponding to the third partial remainder candidate (one of San1 ... SanN) corresponding to the second quotient value to be measured qp1 ... qpN) is used as the third quotient value qan. In particular, the second quotient table and the second multiplexer (208) are used in a first round operation of the floating-point divider 200, corresponding to a dividend w and the divisor d to supply the first The quotient qa and the first partial remainder Sa go to the current round partial remainder generator 202. As shown in the figure, the quotient value converter 210 converts and combines the first quotient value qa and the second quotient value qb that each provide M-bit information into a 2M-bit combined quotient value Q in each round of operations. M is a numerical value. As for the third quotient qan, this embodiment uses it as a part of the bits of the combined quotient Q in the next round. The third quotient qan will be switched and supplied by the second multiplexer in block 208 as the first quotient qa for the next round of calculation. As for the first part of the remainder Sa required for the next round of combined quotient Q operation, it is provided by the subsequent part of the remainder generator 212. The subsequent round partial remainder generator 212 generates a third partial remainder San based on the second partial remainder Sb, the divisor d, and the second quotient value qb. The second multiplexer in block 208 switches to supply the first partial remainder Sa required for the next round of operations. As mentioned above, the second quotient table and the second multiplexer (208) are used to query the dividend w and the divisor d in the first round of the floating-point divider 200 to obtain the first remainder Sa and the first A quotient qa is used; in subsequent calculations, the second quotient table in block 208 need not be used. Instead, the second multiplexer in block 208 directly selects the third quotient obtained in the previous calculation. qan is used as the first quotient value qa of the current round of operations, and the third part of the remainder San obtained from the previous round of operations is selected as the first part of the remainder Sa of this round of operations.

In one embodiment, the current round part remainder generator 202, the partial remainder simulator 204, and the subsequent round part remainder generator 212 are all based on r × wi-q (i + 1) × d = w (i + 1) Designed for operations, where r is the intermediate remainder wi shift bit amount. For example, in the embodiment of FIG. 1A, r has a value of 4, w (i + 1) = 4 × wi-q (i + 1) × d, and part of the remainder S (i + 1) = 4 × wi. Specifically, For example, d = 1.101B, and query the quotient table according to the first part of the remainder S1 = 4 × w0 = 1.110101B to get q1 = 1; then w1 = 4 × w0-q1 × d = 1.110101B-1 × 1.101B = 0.001101B, the remainder of the second part S2 = 4 × w1 = 0.1101B. Depending on the different definitions of the partial remainder S (i + 1) (for example, S (i + 1) = r × wi or S (i + 1) = wi), the current partial remainder generator 202 and the partial remainder simulator The logic circuit design of 204 and the subsequent round partial remainder generator 212 will be adjusted accordingly. The current round part remainder generator 202, the partial remainder simulator 204, and the subsequent round part remainder generator 212 may use serial adders, adders, multipliers, etc. to implement the above-mentioned r × wi-q (i +1) × d = w (i + 1) operation, so that the partial remainder S (is output according to the partial remainder S (i + 1) (that is, r × wi or wi), the divisor d, and the quotient value q (i + 1) i + 2) (i.e. r × w (i + 1) or w (i + 1)). First quotient form 206 It is also established based on the definition of some remainders.

Taking the base 256 as an example, the combined quotient value Q that each round of operations of the floating-point divider 200 should output is 8 bits, in which the higher 4 bits are provided by the first quotient qa and the lower 4 bits are provided by the second quotient. qb provided. The 4-bit quotient calculation is much less expensive and simpler than the 8-bit hardware. The displacement of the intermediate remainder wi is only ²⁴ bits, which is far lower than the ²⁸ bits required by the traditional floating-point divider architecture. In addition, regarding the architecture of the floating-point divider 200 with a base of 256, the second quotient values to be measured qp1 ... qpN can be set to {-15, -14, -13, -12, ...- 1,0,1 ,. ..12,13,14,15} so 31 values to estimate 31 candidates for the third part of the remainder. Of course, the present invention is not limited to the quotient range of the base 256 being [-15,15]. When different quotient encoding methods are adopted, the range of the quotient value will be different, which is [-N, N] in total. 2N + 1 values, where N {8,9,10,11,12,13,14,15}.

FIG. 3 is a flowchart illustrating the operation method of the floating-point divider 200 of FIG. 2 to provide a division operation (w / d).

Step S302 receives the dividend w and the divisor d, and obtains the first quotient qa according to the second quotient table in the query block 208. Step S304 operates the current round partial remainder generator 202 to generate a second partial remainder Sb according to the dividend w (the first partial remainder Sa calculated as the first round combined quotient value Q), the divisor d, and the first quotient qa. Step S306 operates the partial remainder simulator 204 to generate a third partial remainder candidate San1 ... SanN according to the second partial remainder Sb, the divisor d, and the second quotient values to be measured qp1 ... qpN. Step S308 queries the first quotient table 206 to obtain the second quotient qb according to the second partial remainder Sb and the divisor d. Step S310 queries the first quotient table 206 to obtain the third quotient candidates qan1 ... qanN according to the third part of the remaining candidate candidates San1 ... SanN and the divisor d, and passes them to the first multiplexer 207 to generate according to step S308. The second quotient value qb is selected from the third quotient value candidates qan1 ... qanN as an output corresponding to the second quotient value qb as the third quotient value qan. Step S312 operates the subsequent-round partial remainder generator 212 to generate a third partial remainder San based on the second partial remainder Sb, the divisor d, and the second quotient value qb. In step S314, the third quotient qan and the third part remainder San are passed to the current round part remainder generator 202 via the second multiplexer in block 208, respectively, and are used as the first round required for the new round of operation of the floating-point divider 200. A quotient qa and the first part of the remainder Sa, that is, the third quotient value qan generated in the previous operation is used as the first quotient qa required for the new operation, and the third part of the remainder San generated in the previous operation is used as the new The first part of the remainder Sa required for the operation is used to generate the second part of the remainder Sb for the new round of operation, and the flow returns to step S306. The process shown in Figure 3 can be cyclically operated until some of the remaining bits are insufficient. The disclosed division process will obtain the first quotient value qa and the second quotient value qb in each round of operation, and convert and combine them into a combined quotient value Q. All the combined quotients Q obtained in different rounds of operation will be recombined into the result of the division operation w / d. In other embodiments, step S308 may be arranged before step S306, or may be arranged in step S310, that is, step S306 and step S308 are not in any order.

FIG. 4 illustrates a floating-point divider 400 according to another embodiment of the present case. Compared with the floating-point divider 200, a partial remainder simulator 410, a first quotient table, and a first multiplexer (combined with block 420) Representation), quotient value converter 430, and subsequent round part remainder generator 440, so that the combined quotient value Q obtained by each round of operation is converted from three quotient values qa, qb, and qc.

The partial remainder simulator 410 generates a plurality of third partial remainder candidates Sc1 ... ScN based on the second partial remainder Sb, the divisor d and a plurality of second quotient values to be measured qp1 ... qpN. Remainder candidate Sc1 ... ScN, the divisor d, and a plurality of third quotient values to be measured (this example is also qp1 ... qpN) generate a plurality of fourth part remainder candidates San11 ... San1N, ..., SanN1 ... SanNN. After querying the first quotient table in block 420, a second quotient value qb corresponding to the second part remainder Sb and the divisor d is supplied; the first quotient table in block 420 is further queried, corresponding to Wait for the third part of the remainder candidates Sc1 ... ScN and the divisor d to supply a plurality of third quotient candidates qc1 ... qcN (not shown in the figure) to the first multiplexer in block 420 from this second quotient qb from the After the third quotient candidate qc1 ... qcN is selected, an output corresponding to the second quotient value qb is selected as a third quotient value qc, that is, the second quotient value qb is selected first (as a plurality of second quotient values to be measured qp1). The third quotient candidate (one of qc1 ... qcN) corresponding to the third partial remainder candidate (one of Sc1 ... ScN) corresponding to one of qpN) is used as the third quotient value qc. In addition, the first quotient table in block 420 is further queried. According to the (N × N) fourth part remainder candidates San11 ... San1N, ..., SanN1 ... SanNN and the divisor d, a plurality of fourth quotients are supplied. The value candidates qan11 ... qan1N, ..., qanN1 ... qanNN (not shown) are assigned to the first multiplexer in block 420 corresponding to the second quotient value qb and the third quotient value qc as a fourth quotient. The value qan is output. Specifically, for example, the first multiplexer in block 420 selects the second quotient value qb (as one of the plurality of second quotient values to be measured qp1 ... qpN) according to the second quotient value qb obtained from the look-up table. Corresponding to the N fourth part remainder candidates (San11 ... San1N, ..., SanN1 ... SanNN, for example, Sani1 ... SaniN); then according to the table The third quotient value qc is selected from the N selected fourth partial remainder candidates (such as Sani1 ... SaniN) as the third quotient value qc (as a plurality of third quotient values to be measured, which is also qp1 ... the fourth corresponding to qpN) The fourth quotient candidate (which is one of qani1 ... qaniN) corresponding to the partial remainder candidate (which is one of Sani1 ... SaniN) is output as the fourth quotient value qan. In other embodiments, the second quotient value qb may be further input to the partial remainder simulator 410, so that the partial remainder simulator 410 no longer redundantly provides the third partial remainder candidates Sc1 ... ScN and the fourth partial The remaining candidates San11 ... San1N, ..., SanN1 ... SanNN do not correspond to the second quotient qb.

As for the quotient converter 430, it is designed in each round of operation to convert the first quotient value qa, the second quotient value qb, and the third quotient value qc, which provide M-bit information, into 3M bits. The combined quotient Q is the value of M. Taking radix 2 ⁹ as an example, the floating-point divider 400 can generate a 9-bit combined quotient value Q in each round of operation, which is a 3-bit first quotient value qa, a 3-bit second quotient value qb, and The 3 digit third quotient qc is combined with the conversion.

The operation of the remainder generator 440 in the subsequent rounds is as follows. Based on the second partial remainder Sb, the divisor d, and the second quotient value qb, the subsequent round partial remainder generator 440 generates a third partial remainder Sc (inside block 440, not shown in the figure), and more The third partial remainder Sc (not shown in the figure), the divisor d and the third quotient value qc generate a fourth partial remainder San. The fourth quotient qan and the fourth partial remainder San generated by the floating-point divider 400 are switched by the second multiplexer in block 208 after the first round of operations of the floating-point divider 400, and the next round of operations is switched. The required first quotient qa and the first partial remainder Sa. Compared with the floating-point divider 200, the third quotient qc generated by the floating-point divider 400 is used as part of the combined quotient value Q of the current round, but is more used to predict the content required for the next round of operations (for example, qan and San were obtained based on qc). Compared to the floating-point divider 200, the floating-point divider 400 performs three operations of querying the quotient table in parallel in the same round of operations. In which, the partial remainder simulator 410 performs operations to generate N third partial remainder candidates Sc1 ... ScN, and then performs nested operations based on the generated N third partial remainder candidates Sc1 ... ScN to generate N × N fourth parts Residual candidates San11 ... San1N, ..., SanN1 ... SanNN, with the determined qb and qc as the selection signals of the multiplexer logic in the first multiplexer in block 420, from N × N fourth partial remainder candidates San11 ... San1N , ..., SanN1 ... SanNN selects one of the N × N q values corresponding to as the qan output. The embodiment of FIG. 4 performs the query operations of the three quotient tables of the time-consuming outputs qb, qc, and qan side by side so that they can be completed in the same round of calculations. Compared with the prior art, it must wait for the first round of table lookups to obtain the first After the second quotient value qb, the third quotient value Sc is calculated by the second quotient value qb for the second round of table lookup to obtain the third quotient value qc, and then the fourth quotient value San is calculated by the third quotient value qc. The third round of table lookup was qan, which greatly reduced the time consuming.

5A and 5B are flowcharts illustrating the operation method of the floating-point divider 400 in FIG. 4 to provide a division operation (w / d).

Step S502 receives the dividend w and the divisor d, and obtains the first quotient qa by querying the second quotient table in the block 208. Step S504 operates the current round partial remainder generator 202 to generate a second partial remainder Sb according to the dividend w (the first partial remainder Sa calculated as the first round combined quotient value Q), the divisor d, and the first quotient qa. Step S506 operates the partial remainder simulator 410 to generate a third partial remainder candidate Sc1 ... ScN according to the second partial remainder Sb, the divisor d, and the second quotient value to be measured qp1 ... qpN. Step S508 operates the partial remainder simulator 410 again to generate the fourth partial remainder candidates San11 ... San1N, based on the third partial remainder candidates Sc1 ... ScN, the divisor d, and the third quotient value to be measured (the same example is qp1 ... qpN). ..., SanN1 ... SanNN. Step S510: query the block based on the second part of the remainder Sb and the divisor d The first quotient table in 420 obtains the second quotient qb. Step S512 queries the first quotient table in block 420 to obtain the third quotient candidates qc1 ... qcN according to the third part of the remaining candidate Sc1 ... ScN and the divisor d, and passes it to the first multiplexer in block 420 according to step S510 The generated second quotient value qb selects an output corresponding to the second quotient value qb from the third quotient value candidates qc1 ... qcN as the third quotient value qc. In step S514, the fourth quotient candidates qan11 ... qan1N, ..., according to the fourth part of the remaining candidate candidates San11 ... San1N, ..., SanN1 ... SanNN (N × N) and the divisor d are searched for the first quotient value table in the block 420. qanN1... qanNN (N × N) are selected by the first multiplexer in block 420 and corresponding to the second and third quotients qb and qc are output as the fourth quotient qan. Step S516 operates the subsequent partial remainder generator 440 to generate a third partial remainder Sc (within block 440) based on the second partial remainder Sb, the divisor d, and the second quotient value qb, and further according to the third partial remainder Sc, the The divisor d and the third quotient qc produce a fourth partial remainder San. In step S518, the fourth quotient qan and the fourth partial remainder San are passed to the current round partial remainder generator 202 via the second multiplexer in block 208, respectively, and are used as the first round required by the new round of floating-point divider 400 operation. A quotient qa and the first part remainder Sa are used to generate the second part remainder Sb of the new round of operation, and the flow returns to step S506. The processes shown in Figures 5A and 5B can be cyclically operated until some of the remaining bits are insufficient. The disclosed division process will obtain the first quotient value qa, the second quotient value qb, and the third quotient value qc in each round of operation, and the operation quotient converter 430 converts and combines the combined quotient value Q. All the combined quotients Q obtained in different rounds of operation will be recombined into the result of the division operation w / d. In other embodiments, steps S510 and S512 can be fine-tuned to the front or back steps.

In other embodiments, part of the remainder simulator can simulate The number of quotients can be more than one (qan) shown in Figure 2 or two (qc and qan) shown in Figure 4. Following the same concept as above, some remainder simulators can even simulate more than two quotients.

Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

200‧‧‧ floating-point divider

202‧‧‧ Partial remainder generator

204‧‧‧Partial Residual Simulator

206‧‧‧First Quotient Form

207‧‧‧The first multiplexer

208‧‧‧Second quotient form and second multiplexer

210‧‧‧Quotient Converter

212‧‧‧Partial remainder generator for subsequent rounds

d‧‧‧Divisor

Q‧‧‧Combined Quotient

qa, qb, qan‧‧‧‧ the first, second and third quotients

qp1… qpN‧‧‧Second quotient value to be measured

qan1… qanN‧‧‧ third quotient candidate

Sa, Sb, San‧‧‧‧ remainder of the first, second and third parts

San1 ... SanN‧‧‧ Part III Remaining Candidate

w‧‧‧ dividend

Claims (16)

A floating-point divider includes: a round partial remainder generator that generates a second partial remainder based on a first partial remainder, a divisor, and a first quotient; a partial remainder simulator based on the second partial remainder , The divisor and a plurality of second quotient values to be measured to generate a plurality of third partial remainder candidates; and a first quotient value table and a first multiplexer, wherein: the first quotient value table is queried, The supply corresponds to the second part of the remainder and a second quotient of the divisor; the first quotient table is further queried to supply the third part of the remainder candidates and the plurality of third quotient candidates of the divisor; And the first multiplexer selects the output corresponding to the second quotient from the third quotient candidates as a third quotient. The floating-point divider according to item 1 of the scope of patent application, wherein the first multiplexer selects the third corresponding to the third quotient among the plurality of second quotient values to be measured. The third quotient candidate corresponding to the partial remainder candidate is used as the third quotient. The floating-point divider described in item 1 of the patent application scope further includes a second quotient table, in which, in a first round operation of the floating-point divider, the second quotient table is queried and corresponds to A dividend and the divisor supply the above-mentioned first quotient; and in the above-mentioned first round of operation, the dividend is used as the first-part remainder input to the current-part remainder generator. The floating-point divider described in item 1 of the scope of patent application, further includes: a quotient converter, which provides the first quotient value and the second quotient value of M bits of information in each round of operation. The combination is converted into a quotient of 2M bits, where M is a value. The floating-point divider according to item 1 of the scope of patent application, further comprising: a subsequent round of partial remainder generators, which generates a third partial remainder based on the second partial remainder, the divisor, and the second quotient; And a second multiplexer, switching to output the third quotient value as the first quotient value, and outputting the third part remainder as the first part remainder. The floating-point divider according to item 1 of the scope of patent application, wherein: the remainder simulator of the part is further based on the third part of the remainder candidates corresponding to the second quotient, the divisor, and a plurality of third quotients The measured value generates a plurality of fourth-part remainder candidates; the first quotient value table is further queried to supply the plurality of fourth-part remainder candidates corresponding to the fourth-part remainder candidates and the divisor; and the first plurality The worker further selects the output corresponding to the third quotient from these fourth quotient candidates as a fourth quotient. The floating-point divider described in item 1 of the scope of patent application, further includes: a quotient converter, which provides the first quotient value and the second quotient value of M bits of information in each round of operation. And the third quotient conversion is combined into a quotient of 3M bits, where M is a numerical value. The floating-point divider according to item 6 of the scope of patent application, further comprising: a subsequent round of partial remainder generators, generating a third partial remainder based on the second partial remainder, the divisor, and the second quotient, and More according to the third part The remainder, the divisor, and the third quotient value generate a fourth partial remainder; and a second multiplexer switches the fourth quotient value as the first quotient and outputs the fourth partial remainder as The remainder of the first part above. A floating-point divider operation method for operating a floating-point divider including a first quotient table, comprising: generating a second partial remainder according to a first partial remainder, a divisor, and a first quotient; According to the second part remainder, the divisor, and a plurality of second quotient values to be measured, a plurality of third part remainder candidates are queried; the first quotient table is queried to supply the corresponding second part remainder and the divisor. A second quotient value; querying the first quotient value table, supplying a plurality of third quotient value candidates corresponding to the third partial remainder candidates and the divisor; and providing a first multiplexer from the third Among the quotient candidates, the output corresponding to the second quotient is selected as a third quotient. The method of operating a floating-point divider as described in item 9 of the scope of patent application, wherein operating the first multiplexer selects the corresponding one of the second quotient values among the plurality of second quotient values to be measured corresponding to the second quotient value. The third quotient candidate corresponding to the third partial remainder candidate is used as the third quotient. The method for operating a floating-point divider as described in item 9 of the scope of the patent application, further includes: providing a second quotient table; in each round of operations of the floating-point divider, querying the second quotient table, The first quotient is supplied corresponding to a dividend and the divisor; and in the first round of operation, the dividend is used as the first partial remainder. The method for operating a floating-point divider as described in item 9 of the scope of the patent application, further includes: providing a quotient converter, in each round of operation, each of the first quotient and the first quotient of M bits of information are provided. The two quotient value conversions are combined into a quotient value of 2M bits, where M is a numerical value. The method of operating a floating-point divider as described in item 9 of the scope of patent application, further comprising: generating a third partial remainder according to the second partial remainder, the divisor, and the second quotient; and providing a second multiple And the switch switches and outputs the third quotient value as the first quotient value, and outputs the third part remainder as the first part remainder. The method of operating a floating-point divider as described in item 9 of the scope of the patent application, further includes: according to the third part of the remainder candidates corresponding to the second quotient value, the divisor and a plurality of third quotient values to be measured , Generating a plurality of fourth part remainder candidates; querying the first quotient value table to supply a plurality of fourth quotient candidates corresponding to the fourth part remainder candidates and the divisor; and using the first multiplexer from the After the fourth quotient candidate is selected, the output corresponding to the third quotient is selected as a fourth quotient. The method of operating a floating-point divider as described in item 9 of the scope of patent application, further includes: A quotient converter is provided. In each round of operation, the first quotient value, the second quotient value, and the third quotient value that each provide M bit information are combined into a 3M bit quotient value. The M is a numerical value. The method for operating a floating-point divider according to item 14 of the scope of patent application, further comprising: generating a third part remainder according to the second part remainder, the divisor, and the second quotient value, and further according to the third part The remainder, the divisor, and the third quotient to generate a fourth partial remainder; and providing a second multiplexer to switch the fourth quotient as the first quotient and output the fourth partial remainder as The remainder of the first part above.