TW201818564A - Light-emitting element - Google Patents

Abstract

A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer emitting an UV light, formed between the first semiconductor layer and the second semiconductor layer; a first layer formed on the second semiconductor layer, the first layer including metal oxide; and a second layer formed on the first layer, the second layer including graphene, wherein the first layer is formed over all top surface of the second semiconductor layer, the first layer comprises a thickness smaller than 10 nm.

Description

Light emitting element

The present invention relates to a light emitting element, and more particularly to a light emitting element, which includes a semiconductor stack and a conductive layer on the semiconductor stack.

Light-Emitting Diode (LED) is a solid-state semiconductor light-emitting element, which has the advantages of low power consumption, low thermal energy generation, long working life, shock resistance, small size, fast response speed, and good photoelectric characteristics, such as Stable emission wavelength. Therefore, light-emitting diodes are widely used in household appliances, equipment indicators, and optoelectronic products.

A light-emitting element includes a semiconductor stack having a first semiconductor layer, a second semiconductor layer, and an active layer capable of emitting UV light is located between the first semiconductor layer and the second semiconductor layer; a first layer is located at the second Above the semiconductor layer, the first layer contains a metal oxide; and a second layer is located above the first layer and the second layer contains graphene, wherein the first layer covers the entire surface of the second semiconductor layer, and the first layer The layer contains a thickness of less than 10 nm.

A method for manufacturing a light-emitting element includes providing a semiconductor stack, the semiconductor stack having a first semiconductor layer, a second semiconductor layer, and an active layer capable of emitting UV light, which is located between the first semiconductor layer and the second semiconductor layer. Forming a first layer on the second semiconductor layer, the first layer comprising a metal oxide; and forming a second layer on the first layer, the second layer comprising graphene, wherein the first layer is the entire surface Covering the second semiconductor layer, the first layer includes a thickness less than 10 nm.

In order to make the description of the present invention more detailed and complete, please refer to the description of the following embodiments and cooperate with related drawings. However, the examples shown below are for exemplifying the light-emitting element of the present invention, and the present invention is not limited to the following examples. In addition, the dimensions, materials, shapes, relative arrangement, etc. of the component parts described in the examples in the present specification are not limited, and the scope of the present invention is not limited thereto, but merely a simple description. In addition, the size or positional relationship of the components shown in each illustration may be exaggerated for clarity. Furthermore, in the following description, in order to appropriately omit detailed descriptions, components of the same or the same nature are displayed with the same name and symbol.

FIG. 1 to FIG. 3 are manufacturing methods of a light emitting element 1 disclosed in an embodiment of the present invention.

As shown in FIGS. 1 to 3, the manufacturing method of the light-emitting element 1 includes providing a substrate 10; forming a semiconductor stack 20 on the substrate 10, wherein the semiconductor stack 20 includes a first semiconductor layer 21 and a second The semiconductor layer 22 and an active layer 23 are located between the first semiconductor layer 21 and the second semiconductor layer 22; a first layer 51 is formed on the semiconductor stack 20; a carrier 500 is provided; a second layer 52 is formed on the carrier 500; forming a support layer 55 on the second layer 52; removing the carrier 500; bonding the second layer 52 to the first layer 51 and removing the support layer 55; forming a first electrode 30 on the first semiconductor layer 21 And a second electrode 40 on the second semiconductor layer 22; and an insulating layer 60 is formed to cover the semiconductor stack 20 and / or one surface of the first electrode 30 and the second electrode 40.

In one embodiment of the present invention, the substrate 10 is provided as a growth substrate, and includes a gallium arsenide (GaAs) wafer for growing aluminum gallium indium phosphide (AlGaInP), or for growing indium gallium nitride (AlGaInP) InGaN), sapphire (Al ₂ O ₃ ) wafers, aluminum gallium nitride (AlGaN) wafers, gallium nitride (GaN) wafers, or silicon carbide (SiC) wafers.

In one embodiment of the present invention, organic metal chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), physical vapor deposition (PVD), or ions are used. An electroplating method is used to form a semiconductor stack 20 having optoelectronic characteristics on the substrate 10, such as a light-emitting stack. The physical weather deposition method includes a sputtering method or an evaporation method. The first semiconductor layer 21 and the second semiconductor layer 22 may be a cladding layer or a confinement layer. The two have different conductivity types, electrical properties, polarities, or different doping elements. An electron or a hole is provided. For example, the first semiconductor layer 21 is an n-type semiconductor and the second semiconductor layer 22 is a p-type semiconductor. The active layer 23 is formed between the first semiconductor layer 21 and the second semiconductor layer 22, and electrons and holes are recombined in the active layer 23 under a current drive to convert electric energy into light energy to emit a light. The wavelength of light emitted by the light emitting element 1 is adjusted by changing the physical and chemical composition of one or more layers in the semiconductor stack 20. The material of the semiconductor stack 20 includes a III-V semiconductor material, such as Al _x In _y Ga _(1-xy) N or Al _x In _y Ga _(1-xy) P, where 0 ≦ x, y ≦ 1; (x + y) ≦ 1.

In one embodiment of the present invention, when the material of the active layer 23 is an AlGaN series or AlInGaN series material, it can emit ultraviolet light (UV) with a wavelength between 400 nm and 250 nm. The active layer 23 may be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), a multi-quantum well structure (multi-quantum well, MQW). The material of the active layer 23 may be a neutral, p-type or n-type semiconductor.

In one embodiment of the present invention, PVD aluminum nitride (AlN) is formed between the semiconductor stack 20 and the substrate 10. PVD aluminum nitride (AlN) can be used as a buffer layer to improve the semiconductor stack 20 Crystal quality. In one embodiment, the target used to form the PVD aluminum nitride (AlN) is composed of aluminum nitride. In another embodiment, a target made of aluminum is used to react with the aluminum target to form aluminum nitride under the environment of a nitrogen source.

In an embodiment of the present invention, as shown in FIG. 1, a carrier 500 having a thickness is first placed in a horizontal furnace tube, and hydrogen is passed under an inert environment and heated to more than 800 ° C. to remove the surface of the carrier 500. The primary oxide layer is passed into a carbon-containing gas source to form a second layer 52 on the surface of the carrier 500. Finally, an inert gas is passed to accelerate the cooling of the furnace tube, and the furnace tube is cooled to room temperature. The carrier 500 is then provided with a support layer 55 to cover the surface of the second layer 52 and the carrier 500 is removed. Specifically, for example, a copper foil is selected as the carrier 500, and the thickness of the copper foil itself is 25 μm. The copper foil is placed in a horizontal furnace tube, and 10 sccm of hydrogen gas is passed under an argon (Ar) gas environment and heated to 900 ° C. To remove the primary oxide layer on the surface of the copper foil, a 5 sccm carbon-containing gas source, such as methane, is passed to form a second layer 52, such as graphene, on the surface of the copper foil, and finally 100 sccm argon is passed to accelerate it. The furnace tube is cooled, the furnace tube is cooled to room temperature, and the copper foil formed with graphene is taken out. Then, a thermal release tape is used as the support layer 55, and it is pasted on the surface of the graphene, and Immerse in a solution of iron trichloride (FeCl ₃ ) to remove copper foil by etching.

In one embodiment of the present invention, the carrier 500 includes a metal material as a metal catalyst to grow graphene. The carrier 500 may be a flexible substrate. The shape of the carrier 500 is not limited, including rectangular or circular.

In one embodiment of the present invention, the support layer 55 includes a polymer material, such as polymethyl methacrylate (PMMA). The thickness of the support layer 55 is, for example, 10 nm to 2 cm.

In an embodiment of the present invention, as shown in FIG. 2, a metal oxide, such as nickel oxide, is deposited by atomic layer chemical vapor deposition (ALD) to a thickness of 0.1 to 5 nanometers on the semiconductor stack 20 to form First layer 51. In one embodiment of the present invention, the precursors are, for example, water and NiCp ₂ , and the plating rate is 0.42 A / cycle. In one embodiment of the present invention, the thickness of the first layer 51 is between 0.1 and 5 nm.

In one embodiment of the present invention, the first layer 51 is used as a thin film having high transmittance in the UV light range and good conductivity. To increase the transmittance of the first layer 51 in UV light, it is necessary to Make extremely thin films, such as less than 10 nanometers, but when the film thickness is less than 10 nanometers, the film will form island discontinuities, which will increase the contact resistance of the film; if you want to make a continuous film, then The disadvantage of increasing the thickness of the film is to reduce the penetration of the film to UV light. In one embodiment of the present invention, a first layer 51 containing a metal oxide is formed by using atomic layer chemical vapor deposition (ALD). The first layer 51 is entirely covered on the semiconductor stack 20, and the first layer 51 is Has a thickness variation of less than 5 nm, preferably 2 nm.

In one embodiment of the present invention, as shown in FIG. 1 and FIG. 2, the support layer 55 is pressed by a hot stamping method and heated to a temperature above 130 ° C. to attach the second layer 52 to the plated substrate. On the semiconductor stack 20 of layer 51, the support layer 55 is removed, leaving a second layer 52 on top of the first layer 51.

In one embodiment of the present invention, the first electrode 30 and / or the second electrode 40 may be a single layer or a stacked structure. In order to reduce the resistance connected to the semiconductor stack 20, the material of the first electrode 30 and / or the second electrode 40 includes a metal material, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), Metals such as aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or alloys of the above materials.

In one embodiment of the present invention, the material of the first electrode 30 and / or the second electrode 40 includes a metal having high reflectivity, such as aluminum (Al), silver (Ag), or platinum (Pt).

In one embodiment of the present invention, one side of the first electrode 30 and / or the second electrode 40 in contact with the semiconductor stack 20 includes chromium (Cr) or titanium (Ti) to increase the first electrode 30 and / or The bonding strength between the second electrode 40 and the semiconductor stack 20.

In one embodiment of the present invention, the insulating layer 60 is used to protect the semiconductor layer from the external environment. The insulating layer 60 is light-transmissive and is formed of a non-conductive material, including organic materials such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), acrylic resin (Acrylic Resin), Cyclic olefin polymer (COC), Polymethyl methacrylate (PMMA), Polyethylene terephthalate (PET), Polycarbonate (PC), Polyetherimide Fluorocarbon polymer, or inorganic materials, such as Silicone, Glass, or dielectric materials, such as aluminum oxide (Al ₂ O ₃ ), silicon nitride (SiN _x ), Silicon oxide (SiO _x ), titanium oxide (TiO _x ), or magnesium fluoride (MgF _x ).

The structure shown in FIG. 3 is a light-emitting element 1 according to an embodiment of the present invention. The light-emitting element 1 includes a semiconductor stack 20 having a first semiconductor layer 21, a second semiconductor layer 22, and an active layer 23 capable of emitting UV light between the first semiconductor layer 21 and the second semiconductor layer 22; The conductive layer 50 is located on the second semiconductor layer 22. The conductive layer 50 includes a first layer 51 on one side close to the second semiconductor layer 22, and a second layer 52 on a side far from the second semiconductor layer 22.

In one embodiment of the present invention, the conductive layer 50 includes a plurality of layers each having a different material to form a transparent electrode. For example, the material of the first layer 51 includes a metal or a metal oxide, and the second layer 52 includes a non-metal material, such as Graphene.

In one embodiment of the present invention, the first layer 51 includes a sheet of resistance value greater than that of the second layer 52. In one embodiment of the present invention, the chip resistance value included in the second layer 52 is between 2.1 and 3.9 ohm / square.

In one embodiment of the present invention, the conductive layer 50 and the second semiconductor layer 22 have a contact resistance of less than 10 ^-3 ohm / cm ² .

In one embodiment of the present invention, the second semiconductor layer 22 has a p-type dopant and has a doping concentration greater than 1E + 19 cm ^-3 . The p-type dopant contains group II elements such as magnesium (Mg), zinc (Zn), cadmium (Cd), beryllium (Be), or calcium (Ca).

In one embodiment of the present invention, the first layer 51 forms a low-resistance contact, such as an ohmic contact, with the second semiconductor layer 22. In an embodiment, when the second semiconductor layer 22 is a p-type gallium nitride (GaN), the material included in the first layer 51 has a work function greater than 4.5 eV, preferably between 5 and 7 eV. Or when the second semiconductor layer 22 is p-type aluminum gallium nitride (AlGaN), the material included in the first layer 51 has a work function greater than 4.5 eV, preferably between 5 and 7 eV. The material of the first layer 51 includes a metal or a metal oxide, such as nickel oxide (NiO), cobalt oxide (Co ₃ O ₄ ), and copper oxide (Cu ₂ O).

In one embodiment of the present invention, the second semiconductor layer 22 includes Al _x Ga _1-x N, and 0.55 <x <0.65. The second semiconductor layer 22 includes ㄧ with a thickness less than 1000 Angstroms (Å) or between 1000 Angstroms. (Å) and 250 Angstroms (Å). The light-emitting element 1 includes a contact layer (not shown) located between the second semiconductor layer 22 and the first layer 51. The contact layer includes GaN, and the contact layer includes a ytterbium thickness. The light emitted from the active layer 23 penetrates and forms a low-resistance contact, such as an ohmic contact, with the first layer 51. In this embodiment, the thickness of the contact layer is less than 150 Å (Å) or between 50 Å (Å) and 150 Å (Å). When the film thickness of the GaN layer is less than 100 Å (Å), About 90% or more of the light of the light emitting element 1 is taken out. The GaN included in the contact layer has a p-type dopant and has a doping concentration greater than 1 * 10 ²⁰ cm ^-3 or between 1 * 10 ²⁰ and 2 * 10 ²⁰ cm ^-3 .

In one embodiment of the present invention, the second semiconductor layer 22 includes Al _x Ga _1-x N, and the light-emitting element 1 includes a contact layer (not shown) located between the second semiconductor layer 22 and the first layer 51. The layer contains Al _y Ga _1-y N, where x, y> 0, and x> y. The second semiconductor layer 22 includes a thickness of less than 1000 Angstroms (Å) or between 1000 Angstroms (Å) and 250 Angstroms (Å). The contact layer includes ㄧ with a thickness of less than 150 Angstroms (Å) or between 150 Angstroms (Å) and 50 Angstroms (Å). The AlGaN included in the contact layer has a p-type dopant and has a doping concentration greater than 1 * 10 ¹⁹ cm ^-3 or between 1 * 10 ¹⁹ and 8 * 10 ¹⁹ cm ^-3 .

In one embodiment of the present invention, the second semiconductor layer 22 includes Al _x Ga _1-x N, and the light-emitting element 1 includes a contact layer (not shown) located between the second semiconductor layer 22 and the first layer 51. The layer contains Al _y Ga _1-y N, where 0.55 <x <0.65, 0.05 <y <0.1.

In one embodiment of the present invention, the Al _y Ga _1-y N contained in the contact layer has a p-type dopant, such as magnesium (Mg), zinc (Zn), cadmium (Cd), beryllium (Be), or Group II elements such as calcium. And preferably, 0.01 ≦ y ≦ 0.1.

In one embodiment of the present invention, the Al _y Ga _1-y N contained in the contact layer has a p-type dopant and has a doping concentration greater than 1 * 10 ¹⁹ cm ^-3 or between 1 * 10 ¹⁹ and 8 * 10 between ¹⁹ cm ^-3 .

In one embodiment of the present invention, the conductive layer 50 and the contact layer have a contact resistance of less than 10 ^-3 ohm / cm ² .

In one embodiment of the present invention, the metal oxide contained in the first layer 51 includes a metal, and the metal has multiple oxidation states. For example, nickel atoms of nickel oxide (NiO _x ) include a first oxidation state of +2 valence. And a second oxidation state is +3 valence.

In one embodiment of the present invention, the metal oxide included in the first layer 51 includes a metal, and the metal has a single oxidation state.

In one embodiment of the present invention, the stoichiometry of the metal to oxygen of the metal oxide contained in the first layer 51 is not equal to one.

In one embodiment of the present invention, the first layer 51 includes a p-type dopant to reduce contact resistance.

In one embodiment of the present invention, the metal oxide contained in the first layer 51 has an energy gap greater than 3 eV, preferably greater than 3.2 eV, and more preferably greater than 3.4 eV. For example, a metal oxide, such as nickel oxide (NiO _x ), has an energy gap of about 3.6 to 4 eV.

In one embodiment of the present invention, the entire surface of the first layer 51 completely covers the second semiconductor layer 22. The first layer 51 includes a thickness of less than 10 nm, preferably less than 5 nm, and more preferably Less than 2 nm. The first layer 51 has a thickness variation of less than 5 nm, preferably 2 nm. In this embodiment, the case where the first layer 51 completely covers the second semiconductor layer 22 means that the upper surface of the second semiconductor layer 22 is completely covered by the first layer 51 without exposing the second semiconductor layer 22. surface.

In one embodiment of the present invention, the first layer 51 and the second layer 52 have a transmittance of more than 80% for a wavelength of 200 to 280 nm.

In one embodiment of the present invention, the second layer 52 includes a translucent material, such as graphene. Graphene is a hexagonal two-dimensional planar material composed of carbon atoms mixed with orbital domains with sp ^{2. The} carbon-carbon bond in the graphene structure is about 0.142 nm and the area of the hexagonal structure is about 0.052 nm ² . The thickness is only 0.34 nm, has a thermal conductivity higher than 5300 W / m · K, an electron mobility higher than 15000 cm ² / V · s, and a resistivity lower than 10 ^-6 Ω · cm

In one embodiment of the present invention, the second layer 52 has a p-type dopant, and the p-type dopant includes magnesium (Mg), zinc (Zn), cadmium (Cd), beryllium (Be), or calcium ( Ca) and other group II elements.

In one embodiment of the present invention, the second layer 52 includes a plurality of sub-layers, such as 2-10 layers of graphene layers.

In one embodiment of the present invention, the graphene layer is composed of a plurality of cells, and any one of the cells includes a hexagon composed of carbon atoms. The plurality of cells are connected to each other to form a two-dimensional planar material with an armchair structure. Or a two-dimensional planar material with a zigzag structure.

In one embodiment of the present invention, the second layer 52 includes one or more graphene layers, wherein each graphene layer has a thickness.

FIG. 4 is a schematic diagram of a light emitting device 2 according to an embodiment of the present invention. The light-emitting element 1 in the foregoing embodiment is mounted on the first pad 711 and the second pad 712 of the package substrate 70 by wire bonding or flip chip. The first gasket 711 and the second gasket 712 are electrically insulated by an insulating portion 700 including an insulating material. Flip-chip mounting is to set the side of the growth substrate facing the pad formation surface upward as the main light extraction surface. In order to increase the light extraction efficiency of the light-emitting device 2, a reflective structure 74 may be provided around the light-emitting element 1.

FIG. 5 is a schematic diagram of a light emitting device 3 according to an embodiment of the present invention. The light-emitting device 3 is a bulb lamp including a lamp cover 602, a reflector 604, a light-emitting module 610, a lamp holder 612, a heat sink 614, a connection portion 616, and an electrical connection element 618. The light emitting module 610 includes a supporting portion 606 and a plurality of light emitting units 608 are located on the supporting portion 606. The plurality of light emitting units 608 may be the light emitting element 1 or the light emitting device 2 in the foregoing embodiment.

The embodiments listed in the present invention are only used to illustrate the present invention and are not intended to limit the scope of the present invention. Any obvious modification or change made by anyone to the present invention will not depart from the spirit and scope of the present invention.

1‧‧‧light-emitting element

2, 3‧‧‧ light-emitting device

55‧‧‧ support layer

10‧‧‧ substrate

20‧‧‧ semiconductor stack

21‧‧‧First semiconductor layer

22‧‧‧Second semiconductor layer

23‧‧‧active layer

30‧‧‧first electrode

40‧‧‧Second electrode

50‧‧‧ conductive layer

51‧‧‧First floor

52‧‧‧Second floor

70‧‧‧ package substrate

500‧‧‧ carrier

711‧‧‧first gasket

712‧‧‧Second gasket

700‧‧‧ Insulation Department

74‧‧‧Reflective structure

602‧‧‧Shade

604‧‧‧Mirror

606‧‧‧bearing department

608‧‧‧light-emitting unit

610‧‧‧light emitting module

612‧‧‧ lamp holder

60‧‧‧ Insulation

614‧‧‧ heat sink

616‧‧‧Connection Department

618‧‧‧Electrical connection element

FIG. 1 is a method for manufacturing a light emitting device 1 disclosed in an embodiment of the present invention.

FIG. 2 is a method for manufacturing a light emitting device 1 disclosed in an embodiment of the present invention.

FIG. 3 is a structure of a light-emitting element 1 disclosed in an embodiment of the present invention.

Fig. 4 is a structure of a light-emitting device 2 disclosed in an embodiment of the present invention.

FIG. 5 is a structure of a light emitting device 3 disclosed in an embodiment of the present invention.

Claims (10)

A light-emitting element includes: a semiconductor stack having a first semiconductor layer, a second semiconductor layer, and an active layer capable of emitting UV light between the first semiconductor layer and the second semiconductor layer; a first A layer is located on the second semiconductor layer, the first layer includes a metal oxide; and a second layer is located on the first layer, the second layer includes graphene, wherein the first layer covers the entire surface Above the second semiconductor layer, the first layer includes a thickness less than 10 nm. The light-emitting element according to item 1 of the patent application scope, wherein the metal oxide has a work function greater than 4.5 eV. The light-emitting device according to item 1 of the scope of patent application, wherein the metal oxide has a work function between 5 eV and 7 eV. The light-emitting element according to item 1 of the patent application scope, wherein the metal oxide comprises nickel oxide, copper oxide, and cobalt oxide. The light-emitting element according to item 1 of the scope of patent application, wherein the metal oxide comprises a metal having a first oxidation state and a second oxidation state. The light-emitting element according to item 1 of the patent application range, wherein the UV light includes a wavelength between 100 and 290 nanometers. The light-emitting element according to item 1 of the patent application scope further includes a contact layer between the second semiconductor layer and the first layer, wherein the second semiconductor layer includes AlGaN and the contact layer includes GaN. The light-emitting element according to item 6 of the patent application scope, wherein a contact resistance between the first layer and / or the second layer and the second semiconductor layer is less than 10 ^-3 Ω · cm ² . The light-emitting element according to item 1 of the patent application scope, wherein the first layer includes a sheet having a resistance value greater than a sheet resistance value of the second layer. The light-emitting element according to item 1 of the patent application scope, wherein the second layer includes a plurality of sub-layers.