TW201816475A - Active device array substrate - Google Patents

Abstract

An active device array substrate includes a substrate, plural pixel units, a source driver, at least one gate driver, plural data line, plural gate lines, and plural gate signal transmiting lines. The substrate has an active area and a peripheral area. The pixel units are arrayed on the active area. The source driver and the gate driver are disposed on the peripheral area and respectively disposed at the same side or opposite sides of the active area. The data lines electrically connect the pixel units to the source driver. The gate lines electrically connect the pixel units. The gate signal transmiting lines extend from the active area to the peripheral area and thereto respectively electrically connect the gate lines to the gate driver. The gate driver scans the gate signal transmiting lines in a seqence corresponding to distances between the gate lines and the gate driver from closest to distant.

Description

   Active element array substrate   

The invention relates to an active element array substrate.

With the development of display technology, the requirements for display quality have gradually increased. At present, narrow bezels or even no bezels are the current development trend in the display field. In order to achieve a narrow frame design of the display device, a technology of integrating a gate driving circuit on an array substrate (Gate On Array; GOA) is generally adopted. That is, the gate driving circuit is arranged on both sides of the effective display area of the array substrate, and the gate lines of each row are scanned sequentially by bilateral cross driving to realize screen display. In this way, the central area of the array substrate is an effective display area, and the edge area of the array substrate is a non-display area, and the form of the non-display area is a mouth shape. Therefore, the non-display area is also called a frame area.

With the further improvement of the requirements for the aesthetics of the display panel, the frame size of the display panel needs to be as small as possible to achieve ultra-narrow bezels or even borderless design. Therefore, how to further reduce the width of the frame of the display device is a technical problem to be solved by those skilled in the art.

In various embodiments of the present invention, the gate driver and the source driver are provided on the same side of the active area, and a gate signal transmission line connecting the gate driver and the gate line is provided to achieve a narrow frame effect. By sequentially scanning the corresponding gate signal transmission lines from near to far, the pixel unit can be driven with minimal waveform distortion.

According to some embodiments of the present invention, the active device array substrate includes a substrate, a plurality of pixel units, a source driver, at least one gate driver, a plurality of data lines, a plurality of gate lines, and a plurality of gate signal transmissions. line. The substrate has an active area and a peripheral area. The pixel unit is disposed in the active area of the substrate. The source driver is disposed in the peripheral area. The gate driver is disposed in the peripheral region, wherein the gate driver and the source driver are disposed on the same side or opposite sides of the active region, respectively. The data lines are electrically connected to the pixel units, and the data lines are connected to the source driver. The gate lines are arranged in the active area of the substrate and are interleaved with the data lines. The gate lines are electrically connected to the pixel units. The gate signal transmission line is substantially parallel to the data line and is electrically connected to the gate lines, respectively. The gate signal transmission line is connected to the gate driver, and the gate driver depends on the distance from the gate line to the gate driver. Sequential scanning of the corresponding gate signal transmission line.

In some embodiments of the present invention, the active device array substrate further includes a plurality of connection points, which are arranged in the active area and electrically connect the gate signal transmission line to the gate line, respectively. At least part of the center of the gate line and The distance between the corresponding connection points has a negative correlation with the distance between at least part of the gate line and the gate driver to which the at least part of the gate line is connected.

In some embodiments of the present invention, the gate line includes a remote gate line, the active device array substrate includes a remote connection point, and the remote connection point connects the remote gate line to the gate driver, wherein the remote connection point is adjacent to the remote gate In the center of the line, the gate line extends in one direction, and the distance between the far connection point and the center of the far gate line is less than the pixel length of the three pixel units in the direction.

In some embodiments of the present invention, the number of gate drivers is plural. The gate driver includes a first gate driver and a second gate driver. The gate signal transmission line includes a plurality of first gate signals. The transmission line and a plurality of second gate signal transmission lines, the first gate signal transmission line is connected to the first gate driver, and the second gate signal transmission line is connected to the second gate driver, respectively.

In some embodiments of the present invention, the active device array substrate further includes a plurality of connection points, which are disposed in the active area and are respectively connected to the gate signal transmission line and the gate line, wherein the connection points are arranged in a V shape.

In some embodiments of the present invention, the active device array substrate further includes an auxiliary gate driver, a plurality of auxiliary gate signal transmission lines, and a plurality of auxiliary connection points. The auxiliary gate driver is disposed in the peripheral area. The auxiliary gate signal transmission line is substantially parallel to the data line, wherein the auxiliary gate signal transmission line is connected to the auxiliary gate driver. The auxiliary connection point is arranged in the active area and connects the auxiliary gate signal transmission line and the gate line, respectively. The gate driver and the auxiliary gate driver are located on opposite sides of the active area, respectively.

In some embodiments of the present invention, the gate line includes an auxiliary remote gate line, the auxiliary connection point includes an auxiliary remote connection point, and the auxiliary connection point connects the auxiliary remote gate line to the auxiliary gate driver. Extending in one direction, the distance between the auxiliary remote connection point and the center of the auxiliary remote gate line is less than the pixel length of the three pixel units in that direction.

In some embodiments of the present invention, the auxiliary connection points are arranged in a V shape.

In some embodiments of the present invention, the auxiliary data line, the auxiliary gate signal transmission line and the gate signal transmission line are evenly arranged.

In some embodiments of the present invention, each data line is electrically connected to at least two rows of pixel units.

100‧‧‧ Active Element Array Substrate

110‧‧‧ substrate

120‧‧‧ Pixel Unit

120R, 120G, 120B ‧‧‧ pixel units

120 ’, 120”, 120 ’” ‧‧‧ end pixel units

1201 ~ 1209‧‧‧Pixel Unit

130‧‧‧Source Driver

140‧‧‧Gate driver

142‧‧‧First gate driver

144‧‧‧Second gate driver

150‧‧‧ Data Line

150a ~ 150c‧‧‧Data line

180‧‧‧ connection point

180a‧‧‧Far connection point

182‧‧‧First connection point

184, 184d‧‧‧Second connection point

190‧‧‧Auxiliary gate signal transmission line

200‧‧‧ auxiliary connection point

200a‧‧‧ auxiliary remote connection point

210‧‧‧Auxiliary gate driver

TT‧‧‧Thin film transistor

PE‧‧‧Pixel electrode

Cst‧‧‧Storage capacitor

Clc‧‧‧LCD Capacitor

AR‧‧‧Active Zone

PR‧‧‧Peripheral area

160‧‧‧Gate line

160a ~ 160c‧‧‧Gate line

162a ~ 162d‧‧‧First gate line

164a ~ 164d‧‧‧Second gate line

170‧‧‧Gate signal transmission line

172a ~ 172d‧‧‧The first gate signal transmission line

174a ~ 174d‧‧‧Second gate signal transmission line

DR‧‧‧ direction

D1 ~ D5‧‧‧Distance

L1 ~ L3‧‧‧Distance

S1‧‧‧Space

PL‧‧‧ Pixel Length

SR‧‧‧Scanning direction

CL‧‧‧Control signal line

FIG. 1 is a schematic top view of an active device array substrate according to a first embodiment of the present invention.

FIG. 2 is a schematic top view of an active element array substrate according to a second embodiment of the present invention.

FIG. 3 is a schematic top view of an active element array substrate according to a third embodiment of the present invention.

FIG. 4 is a schematic top view of an active element array substrate according to a fourth embodiment of the present invention.

FIG. 5 is a schematic top view of an active element array substrate according to a fifth embodiment of the present invention.

FIG. 6 is a schematic top view of an active element array substrate according to a sixth embodiment of the present invention.

FIG. 7 is a schematic top view of an active element array substrate according to a seventh embodiment of the present invention.

FIG. 8 is a schematic top view of an active element array substrate according to an eighth embodiment of the present invention.

FIG. 9 is a schematic diagram of a top-view operation of an active element array substrate according to some embodiments of the present invention.

Several embodiments of the present invention will be disclosed in the following drawings. For the sake of clear description, many practical details will be described in the following description. It should be understood, however, that these practical details should not be used to limit the invention. That is, in some embodiments of the present invention, these practical details are unnecessary. In addition, in order to simplify the drawings, some conventional structures and elements will be shown in the drawings in a simple and schematic manner.

FIG. 1 is a schematic top view of an active device array substrate 100 according to a first embodiment of the present invention. The active device array substrate 100 includes a substrate 110, a plurality of pixel units 120, a source driver 130, at least one gate driver 140, a plurality of data lines 150, a plurality of gate lines 160, and a plurality of gate signal transmission lines 170. The substrate 110 has an active region AR and a peripheral region PR. The peripheral region PR is located around the active region AR. For example, the peripheral region PR may surround or surround the periphery of the active region AR, or be located on one side or both sides of the active region AR. The side or three sides, that is, all or part of the area outside the active area AR of the substrate 110 can be regarded as the peripheral area PR. In this embodiment, the pixel units 120 are arrayed in the active area AR of the substrate 110. Although the pixel unit 120 is shown here as a rectangle, the present invention is not limited to this. The pixel unit 120 may also have different shapes of arrangements, such as honeycomb or rhombus patterns, due to different needs.

In the embodiment shown in FIG. 1, the source driver 130 and the gate driver 140 are disposed in the peripheral region PR. The gate driver 140 and the source driver 130 are disposed on the same side or opposite sides of the active region AR, respectively. The data line 150 and the gate line 160 are electrically connected to the pixel units 120 respectively. The data line 150 extends from the active area AR of the substrate 110 to the peripheral area PR of the substrate 110 to be connected to the source driver 130. The gate line 160 is disposed in the active area AR of the substrate 110 and is staggered with the data line 150. In this embodiment, the gate signal transmission line 170 is substantially parallel to the data line 150 and is electrically connected to the gate line 160, respectively. The gate signal transmission line 170 extends from the active area AR of the substrate 110 to the peripheral area PR of the substrate 110. To be connected to the gate driver 140. The gate driver 140 sequentially scans the corresponding gate signal transmission line 170 according to the distance from the gate line 160 to the gate driver 140 from near to far. Here, the scanning direction SR of the gate driver 140 is indicated by an arrow.

In this way, by scanning the corresponding gate signal transmission lines 170 in order from near to far, the pixel unit 120 can be driven with minimal waveform distortion. The gate scanning transmission method of this embodiment is simple (single direction), which makes the circuit layout relatively simple and easy. In addition, in some embodiments, the active device array substrate 100 further includes a control signal line CL, and the source driver 130 provides a control signal to the gate driver 140 through the control signal line CL. In this embodiment, the control signal line CL may The peripheral areas PR, which are set on both sides of the active area AR, can be driven bilaterally with sufficient thrust.

Herein, the gate signal transmission line 170 is substantially parallel to the data line 150, where "substantially parallel" means that the overall direction of the gate signal transmission line 170 is substantially the same as that of the data line 150 as a whole, and is not used to limit the gate signal transmission The line 170 and the data line 150 point in the same direction. In various embodiments of the present invention, the extending direction of the data line 150 may change with the arrangement of the pixel units 120, and the gate signal transmission line 170 may also change accordingly. For example, when the pixel unit 120 is in a honeycomb or diamond pattern, the data line 150 and the gate signal transmission line 170 may be a zigzag type or a lightning type, in which the data lines 150 and the gate signal transmission line 170 are partially shaped. Can be the same or different.

In some embodiments of the present invention, each gate line 160 is electrically connected to a plurality of pixel units 120 in each column, and each data line 150 is electrically connected to at least two rows of pixel units 120. In other words, the pixel units 120 in multiple rows share a data line 150 and are controlled by different gate lines 160. In this way, there can be enough space S1 between the adjacent data lines 150 to set the gate signal transmission line 170.

In some embodiments, a data line 150 can be set to correspond to one of the three rows of pixel units 120, and a gate signal transmission line 170 can be set to correspond to two of the rows. For example, as shown in Figure 1, similar three rows of pixel units 120R, 120G, and 120B share a data line 150. The data line 150 corresponds to the position of the pixel unit 120R, and the two gate signal transmission lines 170 correspond to each other. The positions of the pixel units 120R and 120B. With this, the gate driver 140 can be arranged on the upper and lower sides of the active area AR (on the same side or opposite sides to the source driver 130) without changing the number of layers of the process, so as to achieve the effect of a narrow frame. In this embodiment, the three pixel units 120 of the common data line may be adjacent, and no other pixel unit 120 is provided therein, but the scope of the present invention should not be limited by this. In other embodiments, through appropriate circuit structure design, the three pixel units 120 of the common data line may be non-adjacent, and other pixel units 120 may be provided therein. In some embodiments, the number of the gate lines 160 may be larger than the number of the data lines 150 due to the factor of the common data line 150. The operation method of the common data line 150 will be described in the last FIG. 9, and it is not mentioned here.

In some embodiments, the data line 150 and the gate signal transmission line 170 are patterned from the same conductive layer. Specifically, the data line 150 and the gate signal transmission line 170 are formed of the same conductive material, and both are formed or disposed on the same material or on the same horizontal plane, that is, they can be produced on the same layer using the same mask and process. In contrast, the gate line 160 and the data line 150 are not disposed on the same layer, and the gate line 160 and the data line 150 may be formed of the same or different materials. In some embodiments, the layer where the data line 150 and the gate signal transmission line 170 are located is separated from the gate line 160 by a dielectric layer (not shown), and the dielectric layer includes a plurality of contact holes. (Not shown), thereby forming a plurality of connection points 180 of the active device array substrate 100. In detail, when the gate signal transmission line 170 is formed, the material is filled in the contact hole of the dielectric layer to form a connection point 180, so that the gate signal transmission line 170 can contact the gate line 160 through the contact hole. In this embodiment, the connection points 180 are disposed in the active area AR, and are electrically connected to the gate signal transmission line 170 to the gate line 160, respectively.

It should be understood that a plurality of insulating layers may be provided on the substrate 110 to assist each conductive element to form an operable circuit structure. An insulation layer (not shown) may be provided between the data line 150 and the pixel unit 120, and the insulation layer may have an opening for the electrical connection between the data line 150 and the pixel unit 120. Similarly, a plurality of insulation layers (not shown) may be provided between the gate line 160 and the pixel unit 120, and these insulation layers may also have openings for the electrical properties of the gate lines 160 and the pixel unit 120. connection. So far, the gate signal transmission line 170 and the pixel unit 120 are not directly electrically connected, and the gate signal transmission line 170 is electrically connected to the pixel unit 120 at least through the gate line 160. There are many possible implementations of the insulation layer, which are not described here one by one.

In some embodiments, for example, the material of the substrate 110 may be glass, quartz, ceramic, metal, alloy, or polyimide (PI), polyethylene terephthalate (PET), Organic materials such as polyethylene naphthalate (PEN), polyamide (PA), or other suitable materials or a combination of at least two of the above materials.

In some embodiments, the pixel unit 120 may include other devices such as an active device and a pixel electrode. In some embodiments, the active device array substrate 100 is a substrate that integrates a color filter array and a thin film transistor array (COA). Each pixel unit 120R, 120G, and 120B may include a color filter of a corresponding color. Light units, such as a red filter unit, a green filter unit, and a blue filter unit.

FIG. 2 is a schematic top view of an active device array substrate 100 according to a second embodiment of the present invention. This embodiment is similar to the embodiment in FIG. 1 except that, in this embodiment, the gate driver 140 includes a first gate driver 142 and a second gate driver 144. The gate signal transmission line 170 includes a plurality of first gate signal transmission lines 172a to 172d and a plurality of second gate signal transmission lines 174a to 174d. The first gate signal transmission lines 172a to 172d are connected to the first gate driver 142. The second gate signal transmission lines 174a to 174d are connected to the second gate driver 144.

In detail, in this embodiment, the connection point 180 includes a plurality of first connection points 182 and a plurality of second connection points 184, and the gate line 160 includes first gate lines 162a to 162d and second gate lines 164a. ~ 164d. The plurality of first connection points 182 electrically connect the first gate signal transmission lines 172a to 172d to the first gate lines 162a to 162d, respectively, and the plurality of second connection points 184 respectively connect the second gate signal transmission lines 174a. Each of ~ 174d is electrically connected to the second gate lines 164a ~ 164d.

In some embodiments of the present invention, the first gate driver 142 and the second gate driver 144 alternately scan the first gate signal transmission lines 172a to 172d and the second gate signal transmission lines 174a to 174d. So far, the first gate lines 162a to 162d and the second gate lines 164a to 164d are designed to be alternately arranged, so that the first gate driver 142 and the second gate driver 144z can be aligned with the first gate lines 162a to 162d and the first The distance between the two gate lines 164a ~ 164d to the first gate driver 142 and the second gate driver 144, and the corresponding first gate signal transmission lines 172a ~ 172d and the second gate are sequentially scanned from a short distance to a long distance. Signal transmission lines 174a ~ 174d. Specifically, the first gate line 162a, the second gate line 164a, the first gate line 162b, the second gate line 164b, the first gate line 162c, the second gate line 164c, and the first gate The line 162d and the second gate line 164d sequentially receive the gate signals. The scanning directions SR of the first gate driver 142 and the second gate driver 144 are the same, and both are from left to right.

Herein, the “alternate scanning” of the first gate driver 142 and the second gate driver 144 means that the first gate driver 142 and the second gate driver 144 alternately provide respective signals. In other words, the first gate driver 142 and the second gate driver 144 provide respective signals at different points in time. For example, the timing is divided into the first to eighth timings. At the first timing, the first gate driver 142 provides a signal to the first gate line 162a. At the second timing, the second gate driver 144 provides A signal is provided to the second gate line 164a; at the third timing, the first gate driver 142 provides a signal to the first gate line 162b; at a fourth timing, the second gate driver 144 provides a signal to the second gate line 164b. ; At the fifth timing, the first gate driver 142 provides a signal to the first gate line 162c; at the sixth timing, the second gate driver 144 provides a signal to the second gate line 164c; at the seventh timing, the first The gate driver 142 provides a signal to the first gate line 162d; at the eighth timing, the second gate driver 144 provides a signal to the second gate line 164d.

The other details of this embodiment are substantially the same as those of the embodiment in FIG. 1 and will not be repeated here.

FIG. 3 is a schematic top view of an active device array substrate 100 according to a third embodiment of the present invention. This embodiment is similar to the embodiment of FIG. 2 except that in this embodiment, the distance between the center of at least part of the gate line 160 and the corresponding connection point 180 and the at least part of the gate line 160 and The distance between the gate drivers 140 connected to the at least part of the gate lines 160 has a negative correlation. Specifically, the distance between the center of each first gate line 162a-162d and the corresponding first connection point 182, and each of the first gate lines 162a-162d and the first gate driver The distance between 142 is negatively correlated. Similarly, the distance between the center of each second gate line 164a-164d and the corresponding second connection point 184 and the second gate line 164a-164d and the second gate driver 144 The distance between them is negatively correlated.

Herein, the “center of the gate line” refers to the center point of each gate line 160 in the direction DR, wherein the distance from the center point of each gate line 160 to the two ends of the gate line 160 is the same. In addition, in this article, for convenience of explanation, the gate driver 140 is represented by a box, and the box represents the distribution range of the gate driver 140 and its related circuit components, and is not limited to the integrated circuit in the gate driver 140. Device. Ideally, the bottom edge of the gate driver 140 is parallel to the direction DR, so that "the distance between the gate line 160 and the gate driver 140 connected to the gate line 160" is the same reference line (i.e. the gate The bottom edge of the driver 140). In some embodiments, the frame may be close to the active area AR, so that the “distance between the gate line 160 and the gate driver 140 connected to the gate line 160” is the distance between the active area AR and the peripheral area PR. Think about the boundaries.

For example, in an embodiment, there is a distance D1 between the center of the first gate line 162b and the corresponding first connection point 182, and a distance L1 between the first gate line 162b and the first gate driver 142. There is a distance D2 between the center of the first gate line 162c and the corresponding first connection point 182, and there is a distance L2 between the first gate line 162c and the first gate driver 142. Here, the distance D2 is smaller than the distance D1, and the distance L2 is larger than the distance L1. The two have a negative correlation. In other words, when the distance from the center of one of the gate lines to the connection point is greater than the distance from the center of the other gate line to the connection point, the distance from one of the gate lines to the gate driver It is smaller than the distance from the other gate line to the gate driver. Conversely, when the distance from the center of one gate line to the connection point is smaller than the distance from the center of the other gate line to the connection point, the distance from one gate line to the gate driver Is greater than the distance from the other gate line to the gate driver.

In this way, the length of the transmission path of the signal from the gate driver 140 to the end pixel unit 120 'of the first gate line 162b is approximately the sum of the distance D1, the distance L1, and the half of the length of the first gate line 162b. The length of the transmission path of the signal from the pole driver 140 to the end pixel unit 120 "of the first gate line 162c is approximately the sum of the distance D2, the distance L2, and the half of the length of the first gate line 162c. The length of the line 162b and the first gate line 162c are approximately the same. Through the design of the negative correlation described above, the sum of the distance D1 and the distance L1 will not be too different from the sum of the distance D2 and the distance L2. The signals of the driver 140 are transmitted to the end pixel unit 120 'and the end pixel unit 120 ", respectively, and the lengths of the transmission paths will not be too large, so that the impedances of the two transmission paths can be averaged, thereby reducing the problem of waveform distortion.

In some embodiments, the distance between the center of the first gate line 162a-162d and each corresponding first connection point 182 and the first gate line 162a-162d and the first gate may be designed. The sum of the distances between the pole drivers 142 is substantially the same (for example, the sum of the distance D1 and the distance L1 is equal to the sum of the distance D2 and the distance L2), so that the signal of the first gate driver 142 is transmitted to each first The lengths of the transmission paths of the end pixel units 120 on the gate lines 162a to 162d are substantially the same. In this way, the problem of waveform distortion can be reduced more effectively.

In another embodiment, there is a distance D3 between the center of the second gate line 164b and the corresponding second connection point 184, and there is a distance L3 between the second gate line 164b and the second gate driver 144. Here, the distance D3 is greater than the distance D2, and the distance L3 is less than the distance L2. The two have a negative correlation. However, it should be understood that, because the circuit configuration connecting the first gate driver 142 and the first gate lines 162a to 162d is not the same as the circuit configuration of the second gate driver 144 and the second gate lines 164a to 164d, There are essentially path differences. For example, here, compared to the second gate lines 164a to 164d, the first gate lines 162a to 162d are generally closer to the gate driver 140 and the first connection point 182 is closer to the center of each gate line 160. . Therefore, the first gate lines 162a to 162d and the first gate lines 162a to 162d do not necessarily adhere to the above-mentioned negative correlation relationship setting. For example, the distance D3 is greater than the distance D1, and the distance L3 is greater than the distance L1. relationship.

In this embodiment, the first connection point 182 and the second connection point 184 are generally arranged in a V-shape, wherein the V-shaped tips face away from the first gate driver 142 and the second gate driver 144. Specifically, the first connection point 182 constitutes one oblique side of the V-shape (such as the left oblique side in FIG. 3), and the second connection point 184 constitutes the other oblique side of the V-shaped (such as the right oblique side in FIG. 3). .

In this embodiment, the gate line 160 includes a far gate line (such as the second gate line 164d in FIG. 3) and a remote connection point (such as the second connection point 184d in FIG. 3). Is the gate line 160 farthest from the gate driver 140, and the far connection point is the far gate line connected to the gate driver, wherein the far connection point is adjacent to the center of the far gate line. The gate line 160 extends in the direction DR. The distance D4 between the far connection point and the center of the far gate line is less than the pixel length PL of the three pixel units 120 in the direction DR, that is, D4 is less than 3PL. In other words, by design, the distance between the center of the gate line 160 farthest from the gate driver 140 and its corresponding connection point 180 is smaller than the pixel length PL of the three pixel units 120 in the direction DR. In this way, the transmission path of the end pixel unit 120 '' 'connected to the gate line 160 (here, the second gate line 164d) farthest from the gate driver 140 is relatively even, so that the signal transmission path faces Impedance is more even to reduce waveform distortion.

Under the above settings, the first gate driver 142 and the second gate driver 144 scan the first gate signal transmission lines 172a to 172d and the second gate signal transmission lines 174a to 174d alternately from outside to inside, respectively, and further The first gate lines 162a-162d and the second gate lines 164a-164d are scanned alternately from near to far scanning. Here, "from near to far" refers to the distance from the first gate line 162a to 162d and the second gate line 164a to 164d to the first gate driver 142 and the second gate driver 144. "From "Outward" refers to the direction from the peripheral areas PR on both sides of the active area AR to the active area AR. Specifically, the first gate line 162a, the second gate line 164a, the first gate line 162b, the second gate line 164b, the first gate line 162c, the second gate line 164c, and the first gate The line 162d and the second gate line 164d sequentially receive the gate signals. In addition, the scanning directions SR of the first gate driver 142 and the second gate driver 144 are opposite. The other details of this embodiment are substantially as described in the foregoing embodiment, and are not repeated here.

FIG. 4 is a schematic top view of an active device array substrate 100 according to a fourth embodiment of the present invention. This embodiment is similar to the embodiment in FIG. 3, except that in this embodiment, the first connection point 182 and the second connection point 184 are arranged in a substantially V-shape, and the V-shaped tip faces the first gate driver 142 and Second gate driver 144.

In this way, the first gate driver 142 and the second gate driver 144 scan the first gate signal transmission lines 172a to 172d and the second gate signal transmission lines 174a to 174d alternately from inside to outside and from near to far, respectively. . In addition, the scanning directions SR of the first gate driver 142 and the second gate driver 144 are opposite. The other details of this embodiment are substantially as described in the foregoing embodiment, and are not repeated here.

FIG. 5 is a schematic top view of an active device array substrate 100 according to a fifth embodiment of the present invention. This embodiment is similar to the embodiment of FIG. 3, except that in this embodiment, the gate driver 140 and the source driver 130 are respectively disposed on the same side of the active area AR.

Similarly, the first connection point 182 and the second connection point 184 are generally arranged in a V-shape, wherein the V-shaped tips point toward the side far from the first gate driver 142 and the second gate driver 144. In this way, the first gate driver 142 and the second gate driver 144 scan the first gate signal transmission lines 172a to 172d and the second gate signal transmission lines 174a to 172, respectively, from outside to inside, and from near to far. 174d. The scanning direction SR of the first gate driver 142 and the second gate driver 144 are different.

The other details of this embodiment are generally as described above, and are not repeated here.

FIG. 6 is a schematic top view of an active device array substrate 100 according to a sixth embodiment of the present invention. This embodiment is similar to the embodiment in FIG. 3, except that in this embodiment, the first gate signal transmission lines 172a to 172c, the second gate signal transmission lines 174a to 174c, and the data line 150 are not evenly arranged, and The first gate signal transmission lines 172 a to 172 c and the second gate signal transmission lines 174 a to 174 c are disposed adjacent to the center of the gate line 160.

In this article, "non-averaged setting" means that the distribution positions of the components are uneven. For example, the gate signal transmission line 170 (including the first gate signal transmission lines 172a to 172c and the second gate signal transmission line 174a ~ 174c) and the data line 150, the pitches of at least two adjacent components are different. In contrast, in this article, “average setting” means that the distribution positions of the components are uniform. For example, in the embodiments of FIGS. 1 to 5, the gate signal transmission line 170 (including the first gate signal In the transmission lines 172a to 172d, the second gate signal transmission lines 174a to 174d), and the data line 150, the pitches of any two adjacent elements are the same.

As mentioned above, in some embodiments of the present invention, the pixel units 120 in multiple rows share a data line 150, so that there is sufficient space S1 between adjacent data lines 150 for setting the gate signal transmission. Line 170. Here, the gate signal transmission line 170 is selectively disposed in a part of the space S1 to reduce the distance between the center of each gate line 160 and each corresponding connection point 180. In this way, the impedance faced by the signal from the gate driver 140 can be reduced as much as possible to reduce the problem of waveform distortion. The other details of this embodiment are generally as described above, and are not repeated here.

FIG. 7 is a schematic top view of an active device array substrate 100 according to a seventh embodiment of the present invention. This embodiment is similar to the embodiment of FIG. 3, except that in this embodiment, the first gate signal transmission lines 172a to 172c, the second gate signal transmission lines 174a to 174c, and the data line 150 are not evenly arranged. As mentioned above, in some embodiments of the present invention, the pixel units 120 in multiple rows share a data line 150, so that there is sufficient space S1 between adjacent data lines 150 for setting the gate signal transmission. Line 170. In some embodiments, a data line 150 corresponding to one of the three rows of pixel units 120 may be provided, and a gate signal transmission line 170 (the first gate signal transmission lines 172a to 172c and the first The two gate signal transmission lines 174a to 174c) correspond to the positions of one of the lines. For example, as shown in FIG. 7, the pixel units 120R, 120G, and 120B of three similar rows share a data line 150. The data line 150 corresponds to the position of the pixel unit 120R, and the first gate signal transmission line 172a ~ 172c and the second gate signal transmission lines 174a to 174c correspond to the position of the pixel unit 120G. In this way, the gate signal transmission line 170 or the data line 150 is not set on the pixel unit 120B, rather than an average setting. In practice, this should not limit the scope of the invention. In other embodiments, a gate signal transmission line 170 or a data line 150 may be provided on a part of the pixel unit 120B, and a gate signal transmission line 170 or a data line 150 may not be provided on the other pixel unit 120B. The pixel units 120R and 120G can also be adjusted accordingly.

In this embodiment, the three pixel units 120 of the common data line may be adjacent, and no other pixel unit 120 is provided therein, but the scope of the present invention should not be limited by this. In other embodiments, through appropriate circuit structure design, the three pixel units 120 of the common data line may be non-adjacent, and other pixel units 120 may be provided therein.

The other details of this embodiment are generally as described above, and are not repeated here.

FIG. 8 is a schematic top view of an active device array substrate 100 according to an eighth embodiment of the present invention. This embodiment is similar to the embodiment of FIG. 7 except that in this embodiment, the active device array substrate 100 further includes a plurality of auxiliary gate signal transmission lines 190 and a plurality of auxiliary connection points 200. The auxiliary gate signal transmission line 190 is substantially parallel to the data line 150. The auxiliary gate signal transmission line 190 extends from the active area AR to the peripheral area PR to be connected to the auxiliary gate driver 210. The auxiliary connection point 200 is disposed in the active area AR, and connects the auxiliary gate signal transmission line 190 and the gate line 160, respectively. The gate driver 140 and the auxiliary gate driver 210 are respectively disposed on opposite sides of the active area AR.

As mentioned above, in some embodiments of the present invention, the pixel units 120 of multiple rows share a data line 150, so that there is sufficient space S1 between adjacent data lines 150 for setting gate signal transmission. Line 170 and auxiliary gate signal transmission line 190. Here, the pixel units 120 of the three similar rows share a data line 150. In some embodiments, in a similar three-line pixel unit 120, a data line 150 can be set to correspond to one of the lines, a gate signal transmission line 170 can be set to correspond to one of the lines, and an auxiliary gate signal transmission line can be set. 190 corresponds to the position of one of the lines. For example, the data line 150 corresponds to the position of the pixel unit 120R, the gate signal transmission line 170 corresponds to the position of the pixel unit 120G, and the auxiliary gate signal transmission line 190 corresponds to the position of the pixel unit 120B.

In some embodiments of the present invention, the gate driver 140 sequentially scans from the outside to the inside, so that the first gate line 162a, the second gate line 164a, the first gate line 162b, and the second gate line 164b, the first gate line 162c, the second gate line 164c, the first gate line 162d, and the second gate line 164d sequentially receive gate signals.

In some embodiments of the present invention, the auxiliary gate driver 210 sequentially scans from the inside to the outside, so that the first gate line 162a, the second gate line 164a, the first gate line 162b, and the second gate line 164b, the first gate line 162c, the second gate line 164c, the first gate line 162d, and the second gate line 164d sequentially receive the auxiliary gate signals. In some embodiments, the scanning directions of the auxiliary gate driver 210 and the gate driver 140 are opposite. The auxiliary gate driver 210 and the gate driver 140 can operate simultaneously. In this way, when the transmission path is too far, and it is difficult for each gate line 160 to receive an appropriate gate signal from the gate driver 140, the auxiliary gate driver 210 can provide the appropriate gate line 160 through the auxiliary gate signal 190. Signal.

Here, "from outside to inside" refers to the direction from the peripheral areas PR on both sides of the active area AR to the active area AR. "From inside to outside" refers to the direction from the active area AR to the peripheral areas PR on both sides of the active area AR.

In some embodiments of the present invention, the gate line 160 includes an auxiliary remote gate line (such as the first gate line 162a in FIG. 8). The auxiliary remote gate line is the farthest from the auxiliary gate driver 210, The connection point 200 includes an auxiliary remote connection point 200a, which connects the auxiliary remote gate line to the farthest auxiliary gate driver 210, wherein the auxiliary remote connection point 200a is adjacent to the center of the auxiliary remote gate line. Here, the distance D5 between the auxiliary remote connection point 200a and the center of the auxiliary remote gate line is less than the pixel length PL of the three pixel units 120, that is, D5 is less than 3PL. In other words, by design, the distance between the center of the gate line 160 farthest from the auxiliary gate driver 210 and its corresponding auxiliary connection point 200 is smaller than the pixel length PL of the three pixel units 120. In this way, the transmission path of the end pixel unit 120 ′ ″ connected to the gate line 160 (here, the first gate line 162 a) farthest from the auxiliary gate driver 210 can be reduced, so that each pixel unit 120 The impedance of the signal transmission path is relatively average to reduce the problem of waveform distortion.

Similarly, here, the gate line 160 includes a far gate line (such as the second gate line 164c in FIG. 8), and the far gate line is the gate line 160 farthest from the gate driver 140, and is far connected The point 180a connects the far gate line to the gate driver, wherein the far connection point 180a is adjacent to the center of the far gate line. The distance between the far connection point 180a and the center of the far gate line is less than the pixels of the three pixel units 120 Length PL.

Here, the connection point 180 and the auxiliary connection point 200 are represented by different oblique line patterns, but they may be completely identical in structure. The connection point 180 and the auxiliary connection point 200 are arranged in a V shape, wherein the V-shaped tip of the connection point 180 faces the auxiliary gate driver 210 and the V-shaped tip of the auxiliary connection point 200 faces the gate driver 140.

In this embodiment, the gate signal transmission line 170, the auxiliary gate signal transmission line 190, and the data line 150 are evenly arranged. In other words, in the gate signal transmission line 170, the auxiliary gate signal transmission line 190, and the data line 150, the distance between any two adjacent components is the same. Of course, the scope of the present invention should not be limited by this. In other embodiments, the gate signal transmission line 170, the auxiliary gate signal transmission line 190, and the data line 150 may also be arranged in an uneven manner.

The other details of this embodiment are generally as described above, and are not repeated here.

FIG. 9 is a schematic diagram of a top-view operation of an active device array substrate 100 according to some embodiments of the present invention. The gate line 160 includes the gate lines 160a to 160c, the data line 150 includes the data lines 150a to 150c, and the pixel units 1201 to 1209 respectively include a thin film transistor TT and a pixel electrode PE. For example, the thin film transistor TT is, for example, Low temperature poly-silicon (LTPS) thin film transistor, in which the pixel electrode PE is connected to the drain of the thin film transistor TT. The active device array substrate 100 can be matched with a liquid crystal display medium. As shown in the figure, the pixel electrode PE is connected to a liquid crystal capacitor Clc. In some embodiments, the pixel electrode PE may be connected to the storage capacitor Cst to maintain a stable potential.

Here, the pixel units 1201 to 1209 are respectively set in groups of three. For example, as shown in FIG. 9, the source of the thin film transistor TT of the pixel unit 1207 is connected to the data line 150a, and the source of the thin film transistor TT of the pixel unit 1205 is connected to the thin film transistor TT of the pixel unit 1207. The drain of the thin film transistor TT of the pixel unit 1203 is connected to the drain of the thin film transistor TT of the pixel unit 1205. The pixel units 1203, 1205, and 1207 are electrically connected to the gate lines 160a to 160c, respectively.

Here, as described above, the gate lines 160a to 160c are electrically connected to the gate signal transmission lines 170a to 170c through the connection point 180, respectively, and are electrically connected to the gate driver.

In this way, by electrically connecting the gate signal transmission lines 170a to 170c of the gate lines 160a to 160c, the electrical signals from the data line 150a can be charged to the pixel electrodes of the pixel units 1203, 1205, and 1207, respectively. For example, if the gate lines 160a ~ 160c are turned on, the electrical signal from the data line 150c will be charged to the pixel unit 1203; if the gate lines 160b ~ 160c are turned on and the gate line 160a is turned off, the data from the data line 150a The electric signal will be charged to the pixel unit 1205; if the gate line 160c is turned on and the gate lines 160a to 160b are closed, the electric signal from the data line 150c will be charged to the pixel unit 1207. So far, the pixel units 1203, 1205, and 1207 can be operated with the common data line 150c. The control of other pixel units can also be operated in accordance with this, which will not be repeated here.

As described above, the active device array substrate 100 may be a substrate that integrates a color filter array and a thin film transistor array (COA), and each pixel unit 120 may include a color filter unit of a corresponding color. Here, the pixel units 1203, 1205, and 1207 may include color filter units of different colors, such as a green filter unit, a red filter unit, and a blue filter unit, which are represented by different dot patterns here. Other pixel units are also set accordingly, and will not be repeated here.

In various embodiments of the present invention, the gate driver and the source driver are arranged on the same side of the active area, and a gate signal transmission line connecting the gate driver and the gate line is provided to achieve a narrow frame effect. By sequentially scanning the corresponding gate signal transmission lines from near to far, the pixel unit can be driven with minimal waveform distortion.

Although the present invention has been disclosed in various embodiments as above, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

Claims (10)

    An active element array substrate includes: a substrate having an active region and a peripheral region; a plurality of pixel units disposed in the active region of the substrate; a source driver disposed in the peripheral region; and at least one gate driver , Located in the peripheral area, wherein the gate driver and the source driver are respectively disposed on the same side or opposite sides of the active area; a plurality of data lines are electrically connected to the pixel units, and the data Lines are connected to the source driver; a plurality of gate lines are disposed in the active area of the substrate and are interleaved with the data lines, wherein the gate lines are respectively electrically connected to the pixel units; and The gate signal transmission lines are substantially parallel to the data lines and are electrically connected to the gate lines, respectively, wherein the gate signal transmission lines are connected to the at least one gate driver, and the at least one gate driver is in accordance with the The distances from the gate lines to the gate driver sequentially scan the corresponding gate signal transmission lines from near to far.         The active element array substrate according to claim 1, further comprising: a plurality of connection points disposed in the active area, and electrically connecting the gate signal transmission lines to the gate lines, respectively, at least part of which The distance between the centers of the gate lines and the corresponding connection points is the distance between the at least part of the gate lines and the gate driver to which the at least part of the gate lines are connected. Negative correlation.         The active device array substrate according to claim 1, wherein the gate lines include a remote gate line, the active device array substrate includes a remote connection point, and the remote connection point connects the remote gate line to the gate Pole driver, wherein the gate lines extend in a direction, and the distance between the far connection point and the center of the far gate line is less than the pixel length of the three pixel units in the direction.         The active device array substrate according to claim 1, wherein the number of the at least one gate driver is plural, and the gate drivers include a first gate driver and a second gate driver, and the gate signals The transmission line includes a plurality of first gate signal transmission lines and a plurality of second gate signal transmission lines. The first gate signal transmission lines are respectively connected to the first gate driver and the second gate signal transmission lines. Connect the second gate drivers respectively.         The active device array substrate according to claim 4, further comprising: a plurality of connection points disposed in the active area, and respectively connecting the gate signal transmission lines and the gate lines, wherein the connection points are represented by V Type arrangement.         The active element array substrate according to claim 1, further comprising: an auxiliary gate driver provided in the peripheral area; a plurality of auxiliary gate signal transmission lines substantially parallel to the data lines, among which the auxiliary gates The signal transmission line is connected to the auxiliary gate driver; and a plurality of auxiliary connection points are disposed in the active area and connect the auxiliary gate signal transmission lines and the gate lines, respectively, wherein the gate driver and the auxiliary The gate drivers are located on opposite sides of the active area.         The active device array substrate according to claim 6, wherein the gate lines include an auxiliary remote gate line, the auxiliary connection points include an auxiliary remote connection point, and the auxiliary remote connection point is connected to the auxiliary remote gate line To the auxiliary gate driver, wherein the gate lines extend in a direction, and the distance between the auxiliary remote connection point and the center of the auxiliary remote gate line is less than the pixel length of the three pixel units in the direction .         The active device array substrate according to claim 6, wherein the auxiliary connection points are arranged in a V shape.         The active device array substrate according to claim 6, wherein the data lines, the auxiliary gate signal transmission lines, and the gate signal transmission lines are arranged evenly.         The active device array substrate according to claim 1, wherein each of the data lines is electrically connected to the pixel units of at least two rows.