TW201814846A - Semiconductor package manufacturing method - Google Patents

Abstract

An object of the present invention is to provide a method for manufacturing a semiconductor package in which the thicknesses of the shielding layers on the upper and side surfaces of a semiconductor wafer sealed with a sealing resin layer are made uniform. The solution includes: (1) a bonding process (S1) for bonding a plurality of semiconductor wafers to a plurality of mounting areas on a wiring substrate divided by cross-cuts; (2) a sealing substrate fabrication process (S2) for the plurality of semiconductor wafers The surface side of the bonded wiring substrate is supplied with liquid resin and sealed together to form a sealing substrate. The chip forming process S3 is cut along a region corresponding to a cutout on the sealing substrate, so that the sealing wafer can have an upper surface and The lower surface is larger than the upper surface, and is provided with a side surface that is inclined from the upper surface to the lower surface; and a shield layer forming process S4, which forms a conductive shield layer on the upper surface and the side surface of a plurality of sealed wafers.

Description

Manufacturing method of semiconductor package

[0001] The present invention relates to a method for manufacturing a semiconductor package having a shielding function.

[0002] In order to prevent adverse effects on communication characteristics, semiconductor devices of portable communication devices such as mobile phones are generally required to suppress leakage of unnecessary electromagnetic waves to the outside. Therefore, the semiconductor package must have a shielding function. As a semiconductor package having a shielding function, a structure in which a shielding layer is provided along an outer surface of a sealing resin layer for sealing a semiconductor wafer mounted on an interposer is known (for example, refer to Patent Document 1). The shield provided on the outer surface of the sealing resin layer may be formed by a sheet metal shield. However, as the thickness of the shield becomes thicker, it becomes an obstacle to miniaturization or thinning of the device. Therefore, in order to reduce the thickness of the shielding layer, a technology for forming the shielding layer by a screen printing method, a spray coating method, an inkjet method, a sputtering method, or the like has been developed. [Prior Art Document] [Patent Document] [0003] [Patent Document 1] Japanese Patent Laid-Open No. 2012-039104

(Problems to be Solved by the Invention) [0004] However, since the side surface (side wall) of a semiconductor wafer sealed with a sealing resin layer is substantially vertical, it is difficult to form a shielding layer that shields electromagnetic waves on the top surface and the side surface as uniformly as possible. The upper film thickness and the side film thickness. In addition, it is difficult to form a shielding layer on the side surface (side wall) compared to the upper surface of a semiconductor wafer. Therefore, in order to form a film thickness that exhibits a sufficient shielding effect on the side surface, there is a problem that it takes a long time to form a film. [0005] The present invention has been developed in view of the foregoing, and an object thereof is to provide a manufacturing method of a semiconductor package which can efficiently form a shielding layer on a side surface of a semiconductor wafer sealed with a sealing resin layer with a predetermined film thickness. (Means for Solving the Problems) [0007] According to an aspect of the present invention, a method for manufacturing a semiconductor package can be provided. The method for manufacturing a semiconductor package for manufacturing a semiconductor package sealed with a sealant is characterized in that Equipped with: (1) a bonding process for bonding a plurality of semiconductor wafers on a plurality of areas on a wiring substrate divided by a plurality of intersecting predetermined division lines; (2) a sealing substrate manufacturing process for the semiconductor wafers to which the plurality of semiconductor wafers are bonded The sealing substrate is supplied together with a sealing agent on the surface side of the wiring substrate to be sealed together to form a sealing substrate. The chipping process is to cut the sealing substrate along a region corresponding to the predetermined division line on the wiring substrate, so that the sealed semiconductor wafer can be sealed. The upper side and the lower side that are larger than the upper side are provided in small pieces to form a side wall inclined from the upper side to the lower side; and a shield layer forming process is formed on the upper side and the side wall of the plurality of sealed semiconductor wafers. Conductive shielding layer. [0007] According to another aspect of the present invention, a method for manufacturing a semiconductor package can be provided, which is a method for manufacturing a semiconductor package that is sealed with a sealant, and is characterized by: (1) a wafer configuration process, A semiconductor wafer is arranged in each device arrangement area on a support substrate divided by a plurality of predetermined division lines that are crossed. A sealing body production process is performed after the wafer arrangement process is performed, and the sealant is used to seal the device. A semiconductor wafer, thereby forming a sealing body on the support substrate; a redistribution process, after removing the supporting substrate from the sealing body, forming a redistribution layer and a bump on the semiconductor wafer side of the sealing body; The sealing body is cut along a region corresponding to the predetermined division line on the support substrate, so that the sealed semiconductor wafer can have an upper surface and a lower surface larger than the upper surface, and can be inclined from the upper surface to the lower surface. And the formation of the shielding layer is based on the sealed half The above wafer and the sidewall of the conductive shield layer is formed. [0008] According to the above-mentioned configuration, since the sealed semiconductor wafer can have an upper surface and a lower surface larger than the upper surface, and is provided with a side-by-side chip forming process in which the side wall inclined from the upper surface to the lower surface is provided, Therefore, the shielding layer can be easily formed on the inclined sidewall, and the shielding layer on the sidewall of the semiconductor wafer sealed with the sealing resin layer can be efficiently formed into a predetermined film thickness. [0009] It is desirable that the chip forming process is performed by rotating a cutting blade having a ring-shaped cutting edge while cutting into the sealing substrate or the sealing body to form a chip. [0010] It is desirable that the miniaturization process is to tilt the laser beam for a direction perpendicular to the laser beam irradiation surface of the sealing substrate or the sealing body to a direction orthogonal to the processing feed direction, and then The sealing substrate or the sealing body is irradiated to form a small piece. [Effects of the Invention] 001 [0011] According to the present invention, since the sealed semiconductor wafer can have an upper surface and a lower surface larger than the upper surface, and a side-by-side chip forming process having side walls inclined from the upper surface, Therefore, the shielding layer can be easily formed on the inclined sidewall, and the shielding layer on the sidewall of the semiconductor wafer sealed with the sealing resin layer can be efficiently formed into a predetermined film thickness.

[0013] The form (embodiment) for implementing the present invention will be described in detail with reference to the drawings. The present inventors are not limited by the contents described in the following embodiments. In addition, the constituent elements described below include those which are easily conceivable by those skilled in the art and which are substantially the same. The configurations described below can be appropriately combined. In addition, various omissions, substitutions, or changes can be made in the configuration without departing from the gist of the present invention. First Embodiment FIG. 1 is a flowchart showing a procedure of a method of manufacturing a semiconductor package according to a first embodiment. The semiconductor package is described later in detail, and is a package type semiconductor device (for example, CSP, BGA, etc.) including a resin layer for sealing a semiconductor wafer and a conductive shielding layer covering the outer surface of the resin layer. In this embodiment, as shown in FIG. 1, the method for manufacturing a semiconductor package includes a bonding process S1, a sealing substrate production process S2, a chip forming process S3, and a shield layer forming process S4. The manufacturing method according to this embodiment is only required to include at least such processes, and other processes may be provided between the processes. Next, each of these processes will be described. [Joining Process S1] FIG. 2 is a side sectional view showing a state where a semiconductor wafer is bonded to a wiring substrate. In the bonding process S1, the semiconductor wafer 11 is mounted on the surface (one surface) 10a of the wiring substrate 10 by bonding. In the wiring substrate 10, a plurality of mounting areas (areas) A divided by a plurality of streets (planned division lines) S crossing each other are formed into a matrix. Although the illustration is omitted in each mounting area A, an electrode connected to a terminal of the semiconductor wafer 11 or a wiring including a ground wire is actually applied. The semiconductor wafer 11 is a so-called die formed by dividing a wafer including a semiconductor device on a substrate formed of silicon, sapphire, gallium, or the like. [0016] Such semiconductor wafers 11 are respectively bonded and mounted in a mounting area A formed on the surface 10a of the wiring substrate 10. Specifically, it may be a mounting form that directly connects a terminal formed on the lower surface of the semiconductor wafer 11 and an electrode formed in the mounting area A, or a connection formed on the upper surface of the semiconductor wafer 11 via a metal wire. A wire bonding type mounting type of the terminals and electrodes formed in the mounting area A. [0017] In this bonding process S1, the wiring substrate 10 is placed on a jig (not shown) with the back surface (other surface) 10b side of the wiring substrate 10 facing downward. This jig has, for example, a suction mechanism and holds the wiring substrate 10. [0018] [Sealing Substrate Production Process S2] FIG. 3 is a diagram showing a configuration for supplying a liquid resin for sealing to a wiring substrate on which a semiconductor wafer is mounted, and FIG. 4 is a side sectional view of the sealing substrate sealed with a resin. In the sealing substrate production process S2, the semiconductor wafer 11 mounted in the mounting area A formed on the wiring substrate 10 is sealed. In this embodiment, as shown in FIG. 3, the wiring substrate 10 on which the semiconductor wafer 11 is mounted is held on a sealing jig 20, and a template 12 is arranged above the wiring substrate 10. This template 12 is provided with an injection port 12A on the upper surface, and a resin supply nozzle 15 is disposed above the injection port 12A. The liquid resin (molded resin) 16 supplied from the resin supply nozzle 15 is filled into the gap between the wiring substrate 10 and the template 12 through the injection port 12A. The liquid resin 16 is made of a hardening material, and can be selected from, for example, epoxy resin, silicone resin, urethane resin, unsaturated polyester resin, acrylic urethane resin, or polyimide resin. The plurality of semiconductor wafers 11 mounted on the wiring substrate 10 can be sealed together by the liquid resin 16 filled in the template 12. [0019] Next, the liquid resin 16 sealing the semiconductor wafer 11 is heated or dried to be cured. As a result, as shown in FIG. 4, the liquid resin is hardened to constitute the sealing resin layer 17. The sealing resin layer 17 is a semiconductor substrate 11 that is closely adhered to the wiring substrate 10 and mounted on the wiring substrate 10, and is integrated with the wiring substrate 10 and the semiconductor wafer 11 to form a sealing substrate 18. [0020] Here, it is desirable that the surface 18a of the sealing substrate 18 (the sealing resin layer 17) is ground and planarized (planarization process). As described above, since the sealing resin layer 17 is a hardened material after the liquid resin 16 is supplied to the surface 10 a of the wiring substrate 10, unevenness is generated on the surface 18 a of the sealing substrate 18 (seal resin layer 17). Therefore, the sealing substrate 18 can be ground by a grinding unit (not shown), thereby flattening the surface 18 a of the sealing substrate 18. In this case, not only the surface 18a is simply flattened, but also the sealing resin layer 17 covering the upper surface of the semiconductor wafer 11 can be adjusted to a desired thickness. [0021] Next, a bump BP is formed on the back surface 10b of the wiring substrate 10 (bump formation process). 5 is a side cross-sectional view of a sealing substrate having bumps formed on a rear surface of the wiring substrate. When the bumps BP are formed, the sealing substrate 18 is held on a jig (not shown) with the surface 18 a side as a lower surface. Thereby, as shown in FIG. 5, the back surface 10b of the wiring board 10 is exposed as an upper surface. In this state, bumps BP are formed on the back surface 10 b of the wiring substrate 10. This bump BP is a member that becomes a terminal or an electrode when a semiconductor package in a final form is mounted on various substrates (not shown), and is formed at a predetermined position corresponding to a wiring pattern provided on the wiring substrate 10. In addition, in this embodiment, the bump formation process is performed after the sealing substrate preparation process S2, but when the formation position of the bumps BP is known, it may be formed on the back surface 10b of the wiring substrate 10 in advance. [0022] [Slicing process S3] FIG. 6 is a side cross-sectional view showing an example of a configuration in which a sealing substrate is chipped by cutting, and FIG. 7 is a side cross-sectional view illustrating a sealed wafer chipped by cutting. As shown in FIG. 6, the wiring substrate 10 is held on the die 21 with the back surface 10 b on which the bumps BP are formed as a lower surface. A plurality of cavity portions 21A of the chip forming jig 21 are formed on the matrix in a matrix shape, and the bumps BP corresponding to the semiconductor wafers 11 are accommodated in the cavity portions 21A. In addition, each cavity portion 21A is connected to a suction path 21B connected to a vacuum suction source (not shown), and sucks and holds the wiring substrate 10. Further, the chipping jig 21 is formed with a cutting groove 21C between each of the hole portions 21A. This cutting groove 21C is formed to correspond to the scribe line S of the wiring substrate 10 when the wiring substrate 10 is held on the chip forming jig 21. [0023] Next, the sealing substrate 18 is cut along a region 18S corresponding to the above-mentioned sipe S. In this embodiment, as shown in FIG. 6, cutting of the sealing substrate 18 is performed by the cutting unit 30. The cutting unit 30 is provided with a cutting blade 32 attached to a rotary spindle 31. The cutting blade 32 is formed in a circular plate shape, and a cutting edge 33 formed in a ring shape is provided at a peripheral portion. This cutting edge 33 is a V-shaped edge having a predetermined edge angle θ with respect to a lead straight line, as shown in FIG. 6. In addition, the cutting unit 30 moves the cutting blade 32 forward and backward with respect to the sealing substrate 18 in a height direction by a lifting mechanism (not shown). Therefore, the sealing substrate 18 is cut into the sealing substrate 18 by rotating the cutting blade 32, and the sealing substrate 18 is cut at an inclination angle corresponding to the blade angle θ. In addition, since the cutting jig 21 is formed with a cutting groove 21C corresponding to the cutting path S of the wiring substrate 10, the cutting edge of the cutting edge 33 after cutting the sealing substrate 18 enters the cutting groove 21C. Interference between the chipping jig 21 and the cutting blade 32 (cutting edge 33) is prevented. [0024] In addition, the sealing substrate 18 held by the miniaturization jig 21 is moved in the horizontal direction with respect to the cutting unit 30 by a moving mechanism (not shown). Thereby, the sealing substrate 18 is chipped into a plurality of sealing wafers 40 as shown in FIG. 7 by cutting along the area 18S corresponding to all the scribe lines S. The sealing wafer 40 is configured by including an upper surface 40a, a lower surface 40b larger than the upper surface 40a, and a side surface (side wall) 40c inclined from the upper surface 40a to the lower surface 40b. In addition, the above-mentioned raising and lowering mechanism and moving mechanism may be any structure as long as the cutting unit 30 is relatively raised and lowered and the die-forming jig 21 is relatively moved. [0025] The chipping of the sealing substrate 18 by cutting can also be implemented by other structures. 8 and 9 are side cross-sectional views showing other examples of a configuration in which the sealing substrate is made small by cutting. In the example of FIG. 8, the cutting unit 30A is configured such that the cutting blade 32A is inclined only by a predetermined angle θ with respect to the lead straight line. Therefore, even with the configuration of the cutting blade 32A that forms a general cutting groove, it is possible to cut along a predetermined cutting line 42, thereby forming an inclined groove 41 inclined at a predetermined angle θ in the sealing substrate 18. The side surface of this inclined groove 41 is a side surface 40 c defining the aforementioned sealed wafer 40. [0026] Further, in the example of FIG. 9, the laser processing is performed using a laser beam irradiation device 34 to reduce the size of the chips. The laser beam irradiation device 34 irradiates a laser beam (laser beam) L toward an area 18S corresponding to the tangent S of the sealing substrate 18 and performs cutting by ablation processing. The laser beam irradiation device 34 is provided with an oscillator (not shown) that oscillates the laser beam L, and a light collector 35 that collects light by the laser beam L oscillated by the oscillator. The light collector 35 is configured by a total reflection mirror that changes the traveling direction of the laser beam L oscillated by the oscillator, or a light collecting lens that collects the laser beam L. The light collector 35 is inclined to a direction (vertical direction) perpendicular to the surface (laser beam irradiation surface) 18a of the sealing substrate 18 by a predetermined angle θ to be orthogonal to the direction (processing feed direction) where the tangent S extends It is arranged in a direction and emits a laser beam L inclined at this predetermined angle θ. Thereby, the sealing substrate 18 can be formed with an inclined groove 43 inclined at a predetermined angle θ. The side surface of this inclined groove 43 is a side surface 40 c defining the above-mentioned sealed wafer 40. In addition, although the illustration is omitted, it is also possible to use a cutting unit or a laser beam irradiation device to cut (cut) the sealing substrate 18 vertically (vertically) along the tangent path using a cutting unit or a laser beam irradiation device, and then the The side surface of the separated sealed wafer is configured to perform inclined surface processing by a profiler device or the like. [0027] In the example described above, the side surface 40c of the sealing wafer 40 is configured to be inclined from the upper surface 40a to the lower surface 40b, but is not limited thereto. FIG. 10 is a partial side cross-sectional view showing a modification example when cutting a sealing substrate. As shown in FIG. 10, the side surface 40c of the sealing wafer 40 may be provided with a first side surface 40c1 extending obliquely from the upper surface 40a to the lower surface 40b, and a second side surface extending vertically from the first side surface 40c1 to the lower surface 40b. The composition of 40c2. In this configuration, by providing the portion of the second side surface 40c2, the size of the lower surface 40b of the sealed wafer 40 can be reduced, and the size of the sealed wafer 40 can be reduced. In this configuration, for example, a V-shaped cutting edge 33 is used to cut the sealing resin layer 17 (see FIG. 6) of the sealing substrate 18 from the upper surface 40a side to form the first side surface 40c1, and then from the upper surface 40a side or the lower surface. The second side surface 40c2 is formed by cutting the wiring substrate 10 perpendicularly on the 40b side, thereby reducing the size of the second side surface 40c2. Alternatively, for example, in the bump formation process, when bumps BP are formed on the back surface 10b of the wiring substrate 10, the wiring substrate 10 is cut vertically from the back surface 10b side of the wiring substrate 10 to form a second side surface 40c2. For example, the V-shaped cutting edge 33 is used to cut the sealing resin layer 17 (see FIG. 6) of the sealing substrate 18 from the upper surface 40a side to form the first side surface 40c1. In this case, as shown in FIG. 10, the first side surface 40 c 1 is provided to a position where it reaches the ground line GL provided in the wiring substrate 10. According to this configuration, the electromagnetic wave shielded by the conductive shielding layer (not shown) provided on the first side surface 40c1 can reliably flow to the outside through the ground line GL. [0028] [Shield Layer Forming Process S4] FIG. 11 is a side cross-sectional view showing a sealed wafer on which a conductive shield layer is formed. First, before the conductive shielding layer 45 is formed, the sealing wafer 40 is picked up from the chip forming jig 21 holding the chipped sealing wafer 40, and the sealing wafer 40 is arranged on another coating jig 22 and arranged. This covering jig 22 is a plurality of cavity portions 22A formed on the upper surface in the same manner as the miniaturization jig 21, and the bumps BP of the sealing wafer 40 are housed in the cavity portions 22A, respectively. In the coating jig 22, the sealing wafer 40 is arranged with a predetermined interval P between adjacent sealing wafers 40 and 40. This interval P is sufficient to form the conductive shielding layer 45 to the lower end of the side surface 40 c of the sealing wafer 40. Although not shown in FIG. 11, the covering jig 22 may include a suction path connected to each of the cavity portions 22A to suck and hold the sealed wafer 40. [0029] Next, a conductive shielding layer 45 is formed on the upper surface 40a and the side surface 40c of the sealing wafer 40. The conductive shielding layer 45 is a multilayer film composed of one or more metals such as copper, titanium, nickel, and gold, and has a thickness of several μm to several hundreds μm. For example, sputtering, CVD (Chemical Vapor Deposition: Chemical vapor growth) or spray coating. The conductive shielding layer 45 can also be formed by vacuum lamination. This vacuum lamination is performed by laminating a metal thin film having the above-mentioned multilayer film on the sealing wafer 40 using a conductive adhesive under a vacuum environment. Upper surface 40a and side surface 40c. In this embodiment, since the side surface 40c of the sealing wafer 40 is an inclined surface inclined from the upper surface 40a to the lower surface 40b, when the conductive shielding layer 45 is formed by sputtering or the like from above the sealing wafer 40, not only the upper surface 40a It is also possible to easily form a metal film on the side surface 40c. Therefore, the film thickness of the conductive shielding layer 45 of the upper surface 40a and the side surface 40c of the sealing wafer 40 can be made uniform. [0030] Finally, the sealed wafer 40 on which the conductive shielding layer 45 is formed, that is, the semiconductor package 50 is picked up from the coating jig 22 by a pick-up unit and transferred to the next process. 12 is a side sectional view showing a configuration of a semiconductor package, and FIGS. 13 and 14 are side sectional views showing a modified example of the semiconductor package. As shown in FIG. 12, the semiconductor package 50 includes a sealing wafer 40 including a semiconductor wafer 11 mounted on the wiring substrate 10, and a sealing resin layer 17 that seals the semiconductor wafer 11 with a resin; The shielding layer 45 is formed on the upper surface 40 a and the side surface 40 c of the sealing wafer 40. In this embodiment, the side surface 40c of the sealing wafer 40 is an inclined surface inclined from the upper surface 40a to the lower surface 40b. Therefore, not only the upper surface 40a of the wafer 40 but also the side surface 40c can be easily formed with a metal film. The film thickness of the conductive shielding layer 45 on the upper surface 40a and the side surface 40c is uniformized. [0032] In this embodiment, a description is given of a configuration including a sealing wafer 40 in which one semiconductor wafer 11 is mounted on the wiring substrate 10 as the semiconductor package 50, but it is not limited to this. As shown in FIG. 13, for example, a semiconductor package 51 including a sealing wafer 40-1 may be manufactured, and a plurality of (3) semiconductor wafers 11α, 11β, and 11γ are mounted on the wiring substrate 10 to seal the sealing wafer 40-1. The resin layer 17 seals the semiconductor wafers 11α, 11β, and 11γ. In this configuration, the semiconductor wafers 11α, 11β, and 11γ are semiconductor wafers having different functions, and are mounted adjacent to each other in the bonding process S1. Further, in the miniaturization process S3, miniaturization is performed as the sealed wafer 40-1 including the semiconductor wafers 11α, 11β, and 11γ. In the semiconductor package 51 provided with such a sealed wafer 40-1, since the side surface 40c of the sealed wafer 40-1 is an inclined surface inclined from the upper surface 40a to the lower surface 40b, not only the upper surface 40a of the wafer 40-1, A metal film can also be easily formed on the side surface 40c, and the thickness of the conductive shield layer 45 on the upper surface 40a and the side surface 40c of the sealing wafer 40-1 can be made uniform. [0033] As shown in FIG. 14, a semiconductor package (SIP) 52 including sealed wafers 40-2 and 40-3 may be manufactured, and the sealed wafers 40-2 and 40-3 are mounted on the wiring substrate 10. The two semiconductor wafers 11α, 11β are sealed with a sealing resin layer 17 respectively. In this configuration, the semiconductor wafers 11α and 11β are semiconductor wafers having different functions, and are mounted adjacent to each other in the bonding process S1. In the chip reduction process S3, the chip reduction is performed as an integrated sealed wafer including the semiconductor wafers 11α and 11β. In this miniaturization process S3, the sealed wafer is divided into two sealed wafers 40-2, 40-3 between the semiconductor wafers 11α, 11β, and each side 40c will be inclined from the upper 40a to the lower 40b. surface. According to this structure, a metal film can be easily formed not only on the upper surface 40a of each of the sealing wafers 40-2, 40-3, but also on the side surface 40c, and the sealing of the upper surface 40a and the side surface 40c of the wafers 40-2 and 40-3 can be achieved. The thickness of the conductive shielding layer 45 is made uniform. In addition, the conductive shielding layer 45 for shielding between the sealed wafers 40-2 and 40-3 can be easily formed. [0034] According to this embodiment, it includes: a bonding process S1, which is a process of bonding a plurality of semiconductor wafers 11 to a plurality of mounting areas A on a wiring substrate 10 divided by crossing tangents S; a sealing substrate is produced; Process S2, which is performed by supplying liquid resin 16 on the surface 10a side of the wiring substrate 10 to which the plurality of semiconductor wafers 11 are bonded, and sealing together to form a sealing substrate 18; The area 18S of the tangent path S on 18 is cut to reduce the size of the sealing wafer 40 to have an upper surface 40a and a lower surface 40b larger than the upper surface 40a, and a side surface 40c inclined from the upper surface 40a to the lower surface 40b. And shield layer forming process S4, since the conductive shield layer 45 is formed on the upper surface 40a and the side surface 40c of the plurality of seal wafers 40, the conductive shield layer 45 is formed by sputtering or the like from above the seal wafer 40 In this case, a metal film can be easily formed not only on the upper surface 40a but also on the side surface 40c. Therefore, the conductive shielding layer 45 of the side surface 40c of the sealing wafer 40 can be effectively formed into a predetermined film thickness capable of exhibiting a sufficient shielding effect, and the film of the conductive shielding layer 45 of the upper surface 40a and the side surface 40c of the sealing wafer 40 can be obtained. Thick uniformity. [0035] Further, in this embodiment, the chip forming process S3 is a cutting blade 32 having a ring-shaped cutting edge 33 while rotating, and is cut into the sealing substrate 18 to be chipped, so that the sealing substrate 18 can be easily chipped. Into. In this case, by setting the cutting blade 32 to a V-shaped blade having a cutting edge angle θ of the cutting edge 33 or arranging the cutting blade 32A to be inclined only by a predetermined angle θ with respect to the lead straight line, the sealing wafer 40 can be easily cut into smaller pieces. The side surface 40c is formed as an inclined surface inclined from the upper surface 40a to the lower surface 40b. [0036] In another example of the present embodiment, the light collector 35 of the laser beam irradiation device 34 is inclined at a predetermined angle θ to a direction perpendicular to the tangent S in a direction perpendicular to the surface 18 a of the sealing substrate 18. Since the directions (processing feed directions) are arranged orthogonally, the side surface 40c of the sealing wafer 40 can be easily formed as an inclined surface that is inclined from the upper surface 40a to the lower surface 40b when the wafer is reduced to pieces by laser processing. [0037] [Second Embodiment] FIG. 15 is a flowchart showing a procedure of a method of manufacturing a semiconductor package according to a second embodiment. The semiconductor package produced by the manufacturing method of the second embodiment is a package type semiconductor device (for example, FO-WLP) having a resin layer sealing a semiconductor wafer and a conductive shielding layer covering the outer surface of the resin layer. In this embodiment, as shown in FIG. 15, the method for manufacturing a semiconductor package includes a wafer placement process S11, a sealing body production process S12, a rewiring process S13, a chip formation process S14, and a shield layer formation process S15. The manufacturing method according to this embodiment is only required to include at least such processes, and other processes may be provided between the processes. Next, each of these processes will be described. [0038] [Wafer Placement Process S11] FIG. 16 is a side sectional view showing a state where a semiconductor wafer is placed on a support substrate. The support substrate 25 holds a plurality of semiconductor wafers 11 arranged on the support substrate 25 and is formed of a rigid material (for example, glass) having a certain degree of rigidity. In the support substrate 25, a plurality of device arrangement areas A1 divided by a plurality of tangents S crossing each other are set in a matrix shape. The positions or sizes of the tangent paths S and the device arrangement area A1 are determined according to the semiconductor package to be made. [0039] The semiconductor wafer 11 is a so-called die formed by dividing a wafer including a semiconductor device on a substrate formed of silicon, sapphire, gallium, or the like. In this embodiment, various terminals are formed on the surface (one surface) 11 a of the semiconductor wafer 11. With this surface (one surface) 11 a as a bottom, the semiconductor wafer 11 is disposed on the support substrate 25 in a device arrangement area A1. . The semiconductor wafer 11 is fixed to the support substrate 25 via, for example, a protective tape 26 whose adhesive force is reduced by irradiating ultraviolet rays of a predetermined wavelength (300 to 400 nm). [0040] [Sealing Body Preparation Process S12] FIG. 17 is a side sectional view of a sealing body sealed with a resin. In the sealing body production process S12, the semiconductor wafer 11 disposed in the device arrangement area A1 set on the support substrate 25 is sealed. For example, a template (not shown) is arranged above the support substrate 25 on which the semiconductor wafer 11 is arranged, and the liquid resin 16 (see FIG. 3; a sealing material) is filled in the support substrate 25 (protective tape) through an injection port of the template. 26) Clearance from the template. [0041] Next, the liquid resin 16 sealing the semiconductor wafer 11 is heated or dried to be hardened. Thereby, as shown in FIG. 17, the liquid resin hardens | cures, and the sealing resin layer 17 is comprised. This sealing resin layer 17 is in contact with a plurality of semiconductor wafers 11 on a support substrate 25 (protective tape 26), and is integrated with these semiconductor wafers 11 to form a sealing body 19. [0042] Here, the surface 19A (the surface 17A of the sealing resin layer 17) of the sealing body 19 (the sealing resin layer 17) is ground and flattened (planarization process). The surface 19A of the sealing body 19 is flattened by grinding the sealing body 19. In this case, not only the surface 19A is simply flattened, but also the sealing resin layer 17 covering the upper surface of the semiconductor wafer 11 can be adjusted to a desired thickness. [Rewiring Process S13] FIG. 18 is a side cross-sectional view showing a state where a rewiring layer and a bump are formed on the semiconductor wafer side of the sealing body. When the redistribution layer 60 is formed, the support substrate 25 and the protective tape 26 are peeled from the surface 11a side of the semiconductor wafer 11 which is the back surface of the sealing body 19, and the sealing body 19 is placed on the jig with the surface 19A side facing downward Icon). This jig has, for example, a suction mechanism and holds the sealing body 19. Thereby, as shown in FIG. 18, the semiconductor wafer 11 side of the sealing body 19 is exposed as an upper surface. [0044] A redistribution layer 60 and a bump BP are formed on the semiconductor wafer 11 side of the sealing body 19. The rewiring layer 60 is provided with a metal wiring 61 made of aluminum or the like connected to selected terminals (not shown) of the semiconductor wafer 11, and an insulating film covering the surface 11 a of the semiconductor wafer 11 and the wiring 61. 62 and constituted. In order to form the rewiring layer 60, the wiring 61 is first formed by a film formation method such as CVD or electroplating, and then the insulating film 62 is formed. The material of the insulating film 62 is an insulating resin such as polyimide, or a glass-based oxide film such as SOG (Spin On Glass) or BPSG (Boron Phosphorous Silicate Glass). In the case of an insulating resin or SOG, the insulating film 62 is formed by the spin coating method described above. In the case of BPSG, the insulating film 62 is formed by a film formation method such as CVD. The bump BP is a member that becomes a terminal or an electrode when a semiconductor package in a final form is mounted on various substrates (not shown), and is formed at a predetermined position corresponding to a pattern of the wiring 61 that is formed on the substrate. Wiring layer 60. [0045] [Slicing process S14] FIG. 19 is a side sectional view showing a sealing body provided with a redistribution layer, and FIG. 20 is a side sectional view showing an example of a structure in which the sealing body is made small by cutting. It is a side cross-sectional view showing a sealed wafer that is reduced to pieces by cutting. As shown in FIG. 19, the sealing body 19 is held on the die 21 with the redistribution layer 60 as a lower surface. The chip forming jig 21 includes a plurality of cavity portions 21A formed on the upper surface in a matrix shape, and the bumps BP corresponding to the redistribution layer 60 of each semiconductor wafer 11 are accommodated in the cavity portions 21A. A suction path 21B connected to a suction source (not shown) is connected to each of the hole portions 21A, and the redistribution layer 60 and the sealing body 19 are sucked and held. Further, the chipping jig 21 is formed with a cutting groove 21C between each of the hole portions 21A. This cutting groove 21C is formed corresponding to the above-mentioned cutting path S when the redistribution layer 60 and the sealing body 19 are held on the die 21 for chip formation. [0046] Next, the sealing body 19 and the redistribution wiring layer 60 are cut along the area 19S corresponding to the above-mentioned sipe S. In this embodiment, as shown in FIG. 20, cutting of the sealing body 19 is performed by the cutting unit 30. The cutting unit 30 is provided with a cutting blade 32 attached to a rotary spindle 31. The cutting blade 32 is formed in a circular plate shape, and a cutting edge 33 formed in a ring shape is provided at a peripheral portion. This cutting edge 33 is a V-shaped edge having a predetermined edge angle θ with respect to a lead straight line, as shown in FIG. 20. In addition, the cutting unit 30 moves the cutting blade 32 forward and backward with respect to the sealing body 19 in a height direction by a lifting mechanism (not shown). Therefore, the sealing body 19 and the redistribution layer 60 are cut into the sealing member 19 and the redistribution layer 60 while the cutting blade 32 is rotated, and the sealing body 19 and the redistribution layer 60 are cut at an inclination angle corresponding to the blade angle θ. In addition, since the cutting groove 21C corresponding to the cutting path S is formed in the chip forming jig 21, the cutting edge of the cutting edge 33 after cutting the rewiring layer 60 enters the cutting groove 21C to prevent chipping. Interference between the jig 21 and the cutting blade 32 (cutting edge 33). [0047] Further, the sealing substrate 18 held by the chip forming jig 21 is moved in the horizontal direction with respect to the cutting unit 30 by a moving mechanism (not shown). Thereby, the sealing body 19 and the redistribution layer 60 are cut into a plurality of sealing wafers 70 as shown in FIG. 21 by cutting along the area 19S corresponding to all the scribe lines S. The sealing wafer 70 is configured by including an upper surface 70a, a lower surface 70b larger than the upper surface 70a, and a side surface (side wall) 70c inclined from the upper surface 70a to the lower surface 70b. In addition, as long as the said raising-lowering mechanism and a moving mechanism are relatively up-and-down and movable with the cutting unit 30 and the jig | tool 21 for chip | tip formation, what kind of a structure may be sufficient. [0048] As described above, the cutting of the sealing body 19 and the redistribution layer 60 into small pieces can be a cutting unit (see FIG. 8) that can be disposed by tilting the lead straight line by a predetermined angle with respect to the lead line, or A laser beam irradiating unit (see FIG. 9) is used, which is inclined at a predetermined angle from the direction (vertical direction) perpendicular to the surface (laser beam irradiating surface) of the sealing body to extend from the tangent The directions (processing feed directions) are arranged orthogonally, and a laser beam inclined at a predetermined angle is emitted. In addition, although the illustration is omitted, it is also possible to use a cutting unit or a laser beam irradiation device to cut (cut) the sealing body 19 and the redistribution layer vertically (vertically) along the cutting path using a cutting unit or a laser beam irradiation device. After 60, the side surface of the separated sealed wafer is configured to perform inclined surface processing by a profiler device or the like. [0049] [Shield Layer Forming Process S15] FIG. 22 is a side cross-sectional view showing a sealed wafer on which a conductive shield layer is formed. Before the conductive shielding layer 45 is formed, the sealing wafer 70 is picked up from the chip forming jig 21 holding the chipped sealing wafer 70, and the sealing wafer 70 is arranged on another coating jig 22. This covering jig 22 is the same as the chip forming jig 21 in that a plurality of cavity portions 22A are formed in a matrix form, and the bumps BP of the sealing wafer 70 are housed in the cavity portions 22A, respectively. In the coating jig 22, the sealing wafer 70 is arranged with a predetermined interval P between adjacent sealing wafers 70 and 70. This interval P is sufficient to form the conductive shielding layer 45 to the lower end of the side surface 70 c of the sealing wafer 70. Although not shown in FIG. 22, the covering jig 22 may include a vacuum suction path connected to each of the cavity portions 22A to suck and hold the sealed wafer 70. [0050] Next, a conductive shielding layer 45 is formed on the upper surface 70a and the side surface 70c of the sealing wafer 70. The conductive shielding layer 45 is a multilayer film composed of one or more metals such as copper, titanium, nickel, and gold, and has a thickness of several μm to several hundreds μm. For example, it is formed by sputtering, CVD, or spray coating. form. The conductive shielding layer 45 can also be formed by vacuum lamination. The vacuum lamination is performed by laminating a metal thin film having the above-mentioned multilayer film on a sealing wafer 70 with a conductive adhesive under a vacuum environment.的 上 上 70a 和 边 70c。 70a and the side 70c. In this embodiment, since the side surface 70c of the sealing wafer 70 is an inclined surface inclined from the upper surface 70a to the lower surface 70b, when the conductive shielding layer 45 is formed by sputtering or the like from above the sealing wafer 70, not only the upper surface 70a It is also possible to easily form a metal film on the side surface 70c. Therefore, the film thickness of the conductive shielding layer 45 of the upper surface 70a and the side surface 70c of the sealing wafer 70 can be made uniform. [0051] Finally, the sealed wafer 70 having the conductive shielding layer 45 formed thereon, that is, the semiconductor package 80 is picked up from the coating jig 22 by a picking unit, and is transferred to the next process. [0052] According to this embodiment, since it includes: a wafer placement process S11, each of the semiconductor wafers 11 is arranged on the support substrate 25 divided by a plurality of crossing tangents S with the surface 11a as the downside. Device arrangement area A1; the sealing body preparation process S12 is performed after the wafer placement process S11 is performed, and the back surface 11b side of the semiconductor wafer 11 is sealed with a liquid resin to form a sealing body 19 on the support substrate 25; The rewiring process S13 is performed after removing the support substrate 25 from the sealing body 19, and then a rewiring layer 60 and a bump BP are formed on the semiconductor wafer 11 side of the sealing body 19; The area 19S of the tangent S on the body 19 is cut so that the wafer 70 can have an upper surface 70a and a lower surface 70b larger than the upper surface 70a, and a small piece having a side surface 70c inclined from the upper surface 70a to the lower surface 70b. And shield layer forming process S15, which forms the conductive shield layer 45 on the upper surface 70a and the side surface 70c of the plurality of sealed wafers 70, and therefore, a conductive shield is formed by sputtering or the like from above the sealed wafer 70 In the layer 45, a metal film can be easily formed not only on the upper surface 70a but also on the side surface 70c. Therefore, the thickness of the conductive shielding layer 45 of the upper surface 70 a and the side surface 70 c of the sealing wafer 70 can be made uniform. [0053] Furthermore, in this embodiment, the chipping process S14 is a cutting blade 32 having a ring-shaped cutting edge 33 while rotating, and is cut into the sealing body 19 to be chipped, so that the sealing body 19 can be easily chipped. In this case, by setting the cutting blade 32 to a V-shaped edge having a cutting edge angle θ of the cutting edge 33 or arranging the cutting blade 32 to incline only a predetermined angle θ with respect to a lead straight line, it is possible to easily seal the wafer at the time of chip reduction The side surface 70c of the 70 is formed as an inclined surface inclined from the upper surface 70a to the lower surface 70b. [0054] Furthermore, in another example of the present embodiment, the light collector of the laser beam irradiation device is inclined toward the direction perpendicular to the surface 19A of the sealing body 19 by a predetermined angle θ to the direction in which the tangent S extends ( The processing feed direction) is arranged in a direction orthogonal to each other. Therefore, when the wafer is reduced in size by laser processing, the side surface 70c of the sealing wafer 70 can be easily formed as an inclined surface inclined from the upper surface 70a to the lower surface 70b. [0055] In this embodiment, in the wafer placement process S11, the semiconductor wafer 11 on which the device is provided is placed on the surface (one side) 11a of the semiconductor wafer 11 on the support substrate 25. The area A1 is arranged, but it is not limited to this. The back surface (other surface) 11b of the semiconductor wafer 11 may be lowered, and the device area A1 in which the semiconductor wafer 11 is arranged on the support substrate 25 may be arranged. In this case, although the illustration is omitted, a device that actually exposes the surface (one side) 11a of the semiconductor wafer 11 on the support substrate 25 is provided with an auxiliary redistribution layer containing polyimide or silica. The semiconductor wafer 11 having the redistribution layer is sealed with a resin. Then, the surface of the sealing body (the surface 11a side of the semiconductor wafer 11) is ground to such an extent that the device is not exposed, and a rewiring layer communicating with the device is formed on the surface of the sealing body. Then, the sealing body on which the redistribution layer is formed is subjected to the above-described miniaturization process and shielding layer formation process, thereby forming a sealed wafer. [0056] Next, the relationship between the inclination angle of the side surface of the sealed wafer and the film thickness of the conductive shielding layer formed on the side surface in the above-described embodiment will be described. FIG. 23 is a diagram showing the film thickness of the conductive shielding layer provided on the test body, and FIG. 24 is a diagram showing the relationship between the inclination angle of the side surface of the test body and the film thickness. The inventor focused on the relationship between the inclination angle of the side surface 40c (70c) of the sealing wafer 40 (70) and the film thickness of the conductive shielding layer 45 formed on the side surface 40c (70c). The difference between the side surface 40c (70c) To measure the film thickness of the conductive shielding layer 45. [0057] Specifically, as shown in FIG. 23, a plurality of test bodies TE are formed of silicon, and have upper TEa, lower TEb, and side TEc, and the inclination angle θ1 of each side TEc is changed. A conductive shielding layer 45 is provided on the upper TEa and the lateral TEc of TE. The conductive shielding layer 45 is made of titanium, and is 180 ° C, 8 × 10. ^-4 It is formed by the ion plating method under the condition of Pa. The inclination angle θ1 is set to 90 degrees, 82 degrees, 68 degrees, 60 degrees, and 45 degrees. Here, the inclination angle θ1 is related to the following formula (1) having a predetermined edge angle θ for the lead straight line. θ1 (degree) = 90-θ (1) [0058] The conductive shielding layer 45 is divided into: an upper shielding layer 45A formed on the upper TEa and a side shielding layer 45B formed on the side TEc. The observation image of a scanning electron microscope (SEM) was used to measure the thickness t1 of the upper shielding layer 45A and the thickness t2 of the lower portion of the side shielding layer 45B. The thickness t1 of the upper shielding layer 45A after measurement and the thickness t2 of the lower portion of the side shielding layer 45B are calculated as the value of the step coverage shown by the following formula (2), and this value and the tilt angle are calculated. The relationship of θ1 is summarized in FIG. 24. step coverage = (t2 / t1) × 100 (%) (2) [0059] As shown in FIG. 24, as the value of the tilt angle θ1 decreases from a state of 90 degrees (the side is vertical), the step is covered The value gradually increases, and becomes 100% when the inclination angle θ1 is 45 degrees. That is, when the inclination angle θ1 is set to form 45 degrees, the thickness t1 of the upper shielding layer 45A and the thickness t2 of the lower portion of the side shielding layer 45B are consistent, and the conductive shielding layer 45 of the upper TEa and the lateral TEc can be realized Uniform film thickness. [0060] According to the experiments of the inventor, when the film is formed by the above-mentioned ion plating method, once the value of the step coverage is less than 50%, the film formation of the side shielding layer 45B requires time and process. Since the cost increases, at least the value of the step coverage is preferably in a range of 50% or more. Therefore, the inclination angle θ1 of the side surface 40c (70c) of the sealed wafer 40 (70) constituting the semiconductor package 50 (80) is preferably 45 degrees or more and 82 degrees or less. [0061] When the inclination angle θ1 is 45 degrees, it is a value showing a good step coverage. However, when the inclination angle θ1 is set to 45 degrees, it is estimated that the length of the lower TEb relative to the upper TEa will increase, and the semiconductor package 50 ( 80) When the size of the upper TEb is increased or the size of the lower TEb is the same, the upper TEa (device area) is reduced. Therefore, from the standpoint of miniaturization of the semiconductor package 50 (80), the inclination angle θ1 is preferably 60 degrees to 68 degrees, and the most desirable condition is the inclination angle θ1 = 60 degrees. On the other hand, the area where the inclination angle θ1 is 45 degrees or more and 60 degrees or less is a rate of change of the value of the step coverage smaller than the area where the inclination angle is 60 degrees or more and 82 degrees or less. Therefore, for example, even when the inclination angle of the cutting edge 33 is changed during processing, a change in the film thickness of the shielding layer to be formed can be suppressed. Therefore, in order to obtain a sound effect such as in the case of mass production, the inclination angle θ1 is preferably set to 45 degrees or more and 60 degrees or less. As long as the area with a small rate of change in the value covered by such a step is shifted to an area with a larger inclination angle θ1, the miniaturization and productivity of the semiconductor package 50 (80) can be taken into consideration, which is ideal. [0062] As mentioned above, one embodiment of the present invention has been described, but the above embodiment is presented as an example, and is not intended to limit the scope of the invention. In the first embodiment described above, the wiring board 10 is configured to be held by each jig to perform various processes, but it is not limited to this. For example, the back surface (other side) 10b of the wiring board 10 may be attached and protected. Each process is performed with the adhesive tape (not shown) and the wiring board 10 arrange | positioned on the base (not shown) via this protective tape. The base may also have a suction mechanism or a moving mechanism in the horizontal and vertical directions, for example, and may hold the wiring board movably. In addition, in the first embodiment, the semiconductor package to be produced will be described mainly around a BGA (ball grid array) in which bumps are formed on the back surface of the wiring substrate. A land LGA (land grid array) or a QFN (Quad Flat No lead package) is formed on the back surface. Furthermore, in the second embodiment, an example is described in which the semiconductor wafer 11 is so-called flip-chip mounting, and the surface (one side) 11 a of the semiconductor wafer 11 is placed on the support substrate 25. However, when the semiconductor wafer 11 is mounted by wire bonding, the device arrangement area A1 is arranged on the support substrate 25 with the rear surface (other surface) 11b of the semiconductor wafer 11 as the lower side. Further, for example, when the semiconductor device is a CSP, the device corresponding to the device formed on the wafer W (silicon substrate) may be divided so as to have an inclined surface, and the shield layer may be formed until it is grounded.

[0063]

10‧‧‧wiring board

10a‧‧‧ surface

10b‧‧‧ back

11‧‧‧Semiconductor wafer

12‧‧‧Template

16‧‧‧Liquid resin (sealing material)

17‧‧‧sealing resin layer

18‧‧‧sealed substrate

18S, 19S‧‧‧ field (corresponds to the field dividing the planned line)

19‧‧‧Sealed body

25‧‧‧Support substrate

32, 32A‧‧‧Cutter

33‧‧‧ cutting edge

34‧‧‧laser irradiation device

35‧‧‧light collector

40、70‧‧‧Sealed Chip

40a, 70a‧‧‧ above

Below 40b, 70b‧‧‧‧

40c, 70c‧‧‧side

45‧‧‧ conductive shield

50, 80‧‧‧ semiconductor packages

60‧‧‧ redistribution layer

61‧‧‧Wiring

62‧‧‧Insulation film

S1‧‧‧Joint Engineering

S2‧‧‧Sealed substrate production process

S3‧‧‧Fragmentation project

S4‧‧‧Shield layer formation project

S11‧‧‧ Wafer configuration project

S12‧‧‧Construction of sealing body

S13‧‧‧Re-wiring project

S14‧‧‧Fragmentation project

S15‧‧‧Shield layer formation project

BP‧‧‧ bump

S‧‧‧ cut (cutting line)

θ1‧‧‧Tilt angle

[0012] FIG. 1 is a flowchart showing a procedure of a method of manufacturing a semiconductor package according to a first embodiment. FIG. 2 is a cross-sectional view showing a state where a semiconductor wafer is bonded to a wiring substrate. FIG. 3 is a cross-sectional view showing a configuration for supplying a liquid resin for sealing to a wiring substrate on which a semiconductor wafer is mounted. FIG. 4 is a cross-sectional view of a sealing substrate sealed with a resin. FIG. 5 is a cross-sectional view of a sealing substrate having bumps formed on a rear surface of the wiring substrate. FIG. 6 is a cross-sectional view showing an example of a configuration in which the sealing substrate is made small by cutting. FIG. 7 is a cross-sectional view showing a hermetically sealed wafer that has been chipped by cutting. FIG. 8 is a cross-sectional view showing another example of a configuration in which the sealing substrate is made small by cutting. FIG. 9 is a cross-sectional view showing another example of a configuration in which the sealing substrate is made small by cutting. FIG. 10 is a partial cross-sectional view showing a modification example when the sealing substrate is cut. FIG. 11 is a cross-sectional view showing a sealed wafer on which a conductive shielding layer is formed. FIG. 12 is a cross-sectional view showing a configuration of a semiconductor package. 13 is a cross-sectional view showing a modified example of the semiconductor package. FIG. 14 is a cross-sectional view showing another modification of the semiconductor package. 15 is a flowchart showing a procedure of a method of manufacturing a semiconductor package according to the second embodiment. FIG. 16 is a cross-sectional view showing a state where a semiconductor wafer is arranged on a support substrate. 17 is a cross-sectional view of a sealing body sealed with a resin. FIG. 18 is a cross-sectional view showing a state where a rewiring layer and a bump are formed on the semiconductor wafer side of the sealing body. FIG. 19 is a cross-sectional view showing a sealing body provided with a redistribution layer. FIG. 20 is a cross-sectional view showing an example of a configuration in which a sealing body is made small by cutting. FIG. 21 is a cross-sectional view showing a hermetically sealed wafer that has been chipped by cutting. FIG. 22 is a cross-sectional view showing a sealed wafer on which a conductive shielding layer is formed. FIG. 23 is a view showing a film thickness of a conductive shielding layer provided on a test body. FIG. 24 is a diagram showing the relationship between the inclination angle of the side surface of the test body and the film thickness.

Claims (4)

A method for manufacturing a semiconductor package is a method for manufacturing a semiconductor package that is sealed with a sealant, and is characterized by: (1) a bonding process, which is based on a wiring substrate divided by a plurality of predetermined division lines that are crossed;复 A plurality of semiconductor wafers are bonded to a plurality of fields; A sealing substrate manufacturing process is performed by supplying a sealant on the surface side of the wiring substrate to which the plurality of semiconductor wafers are bonded and sealing together to form a sealing substrate; The sealing substrate is cut in a region corresponding to the predetermined division line on the wiring substrate, so that the sealed semiconductor wafer can have an upper surface and a lower surface larger than the upper surface, and has a side wall inclined from the upper surface to the lower surface. And forming a shielding layer, which forms a conductive shielding layer on the upper surface and the side wall of the plurality of sealed semiconductor wafers. A method for manufacturing a semiconductor package, which is a method for manufacturing a semiconductor package sealed by a sealant, and is characterized by: (1) a wafer configuration process, which is divided by a plurality of intersecting predetermined division lines; A semiconductor wafer is provided for each device configuration field on the support substrate; a sealing body production process, which is to seal the semiconductor wafer with a sealant after implementing the wafer configuration process, thereby forming a seal body on the support substrate; Wiring process, after removing the support substrate from the sealing body, forming a redistribution layer and bumps on the semiconductor wafer side of the sealing body; miniaturization process, which follows the predetermined division line on the support substrate The sealing body is cut in a field, and the sealed semiconductor wafer can be chipped in such a manner that the sealed semiconductor wafer can have an upper surface and a lower surface larger than the upper surface and side walls inclined from the upper surface to the lower surface; A conductive shielding layer is formed on the upper surface and the sidewall of the plurality of sealed semiconductor wafers. For example, the method of manufacturing a semiconductor package according to item 1 or 2 of the patent application scope, wherein the chip forming process involves turning a cutting blade having a circular cutting edge while cutting into the sealing substrate or the sealing body to form a chip. For example, the method for manufacturing a semiconductor package according to item 1 or 2 of the patent application scope, wherein the chip forming process is to incline a predetermined angle to the processing direction perpendicular to the laser beam irradiation surface of the sealing substrate or the sealing body. A laser beam is irradiated onto the sealing substrate or the sealing body in a direction orthogonal to the feeding direction, and is formed into a small piece.