TW201814834A - Graphene nanoribbon interconnects and interconnect liners - Google Patents

Abstract

The present invention describes graphite nanoribbon interconnects. Graphite nanoribbon interconnects are manufactured by forming a graphite layer (such as graphene) on a metal feature growth catalyst. The metal feature growth catalyst is selectively removed, leaving graphite nanobelts remaining as interconnects. The graphite nanoribbon interconnect has a thickness of 0.3 nanometers (nm) to 2 nanometers and a height of at least 40 nanometers. Conductive graphite nanoribbon interconnects overcome the need for interconnection pads including conventional combinations. Furthermore, the reduced feature size of the graphite nanoribbon interconnect can have a larger interconnect density and semiconductor device density compared to conventional pads.

Description

Graphene nanoribbon interconnects and interconnection pads

The present invention relates to graphene nanoribbon interconnects and interconnect pads.

In manufacturing integrated circuits, interconnects can be formed on the semiconductor substrate using a copper damascene process. Such a process typically begins with trenches and/or vias being etched into the insulator layer, barrier material deposited in the trenches, and then copper metal deposited on the barrier material to form interconnects. As device sizes continue to decrease, various interconnect features become narrower and tighter, causing many problems.

100‧‧‧Integrated circuit

102‧‧‧device layer

104, 304, 1116‧‧‧ interlayer dielectric (ILD) layers

106‧‧‧Interconnect structure

112‧‧‧Metal features

116、720‧‧‧Graphite barrier layer

120、320‧‧‧First ILD layer

200, 400, 600, 800, 1000, 1200

304, 1300‧‧‧ base ILD layer

308, 712, 1404 ‧‧‧ blanket metal layer

312, 1312, 1412‧‧‧ First metal features

316、916、1416‧‧‧Graphite layer

324、1112‧‧‧Etching stop barrier

328、1316‧‧‧The first interconnection structure

504, 704, 920, 1320 ‧‧‧ second ILD layer

508, 708, 1118‧‧‧ barrier layer

512, 714, 912‧‧‧Second metal features

516、722‧‧‧Second interconnection structure

706‧‧‧Second etching stop barrier

724‧‧‧third layer ILD

904‧‧‧Second blanket metal layer

1104‧‧‧ Cavity

1108‧‧‧ Dielectric material

1120‧‧‧Metal layer

1124‧‧‧Graphene Nanobelt Interconnect

1304‧‧‧Temporary ILD layer

1308‧‧‧Temporary barrier

1318‧‧‧Graphite barrier

1322‧‧‧Air gap

1000‧‧‧computing system

1002‧‧‧Motherboard

1004‧‧‧ processor

1006‧‧‧Communication chip

FIG. 1A shows an exemplary integrated circuit structure including a graphite barrier layer according to an embodiment of the present invention.

FIG. 1B schematically shows a lateral cross-section of an example interconnect and the thickness of the tantalum-based barrier layer relative to the total width of the interconnect.

FIG. 1C schematically illustrates an example interconnection and a lateral cross section of the thickness of the graphite barrier layer relative to the total thickness of the interconnection according to an embodiment of the present invention.

FIG. 2 is an exemplary method of manufacturing an integrated circuit using an interconnect having a graphite barrier layer according to an embodiment of the invention.

3A-3E are a series of cross-sectional side views illustrating a schematic integrated circuit structure of a graphite barrier layer manufactured according to the method shown in FIG. 2 according to an embodiment of the present invention.

4 is a method flow diagram illustrating an exemplary method for manufacturing additional interconnects and metal levels for electrical communication with graphite liner interconnects according to an embodiment of the invention.

5A-5C are a series of schematic integrated circuit structures showing the formation of an additional interconnection layer that is manufactured according to the method shown in FIG. 4 and is electrically connected to a graphite pad interconnection according to an embodiment of the present invention. Cross-sectional side view.

FIG. 6 is a method flow diagram illustrating an example method for manufacturing a portion of graphite pads and an additional interconnection for electrical communication with the graphite pads interconnect at a low level according to an embodiment of the present invention.

7A-7D show a series of additional interconnect layers formed according to an embodiment of the present invention, showing a portion of the graphite liner manufactured according to the method shown in FIG. 6 and electrically communicating with the graphite liner at a low level A cross-sectional side view of the schematic integrated circuit structure.

FIG. 8 is a method flow diagram illustrating an exemplary method for manufacturing a portion of graphite pads and additional interconnections for electrical communication with the graphite pad interconnects at a low level according to an embodiment of the present invention.

9A-9C are a series of schematic diagrams showing the formation of an additional interconnection layer that partially manufactures graphite circuits manufactured according to the method shown in FIG. 8 according to an embodiment of the present invention and electrically communicates with graphite circuits at a low level. Cross-sectional side view of an integrated circuit structure.

FIG. 10 is a method flowchart illustrating an exemplary method for manufacturing graphite nanoribbon interconnects according to an embodiment of the invention.

11A-11D are a series of cross-sectional side views showing the formation of a schematic integrated circuit structure of graphite nanoribbons manufactured according to the method shown in FIG. 10 according to an embodiment of the present invention.

FIG. 12 is a method flow diagram illustrating an example method for manufacturing graphite liner interconnects including air gaps as elements of interlayer dielectric structures according to an embodiment of the present invention.

13A-13E are a series of schematic integrated circuit structures showing the formation of a graphite barrier layer including an air gap as an element of an interlayer dielectric structure manufactured according to the method shown in FIG. 12 according to an embodiment of the present invention Cross-sectional side view.

14A-14D are a series of schematic integrated circuit structures showing the formation of a graphite barrier layer including an air gap as an element of an interlayer dielectric structure manufactured according to the alternative method shown in FIG. 12 according to an embodiment of the invention Cross-sectional side view.

FIG. 15 shows a mobile computing system configured according to an embodiment of the present invention.

It is understood that the drawings are not necessarily drawn to scale or are intended to limit the invention to the specific configuration shown. For example, although some figures generally indicate straight lines, right angles, and smooth surfaces, actual implementations of structures may have imperfect straight lines and right angles, and some features may have surface topography or otherwise be non-smooth, given that the real world uses Processing equipment and technology limitations. In short, the drawings are provided only to illustrate example structures.

[Summary of the Invention] and [Implementation Mode]

A technique for forming an integrated circuit structure including a graphite barrier layer is disclosed. Examples of graphite barrier layers include, but are not limited to, graphene monolayers and groups of 1 to 5 graphene monolayers. In some examples in this book, the terms "graphene" and "graphitic" and "graphite" are used interchangeably for convenience and without loss of breadth. Instead, all these terms refer to allotropes of carbon organized in crystalline monolayers.

These graphite barrier layers help reduce or eliminate the diffusion of metal from one interconnected metal feature to adjacent metal features in the integrated circuit. In some embodiments, the graphite barrier layer may synthesize a crystal carrier at a position between the dielectric and the metal interconnect, for example, by using a previously deposited metal interconnect structure as a growth substrate for graphite materials (eg, Graphene, graphite, or other carbon allotropes, or carbon-containing compounds composed as one or more crystalline monolayers). In this way, according to some embodiments, a uniform and extremely thin graphite barrier layer can be fabricated in situ on the metal portion of the interconnect. A dielectric material is then deposited around the graphene-coated metal interconnect. In some examples, the metal part of the interconnection of the graphite liner is removed, leaving the graphite nanoribbon as the interconnection. As used herein, a graphite nanoribbon is any nanoscale graphite structure or feature that is used as a conductive interconnect feature, with virtually no other conductive block interconnect materials. It should be noted that there may be residues or traces of the previously removed conductive material block interconnect material, but the main conductive interconnect feature material is graphite.

The disclosed technique may provide various advantages over conventional deposition techniques used to form barrier layers (also referred to as "pads") associated with interconnects. For example, the disclosed methods and materials may allow the production of a single layer of graphite (or other suitable thickness) so that it surrounds the metal of the interconnect structure and is substantially conformal to the metal portion of the interconnect. In some examples, the graphite barrier layer has a thickness ranging from 0.3 nanometer (nm) to 2 nanometers. This thickness is smaller than the thickness of a typical diffusion barrier (eg, tantalum nitride) (which ranges from 5 nm to 10 nm thick). A thinner graphite barrier layer effectively improves the electrical conductivity of metal interconnects, because compared to typical interconnects with thicker pads (eg, tantalum-based pads), a relatively large amount of conductive metal can be deposited as an interconnect Connected metal parts, and therefore the area of the metal parts is smaller. Furthermore, the conventional barrier layer is generally a relatively poor conductor compared to the graphite layer (especially graphene). This improved barrier conductivity also improves the overall interconnect conductivity. Ultimately, the interface between the graphite barrier layer and the interconnected metal produces less surface scattering than the interface between the metal and the conventional barrier layer. Compared to conventional pad interconnects, this lower surface scattering feature also tends to increase the electrical conductivity of the interconnect of the present invention. According to the present invention, many configurations and changes will be apparent.

General overview

The barrier material is deposited in a layer between the non-conductive (eg, dielectric) and conductive (eg, copper metal) features of the integrated circuit. The barrier material can prevent the interconnected metal features from diffusing or otherwise migrating into the dielectric material. In some cases, by making the dielectric material between these interconnects more conductive, especially when the distance between these interconnects is small, the metal diffusion from the interconnects may even be located in adjacent interconnects Short circuit between. However, it is difficult to reduce the size of conventional barrier materials deposited using conventional deposition techniques. As a result, as the size of semiconductor devices and their interconnect structures gradually decreases with the development of technology, conventional (and poorly conductive) barrier materials occupy gradually increasing portions of interconnect cross-sectional areas. Because proportionally less metal can be deposited inside the barrier portion of the interconnect, this increases the resistance of the interconnect. In addition, as the size shrinks, the metal deposited within the interconnect is more likely to include voids or other defects, especially for high aspect ratio via interconnect features. As the size of the metal part shrinks, these defects may have a greater negative impact on the conductivity of the interconnect.

It will be understood from this disclosure that replacing conventional barrier materials with graphite barrier layers, and particularly graphene (atomically thin and conductive carbon allotropes) barrier layers, can increase the effective conductivity of the interconnect. This advantage is achieved by reducing the proportion of interconnects occupied by less conductive pads, while increasing the proportion of cross-sectional area of interconnects occupied by more conductive metal cores. The graphite barrier layer also provides an effective diffusion barrier between the dielectric and the metal of the interconnect structure, thus reducing the possibility of short circuits between adjacent conductive structures. However, there are several challenges associated with forming graphite barriers at or below nanometer thickness. For example, transferring graphene or graphite material grown on a separate substrate to an integrated circuit wafer having a morphology (eg, trench) is not trivial or otherwise difficult to achieve. Furthermore, graphite materials are not easily formed on interlayer dielectric materials. This makes graphene deposition using conventional liner deposition techniques challenging in damascene or dual damascene processes.

Therefore, according to an embodiment of the present invention, a technique for forming a graphite barrier layer (or “graphite liner”) for an interconnect structure is provided. In a specific embodiment, the metal portion of the interconnect (referred to herein as a "metal feature") is formed using a subtractive etching process. This metallic feature is then used as a catalyst on which to grow the graphite barrier layer. In another specific embodiment, a damascene process is used to form metal features. Then the metal features are exposed by removing the interlayer dielectric in which the metal is deposited. Therefore, the exposed metal features can then be used as a catalyst for growing a graphite barrier layer thereon. In some embodiments, the subsequently deposited interlayer dielectric is used to form an air gap around the interconnect portion, thus improving the insulation of the dielectric layer (and reducing the capacitive effects associated therewith). In another embodiment, after the graphite barrier layer is grown on the metal features, the metal features are removed. The remaining conductive graphite structure (generally referred to herein as a nanoribbon, due to its nanoscale size) is then used as an interconnect. Note that the reference to the nanobelt does not imply a specific shape. In contrast, nanoribbons can effectively be of any shape, and generally conform to the shape of the interconnected area in its pad or a portion of that shape. For example, the nanobelt can be ring-shaped or box-shaped, or a single wall or part of such a shape.

The disclosed technique of forming a graphite barrier layer can provide various advantages. For example, the disclosed technology may be able to produce graphite barrier layers having a thickness of less than 5 nanometers or less than 2 nanometers, or in the range of thicknesses below nanometers (eg, less than 1, less than 0.75, less than 0.5 nanometers) Thickness, or single layer). In a specific example, the graphite barrier layer is a single layer of graphene. In other examples, the graphite barrier layer is a group of two to five graphene monolayers. Additionally, the graphite barrier layer may be substantially consistent with the metal features of the interconnect, and in several embodiments provide an interface that generates less surface scattering at the metal-graphene interface. Other advantages include higher interconnect conductivity compared to interconnects with conventional barrier layers, increased (lower) capacitance between interconnects, smaller minimum size that can match continuity with smaller feature sizes Technology generation and higher device density within integrated circuits. According to the present invention, many variations and configurations will be apparent.

Graphite barrier

FIG. 1A shows an example of an interconnected integrated circuit 100 having a graphite barrier layer (graphene) according to an embodiment of the present invention. It should be noted that FIG. 1A (and FIGS. 1B and 1C) are simplified for illustrative purposes, and the actual interconnect structure generally includes structures corresponding to both conductive lines and vias.

As can be seen, the integrated circuit 100 includes a semiconductor device layer 102 (omitted from the following figures for the sake of clear description), a selective base interlayer dielectric (ILD) layer 104, and an interconnect structure 106, the interconnect structure 106 Including a first ILD layer 120 having a plurality of metal features 112 therein, each metal feature 112 has a graphite barrier layer 116. Although only one interconnect structure 106 is shown in this example, other embodiments may include any number of such structures in a stacked configuration (eg, metal layers M0-M9). In addition, other embodiments may not include the selective base ILD layer 104, such as in the case where the graphene-containing interconnect structure 106 is directly provided on the device layer 102, and functional integrated circuits are provided in this manner.

Examples of semiconductor devices that can be formed in the device layer 102 include, but are not limited to, planar field effect transistors (FETs) and non-planar FETs (eg, finned FETs or nanowire FETs), capacitors (eg, embedded DRAM (eDRAM) capacitor), DRAM cell and SRAM cell, etc. As will be understood, the actual device implemented in the device layer 102 will depend on the target application and function of the integrated circuit 100, and the invention is not intended to be limited to any particular application or functional circuit. Conversely, the technology provided herein can be used with any number of device layer 102 configurations. These devices, which are usually fabricated on a semiconductor substrate (eg, a single crystal silicon wafer) and/or within the semiconductor substrate, are in electrical communication with at least one interconnect 106. The interconnection structure 106 connects the semiconductor device of the device layer 102 to other semiconductor devices elsewhere in the integrated circuit or to the upper or lower layer of the integrated circuit 100 through a network of selectively connected vias and conductive lines s contact. For successive layers of each interconnect structure 106, generally a greater number of semiconductor devices 102 can be connected together. Finally, the semiconductor device is placed in electrical communication with the input and/or output through a series of interconnect structures 106 so that commands and/or data can be received at and/or sent from the integrated circuit 100. In other figures herein, the semiconductor device layer 102 is not shown.

The selective base ILD layer 104 (in the example shown) is conformally disposed above the semiconductor device layer 102 to protect the semiconductor device layer 102 from accidental electrical contact with other conductive features within the integrated circuit 100 and Subsequent processing for manufacturing integrated circuit 100. In addition, the base ILD layer 104 may also serve as a surface in which the interconnect structure 106 is formed and one or more interconnect structures 106 are selectively connected to the semiconductor device layer 102. When included, the ILD 104 may be, for example, silicon dioxide or silicon nitride or some other suitable insulating material or passivation material. The thickness of the layer can be set as needed to provide the required insulation and/or protection to the lower device layer 102.

In the example embodiment shown, the side surface of each metal feature 112 included in the interconnect structure 106 is in contact with the graphite barrier layer 116. Together, the metal features 112 and the graphite barrier layer 116 form conductive interconnect features. As described above, the barrier layer is generally used to prevent the diffusion of metal from the metal feature 112 into the adjacent insulator material, thereby preventing short circuits in the integrated circuit 100 and/or otherwise preventing the interconnection and/or integrated body as a whole The electrical performance of the circuit 100 is reduced. Although traditional barrier layers are generally based on tantalum, the barriers described herein include graphene materials, such as graphene, which can be thinner and/or more conductive.

FIGS. 1B and 1C schematically show the lateral cross-sections of the interconnect features, and in the example show the relative thickness of the conventional and graphite barrier layer relative to the total width of the interconnect features. FIG. 1B schematically shows the relative thickness of the tantalum-based barrier layer relative to the overall interconnect feature thickness. Figure 1C schematically shows the thickness of the graphite barrier layer relative to the overall interconnect feature thickness. Upon reviewing these figures (and as described herein), it is apparent that the tantalum-based barrier layer is thicker than the graphite barrier layer and occupies a larger cross-sectional area of the interconnect feature. For example, some interconnect features may have a total width X _{1 of} 25 nanometers to 30 nanometers (and in some specific examples, the target total width X ₁ is 27 nanometers). As shown in FIG. 1B, a conventional (eg, tantalum-based) barrier layer may have a pad thickness Y ₁ of 5 nm to 10 nm, thus occupying the overall interconnect feature width of 10 nm to 20 nm. This is compared to a graphite barrier layer having a pad thickness Y _{2 of,} for example, 0.3 nm to 1.5 nm (as shown in FIG. 1C), and therefore only occupies the overall interconnect thickness of 0.6 nm to 3 nm. Such a considerable amount of metal in graphene liner interconnections can partially improve the conductivity of graphene liner interconnections and improve the efficiency of integrated circuit devices.

Method and architecture

FIG. 2 shows a method 200 for manufacturing an integrated circuit interconnect including a graphite barrier layer according to an embodiment of the present invention. The narrative of method 200 is accompanied by a parallel narrative corresponding to the rough cross-section of the example interconnect structure. These cross-sections are depicted in Figures 3A to 3E.

As can be seen in this example solution, the method 200 includes forming 204 a base ILD layer 304 on, for example, a semiconductor substrate or device layer or other ILD layer. The embodiments described in the context of FIGS. 2 and 3A-3E assume the formation of the base ILD layer 304 first 204, although other embodiments described below do not require the base ILD layer to be formed first (or exactly as previously explained with respect to FIG. 1A ). In addition, it will be understood that the interconnection examples described here are directly or indirectly connected to the semiconductor device and the contacts, regardless of whether the connection is shown in the figure. Devices that can be connected can be passive (eg, capacitors, inductors, resistors) or active (eg, transistors, diodes, amplifiers, memory cells).

In an example embodiment, the base ILD layer 304 insulates the underlying device layer, and may further include one or more interconnect features through the insulating material to electrically couple the device of the device layer to the upper interconnect structure and /Or contact. Exemplary insulator materials that can be used for the base ILD layer 304 include, for example, nitride (eg, Si ₃ N ₄ ), oxide (eg, SiO ₂ , Al ₂ O ₃ ), oxynitride (eg, SiO _x N _y ) , Carbide (for example, SiC), carbon oxide, polymer, silane, siloxane or other suitable insulator material. In some embodiments, depending on the application, the base ILD layer 304 is implemented with an ultra-low-k insulator material, a low-k dielectric material, or a high-k dielectric material. Example low-k and ultra-low-k dielectric materials include, porous silicon dioxide, carbon-doped oxide (CDO), organic polymers such as perfluorinated cyclobutane or polytetrafluoroethylene, fluorosilicate glass ( FSG) and organosilicates such as hemisiloxane, siloxane or organosilicate glass. Examples of high-k dielectric materials include, for example, hafnium oxide, hafnium oxide silicon, lanthanum oxide, aluminum lanthanum oxide, zirconia, zirconia silicon, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide , Yttrium oxide, aluminum oxide, lead scandium tantalum oxide and lead zinc niobate.

The technique used to form 204 the base ILD layer 304 can be any wide range of suitable deposition techniques, including but not necessarily limited to: physical vapor deposition (PVD); chemical vapor deposition (CVD); spin coating/spin coating Deposition (SOD); and/or any combination mentioned above. Other suitable configurations, materials, deposition techniques, and/or thicknesses for the base ILD layer 304 will depend on the given application and will be apparent with reference to the present disclosure.

Although some of the embodiments described herein may use damascene processes (which usually refer to both "single damascene" and "dual damascene" technologies) to etch trenches in the ILD layer, which are then filled with metal, but the method 200 minus the metal etching process is used instead. Therefore, as further shown in FIG. 2 and with further reference to FIG. 3A, the method 200 continues by forming 208 a blanket metal layer 308 on the base ILD layer 304. This blanket metal layer 308 will then be subtractively etched to form metal features. These metallic features can be used as catalysts for growing graphene layers thereon, as described in more detail below.

Exemplary deposition techniques for forming 208 the blanket metal layer 308 include, but are not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). The thickness (α) of the blanket metal layer may be, for example, greater than the final size of the metal feature on which the graphene barrier layer will be deposited, because the blanket metal layer 308 can withstand various etchings that can reduce the thickness. In an example, the size α may be from 10 nm to 500 nm, from 10 nm to 100 nm, from 10 nm to 50 nm, and from 40 nm to 60 nm. As will be understood, the scope of these examples is merely illustrative, as α can be based on the type of interconnect being fabricated (eg, vias or conductive lines) and other factors, such as the metal level within the fabricated integrated circuit, Technology size constraints and other factors are quite different.

Exemplary metals used to form 208 the blanket metal layer 308 and can be subtractively etched and used as a graphene growth catalyst in subsequent stages of the method 200 include, for example, copper, aluminum, tungsten, and tantalum. Practical considerations can often require the least expensive metal acceptable for use.

After forming 208, blanket metal layer 308 is etched 212 to form metal features 312 from blanket metal layer 308, as shown in FIG. 3B. That is, the material is selectively removed from the blanket metal layer 308. The portion of the blanket metal layer 308 remaining after etching is generally referred to herein as a metal feature. In the context of FIGS. 2 and 3A-3E, the metal features deposited above the base ILD layer 304 and within the first ILD layer are described as the first metal features 312. The first metal features 312 are separated by trenches formed by the removal of other portions of the blanket metal layer 308. In some examples, these first metal features 312 will form part of the interconnection between the device and another metal layer or metal contact, or between metal layers, or between metal contacts.

When formed, each first metal feature 312 includes an exposed top surface and one or more exposed side surfaces, as shown in FIG. 3B. As will be understood, the bottom surface (relative to the top surface) of each first metal feature 312 remains in contact with the ILD layer 304 and/or the conductive interconnect features formed within the layer 304, where the conductive interconnect features effectively allow Appropriate electrical connection to the underlying device layer. In the embodiment shown in FIGS. 3B-3E, the bottom surface of the first metal feature 312 is not made of liner, graphene, or other means.

In some embodiments, subtracting the etch 212 includes selectively applying a mask to the blanket metal layer 308, thus protecting portions of the blanket metal layer 308 corresponding to the first metal feature 312 from being etched. Once the mask is applied, a directional (anisotropic) etch 212 can be used to remove portions of the blanket metal layer 308 that are not protected by the mask. Anisotropic etching is used to maintain the feature width dimension β (represented in FIG. 3B) of the first metal feature 312 from the bottom surface to the top surface approximately uniform (e.g., 5 nm or less, or 2 nm or less, Or 1 nanometer or less). Anisotropic etching includes, for example, dry etching, such as reactive ion etching (RIE) using ozone, ionized argon, and the like. Other etching processes (eg, wet or isotropic) can also be used, which can result in more tapered sidewalls if a given circuit is acceptable. In a more general sense, the sidewalls and tops with interconnecting features of graphite cushions thereon can have any shape or contour (eg, s-shape or other wavy shapes, to be wider at the lower part and tapered at the top , Orthogonal on one side and tapered, convex top, concave top, concave side wall on the other side, to name a few examples). The shape of the features can vary widely, and any such shape can be conformally coated or otherwise have graphite pads disposed thereon.

The size β of the first metal feature 312 may include, for example but not limited to, from 10 nm to 50 nm, from 5 nm to 100 nm, from 20 nm to 30 nm, and from 50 nm to 100 nm Scope. The feature height dimension χ of the first metal feature 312 may include, but is not limited to the range indicated above as the dimension α or slightly smaller. Exemplary values of the size χ include but are not limited to the range from 10 nm to 100 nm, from 10 nm to 50 nm, from 40 nm to 60 nm, and from 50 nm to 100 nm. Similar to the size α, the sizes β and χ are one or more types of interconnect types being manufactured, the metal levels are fabricated within the integrated circuit, the design rules of the technology, and the ones used to form the first metal features 312 Etching and so on.

As mentioned above, the metal used for interconnects (eg, Cu, W, Ta, etc.) can diffuse through the ILD material, thus potentially shorting the circuits together and impairing the overall function of the integrated circuit. To prevent this diffusion, barrier layers are typically used to encapsulate (whole or part) interconnected metal features. In damascene processes, where trenches are etched into the ILD layer and then filled with metal, pads are usually deposited before depositing metal features. As shown diagrammatically in FIG. 1B and the above description, conventional liners (usually tantalum or tantalum nitride) occupy one-third or more of the cross-sectional area of the trench, leaving it deposited for a given interconnect Characteristic metal narrow channel. This narrow channel may be difficult to fill uniformly with metal, thus further reducing the electrical performance of the interconnect.

To overcome this and other challenges, a graphite layer 316 (such as graphene) is conformally formed 216 on the exposed top or side surface of the first metal feature 312, as shown in FIG. 3C. In this context, conformal means that the graphene layer is set in a relatively uniform manner (negligible changes within +/- 0.2 nm to 1 nm for the desired level of performance) Above the surface, including any underlying features. As shown, graphene is not deposited on the bottom surface of the first metal feature 312 in this embodiment because the bottom surface is in contact with the substrate ILD 304 (or more likely some potential conductive features of the circuit). The first metal feature 312 acts as a catalyst to promote the deposition of graphene. This is beneficial because graphene and other graphite materials may be difficult to deposit on surfaces composed of materials commonly used in ILD.

In some embodiments, the thickness dimension ε of the graphite layer 316 may range from about 0.3 nm to about 1.5 nm (within normal measurement accuracy and precision limits), which corresponds to 1 graphene single layer to The range of about 5 graphene monolayers. The overall height dimension Φ shown in FIG. 3C is approximately the sum of χ and ε. The benefits of the graphene barrier layer include reduced resistance of the interconnect (the conductive path through the interconnect) and increased short circuit tolerance (between conductive features) and other benefits shown herein. In an embodiment, the aspect ratio of the height Φ and the thickness ε of the graphite layer may be from 26:1 to 133:1, from 40:1 to 200:1, or even higher than 200:1.

Exemplary methods of forming 216 graphene layer 316 on first metal feature 312 (and any other similar metal features as will be understood) include the use of hydrocarbon precursors (such as hexane, methane, ethylene, acetylene, etc.) which are in the plasma Or thermally enhanced chemical vapor deposition process decomposition. In one example, a gas source of carbon (eg, methane) is mixed with hydrogen, and then thermally decomposed by heating the mixed gas between 800°C and 950°C. Pressure enhanced chemical vapor deposition can also be used, which reduces the deposition temperature of the carbon decomposition gas source to between 700°C and 850°C compared to the above method. The copper metal feature is then exposed to the heated gas mixture at a pressure between 0.5 Torr and 50 Torr (for low pressure CVD deposition) or up to atmospheric pressure and at a flow rate of 0.5 standard cubic centimeters per minute (sccm) to 10 sccm. For cases where metal features may be oxidized before graphene deposition, the substrate may be reduced by heating (eg, up to 1000°C for copper) and exposing the metal to hydrogen for between 30 minutes and 60 minutes. This is an example of a set of conditions for depositing graphene on copper metal features. It should be understood that other combinations of gas, thermal profile, pressure, flow rate, and other parameters can be used to deposit graphene on a given metal feature. Additional examples can be found in "A Review of Chemical Vapor Deposition of Graphene on Copper" by Mattevi, which is published in Journal of Materials Chemistry, Volume 21, pages 3324-3334 (2011).

As shown in FIG. 3D, the first ILD material layer 320 is deposited 220 between its first metal features 312 within its corresponding graphene layer 316, and then planarized. The method used to deposit 220 the first ILD layer 320 may be, for example, any method that has been described in the context of FIG. 3A. The method for depositing 220 the first ILD layer 320 also includes techniques for filling high aspect ratio trenches (eg, having a height to width aspect ratio of 2:1 or higher), like those shown in FIG. 3C It is shown between the graphene 316 coated with the first metal feature 312. These subsequent techniques include spin coating/spin coating deposition (SOD) of applying a reaction (optionally at the time the heat is applied) to form one or more chemical precursors of the ILD. Once the first ILD layer 320 has been deposited 220, it is planarized and/or milled 220 to form a uniform flat surface suitable for subsequent manufacturing and processing. The planarization and/or polishing techniques include a chemical mechanical planarization (CMP) process or other suitable polishing/planarization processes as needed so that another layer can be formed on top of the layer already shown in FIG. 3D. This forms a first interconnect structure 328 that includes several conductive interconnect features. The conductive interconnect features as used herein are collectively referred to as the first metal feature 312 and its corresponding graphene barrier layer 316.

As shown in the example embodiment of FIG. 3D, a portion of the graphene layer 316 corresponding to the top surface of the first metal feature 312 is removed. Although not wishing to be bound by theory, it has been observed that the electrical sheet resistance of graphene is extremely low in a direction parallel to the plane of the monolayer carbon atom structure (ie, parallel to the main surface of the graphene sheet). The sheet resistance of the graphene sheet is higher in the direction perpendicular to the plane of the single-layer carbon atom structure. During the deposition of the graphite layer 316, the monolayer is structured parallel to the surface of the metal features 312 formed by the monolayer. Therefore, a single layer of carbon atoms on the measurement surface of the first metal feature 312 is parallel to those side surfaces. This provides low sheet resistance in a direction parallel to the side surface of the first metal feature 312. For similar reasons, the single layer of graphene on the top surface of the first metal feature 312 is parallel to the top surface of the first metal feature 312. The graphene monolayer on top of the first metal feature 312 provides a higher sheet resistance than the graphene monolayer on the side surface of the first metal feature 312 because the monolayer on the top surface is perpendicular to the possible pass The electron flow orientation of the first metal feature. For this reason, in some embodiments, one or more graphene layers on the top surface of the first metal feature 312 are removed, thereby exposing the low sheet resistance graphene layer on the side of the first metal feature 312 to be subsequently formed Second interconnection.

In some examples, an etch stop barrier 324 is deposited 224 on top of the planarized 220 top surface of the first ILD layer 320, the graphene barrier layer 316, and the first metal feature 312. An example embodiment of this configuration is shown in Figure 3E. The etch stop barrier 324 is generally a material that is not affected by the etch used to etch the continuous ILD layer or has a very slow etch rate compared to the ILD. Therefore, the etch stop barrier protects the features below from the processing performed on the features above the etch stop barrier. Examples of the etch stop barrier 324 include aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), silicon nitride, and the like. The etch stop barrier 324 is deposited and planarized using any deposition and planarization techniques previously described in the context of the base ILD layer 304 and ILD 320.

In another example embodiment, the interconnect structure fabricated according to the damascene process and having a conventional pad is placed in electrical configuration with the first interconnect structure 328 of the interconnect feature configuration of the graphene pad manufactured according to the method 200 Sexual communication. According to one such exemplary embodiment, FIG. 4 shows an example method 400 for manufacturing such a structure, and FIGS. 5A-5C schematically show a cross-section of an example structure at various stages of manufacturing according to the method 400. It may be appropriate to mix graphene-based interconnect structures (such as 328) and conventional interconnect structures on the same die or integrated circuit, for example, where relatively crowded or dense interconnect structures or layers are provided herein In the case of a graphene-based interconnect structure implementation, and the next interconnect structure or layer stacked thereon is implemented at a relatively low density with conventional interconnect features. In other embodiments, all interconnect structures in a given circuit or die may be implemented with graphene-based interconnect features. Many such other embodiments and variations according to the invention will be apparent.

It should be understood that in some examples, a liner (whether based on a tantalum liner or a graphite liner) may be disposed between the blanket metal layer 308 and the base ILD layer 304. Although the selective pad is omitted in the examples shown in FIGS. 3A-3E, when the method 200 is performed, an embodiment including such an optional pad will be included in the base ILD layer 304 and the first interconnect structure 328 Part of the liner.

As shown in FIG. 4, and referring to FIGS. 5A-5C at the same time, the method 400 begins by performing 402 the method 200. Therefore, the previous discussion and various permutations and embodiments provided with reference to FIGS. 2 and 3 are equally applicable here. The method 400 continues to deposit 404 a second ILD layer 504 on the etch stop barrier 324 of the structure shown in FIG. 3E. Next, according to the damascene manufacturing method, the trench (shown in FIG. 5B) is etched 408 into the second ILD layer 504 and passes through the etch stop barrier 324. The etch 404 through the etch stop barrier 324 exposes the top surface of the interconnect features of the first interconnect structure 328. Techniques for etching 404 the second ILD layer and etch stop barrier 324 include dry and/or wet etching (such as RIE, potassium hydroxide (KOH), and/or hydrofluoric acid (HF)) formulated to remove the ILD layer The insulator material of 504 and the material used to form the etch stop barrier 324 are removed. As will be understood, several suitable etching schemes are feasible. At 412 and 416, respectively, a barrier layer 508 (such as the conventional tantalum-based barrier layer described above) and a second metal feature 512 (shown in FIG. 5C) are then formed in the trench. As can be seen in this example scenario, the second metal feature 512 shown includes a via portion and a line portion. The barrier layer 508 and the second metal feature 512 collectively form the conductive interconnect feature of the second interconnect structure 516 that directly contacts the conductive interconnect feature of the first interconnect structure 328.

According to an embodiment, another example method 600 for manufacturing an interconnect structure appears in FIG. 6. This method combines the use of both tantalum-based pads and graphite pads, each for a different part of the second interconnect structure. 7A-7D show schematic cross-sections of structures in various stages of manufacturing according to embodiments. As can be seen, examples of devices manufactured by the example method 600 include a first portion with a conventional barrier layer (corresponding to a through hole portion) and a second portion with a graphite liner (corresponding to a metal connected to the through hole) The second interconnect structure configured by the conductive interconnect feature of the line).

The example method 600 includes first performing 602 the method 200 (or equivalent method) to produce the structure shown schematically in FIG. 3E. Therefore, the previous discussion and various permutations and embodiments provided with reference to FIGS. 2 and 3 apply here as well. A second ILD layer 704 (shown in FIG. 7A) is formed 604 on top of the etch stop barrier 324. The second etch stop barrier 706 may be formed on the second ILD layer 704. The second ILD layer 704 and the second etch stop barrier 706 are etched 608 to form an interconnect trench. This interconnect trench is scaled and configured to form vias in a single damascene process (relative to the vias and metal lines typically formed in dual damascene process trenches as shown in FIG. 5B). This etch 608 also exposes the top surface of the conductive interconnect features underneath the first interconnect structure 328 by etching through the etch stop barrier 324. A barrier layer 708 (eg, a tantalum-based barrier layer) is conformally deposited 612 into the trench. The blanket metal layer 712 is then deposited 616 in the via trench and above the second ILD layer 704 using any of the techniques described above in the context of FIGS. 2 and 3A.

As described above in the context of Figures 2 and 3B, the blanket metal layer is etched 620. An etching 620 is performed to form a line portion of the interconnect feature from the blanket metal layer 712 integrated with the via portion of the interconnect feature. The metal surface exposed by etching 620 also serves as a catalyst for forming 624 a graphite barrier layer 720 thereon. The through hole portion and the pad portion form the second metal feature 714. The second metal features 714 and the graphite barrier layer 720 and the barrier layer 708 collectively form the conductive interconnect features of the second interconnect structure 722 directly in contact with the conductive interconnect features of the first interconnect structure 328. A third layer of ILD 724 is deposited 628 to fill the trench between the etched metal features. A diagram of the final structure of the example is presented in FIG. 7D.

Similar to method 600, some or all elements of method 200 may be repeated to create an interconnect stack. An example method 800 for repeating some elements to produce a stacked via configuration including via interconnection through two or more ILD layers is shown in FIG. 8 while referring to corresponding cross-sectional schematic diagrams Figures 9A-9C. Method 800 includes performing 804 method 200. Therefore, the previous discussion and various permutations and embodiments provided with reference to FIGS. 2 and 3 apply here as well. The method 800 continues to expose 808 the top of the conductive interconnect features included in the first interconnect structure 328 by removing a portion of the etch stop barrier 324. A second blanket metal layer 904 is formed 812 such that the metal contacts and integrates with the top surface of the exposed conductive interconnect features of the first interconnect structure 328. The second blanket metal layer 904 is then etched 816 to produce a second metal feature 912, in this case a via integrated with the underlying first metal feature 312. Any suitable metal etching scheme can be used. Next, using a process as previously described, a graphite layer 916 is formed 820 on the top and side surfaces of the second metal feature 912. As will be understood, the second metal feature 912 and its corresponding graphite layer 916 together with the underlying first metal feature 312 and its corresponding graphite layer 316 collectively form a stacked via 918. Note that in this example embodiment, the graphite layer 916 is shown fully aligned with the graphite layer 316. In other embodiments, note that the two graphite layers 916 and 316 may be at least somewhat offset from each other to provide a step or cone when transitioning from one layer to another. A second ILD layer 920 is formed at 820 around the second interconnect 918, which can then be planarized. A second etch stop barrier 924 is deposited on the planarized surface of the second ILD layer 920. The process can then be selectively repeated to create additional interconnects in subsequent levels of the integrated device. These interconnections may be another through hole portion or a line portion.

Graphite Nanobelt Interconnect Architecture

Another example method 1000 (shown in FIG. 10) describes the manufacture of graphite nanoribbons (nano-grade graphite interconnect features) that can be used as interconnects without corresponding metal features. In contrast, the method 1000 uses only the first metal feature 312 as a catalyst for forming the graphite layer. After forming the graphite layer, the metal is removed and replaced with a dielectric material (whole or part). Example diagrams corresponding to some stages of method 1000 are shown in FIGS. 11A-11D. The benefits of these embodiments include those indicated above, and also include reducing the size of interconnects and correspondingly increasing the density of interconnects per unit area. For example, according to some embodiments, graphene nanoribbon interconnects have a cross-sectional width from 0.3 nanometers to 2 nanometers thick, while the cross-sectional width of conventional interconnections far exceeds 5 nanometers, such as greater than 10 nanometers, or From 20nm to 30nm. Therefore, a smaller interconnect size can be used to support a greater number of circuits and more closely spaced circuits than can be achieved using conventional interconnects.

The example method 1000 includes performing 1002 the example method 200 (or equal method) to produce the structure shown schematically in FIG. 3D. Therefore, the previous discussion and various permutations and embodiments provided with reference to FIGS. 2 and 3 apply here as well. As shown in FIG. 11A (and equivalent to FIG. 3D), the top surface of the conductive interconnect feature of the first interconnect structure 328 is exposed. As shown in FIG. 11B, the first metal feature 312 is then removed 1004 to form a cavity 1104 defined by the graphite barrier layer 316 and the underlying ILD layer 304. The first metal features 312 can be removed, for example, using directional etching, such as those above to selectively remove metal features without removing one or more of the ILD 320 materials in the context of FIGS. 2 and 3B. Alternatively, or in addition, a mask may be used to protect the ILD 320 and a portion of the graphene barrier layer 316 from metal etching.

As shown in FIG. 11C, a dielectric material 1108 such as an ILD (which may be the same as or different from one or both of those used for the base ILD 304, the first ILD layer 320) is then selectively formed 1008 in the air Cavity 1104. The techniques used to form the dielectric material 1108 in the cavity 1104 include any of the ILD deposition techniques presented above. These techniques include, but are not limited to those used for deposition into higher aspect ratio cavities, such as spin coating/spin coating deposition (SOD). In some embodiments, other deposition techniques that are not suitable for deposition into higher aspect ratio cavities may be used. This is because the dielectric material 1108 does not necessarily need to be free of defects, and may include voids or other defects that do not impair the function of the graphite nanoribbons as interconnects. In still other embodiments, the cavity 1104 may remain free of ILD, thereby creating an air gap between the graphite layers (the advantages are described below).

When the graphene barrier layer 316 is placed in electrical communication with a semiconductor device or contact (not shown) and/or another electrically conductive interconnect (eg, another metal level within an integrated circuit), each A graphene barrier layer 316 can be used as a graphite nanoribbon interconnect. The following describes the manufacture and connection to another electrical interconnect, as shown in FIG. 11D.

The exposed top surfaces of the dielectric material 1108 and the graphene barrier layer 316 are planarized 1012. An etch stop barrier 1112 is deposited 1016 on this planarized surface. An ILD layer 1116 is deposited 1020 on the etch stop barrier 1112. Both the etch stop barrier 1112 and the ILD layer 1116 can be deposited according to any suitable deposition technique, such as those described above.

According to damascene processing techniques, 1024 trenches are etched in the ILD layer 1116, so that the etch stop barrier 1112 is also partially removed to expose the top surface of the underlying graphite nanoribbon interconnect features (other embodiments provided herein) Used as an interconnection pad). A barrier layer 1118 (eg, aluminum oxide, zirconia, or silicon nitride) and a metal layer 1120 are deposited 1028 in the trench and above the ILD layer 1116. A portion of the metal layer 1120 in the trench directly contacts the graphene nanoribbons, thus forming graphene (or more general graphite) nanoribbon interconnects 1124. This structure is shown in FIG. 11D.

As shown in FIG. 11D, it is a graphite layer previously provided on the side surface of the first metal feature 312 instead of the top surface, which is used as a graphene nanoribbon interconnect. That is, as explained above in the context of FIG. 3D, the graphene layer (eg, one or more monolayers) shown in FIG. 11D is oriented parallel to the side surface. This uses a single layer of graphene with a lower sheet resistance parallel to the direction of current flow as the interconnect. However, in another embodiment not shown, some or all of the graphene layer 316 corresponding to the top surface of the first metal feature may be maintained to increase the area for making contact with another interconnect. This can be achieved by, for example, adjusting the size of the protective mask or otherwise using selectively applied etching to avoid removing a portion of the top surface graphene layer when removing (eg, etching or grinding) other portions of the structure shown .

In other embodiments, it should be understood that the dielectric material 1108 and/or the first ILD layer 320 may be configured to include an "air gap." The manufacture and benefits of air gaps are described in the context of Figures 12 and 13A-13E below. The application of the technology described below to the embodiments shown and described in the context of FIGS. 8 and 9A-9C will be apparent.

Although the damascene process for connecting the metal layer 1120 to the graphene nanoribbon interconnect 1124 is described in the description of FIG. 11D above, the metal layer 1120 can also be manufactured through an etching process, as described in the context of FIG. 2 above. That is, the top surface of the graphene nanoribbon interconnect 1123 is exposed, and a blanket metal layer is deposited on the exposed top surface of the etch stop barrier 1112 and the graphene nanoribbon interconnect. The metal features are then etched from the blanket metal layer, which can then be lined with a tantalum liner or graphite liner (as described herein). In any case, the resulting structure can be encapsulated in ILD material.

It should be understood that although the aforementioned methods are described independently, the combined integrated circuit device having one or more structures shown in FIGS. 3E, 5C, 7D, 9C, 11D, 13E, and 14D can be combined to produce. For example, the graphite nanoribbon interconnect 1124 may be combined with other embodiments described above, such that a tantalum-based barrier layer is disposed between the graphite nanoribbon 1124 and the second interconnect, and the graphite barrier layer is disposed at the graphite nanometer The metal feature between the strip 1124 and the second interconnect, or the second interconnect, is in direct contact with the graphite nanoribbon interconnect 1124. Each of these can in turn be manufactured to include an air gap within one or more insulator layers (described in more detail below). In addition, the foregoing various embodiments may be manufactured to include a graphite barrier layer on the side surface of the second interconnected metal feature. Various other combinations of the embodiments described herein are also possible.

Graphite barrier with air gap dielectric

Yet another embodiment of the present invention can be manufactured to include an air gap. The air gap is the volume within the dielectric layer, and is defined by the dielectric layer free of dielectric material. In addition to the improved conductivity and capacitance of the graphite barriers already discussed above, the benefits of including an air gap in the dielectric layer include reducing the capacitance of the integrated circuit.

An example method 1200 for manufacturing an embodiment including an air gap is shown in FIG. 13A-13E and 14A-14D are also indicated in the description of FIG. 12 below.

As described above in the context of FIGS. 2 and 3A, method 1200 includes forming 1204 a base ILD layer 1300. Recall that the base ILD layer 1300 is selective, and if included, may further include conductive features to facilitate the desired electrical connection with any given interconnect layer or structure. Then one of two techniques is used to form 1208 the first metal feature on the base ILD layer. One technique is the damascene process, and the other technique is the etching process described in the context of FIG. 2.

As shown in FIG. 13A, the formation 1208 of the first metal feature using the damascene process begins by forming 1212 a temporary ILD layer 1304 on the base ILD layer 1300. Next, 1216 trenches are etched in the temporary ILD layer 1304. As shown in FIG. 13B, a temporary barrier layer 1308 is formed 1220 within a trench such as a tantalum-based barrier. This is followed by the formation 1222 of the metal 1312 within the portion of the trench not occupied by the temporary liner 1308, and the exposed surface of the planarization metal, the temporary liner, and the temporary ILD layer 1304. As shown in FIG. 13C, a selective etch (eg, an etch consisting of removing the temporary ILD 1304 at a significantly faster rate than other exposed materials) is then used to remove 1224 the temporary ILD layer 1304, such as ozone or ionization Argon RIE. Examples of the temporary ILD layer 1304 include the composition described above for other ILDs. Although FIGS. 13B to 13E show the complete removal of the temporary ILD layer 1304, this is not necessarily the case. In some examples, for example, a portion of the temporary ILD layer 1304 may remain on the base ILD 1300 until approximately 1/3 of the height of the metal 1312. However, for ease of explanation, the drawings and description assume the temporary removal of the ILD layer 1304.

Regardless, the removal of some or all of the temporary ILD layer 1304 exposes some or all of the first metal features 1312. As a result of the damascene process previously described, which deposits a temporary liner on the exposed surface of the trench before metal deposition, the first metal feature 1312 includes the liner 1308 disposed between the metal 1312 and the substrate ILD 1300 Part, as shown in Figure 13C. It should be understood that a process similar to this can be applied to any of the embodiments described herein so that the first or second interconnect structure (eg, 328, 512, 722) can be included between the interconnect structure and the underlying layer Gaskets, including tantalum-based gaskets manufactured as part of the dual damascene process.

As shown in FIG. 13D, a graphite barrier (eg, graphene) 1318 conformally forms 1228 over the exposed first metal feature 1312 and the remaining temporary liner 1308, which together form the first interconnect structure 1316. Techniques for forming 1228 graphene on metal catalysts (such as first metal features 1312) have been described previously.

As shown in FIG. 13E, a second ILD layer 1320 is formed over the first interconnect 1316 using any suitable deposition process, such as, for example, CVD, PCVD, or PECVD. The formation of the second ILD layer 1320 using vapor deposition techniques (as opposed to the technique of SOD including flowable liquid precursors) facilitates the formation of gas within the second ILD layer 1320 between the first interconnect structures 1316 Aperture 1322. An air gap 1322 is established because the gas-phase precursor molecules nucleate on the surface of the first interconnect 1316 closest to the source of the precursor (ie, the top surface of the first interconnect 1316) and the side surface near the top surface. Once nucleated, the second ILD layer 1320 grows faster than those surfaces of the second ILD material crystallites that have not yet nucleated. Therefore, the second ILD layer 1320 eventually forms a continuous barrier near the top surface of the one or more first interconnects 1316, thereby preventing further deposition between the first interconnects. This results in the gap or air gap 1322 shown in FIG. 13E. The size of the air gap may vary, but in some cases the widest part is in the range of about 1 to 5 nanometers, although larger air gaps can also be implemented. In a more general sense, air gaps can often be discerned from unintentional gaps that are relatively small (eg, less than 1 nanometer). One benefit of including an air gap 1322 in the second ILD layer 1320 includes reduced capacitance between adjacent first interconnects.

FIG. 12 also shows an alternative technique for forming the first metal feature using an etching process (also described in the context of FIG. 2). Cross-sectional views illustrating some stages of this alternative technique appear in Figures 14A-14D. As described above in the context of FIG. 2, a blanket metal layer 1404 is formed 1213 on the base ILD layer 1300. The first metal feature 1412 is etched 1217 from the blanket metal layer 1404. The formation 1213 and the subsequent etching 1217 are collectively referred to as an etching process.

As also described above in the context of FIG. 2, a graphite layer 1416 is formed 1228 on the top and side surfaces of the first metal feature. Unlike techniques using a damascene process, no barrier or intermediate layer is provided between the first metal feature 1412 and the base ILD layer 1300. In contrast, the first metal feature formed during the etching process is similar to the structure shown in FIG. 3D. Method 1200 continues by manufacturing a second ILD layer 1420 that defines an air gap, as described above with respect to device 1232, and as shown in FIG. 14D.

As mentioned above, the method 1200 can be combined with any of the above examples to produce a device having one or more of the above structures.

When analyzing (for example, using scanning/transmission electron microscopy (SEM/TEM), composition mapping, secondary ion mass spectrometry (SIMS), atomic probe tomography, Raman spectroscopy, crystallography, and combinations thereof), according to The structure or device configured in one or more embodiments will show a carbon-rich layer having an atomic percentage greater than 75 atomic% (ie, graphene) at a position within the integrated circuit and the integrated circuit in the drawings ).

Example system

FIG. 15 illustrates a computing system 1500 implemented with one or more integrated circuit structures configured and/or otherwise manufactured in accordance with an example embodiment of the present invention. It can be seen that the computing system 1500 houses the motherboard 1502. The motherboard 1502 may include several components, including but not limited to a processor 1504 and at least one communication chip 1506, each of which may be physically or electrically coupled to the motherboard 1502, or otherwise integrated therein. As will be understood, the motherboard 1502 may be, for example, any printed circuit board, whether it is a motherboard or a motherboard mounted on the computing system 1500 or a daughterboard of a unique board, or the like. Depending on its application, the computing system 1500 may include one or more other components, which may or may not be physically and electrically coupled to the motherboard 1502. These other groups may include but are not limited to volatile memory (eg, DRAM), non-volatile memory (eg, ROM), graphics processor, digital signal processor, cryptographic processor, chipset, antenna, display , Touch monitors, touch controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices ( Such as hard drive, compact disc (CD), digital versatile disc (DVD), etc.). Any components included in the computing system 1500 may include one or more integrated circuit structures configured with one or more conductive interconnect features having a graphite barrier layer or nanoscale conductive interconnect features, as described herein Narrated. These integrated circuit structures can be used, for example, to implement on-board processor caches or memory arrays or other circuit features that include interconnects. In some embodiments, multiple functions may be integrated into one or more chips (eg, note that the communication chip 1506 may be part of the processor 1504 or otherwise integrated into the processor 1504).

The communication chip 1506 enables wireless communication for transferring data to and from the computing system 1500. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc. that can communicate data through non-solid media by using tuned electromagnetic radiation. The term does not imply that the related devices do not contain any lines, although in some embodiments they may not contain any lines. The communication chip 1506 can implement any number of wireless standards or protocols to achieve wireless communication, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, long-range evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols specified as 3G, 4G, 5G, and beyond. The computing system 1500 may include a plurality of communication chips 1506. For example, the first communication chip 1506 may be dedicated to short-range wireless communication such as Wi-Fi and Bluetooth, and the second communication chip 1506 may be dedicated to long-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev- DO, and others.

The processor 1504 of the computing system 1500 includes an integrated circuit die packaged in the processor 1504. In some embodiments of the present invention, the integrated circuit die of the processor includes an on-board memory circuit that is configured by one or more of graphite barrier layers or nano-level conductive interconnect features The integrated circuit structure is implemented as described in this article. The term "processor" may refer to a process such as electronic data from a register and/or memory to convert the electronic data into other electronic data that can be stored in any device or part of the device in the register and/or memory .

The communication chip 1506 may also include an integrated circuit die packaged in the communication chip 1506. According to some such exemplary embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures as described herein (eg, at a given interconnect layer or nanoscale conductive interconnect feature or One or more devices that may benefit from damascene and dual damascene implementations within other semiconductor structures with thin graphite barrier layers. According to the present disclosure, it should be noted that multi-standard wireless capabilities can be directly integrated into the processor 1504 (eg, where the functions of any communication chip 1506 are integrated into the processor 1504 instead of having a separate communication chip). Also note that the processor 1504 may be a chipset with such wireless capabilities. In short, any number of processors 1504 and/or communication chips 1506 can be used. Likewise, any one wafer or wafer set may have multiple functions integrated therein.

In various embodiments, the computing system 1500 may be a laptop, light laptop, laptop, smartphone, tablet, personal digital assistant (PDA), ultra-thin mobile PC, mobile phone, desktop Computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In a further embodiment, the computing system 1500 may be any other electronic device that processes data as described herein or employs integrated circuit features configured with one or more conductive via interconnection features with a graphite barrier layer Device.

Further exemplary embodiments

The following example relates to further embodiments, from which many permutations and configurations can be seen.

Example 1 is an integrated circuit device, including: a first insulator layer; a plurality of first interconnections including: a plurality of first metal features within the first insulator layer, each first metal feature having Top surface, bottom surface, and side surfaces; a graphite barrier layer conformally disposed on the first insulator layer and each of the first metal features on the side surfaces of each of the first metal features Between; and a second insulator layer, wherein there are a plurality of second interconnections, at least one of the second interconnections directly contacts the top of at least one of the first metal features of the plurality of first metal features The surface or the bottom surface, wherein the first insulator layer defines at least one air gap disposed between adjacent first interconnections of the plurality of first interconnections.

Example 2 includes the target of Example 1, and further includes a tantalum-based liner on the bottom surface of at least some of the first metal features.

Example 3 includes the subject matter of Example 2, wherein the tantalum-based liner is between the bottom surface of at least some of the first metal features and the base interlayer dielectric layer.

Example 4 includes the subject matter of any preceding example, wherein at least some of the first metal features do not have a gasket material between the corresponding bottom surface and the interlayer dielectric layer.

Example 5 includes the subject matter of any preceding example, wherein at least one of the second interconnections includes: a second metal feature having a through-hole portion having a bottom surface and a side surface; a non-graphite barrier A layer conformally disposed between the bottom surface of the through hole portion of the second interconnect and the top surface of the first interconnect; and a non-graphite barrier layer conformally disposed on the through Between the side surfaces of the hole portion and the second insulator layer.

Example 6 includes the subject matter of Example 5, wherein the second metal feature further includes: a line portion having a bottom surface and a side surface, at least a portion of the bottom surface of the line portion is integrated with the through-hole portion; and a non-graphite barrier A layer is conformally disposed between the side surfaces of the wire portion of the second metal feature and the third insulator layer.

Example 7 includes the request of Example 5, wherein the second metal feature further includes: a line portion having a bottom surface and a side surface, at least a portion of the bottom surface of the line portion is in contact with the through-hole portion; and a graphite barrier layer It is conformally disposed between the side surfaces of the wire portion of the second metal feature and the third insulator layer.

Example 8 includes the subject matter of Example 5, wherein at least one of the second interconnections includes: a through hole portion having a top surface, a bottom surface, and a side surface, wherein: the bottom surface of the through hole portion and the The top surface of one of the first metal features is in direct contact; the top surface of the through-hole portion of the second interconnection is integrated with the third interconnection; and the graphite barrier layer side, which is conformally disposed on the first Between two insulator layers and the side surfaces of the through hole portion of the second interconnection.

Example 9 includes the subject matter of Example 8, wherein the third interconnection includes: a metal wire integrated with the through-hole portion of the at least one second interconnection, the metal wire has a side surface; and a graphite liner, which is The side surfaces of the metal wire are conformal.

Example 10 includes the subject matter of any preceding example, wherein at least one of the second interconnections is a through-hole disposed within the second insulator layer, the through-hole includes: a second metal feature, which is One of the first metal features is integrated; and a graphite liner that is conformally disposed on the side surface of the second metal feature and between the side surface of the second metal features and the second insulator layer.

Example 11 includes the subject matter of any preceding example, wherein the graphite barrier layer is conformally disposed on the side surfaces of each of the first metal features.

Example 12 includes the subject matter of any previous example, and further includes a second metal feature that directly contacts the top surface of the graphite barrier layer and the top surface of the first metal feature.

Example 13 includes the subject matter of any previous example, where the graphite barrier layer is less than 1.5 nanometers thick.

Example 14 includes the subject matter of any previous example, where the graphite barrier layer is less than 0.5 nanometers thick.

Example 15 includes the request subject of any previous example, wherein the first metal feature is tungsten.

Example 16 includes the request subject of any preceding example, wherein the first metal feature is tantalum.

Example 17 includes the subject of any previous example, wherein the first metal feature is copper.

Example 18 includes the subject matter of any previous example, wherein the graphite barrier layer is a graphene barrier layer.

Example 19 is a computing system including an integrated circuit device as any of the previous examples.

Example 20 includes a method for forming an integrated circuit device, including: forming a base insulator layer; forming a temporary insulator layer on the base insulator layer; etching at least one trench in the temporary insulator layer; at the at least one Forming a temporary liner in the trench; depositing metal in the at least one trench lined with the temporary liner; removing the temporary insulator layer; removing the exposed portion of the temporary liner, the remaining metal and the temporary At least one first metal feature; a graphite barrier is formed on the exposed side surface of the at least one first metal feature, the graphite barrier and the at least one first metal feature collectively form at least a first mutual feature And a second insulator layer deposited on the at least one first interconnect, the second insulator layer defining an air gap between adjacent interconnects and between the base insulator layer and the second insulator layer.

Example 21 includes the request target of Example 20, and further includes planarizing the deposited metal.

Example 22 includes the subject matter of Example 20 or 21, wherein removing the temporary insulator layer includes using selective etching.

Example 23 includes any of the requests of Examples 20 to 22, wherein the temporary liner is a tantalum-based liner.

Example 24 includes any of the requests of Examples 20 to 23, wherein the exposed portion of the temporary liner is removed, while the bottom layer of the temporary liner is left between the at least one first metal feature and the base layer.

Example 25 includes any of the request targets of Examples 20 to 24, and further includes forming a graphite barrier on the top surface of the first metal feature.

Example 26 includes a method for forming an integrated circuit device, including: forming a base insulator layer; forming a blanket metal layer on the base insulator layer; subtractively etching the blanket layer to form from the blanket metal layer A plurality of first metal features, each of the plurality of first metal features has at least a top surface and a side surface; a graphite layer is formed on at least the side surfaces of the plurality of first metal features, and the plurality of first metal features The graphite layers on each of a metal feature form a plurality of first interconnections; and depositing a second insulator layer on the first interconnections, the second insulator layer between adjacent first interconnections An air gap is defined between the base insulator layer and the second insulator layer.

Example 27 includes the request subject of Example 26, and further includes forming a graphite layer on the top surface of each of the plurality of first metal features.

Example 28 includes the request of Example 27, forming a second insulator layer over the graphite layers on the top surfaces of the plurality of first interconnects; etching the trench defined in the second insulator layer to at least expose the At least one of the graphite layers on the top surface of the first interconnects; forming a barrier layer in the trench, a portion of the barrier layer in the trench and the top of the first interconnect The exposed graphite layer on the surface contacts; and a metal is formed on the barrier layer in the trench, the barrier layer and the metal forming a second interconnection.

Example 29 includes the subject matter of Example 28 and further includes: forming an additional blanket metal layer integrated with the second interconnect and disposed above the second insulator layer; subtractively etching the additional blanket metal layer to form an additional Each additional metal feature has a side surface and a top surface; and a graphite layer is formed on at least the side surfaces of the additional metal features.

Example 30 includes any of the request targets of Examples 26 to 29, and further includes forming a second insulator layer over the top surfaces of the plurality of first interconnects; etching the trenches defined in the second insulator layer to expose the ones The top surface of at least one of the first metal features of the first interconnect; forming a barrier layer in the trench, a portion of the barrier layer in the trench and the first interconnect The exposed top surface of the first metal feature contacts; and a metal is formed on the barrier layer in the trench, and the barrier layer and the metal form a second interconnection.

Example 31 includes the subject matter of Example 30, and further includes: forming an additional blanket metal layer integrated with the second interconnect and disposed above the second insulator layer; subtractively etching the additional blanket metal layer to form an additional Each additional metal feature has a side surface and a top surface; and a graphite layer is formed on at least the side surfaces of the additional metal features.

Example 32 includes any of the request targets of Examples 26 to 31, and further includes: forming an etch stop barrier over the plurality of first interconnects; forming an additional blanket metal layer above the etch stop barrier; from the additional blanket Metal features minus ground-etched metal features; and forming a graphite layer on at least the side surfaces of the metal features etched from the additional blanket metal layer.

For purposes of illustration and description, the foregoing description has presented example embodiments. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. According to the present invention, many modifications and changes are possible. The intention is that the scope of the invention is not limited by the detailed description, but by the scope of the attached patent application. Applications filed in the future that claim the priority of this application may request the disclosed subject matter in different ways, and may generally include any set of one or more limitations as disclosed or otherwise indicated herein.

Claims (25)

An integrated circuit device includes: a first insulator layer; a plurality of first interconnections, including: a plurality of first metal features within the first insulator layer, each first metal feature having a top surface and a bottom Surface and side surfaces; a graphite barrier layer conformally disposed between the first insulator layer and each of the first metal features on the side surfaces of each of the first metal features; and A second insulator layer having a plurality of second interconnections, at least one of the second interconnections directly contacting the top surface of at least one of the first metal features of the plurality of first metal features Or the bottom surface, wherein the first insulator layer defines at least one air gap disposed between adjacent first interconnections of the plurality of first interconnections. The integrated circuit device as described in item 1 of the scope of the patent application further includes a tantalum-based pad on the bottom surface of at least some of the first metal features. An integrated circuit device as described in item 2 of the patent application range, wherein the tantalum-based pad is between the bottom surface and the interlayer dielectric layer of at least some of the first metal features. The integrated circuit device as described in item 1 of the patent application range, wherein at least some of the first metal features do not have a gasket material between the corresponding bottom surface and the interlayer dielectric layer. The integrated circuit device according to item 1 of the patent application scope, wherein at least one of the second interconnections includes: a second metal feature having a through hole portion having a bottom surface and a side surface A non-graphite barrier layer, which is conformally disposed between the bottom surface of the through-hole portion of the second interconnect and the top surface of the first interconnect; and a non-graphite barrier layer, which is conformal Is provided between the side surfaces of the through-hole portion and the second insulator layer. The integrated circuit device according to item 5 of the patent application scope, wherein the second metal feature further includes: a line portion having a bottom surface and a side surface, at least a portion of the bottom surface of the line portion and the through-hole portion Integration; and a non-graphite barrier layer conformally disposed between the side surfaces of the wire portion of the second metal feature and a third insulator layer. The integrated circuit device according to item 5 of the patent application scope, wherein the second metal feature further includes: a line portion having a bottom surface and a side surface, at least a portion of the bottom surface of the line portion and the through-hole portion Contact; and a graphite barrier layer conformally disposed between the side surfaces of the wire portion of the second metal feature and the third insulator layer. The integrated circuit device according to item 5 of the patent application scope, wherein at least one of the second interconnections includes: a through-hole portion having a top surface, a bottom surface and a side surface, wherein: the through-hole portion The bottom surface is in direct contact with the top surface of one of the first metal features; the top surface of the via portion of the second interconnection is integrated with the third interconnection; and the graphite barrier layer side, which protects Formed between the second insulator layer and the side surfaces of the through hole portion of the second interconnection. The integrated circuit device according to item 8 of the patent application scope, wherein the third interconnection includes: a metal wire integrated with the through-hole portion of the at least one second interconnection, the metal wire having a side surface; and A graphite liner conforms to the side surfaces of the metal wire. The integrated circuit device as described in item 1 of the patent application scope, wherein at least one of the second interconnections is a through hole provided in the second insulator layer, the through hole including: a second metal feature , Which is integrated with one of the first metal features; and a graphite liner, which is conformally disposed on the side surfaces of the second metal feature and on the side surfaces of the second metal feature and the first Between two insulator layers. An integrated circuit device as described in item 1 of the patent application range, wherein the graphite barrier layer is conformally disposed on the side surfaces of each of the first metal features. The integrated circuit device as described in item 1 of the scope of the patent application further includes a second metal feature that directly contacts the top surface of the graphite barrier layer and the top surface of the first metal feature. The integrated circuit device as described in item 1 of the patent scope, wherein the graphite barrier layer is less than 0.5 nm thick. The integrated circuit device as described in item 1 of the patent application range, wherein the graphite barrier layer is a graphene barrier layer. A computing system including an integrated circuit device as described in any of claims 1-14. A method for forming an integrated circuit device, comprising: forming a base insulator layer; forming a temporary insulator layer on the base insulator layer; etching at least one trench in the temporary insulator layer; in the at least one trench Forming a temporary liner; depositing metal in the at least one trench lined with the temporary liner; removing the temporary insulator layer; removing the exposed portion of the temporary liner, the remaining metal and the temporary liner Forming at least one first metal feature; forming a graphite barrier on the exposed side surface of the at least one first metal feature, the graphite barrier and the at least one first metal feature collectively forming at least one first interconnection; and A second insulator layer is deposited on the at least one interconnect, the second insulator layer defining an air gap between adjacent interconnects and between the base insulator layer and the second insulator layer. The method as described in item 16 of the patent application range, wherein the temporary gasket is a tantalum-based gasket. The method as recited in item 16 of the patent application scope, wherein removing the exposed portion of the temporary liner leaves the bottom layer of the temporary liner between the at least one first metal feature and the base layer. The method described in item 16 of the patent application scope further includes forming a graphite barrier on the top surface of the first metal feature. A method for forming an integrated circuit device, comprising: forming a base insulator layer; forming a blanket metal layer on the base insulator layer; subtractively etching the blanket layer to form a plurality of first layers from the blanket metal layer A metal feature, each of the plurality of first metal features has at least a top surface and a side surface; a graphite layer is formed on at least the side surfaces of the plurality of first metal features, and the plurality of first metal features The graphite layers on each of which form a plurality of first interconnections; and depositing a second insulator layer on the first interconnections, the second insulator layer between the adjacent first interconnections and the substrate An air gap is defined between the insulator layer and the second insulator layer. The method as described in item 20 of the patent application scope further includes forming a graphite layer on the top surface of each of the plurality of first metal features. The method as described in item 21 of the patent application scope further includes: forming a second insulator layer above the graphite layer on the top surfaces of the plurality of first interconnections; etching is defined in the second insulator layer A trench to expose at least the graphite layer on the top surface of at least one of the first interconnects; a barrier layer is formed in the trench, a portion of the barrier layer and the first The exposed graphite layer on the top surface of an interconnect is in contact; and a metal is formed on the barrier layer in the trench, the barrier layer and the metal forming a second interconnect. The method as described in item 22 of the scope of the patent application further includes: forming an additional blanket metal layer integrated with the second interconnect and disposed above the second insulator layer; minusly etching the additional blanket metal Layers to form additional metal features, each additional metal feature having a side surface and a top surface; and forming a graphite layer at least on the side surfaces of the additional metal features. The method as described in item 20 of the patent application scope further includes: forming a second insulator layer over the top surfaces of the plurality of first interconnects; etching the trench defined in the second insulator layer to expose The top surface of at least one of the first metal features of the first interconnects; forming a barrier layer in the trench, a portion of the barrier layer in the trench and the first interconnect The exposed top surface of the first metal feature contacts; and a metal is formed on the barrier layer in the trench, and the barrier layer and the metal form a second interconnection. The method as described in item 20 of the patent application scope further includes: forming an etch stop barrier above the plurality of first interconnects; forming an additional blanket metal layer above the etch stop barrier; from the additional blanket Metal features minus ground-etched metal features; and forming a graphite layer at least on the side surfaces of the metal features etched from the additional blanket metal layer.