TW201802906A - Wafer processing method - Google Patents
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- TW201802906A TW201802906A TW106118066A TW106118066A TW201802906A TW 201802906 A TW201802906 A TW 201802906A TW 106118066 A TW106118066 A TW 106118066A TW 106118066 A TW106118066 A TW 106118066A TW 201802906 A TW201802906 A TW 201802906A
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Abstract
[課題]本發明的課題在於提供一可以在不使器件的品質降低的情形下實行電漿蝕刻之晶圓的加工方法。 [解決手段]根據本發明可提供一種晶圓的加工方法,其為將晶圓分割成一個個的器件,該晶圓是將在正面積層有鈍化膜的器件以分割預定線區劃而在半導體基板的正面形成有複數個,該晶圓的加工方法至少是由下述步驟所構成:半導體基板露出步驟,將切削刀定位於分割預定線,以去除積層於分割預定線的鈍化膜或金屬膜,使半導體基板沿著分割預定線露出;及分割步驟,以覆蓋該器件的鈍化膜作為遮蔽膜,且將已於分割預定線露出的半導體基板藉由電漿蝕刻進行分割。[Problem] An object of the present invention is to provide a method for processing a wafer capable of performing plasma etching without lowering the quality of a device. [Solution] According to the present invention, a method for processing a wafer can be provided, which is to divide a wafer into individual devices. The wafer is a device in which a passivation film is layered on a positive area to divide a predetermined line into a semiconductor substrate. A plurality of front surfaces are formed, and the processing method of the wafer is at least composed of the following steps: a semiconductor substrate exposing step, positioning a cutter at a predetermined division line to remove a passivation film or a metal film laminated on the predetermined division line, Exposing the semiconductor substrate along a predetermined division line; and a division step, using the passivation film covering the device as a shielding film, and dividing the semiconductor substrate that has been exposed at the division line by plasma etching.
Description
發明領域 本發明是有關於一種藉由所謂的電漿蝕刻來將晶圓分割成一個個的器件之晶圓的加工方法。FIELD OF THE INVENTION The present invention relates to a method of processing a wafer by dividing a wafer into individual devices by so-called plasma etching.
發明背景 被分割預定線所區劃而在半導體基板的正面形成有IC、LSI等複數個器件之晶圓,是藉由切割裝置、雷射加工裝置等而被分割成一個個的器件,且利用於行動電話、個人電腦等電氣機器上。BACKGROUND OF THE INVENTION A wafer that is divided by a predetermined division line and has a plurality of devices such as ICs and LSIs formed on the front surface of a semiconductor substrate is divided into individual devices by a dicing device, a laser processing device, and the like, and is used in On electrical equipment such as mobile phones and personal computers.
又,作為使器件的抗折強度提升,並且能一次將晶圓分割成一個個的器件之生產性良好的分割方法,已提出的有一種電漿蝕刻的技術之方案(參照例如專利文獻1) 。 先前技術文獻 專利文獻In addition, as a method for improving the flexural strength of a device, and capable of dividing a wafer into individual devices at a time, a method of plasma etching has been proposed (see, for example, Patent Document 1). . Prior Art Literature Patent Literature
專利文獻1:日本專利特開2002-093752號公報Patent Document 1: Japanese Patent Laid-Open No. 2002-093752
發明概要 發明欲解決之課題 根據記載於上述專利文獻1之電漿蝕刻的技術,雖然所期待的是生產效率變好,且被分割的器件之抗折強度變得良好,但在晶圓的正面將用於保護器件的抗蝕膜(resist film)形成為均勻的厚度的作法比較困難,所塗佈之抗蝕膜(1~5μm)於實行電漿蝕刻時,若在抗蝕膜較薄的部分進行蝕刻時,會有局部地露出器件,而使器件的品質降低的問題。又,在分割預定線上積層有包含TEG(test element group,測試元件群組)的金屬膜的情形下,也有電漿蝕刻被遮蔽而無法以電漿蝕刻進行分割的問題。SUMMARY OF THE INVENTION The problem to be solved by the invention is based on the plasma etching technique described in the above-mentioned Patent Document 1. Although the production efficiency is expected to be improved, and the flexural strength of the divided device is improved, it is on the front side of the wafer. It is difficult to form a resist film for protecting devices to a uniform thickness. When the applied resist film (1 to 5 μm) is subjected to plasma etching, if the resist film is thinner When the etching is performed partially, there is a problem that the device is partially exposed and the quality of the device is lowered. In addition, when a metal film including a TEG (test element group) is laminated on a predetermined division line, there is also a problem that plasma etching is blocked and division cannot be performed by plasma etching.
本發明是有鑒於上述事實而作成之發明,其主要的技術課題在於提供一種可以在不使器件的品質降低的情形下實行電漿蝕刻之晶圓的加工方法。 用以解決課題之手段The present invention has been made in view of the above-mentioned facts, and its main technical problem is to provide a method for processing a wafer capable of performing plasma etching without degrading the quality of a device. Means to solve the problem
為了解決上述之主要的技術課題,根據本發明可提供一種晶圓的加工方法,其為將晶圓分割成一個個的器件,該晶圓是將在正面積層有鈍化膜(passivation film)的器件以分割預定線區劃而在半導體基板的正面形成有複數個,該晶圓的加工方法至少是由下述步驟所構成: 半導體基板露出步驟,將切削刀定位於分割預定線,以去除積層於分割預定線的鈍化膜或金屬膜,使半導體基板沿著分割預定線露出;及 分割步驟,以覆蓋該器件的鈍化膜作為遮蔽膜,且將已於分割預定線露出的半導體基板藉由電漿蝕刻進行分割。In order to solve the above-mentioned main technical problems, a method for processing a wafer may be provided according to the present invention. The method is to divide a wafer into individual devices. The wafer is a device having a passivation film in a positive area. A plurality of divided lines are formed on the front surface of the semiconductor substrate. The method for processing the wafer is composed of at least the following steps: The semiconductor substrate is exposed, and the cutter is positioned at the predetermined division line to remove the build-up layer. A passivation film or a metal film at a predetermined line to expose the semiconductor substrate along the predetermined division line; and a division step of using the passivation film covering the device as a shielding film and etching the semiconductor substrate that has been exposed at the predetermined division line by plasma. Divide.
可以將該鈍化膜藉由SiO2 膜、Si3 N4 膜、聚醯亞胺(polyimide)膜中之任一種來形成,且半導體基板是矽基板,並將在電漿蝕刻中使用的氣體設為氟系氣體,來實施上述晶圓的加工方法。 發明效果The passivation film can be formed by any one of a SiO 2 film, a Si 3 N 4 film, and a polyimide film. The semiconductor substrate is a silicon substrate, and a gas used in plasma etching can be set. The above-mentioned wafer processing method is performed using a fluorine-based gas. Invention effect
本發明之晶圓的加工方法,是將晶圓分割成一個個器件,該晶圓是將在正面積層有鈍化膜的器件以分割預定線區劃而在半導體基板的正面形成有複數個,該晶圓的加工方法至少由下述步驟所構成: 半導體基板露出步驟,將切削刀定位於分割預定線,以去除積層於分割預定線的鈍化膜或金屬膜,使半導體基板沿著分割預定線露出;及 分割步驟,以覆蓋該器件的鈍化膜作為遮蔽膜,且藉由電漿蝕刻對已於分割預定線露出的半導體基板進行分割, 藉此,由於可將實行電漿蝕刻時成為障礙的分割預定線上的鈍化膜、或包含TEG而被構成之金屬膜預先去除,並將積層於器件的正面的鈍化膜作為電漿蝕刻之時的遮蔽膜來利用,所以毋需形成要均勻地塗佈會比較困難之抗蝕膜(1~5μm),也可抑制以該抗蝕膜作為遮蔽膜來實施電漿蝕刻時的品質的降低。The processing method of the wafer of the present invention is to divide the wafer into individual devices. The wafer is a device in which a passivation film is layered on a positive area to divide a predetermined line to form a plurality of lines on the front surface of a semiconductor substrate. The method for processing a circle is composed of at least the following steps: a semiconductor substrate exposing step, positioning the cutter at a predetermined division line to remove a passivation film or a metal film laminated on the predetermined division line, and exposing the semiconductor substrate along the predetermined division line; And the dividing step, the passivation film covering the device is used as a shielding film, and the semiconductor substrate that has been exposed at the predetermined division line is divided by plasma etching, whereby the division can be scheduled as a barrier when performing plasma etching. The passivation film on the line or the metal film composed of TEG is removed in advance, and the passivation film laminated on the front surface of the device is used as a masking film during plasma etching, so it is not necessary to form a uniform coating. A difficult resist film (1 to 5 μm) can also suppress a reduction in quality when plasma etching is performed using the resist film as a shielding film.
用以實施發明之形態 以下,針對本發明的晶圓的加工方法的較佳實施形態,參照附加圖式以詳細地說明。Embodiments for Carrying Out the Invention Hereinafter, preferred embodiments of the wafer processing method of the present invention will be described in detail with reference to the attached drawings.
如圖1所示,在本實施形態中被加工之晶圓10,是由半導體基板(矽基板)10a、與器件14所形成,該器件14是形成在該半導體基板10a的正面側之藉由複數條分割預定線12所區劃出的區域中,此外,如圖1(a)中以局部放大截面圖所示,是在形成有該器件14之正面側的全域中形成有鈍化膜16(例如,二氧化矽膜(SiO2 )),該鈍化膜16具有可從來自外部的污染與不純物等的進入中保護器件14的作用。該鈍化膜16是以電漿CVD法來積層之情形是已知的,在此省略其詳細內容。再者,作為藉由依據本發明之晶圓的加工方法而被加工的晶圓,並不一定限定於圖1(a)所示的晶圓,也可以將例如在分割預定線12上並未形成鈍化膜,而是形成有包含TEG(test element group,測試元件群組)的金屬膜18之晶圓作為對象(參照圖1(b))。As shown in FIG. 1, the wafer 10 to be processed in this embodiment is formed by a semiconductor substrate (silicon substrate) 10a and a device 14, which is formed on the front side of the semiconductor substrate 10a. In the area defined by the plurality of predetermined division lines 12, as shown in a partially enlarged sectional view in FIG. 1 (a), a passivation film 16 (for example, , A silicon dioxide film (SiO 2 )), and the passivation film 16 has a function of protecting the device 14 from external pollution and entry of impurities. It is known that the passivation film 16 is laminated by a plasma CVD method, and the details are omitted here. The wafer processed by the method for processing a wafer according to the present invention is not necessarily limited to the wafer shown in FIG. 1 (a). A passivation film is formed, and a wafer including a TEG (test element group) metal film 18 is formed as an object (see FIG. 1 (b)).
準備作為被加工物之該晶圓10之後,實施半導體基板露出步驟,其為使用圖2所示的切割裝置20(僅顯示一部分)來使其沿著分割預定線12露出半導體基板10a。於切割裝置20中具備有可藉由圖未示之旋轉主軸來使其高速旋轉的切削刀22。作業者是將所準備的晶圓10之以鈍化膜16被覆的正面朝上來載置於該切割裝置20的保持機構24上,並使圖未示的吸引機構作動來進行吸引保持。After the wafer 10 to be processed is prepared, a semiconductor substrate exposing step is performed by using a dicing device 20 (only a part of which is shown) shown in FIG. 2 to expose the semiconductor substrate 10 a along a predetermined division line 12. The cutting device 20 is provided with a cutting blade 22 that can be rotated at a high speed by a rotating spindle (not shown). The worker places the prepared wafer 10 with the front surface covered with the passivation film 16 on the holding mechanism 24 of the dicing apparatus 20, and operates a suction mechanism (not shown) to perform suction holding.
於實施讓作業者進行切割裝置20的切削刀22的位置與晶圓10的分割預定線12的對位之校準之後,將切削刀22定位於該分割預定線12的一端部,並驅動旋轉主軸以使切削刀22旋轉,且使保持機構24在箭頭X所示方向上相對地移動,來沿著分割預定線12進行切削。藉此,如圖2作為局部放大截面圖而顯示地,沿著晶圓10的分割預定線12實行切削加工,以形成相當於至少鈍化膜16(或金屬膜18)的厚度(在本實施形態中為5μm),且使晶圓10的半導體基板10a露出的深度。切削刀22到達分割預定線12的另一端部之後,將保持設備24適當移動、使其旋轉,以將切削位置調整到成為未加工之分割預定線12的位置,並對所有的分割預定線12均施行同樣的切削加工,使半導體基板10a露出。藉此,沿分割預定線12將鈍化膜16去除、或在形成有包含TEG之金屬膜18的情況下將該金屬膜18去除,而成為沿著所有的分割預定線12露出半導體基板10a的狀態。After aligning the position of the cutting blade 22 of the cutting device 20 with the planned division line 12 of the wafer 10, the cutter 22 is positioned at one end of the planned division line 12, and the rotary spindle is driven. The cutting blade 22 is rotated and the holding mechanism 24 is relatively moved in the direction indicated by the arrow X to perform cutting along the planned division line 12. As a result, as shown in FIG. 2 as a partially enlarged sectional view, a cutting process is performed along a predetermined division line 12 of the wafer 10 to form a thickness corresponding to at least the passivation film 16 (or the metal film 18) (in this embodiment) 5 μm), and the semiconductor substrate 10 a of the wafer 10 is exposed to a depth. After the cutter 22 reaches the other end of the planned division line 12, the holding device 24 is appropriately moved and rotated to adjust the cutting position to the position of the unprocessed planned division line 12, and to all the planned division lines 12 The same cutting process is performed to expose the semiconductor substrate 10a. Thereby, the passivation film 16 is removed along the planned division line 12, or when the metal film 18 including TEG is formed, the metal film 18 is removed, and the semiconductor substrate 10a is exposed along all the planned division lines 12. .
如上述地實施半導體基板露出步驟後,實施分割步驟,其為進行用於將晶圓10分割成一個個的器件的電漿蝕刻。於所述的電漿蝕刻中,可以使用例如於圖3簡化而顯示之電漿蝕刻裝置40。此電漿蝕刻裝置40具備供給氟系氣體的氣體供給部41,且具備有在內部進行蝕刻處理的腔室42。可從氣體供給部41在該腔室42內供給例如SF6 、C4 F8 ,作為氟系氣體。After the semiconductor substrate exposure step is performed as described above, a dicing step is performed, which is a plasma etching for dicing the wafer 10 into individual devices. For the plasma etching, a plasma etching apparatus 40 shown in FIG. 3 can be used, for example. This plasma etching apparatus 40 includes a gas supply unit 41 that supplies a fluorine-based gas, and includes a chamber 42 that performs an etching process inside. As the fluorine-based gas, for example, SF 6 and C 4 F 8 can be supplied from the gas supply unit 41 into the chamber 42.
如圖所示,在進行電漿蝕刻的腔室42的上部側,配設有連接於氣體供給部41的蝕刻氣體供給機構43,且於下部側配設有保持會被蝕刻之作為被加工物的晶圓10的工作夾台44。As shown in the figure, an etching gas supply mechanism 43 connected to the gas supply unit 41 is disposed on the upper side of the chamber 42 where plasma etching is performed, and a workpiece to be etched is disposed on the lower side. Work table 44 of the wafer 10.
蝕刻氣體供給機構43在內部具備有氣體流通路徑43a,且具有透過以多孔構件所形成的下表面43b來向保持於工作夾台44的晶圓10的露出面側(形成有器件14之側)供給蝕刻氣體的功能。再者,蝕刻氣體供給機構43是在腔室42內部藉由圖未示的移動機構而被驅動並朝上下升降自如地被構成。The etching gas supply mechanism 43 is provided with a gas flow path 43a inside, and has a lower surface 43b formed by a porous member to supply to the exposed surface side (side where the device 14 is formed) of the wafer 10 held on the stage 44. Function of etching gas. It should be noted that the etching gas supply mechanism 43 is configured to be driven upward and downward in the chamber 42 by a movement mechanism (not shown).
另一方面,工作夾台44是藉由腔室42可旋動地支撐其軸部,並將圖未示的吸引源透過吸引路徑44a連接到構成為具有通氣性之上表面44b。腔室42的底部具備有連接於圖未示的氣體排出部之排氣口45,排氣口45會發揮對腔室內進行減壓、或將使用過的氣體排出的功能。又,於蝕刻氣體供給機構43、工作夾台44連接有高頻電源46,而可以供給高頻電壓,並將腔室42內的蝕刻氣體電漿化。本實施形態中的電漿蝕刻裝置40是如以上概要構成,以下說明關於藉由電漿蝕刻裝置40實行的分割步驟。On the other hand, the work clamp table 44 rotatably supports its shaft portion by the chamber 42 and connects a suction source (not shown) to the upper surface 44b configured to have air permeability through the suction path 44a. The bottom of the chamber 42 is provided with an exhaust port 45 connected to a gas exhaust portion (not shown), and the exhaust port 45 functions to reduce the pressure in the chamber or exhaust used gas. Further, a high-frequency power source 46 is connected to the etching gas supply mechanism 43 and the work table 44 so that a high-frequency voltage can be supplied and the etching gas in the chamber 42 is plasmatized. The plasma etching apparatus 40 in this embodiment is configured as described above. The following describes the division steps performed by the plasma etching apparatus 40.
首先,透過具有黏著性及可撓性的保護膠帶T,將已實施半導體基板露出步驟的晶圓10保持在框架F上。該晶圓10是從圖未示的腔室42的搬入搬出口搬入到腔室42內。將已搬入腔室42內的晶圓10以形成有蝕刻加工中作為遮蔽膜而發揮功能之鈍化膜16的正面側朝上方來載置且吸引固定在工作夾台44上。將晶圓10載置在工作夾台44上後,並將腔室42設成密閉空間後,將內部空氣排氣以進行減壓。First, the wafer 10 on which the semiconductor substrate exposure step has been performed is held on the frame F by a protective tape T having adhesiveness and flexibility. The wafer 10 is transferred into the chamber 42 from a loading / unloading port of a chamber 42 (not shown). The wafer 10 that has been carried into the chamber 42 is placed on the work clamp table 44 with the front side of the passivation film 16 that functions as a shielding film during the etching process being formed facing upward, and is suction-fixed. After the wafer 10 is placed on the work table 44 and the chamber 42 is set as a closed space, the internal air is exhausted to reduce the pressure.
已將腔室42內減壓後,藉由圖未示的移動機構一邊使蝕刻氣體供給機構43下降來調整與晶圓10的距離,一邊從氣體供給部41透過蝕刻氣體供給機構43使蝕刻氣體(SF6 )朝腔室42內噴出,並且使高頻電源46作動以將高頻電壓施加在蝕刻氣體供給機構43與工作夾台44之間,以使已供給到腔室42內的蝕刻氣體(SF6 )電漿化。然後,藉由電漿的蝕刻效果將晶圓10的正面之中,已去除鈍化膜16(或金屬膜18)之半導體基板露出區域10b的底部進行預定時間蝕刻。如此進行而將半導體露出區域10b的底部削除預定量後,接著將從氣體供給部41供給的蝕刻氣體切換成作為另一個蝕刻氣體的C4 F8 ,且使高頻電源作動以使新供給的蝕刻氣體電漿化。藉此,可削除半導體基板露出區域10b的低壁,並且於側壁依序形成藉由電漿聚合而積層的保護膜。其後,同樣進行,並一邊反覆進行SF6 、C4 F8 的供給,一邊使其進行蝕刻。藉由如此進行而實行蝕刻10~15分鐘,可實行如在圖3(b)以概要截面圖所示的異方性蝕刻,且可形成朝向下方且垂直地延伸之良好的分割溝10c。然後,藉由僅蝕刻相當於半導體基板10a的厚度量,可將晶圓10分割成一個個的器件14,而完成分割步驟。再者,一般而言該電漿蝕刻方法是作為波希法(Bosch Process)而廣為周知,圖所示的蝕刻裝置是概要圖,其他的構成已被省略。After the pressure in the chamber 42 has been reduced, the etching gas supply mechanism 43 is lowered by a moving mechanism (not shown) to adjust the distance from the wafer 10, and the etching gas is passed through the etching gas supply mechanism 43 from the gas supply unit 41 to cause the etching gas (SF 6 ) is ejected into the chamber 42, and the high-frequency power source 46 is operated to apply a high-frequency voltage between the etching gas supply mechanism 43 and the work table 44 so that the etching gas that has been supplied into the chamber 42 (SF 6 ) Plasmaization. Then, the bottom of the exposed region 10b of the semiconductor substrate from which the passivation film 16 (or the metal film 18) has been removed from the front surface of the wafer 10 is etched for a predetermined time by the plasma etching effect. After cutting the bottom of the semiconductor exposed region 10b by a predetermined amount in this way, the etching gas supplied from the gas supply unit 41 is switched to C 4 F 8 as another etching gas, and the high-frequency power supply is operated to cause the newly supplied The etching gas is plasmatized. Thereby, the low wall of the exposed region 10b of the semiconductor substrate can be removed, and a protective film laminated by plasma polymerization can be sequentially formed on the side wall. After that, the same was performed, and the SF 6 and C 4 F 8 were repeatedly supplied while being etched. By performing the etching for 10 to 15 minutes in this way, anisotropic etching can be performed as shown in a schematic cross-sectional view in FIG. 3 (b), and a good divided trench 10c extending vertically downward can be formed. Then, by etching only the thickness corresponding to the semiconductor substrate 10a, the wafer 10 can be divided into individual devices 14 to complete the dividing step. In addition, this plasma etching method is generally known as a Bosch process. The etching apparatus shown in the figure is a schematic diagram, and other configurations have been omitted.
藉由該分割步驟沿著全部的分割預定線12形成分割溝後,將保持該晶圓10的框架F移送到圖未示的拾取步驟。然後,利用將保護膠帶T朝半徑方向擴張之圖未示的擴張機構,變得可將該保護膠帶擴張,而可容易地對已分割成一個個的器件14進行拾取。After dividing grooves are formed along all dividing lines 12 by this dividing step, the frame F holding the wafer 10 is transferred to a picking step (not shown). Then, by using an expansion mechanism (not shown) that expands the protective tape T in a radial direction, the protective tape can be expanded, and the devices 14 that have been divided into individual pieces can be easily picked up.
根據本發明之晶圓的加工方法,雖然可藉由上述之實施形態而實施,但本發明並非受限於此之發明。在本實施形態中,雖然作為半導體基板的材料而採用了矽,但並不受限於此,可以採用砷化鎵(GaAs)等其他的半導體基板。Although the wafer processing method according to the present invention can be implemented by the above-mentioned embodiment, the present invention is not limited to the invention. In this embodiment, although silicon is used as the material of the semiconductor substrate, it is not limited to this, and other semiconductor substrates such as gallium arsenide (GaAs) may be used.
又,關於本實施形態方面,雖然作為鈍化膜16而採用了二氧化矽(SiO2 )膜,但並不受限於此,可以選擇聚醯亞胺膜、氮化矽膜(Si3 N4 )。此外,在本實施形態的電漿蝕刻中,雖然藉由作為交互地供給SF6 、C4 F8 之所謂的波希法而已知的蝕刻方法來實行分割步驟,但並不受限於此,也可以採用一般所熟知的其他的電漿蝕刻法。實行電漿蝕刻時,宜選擇會成為異方性蝕刻的蝕刻條件,且可以考慮:半導體基板10a的厚度(例如,200~300μm)、與作為遮蔽膜來發揮功能之作為鈍化膜16的構件而被選擇的膜材之蝕刻速率的比(例如,Si:SiO2 膜=700:1、Si:聚醯亞胺(polyimide)膜、Si:氮化矽膜 (Si3 N4 )=100:1等),來選擇到分割半導體基板10a之前作為遮蔽膜而發揮功能之鈍化膜厚度(例如1~5μm),而適當調整蝕刻條件。再者,關於電漿蝕刻由於已是眾所周知的技術,因此在此省略更多的詳細說明。In this embodiment, although a silicon dioxide (SiO 2 ) film is used as the passivation film 16, the invention is not limited to this, and a polyimide film or a silicon nitride film (Si 3 N 4 ). In addition, in the plasma etching of the present embodiment, the dividing step is performed by an etching method known as a so-called Bosch method of supplying SF 6 and C 4 F 8 alternately, but it is not limited to this. Other generally known plasma etching methods can also be used. When performing plasma etching, it is desirable to select an etching condition that will be anisotropic etching. The thickness of the semiconductor substrate 10a (for example, 200 to 300 μm) and the member that functions as a masking film as the passivation film 16 may be considered. Ratio of etching rate of selected film material (for example, Si: SiO 2 film = 700: 1, Si: polyimide film, Si: silicon nitride film (Si 3 N 4 ) = 100: 1 Etc.), the thickness of the passivation film (for example, 1 to 5 μm) that functions as a shielding film before the semiconductor substrate 10 a is divided is selected, and the etching conditions are appropriately adjusted. In addition, since plasma etching is a well-known technique, more detailed description is omitted here.
10‧‧‧晶圓
10a‧‧‧半導體基板
10b‧‧‧半導體基板區域
10c‧‧‧分割溝
12‧‧‧分割預定線
14‧‧‧器件
16‧‧‧鈍化膜
18‧‧‧金屬膜
20‧‧‧切割裝置
22‧‧‧切削刀
24‧‧‧保持機構
40‧‧‧電漿蝕刻裝置
41‧‧‧氣體供給部
42‧‧‧腔室
43‧‧‧蝕刻氣體供給機構
43a‧‧‧氣體流通路徑
43b‧‧‧下表面
44‧‧‧工作夾台
44a‧‧‧吸引路徑
44b‧‧‧上表面
45‧‧‧排氣口
46‧‧‧高頻電源
F‧‧‧框架
LB‧‧‧雷射光線
T‧‧‧保護膠帶
X‧‧‧方向10‧‧‧ wafer
10a‧‧‧ semiconductor substrate
10b‧‧‧Semiconductor substrate area
10c‧‧‧ divided trench
12‧‧‧ divided scheduled line
14‧‧‧device
16‧‧‧ passivation film
18‧‧‧ metal film
20‧‧‧ cutting device
22‧‧‧Cutter
24‧‧‧ holding agency
40‧‧‧ Plasma Etching Device
41‧‧‧Gas Supply Department
42‧‧‧ chamber
43‧‧‧Etching gas supply mechanism
43a‧‧‧Gas circulation path
43b‧‧‧ lower surface
44‧‧‧Working table
44a‧‧‧Attraction path
44b‧‧‧ Top surface
45‧‧‧ exhaust port
46‧‧‧High Frequency Power
F‧‧‧Frame
LB‧‧‧Laser Ray
T‧‧‧protective tape
X‧‧‧ direction
圖1(a)、(b)是說明在本發明的晶圓的加工方法中被加工之晶圓的說明圖。 圖2是用於說明本發明中的半導體基板露出步驟的說明圖。 圖3(a)、(b)是用於說明實施本發明中的分割步驟用的電漿蝕刻裝置的概要之說明圖。1 (a) and 1 (b) are explanatory diagrams illustrating a wafer to be processed in the wafer processing method of the present invention. FIG. 2 is an explanatory diagram for explaining a semiconductor substrate exposure step in the present invention. 3 (a) and 3 (b) are explanatory diagrams for explaining an outline of a plasma etching apparatus for performing a dividing step in the present invention.
10‧‧‧晶圓 10‧‧‧ wafer
10a‧‧‧半導體基板 10a‧‧‧ semiconductor substrate
10c‧‧‧分割溝 10c‧‧‧ divided trench
14‧‧‧器件 14‧‧‧device
16‧‧‧鈍化膜 16‧‧‧ passivation film
40‧‧‧電漿蝕刻裝置 40‧‧‧ Plasma Etching Device
41‧‧‧氣體供給部 41‧‧‧Gas Supply Department
42‧‧‧腔室 42‧‧‧ chamber
43‧‧‧蝕刻氣體供給機構 43‧‧‧Etching gas supply mechanism
43a‧‧‧氣體流通路徑 43a‧‧‧Gas circulation path
43b‧‧‧下表面 43b‧‧‧ lower surface
44‧‧‧工作夾台 44‧‧‧Working table
44a‧‧‧吸引路徑 44a‧‧‧Attraction path
44b‧‧‧上表面 44b‧‧‧ Top surface
45‧‧‧排氣口 45‧‧‧ exhaust port
46‧‧‧高頻電源 46‧‧‧High Frequency Power
F‧‧‧框架 F‧‧‧Frame
T‧‧‧保護膠帶 T‧‧‧protective tape
Claims (2)
Applications Claiming Priority (2)
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| JP2016132229A JP2018006588A (en) | 2016-07-04 | 2016-07-04 | Wafer processing method |
| JP2016-132229 | 2016-07-04 |
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| Publication Number | Publication Date |
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| TW201802906A true TW201802906A (en) | 2018-01-16 |
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| JP (1) | JP2018006588A (en) |
| KR (1) | KR20180004661A (en) |
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| JP5509057B2 (en) * | 2010-12-20 | 2014-06-04 | パナソニック株式会社 | Manufacturing method of semiconductor chip |
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