TW201801476A - Control device and control method for analog power switch - Google Patents

Abstract

The invention provides a control device and a control method for an analog power switch. The control device for the analog power switch comprises a capacitor and a logic control component, wherein an upper polar plate of the capacitor is connected with a grid of the analog power switch via a diode and connected with an input voltage via a first switch, and a lower polar plate of the capacitor is connected with a source of the analog power switch via a second switch and connected with the ground via a third switch; the logic control component is configured to control charging and discharging of the capacitor by controlling the opening and closing of the first switch, the second switch and the third switch, so that connection and disconnection of the analog power switch are controlled, when the first switch and the third switch are closed, and the second switch is open, the capacitor is charged, and when the first switch and the third switch are open, and the second switch is closed, the capacitor is discharged.

Description

Control device and control method for analog power switch

The present invention relates to the field of circuits, and more particularly, to a control device and a control method for an analog power switch.

Vth時，類比功率開關導通，且其導通阻抗隨Vgs的增大而減小，其中Vth是類比功率開關的導通閾值電壓。 At present, analog power switches are widely used in various circuit systems. When an analog power switch is applied in a circuit system, its conduction and voltage can be controlled by controlling the voltage difference Vgs (Vgate-Vsource) between the gate voltage (Vgate) and the source voltage (Vsource) of the analog power switch. cutoff. Specifically, when Vgs <Vth, the analog power switch is turned off; when Vgs

At Vth, the analog power switch is turned on, and its on-resistance decreases as Vgs increases, where Vth is the turn-on threshold voltage of the analog power switch.

FIG. 1 is a schematic diagram of an example application of an analog power switch (eg, an N-channel Metal-Oxide-Semiconductor (NMOS) power transistor). As shown in FIG. 1, the NMOS power transistor is included in a wafer C; the wafer C has three terminals of VIN, VOUT, and GND, and includes three parts: an NMOS power transistor, a gate driving circuit, and a control circuit. Among them, the drain of the NMOS power transistor is connected to the VIN terminal, and the input voltage VIN is input to the drain of the NMOS power transistor through the VIN terminal; the source of the NMOS power transistor is connected to the VOUT terminal, and the output voltage VOUT is connected to the VOUT terminal. Provided to the load; the control circuit generates a control signal for controlling the on and off of the NMOS power transistor; the gate driving circuit generates a driving signal for driving the on and off of the NMOS power transistor based on the control signal generated by the control circuit, and The driving signal is provided to the gate of the NMOS power transistor.

Vth時，NMOS功率電晶體導通。由於導通後的NMOS功率電晶體的導通阻抗很小，VOUT端子與VIN端子之間可視為短路，因此在NMOS 功率電晶體導通後輸出電壓VOUT沖高到輸入電壓VIN。為了維持NMOS功率電晶體的導通狀態，閘極驅動電路被配置為控制NMOS功率電晶體的閘極電壓Vgate隨輸出電壓VOUT的沖高而變高，即維持閘極電壓Vgate

VOUT+Vth，才能確保滿足Vgs

Vth的導通條件。 Before the NMOS power transistor is turned on, the VOUT terminal is grounded; when Vgs

At Vth, the NMOS power transistor is turned on. Since the on-resistance of the NMOS power transistor after conduction is very small, the VOUT terminal and the VIN terminal can be regarded as a short circuit. Therefore, after the NMOS power transistor is turned on, the output voltage VOUT surges to the input voltage VIN. In order to maintain the on-state of the NMOS power transistor, the gate drive circuit is configured to control the gate voltage Vgate of the NMOS power transistor to increase with the surge of the output voltage VOUT, that is, to maintain the gate voltage Vgate

VOUT + Vth to ensure that Vgs is met

Vth on condition.

Generally, the gate driving circuit generates a driving signal by any one of a bootstrap method and a charge pump method. However, the Bootstrap method and the charge pump method generally require large external capacitors. Due to cost considerations, chip C cannot generally integrate such large capacitors.

The invention provides a control device and method for an analog power switch.

A control device for an analog power switch according to an embodiment of the present invention includes a capacitor. The upper plate of the capacitor is connected to the gate of the analog power switch via a diode and to the input voltage via a first switch. The lower plate is connected to the source of the analog power switch via a second switch and to the ground via a third switch; and a logic control element configured to control closing and breaking of the first switch, the second switch, and the third switch On to control the charging and discharging of the capacitor, thereby controlling the on and off of the analog power switch, where the capacitor is charged when the first and third switches are closed and the second switch is open, and when the first and third switches are open and the second The capacitor is discharged when the switch is closed.

A control method for an analog power switch according to an embodiment of the present invention includes: connecting an upper plate of a capacitor to a gate of the analog power switch via a diode and an input voltage through a first switch; and connecting a lower pole of the capacitor The board is connected to the source of the analog power switch via a second switch and to the ground via a third switch; and controlling the charging and discharging of the capacitor by controlling the closing and opening of the first switch, the second switch, and the third switch, Thus, the analog power switch is controlled to be turned on and off, wherein the capacitor is charged when the first switch and the third switch are closed and the second switch is opened, and the capacitor is discharged when the first switch and the third switch are opened and the second switch is closed.

In a control device for an analog power switch according to an embodiment of the present invention and In the method, the voltage difference between the upper and lower plates of the capacitor is not large, so it is not necessary to use a large capacitor or a cascade capacitor to achieve a high withstand voltage capacitor. Therefore, the implementation of the analog power switch according to the embodiment of the present invention can be effectively reduced. The cost of a control device and method for wafers.

Vgate‧‧‧Gate voltage

MOS_EN‧‧‧Switch enable signal

Vsource‧‧‧Source voltage

SST‧‧‧Soft start signal

Vth‧‧‧on threshold voltage

CLK‧‧‧ clock signal

C‧‧‧Chip

SD, PA, PB, PC‧‧‧ Switch control signal

VIN‧‧‧ input voltage

PH1, PH2‧‧‧‧Voltage selection signal

VOUT‧‧‧Output voltage

AVDD‧‧‧Constant voltage

GND, VS‧‧‧ terminals

Vramp‧‧‧Ramp voltage

C0, C1, C2, C7‧‧‧ capacitors

VCP‧‧‧Pole plate voltage

C3-C6‧‧‧series capacitor

R1, R2, R3, R4‧‧‧ resistance

410‧‧‧Charge pump main circuit

D0‧‧‧diode

430‧‧‧Logic Control Circuit

D1‧‧‧Voltage clamped diode

Vsel‧‧‧Voltage selection

C1p, C2p, C3p, C4p‧‧‧ Capacitance to ground

P1, P3, N1, N2, N3, N4‧‧‧ switches

420‧‧‧Vsel circuit

D‧‧‧Power Power MOS Field Effect Transistor Drain

G‧‧‧Power Power MOS Field Effect Transistor Gate

S‧‧‧Power Power MOS Field Effect Transistor Source

Vgs‧‧‧The voltage difference between the gate voltage (Vgate) and the source voltage (Vsource)

The present invention can be better understood from the following description of specific embodiments of the present invention with reference to the accompanying drawings, wherein similar reference numerals indicate the same or functionally similar elements: Figure 1 is an analog power switch (for example, N-channel metal oxidation Schematic diagram of an example application of a semiconductor (NMOS) power transistor; Figure 2 is an example circuit diagram of a conventional charge pump used in the gate drive circuit shown in Figure 1; Figure 3 is used in Figure 1 An example circuit diagram of a conventional charge pump using a cascade capacitor in a gate drive circuit shown in FIG. 4 is a schematic diagram of a charge pump used in the gate drive circuit shown in FIG. 1 according to an embodiment of the present invention; Fig. 5 shows a timing chart of signals related to the logic control circuit shown in Fig. 4.

Features and exemplary embodiments of various aspects of the invention will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it is obvious to a person skilled in the art that the present invention can be implemented without the need for some of these specific details. The following description of the embodiments is merely for providing a better understanding of the present invention by showing examples of the present invention. The invention is by no means limited to any specific configuration and algorithm proposed below, but covers any modification, replacement and improvement of elements, components and algorithms without departing from the spirit of the invention. In the drawings and the following description, well-known structures and techniques are not shown in order to avoid unnecessarily obscuring the present invention.

FIG. 2 is an example circuit diagram of a conventional charge pump used in the gate driving circuit shown in FIG. 1. FIG. In the case of the high-voltage application of the charge pump shown in Figure 2, because the pressure difference between the upper and lower plates of the capacitors C1 and C2 is too large, it is necessary to achieve a high withstand voltage by cascading capacitors. This will cause a significant increase in the cost of chip C.

FIG. 3 is an example circuit diagram of a conventional charge pump using a cascade capacitor used in the gate driving circuit shown in FIG. 1. FIG. In the charge pump shown in FIG. 3, the problem of the withstand voltage of the upper and lower plates of the capacitors C1 and C2 is solved by using a series capacitor method. However, as shown in Figure 3, the capacitors C1 and C2 and their series capacitors C3-C6 jointly introduce parasitic capacitances to ground (for example, C1p, C2p, C3p, C4p). These parasitic capacitances to ground will cause The equivalent capacitance of the capacitors C1-C6 becomes smaller in the working state. Therefore, to achieve the same effect, more capacitors need to be cascaded, which will further increase the cost of the chip C.

In order to solve one or more problems existing in the charge pumps described in conjunction with FIG. 2 and FIG. 3, a novel charge pump used in the gate driving circuit shown in FIG. 1 is proposed to effectively reduce the chip The cost of C. Hereinafter, a charge pump used in the gate driving circuit shown in FIG. 1 according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is a schematic diagram of a charge pump used in the gate driving circuit shown in FIG. 1 according to an embodiment of the present invention. As shown in FIG. 4, the charge pump according to the embodiment of the present invention includes a charge pump main circuit 410, a voltage selection (Vsel) circuit 420, and a logic control circuit 430. specifically:

The charge pump main circuit 410 includes switches P1, P3, N1-N4, capacitor C0, and diode D0; the VS terminal of the charge pump main circuit 410 is connected to the output of the Vsel circuit 420, and the GATE terminal of the charge pump main circuit 410 is connected to The gate of the NMOS power transistor is connected, and the VOUT terminal of the charge pump main circuit 410 is connected to the source of the NMOS power transistor.

The logic control circuit 430 receives the switch enable signal MOS_EN, the soft start signal SST, and the clock signal CLK, generates a switch control signal SD based on the switch enable signal MOS_EN, and generates a voltage selection signal PH1 and based on the switch enable signal MOS_EN and the soft start signal SST. PH2, and generates switch control signals PA, PB, and PC based on the switch enable signal MOS_EN and the clock signal CLK. among them:

，即當MOS_EN=1時，SD=0；當MOS_EN=0時，SD=1。

That is, when MOS_EN = 1, SD = 0; when MOS_EN = 0, SD = 1.

，即當MOS_EN= 1時，PH1=SST，

；當MOS_EN=0時，PH1=PH2=0。 PH 1 = SST . MOS_EN ,

, When MOS_EN = 1, PH1 = SST,

; When MOS_EN = 0, PH1 = PH2 = 0.

，

，即當 MOS_EN=1時，

，PA=PC=CLK，而當MOS_EN=0時，PB=0，PA=PC=1。

,

, That is, when MOS_EN = 1,

, PA = PC = CLK , and when MOS_EN = 0, PB = 0, PA = PC = 1.

FIG. 5 shows a timing chart of signals related to the logic control circuit shown in FIG. 4. It should be noted that, due to a certain delay in the logic control circuit, the waveforms of the switch control signals PA, PB, and PC are not strictly aligned with the clock signal CLK.

The following describes in detail the functions of the above signals and the working process of the main circuit 410 of the charge pump with reference to FIGS. 4 and 5:

The switch enable signal MOS_EN indicates whether the NMOS power transistor is enabled, and the switch control signal SD controls the closing and opening of the switch N4 to control whether the NMOS power transistor is enabled. Specifically, when the switch enable signal MOS_EN is at a high level, the switch control signal SD is at a low level, the switch N4 is turned off, and the NMOS power transistor is enabled; when the switch enable signal MOS_EN is at a low level, the switch control signal SD is at a high level Switch N4 is closed, the gate of the NMOS power transistor is grounded, and the NMOS power transistor is disabled.

The soft start signal SST indicates whether the soft start process is used. The voltage selection signals PH1 and PH2 control the Vsel circuit 420 to select one of the constant voltage AVDD and the ramp voltage Vramp to the charge pump main circuit 410 (for convenience, the selected voltage will be selected below). Called voltage VS). Specifically, when the soft-start signal SST is at a high level, the voltage selection signal PH1 is at a high level, and the voltage selection signal PH2 is at a low level. The Vsel circuit 420 selects the ramp voltage Vramp as the voltage VS and provides it to the charge pump main circuit 410 (that is, using a soft When the soft-start signal SST is at a low level, the voltage selection signal PH1 is at a low level and the voltage selection signal PH2 is at a high level. The Vsel circuit 420 selects a constant voltage AVDD as the voltage VS and provides it to the charge pump main circuit 410 (ie, does not Using a soft-start process).

The clock signal CLK provides a clock signal of a certain frequency. Switch control signal PA controls the closing and opening of switch N2; switch control signal PB controls the closing and opening of switches N3 and P3 (switch P3 and switch N3 are closed or opened at the same time); switch control signal PC controls switches N1 and P1 Closing and opening (switches P1 and N1 are closed or opened at the same time).

As can be seen from the above description, when the NMOS transistor is enabled, the logic control circuit 430 generates voltage selection signals PH1 and PH2 based on the soft start signal SST, and generates switching control signals PA, PB, and PC based on the clock signal CLK.

When the NMOS transistor is enabled, when the soft-start process is used, the charge pump main circuit 410 switches between the first state and the second state described below, thereby realizing the gate voltage of the NMOS power transistor control. specifically:

In the first state, N2 is on, P1 is on, P3 is off, N4 is off, the lower plate of capacitor C0 is grounded, and the upper plate of capacitor C0 is connected to voltage VS. At this time, capacitor C0 is charged until the upper and lower plates of capacitor C0. The voltage between them reaches the voltage VS.

In the second state, N2 is off, P1 is off, P3 is on, N4 is off, and the lower plate of capacitor C0 is connected to the output voltage VOUT. Because the voltage between the upper and lower plates of capacitor C0 cannot be changed suddenly, the upper of capacitor C0 The plate voltage VCP is instantly raised to VOUT + VS. At this time, the upper plate voltage VCP of the capacitor C0 charges the gate voltage of the NMOS power transistor through the diode D0.

After the charge pump main circuit 410 is repeatedly switched between the first state and the second state, the voltage difference Vgs between the gate voltage Vgate and the source voltage Vsource of the NMOS power transistor gradually increases to the peak value of the voltage Vramp (The peak value is greater than or equal to Vth), the NMOS power transistor is turned on.

Here, the magnitude of the internal resistance of switches N2, P1, and P3 determines the switching speed and conduction capacity of these switches, and the switching speed and conduction capacity of these switches determines the speed of charging or discharging capacitor C0, so you can The charging or discharging speed of the controlled capacitor C0 sets an appropriate internal resistance for these switches; the size of the internal resistance of the switch N4 determines the switching speed and conducting capacity of the switch N4, and the switching speed and conducting capacity of the switch N4 determines the NMOS voltage. The discharge speed of the crystal gate is fast, so an appropriate internal resistance can be set for the switch N4 according to the discharge speed of the NMOS transistor gate to be controlled. That is, the internal resistances of the switches N2, P1, P3, and N4 can be adjusted as required according to the respective switching speeds and conduction capabilities of the switches N2, P1, P3, and N4.

As can be seen from the above, in the charge pump shown in Figure 4, the capacitor The voltage difference between the upper and lower plates of C0 is not large, so it is not necessary to use a large capacitor or a cascade capacitor to achieve a high withstand voltage capacitor, so the cost of the chip C can be effectively reduced.

In some embodiments, the logic control circuit 430 may not receive the soft start signal SST and generate no voltage selection signals PH1 and PH2. At this time, only one of the constant voltage AVDD and the ramp voltage Vramp may be used as the voltage VS.

In the case of using the constant voltage AVDD as the voltage VS, when the charge pump main circuit 410 is in the second state, the upper plate voltage VCP of the capacitor C0 is immediately raised to VOUT + AVDD, so that the gate voltage of the NMOS power transistor Vgate quickly increases to VOUT + AVDD.

In the case where the ramp voltage Vramp (for example, from 0V to AVDD) is used as the voltage VS, after the charge pump main circuit 410 is repeatedly switched between the first state and the second state, the upper plate voltage VCP of the capacitor C0 is changed Gradually increasing to VOUT + AVDD, the gate voltage Vgate of the NMOS power transistor is gradually increased, thereby achieving a soft start of the NMOS power transistor.

In some embodiments, a combination of the constant voltage AVDD and the ramp voltage Vramp can also be adopted as the voltage VS (ie, the soft start signal SST and the voltage selection signals PH1 and PH2 are not required). In this case, the ramp voltage Vramp can be used for soft start first, and then the constant voltage AVDD can be used to increase the gate voltage Vgate of the NMOS power transistor to VOUT + AVDD.

In some embodiments, the switches P1 and P3 shown in FIG. 4 may be implemented as P-channel Metal-Oxide-Semiconductor (PMOS) transistors, and the switches N1-N4 may be implemented It is an NMOS transistor. In addition, the diode D0 shown in FIG. 4 can be implemented as a PMOS transistor with a gate and a source connected together. In other embodiments, the switch shown in FIG. 4 can also be implemented using a transmission gate.

It can be seen from Figs. 1 to 5 that the present invention provides a control device for an analog power switch (for example, an NMOS power transistor), including: a capacitor (for example, a capacitor C0), and an upper plate of the capacitor. Via a diode (e.g., diode D0) and analogy The gate of the power switch is connected and connected to an input voltage (eg, constant voltage AVDD, ramp voltage Vramp, or a combination thereof) via a first switch (eg, switch P1), and the lower plate of the capacitor is connected via a second switch (eg, , Switch P3) is connected to the source of the analog power switch and connected to ground via a third switch (for example, switch N2); and a logic control element (for example, logic control circuit 430) is configured to control the first switch, the first The closing and opening of the second switch and the third switch control the charging and discharging of the capacitor, thereby controlling the on and off of the analog power switch, wherein the capacitor is charged when the first switch and the third switch are closed and the second switch is open. When the first switch and the third switch are opened and the second switch is closed, the capacitor is discharged.

In other words, the present invention provides a control method for an analog power switch (for example, an NMOS power transistor), including: passing an upper plate of a capacitor (for example, the capacitor C0) through a diode (for example, the diode D0) Connected to the gate of an analog power switch and connected to an input voltage (eg, constant voltage AVDD, ramp voltage Vramp, or a combination thereof) via a first switch (eg, switch P1); passing the lower plate of the capacitor via a second switch (Eg, switch P3) is connected to the source of the analog power switch and is connected to ground via a third switch (eg, switch N2); and by controlling the closing and opening of the first switch, the second switch, and the third switch Control the charging and discharging of the capacitor to control the on and off of the analog power switch, where the capacitor is charged when the first and third switches are closed and the second switch is open, and when the first and third switches are open and the second The capacitors are discharged when the switch is closed.

In the control device and method for an analog power switch according to the embodiments of the present invention, the voltage difference between the upper and lower plates of the capacitor is not large, so it is not necessary to use a large capacitor or a cascade capacitor to achieve a high withstand voltage capacitor. The cost of the chip C for implementing the control device and method for the analog power switch according to the embodiments of the present invention can be effectively reduced.

The present invention may be implemented in other specific forms without departing from the spirit and essential characteristics thereof. For example, the algorithms described in particular embodiments may be modified without the system architecture departing from the basic spirit of the invention. Therefore, the current embodiment is considered in all aspects as exemplary rather than limiting, the scope of the present invention is defined by the scope of the attached patent application rather than the above description, and the meanings and equivalents falling within the scope of the patent application All changes within the scope of the substance are thus included in the scope of the present invention.

VIN‧‧‧ input voltage

SST‧‧‧Soft start signal

VOUT‧‧‧Output voltage

CLK‧‧‧ clock signal

GND, VS‧‧‧ terminals

SD, PA, PB, PC‧‧‧ Switch control signal

C0‧‧‧capacitor

PH1, PH2‧‧‧‧Voltage selection signal

Vsel‧‧‧Voltage selection

AVDD‧‧‧Constant voltage

410‧‧‧Charge pump main circuit

Vramp‧‧‧Ramp voltage

430‧‧‧Logic Control Circuit

VCP‧‧‧Pole plate voltage

D0‧‧‧diode

R1, R2, R3, R4‧‧‧ resistance

MOS_EN‧‧‧Switch enable signal

D1‧‧‧Voltage clamped diode

P1, P3, N1, N2, N3, N4‧‧‧ switches

420‧‧‧Vsel circuit

Claims (18)

A control device for an analog power switch includes a capacitor. An upper plate of the capacitor is connected to a gate of the analog power switch via a diode and is connected to an input voltage via a first switch. An electrode plate is connected to a source of the analog power switch via a second switch and to a ground via a third switch; and a logic control element configured to control the first switch, the second switch, and the via The third switch is closed and opened to control the charging and discharging of the capacitor, thereby controlling the analog power switch to be turned on and off. When the first switch and the third switch are closed, the second switch is opened. When the capacitor is charged, the capacitor is discharged when the first switch and the third switch are opened, and the second switch is closed. The control device according to item 1 of the scope of patent application, wherein the logic control element generates a first switch control signal for controlling closing and opening of the first switch based on a clock signal, and controls the first switch A second switch control signal for closing and opening the two switches, and a third switch control signal for controlling the closing and opening of the third switch. The control device according to item 1 of the scope of patent application, wherein the gate of the analog power switch is connected to the ground via a fourth switch, and the logic control element is controlled by controlling the closing and opening of the fourth switch The analog power switch is enabled and disabled. The control device according to item 1 of the scope of patent application, further comprising: a voltage selection element configured to select one of a ramp voltage and a constant voltage as the input voltage. The control device according to item 4 of the scope of patent application, wherein the voltage selection element selects one of the ramp voltage and the constant voltage as the input voltage under the control of the logic control element. The control device according to item 1 of the scope of patent application, wherein the diode is implemented by a P-channel metal oxide semiconductor transistor with a gate and a source connected together. The control device according to item 3 of the scope of patent application, wherein the first switch and the The second switch is implemented by a P-channel metal oxide semiconductor transistor, and the third switch and the fourth switch are implemented by an N-channel metal oxide semiconductor transistor. The control device according to item 3 of the scope of patent application, wherein the first to fourth switches are implemented by transmission gates. The control device according to item 3 of the scope of patent application, wherein the internal resistances of the first to fourth switches are adjusted according to their respective switching speeds and conduction capabilities. The control device according to claim 1, wherein the input voltage is one or a combination of a ramp voltage and a constant voltage. A control method for an analog power switch includes: connecting an upper electrode plate of a capacitor to a gate of the analog power switch via a diode and an input voltage via a first switch; and connecting a lower electrode plate of the capacitor via a second switch. Connected to the source of the analog power switch and connected to ground via a third switch; and controlling the capacitance by controlling closing and opening of the first switch, the second switch, and the third switch Charging and discharging, thereby controlling the analog power switch to be turned on and off, wherein the capacitor is charged when the first switch and the third switch are closed and the second switch is opened, and when the first switch and the The capacitor is discharged when the third switch is opened and the second switch is closed. The control method according to item 11 of the scope of patent application, wherein a first switch control signal for controlling the closing and opening of the first switch is generated based on a clock signal, and a closing and closing of the second switch is generated based on a clock signal. The opened second switch control signal and a third switch control signal for controlling the closing and opening of the third switch. The control method according to item 11 of the scope of patent application, further comprising: connecting a gate of the analog power switch to ground via a fourth switch; controlling the analog by controlling closing and opening of the fourth switch Enable and disable the power switch. The control method according to item 11 of the scope of patent application, further comprising: using one or a combination of a ramp voltage and a constant voltage as the input voltage. The control method according to item 11 of the scope of patent application, wherein the diode is implemented using a P-channel metal oxide semiconductor transistor with a gate and a source connected together. The control method according to item 13 of the scope of patent application, wherein the first switch and the second switch are implemented using a P-channel metal oxide semiconductor transistor, and an N-channel metal oxide semiconductor transistor is used To implement the third switch and the fourth switch. The control method according to item 13 of the scope of patent application, wherein a transmission gate is used to implement the first to fourth switches. The control method according to item 13 of the scope of patent application, wherein the internal resistances of the first to fourth switches are adjusted according to their respective switching speeds and conduction capabilities.