TW201801165A - Method for optimizing metal planarization process - Google Patents

Abstract

The invention discloses a method for optimizing a metal planarization process. The method includes: using chemical mechanical planarization to remove most metal layers on the upper surface of an interconnect structure until the thickness of the remaining metal layer reaches a predetermined value Y, and the remaining metal layer is to cover the interconnection. A continuous layer on the upper surface of the structure, wherein the remaining metal layer has a first average surface roughness Ra1, which is caused by chemical mechanical planarization; a stress-free polishing process is used to remove the upper surface of the interconnect structure After the stress-free polishing process is completed, the upper surface of the metal layer in the recessed area of the interconnect structure is lower than the upper surface of the interconnect structure, and the recess value is H2, where the metal layer in the recessed area has The second surface average roughness Ra2 is caused by the stress-free polishing process. The thickness of the metal layer removed by the stress-free polishing process is divided by Ra2 to obtain the ratio α. When a depression value is set, The minimum surface roughness of the metal after the stress-free polishing process is obtained. The thickness of the remaining metal layer after chemical mechanical planarization satisfies the following equation: Y = α / 6 ^★ H2-αRa1.

Description

Method for optimizing metal planarization process

The present invention relates to the field of semiconductor manufacturing, and in particular, to a method for optimizing a metal planarization process.

In the manufacturing process of interconnect structures, with the reduction of line width and the application of copper and low-k dielectric materials, the planarization technology of interconnect structures has put forward stricter requirements than in the past. Currently, there are at least two planarization techniques for planarizing metals on interconnect structures, including stress-based polishing processes, such as CMP, and stress-free polishing processes, such as electrochemical polishing. CMP uses polishing liquid and down pressure to remove metal. Although CMP is still the most commonly used planarization technology, with the development of semiconductor technology, bottlenecks and problems in the CMP process are gradually exposed. Because of the relatively strong mechanical force involved, CMP has many harmful effects on the underlying structure of the interconnect structure, especially when the k value of the dielectric material gradually decreases, the mechanical force will cause permanent damage to the dielectric material.

Electrochemical polishing uses a charged electrolyte to remove metal from interconnect structures. Because only the charged electrolyte contacts the metal surface, the electrochemical polishing process does not generate mechanical forces and does not cause damage to low-k dielectric materials. The charged electrolyte is sprayed on the metal surface and reacts with the metal, and the metal ions move Move to the cathode. In the electrochemical polishing process, the metal surface is regarded as an anode. Therefore, as a by-product, a large number of air bubbles are generated on the metal surface, causing the surface roughness of the metal to deteriorate. It is well known that the smaller the number of bubbles on the metal surface, the smaller the roughness of the metal surface after electrochemical polishing. Therefore, in order to improve the roughness of the metal surface, the number of bubbles on the metal surface needs to be controlled. The number of bubbles is proportional to the time of electrochemical polishing. The shorter the time of electrochemical polishing, the smaller the number of bubbles. The time of electrochemical polishing is directly proportional to the thickness removed by electrochemical polishing. The smaller the thickness of electrochemical polishing removal, the shorter the time of electrochemical polishing. Based on these relationships, it can be concluded that the smaller the thickness removed by electrochemical polishing, the smaller the roughness of the metal surface after electrochemical polishing.

In order to improve the efficiency of planarization and reduce the thickness removed by electrochemical polishing, CMP and electrochemical polishing are combined to planarize the metal on the interconnect structure. First, most of the metal on the upper surface of the interconnect structure is removed by CMP and a continuous metal layer covering the upper surface of the interconnect structure remains. The continuous metal layer can resist the mechanical force of CMP to protect the low-k dielectric material from damage. Then, electrochemical polishing is used to remove the continuous metal layer on the upper surface of the interconnect structure, exposing the underlying structure of the interconnect structure, such as blocking Floor. How to obtain the best remaining thickness after CMP, that is, the thickness removed by electrochemical polishing, is very important to control the final metal surface roughness and dish-shaped pits. If the thickness of the remaining metal layer after CMP is too thin, it is difficult to ensure that the metal layer completely covers the upper surface of the interconnect structure. The low-k dielectric material is likely to be damaged during the process; if the remaining metal layer is too thick after CMP, then It means that the thickness removed by electrochemical polishing is too thick, and the roughness of the metal surface after electrochemical polishing is not very good.

The invention proposes a method for optimizing a metal planarization process, which includes the following steps: a chemical mechanical planarization process is used to remove most of the metal layers on the upper surface of the interconnect structure until the thickness of the remaining metal layer reaches a predetermined value Y, and the remaining metal layer is A continuous layer covering the upper surface of the interconnect structure, wherein the remaining metal layer has a first surface average roughness Ra1, the first surface average roughness Ra1 is caused by chemical mechanical planarization; the stress-free polishing process is used to remove the interconnect The remaining metal layer on the upper surface of the structure. After the stress-free polishing process is completed, the upper surface of the metal layer in the recessed area of the interconnect structure is lower than the upper surface of the interconnect structure. The recess value is H2, where the recessed area The metal layer has a second average surface roughness Ra2, which is caused by stress-free polishing. The thickness of the metal layer removed by the stress-free polishing process is divided by Ra2 to obtain the ratio α; when the depression value H2 is set In order to obtain the minimum metal surface roughness after the stress-free polishing process, the thickness Y of the remaining metal layer after the chemical mechanical planarization process is The following ^{equation: Y = α / 6 ★ H2} -αRa1.

In summary, in order to resist the mechanical force of the chemical mechanical planarization process, to avoid damage to the underlying structure of the interconnect structure, and to improve the roughness of the metal surface after the stress-free polishing process, the thickness of the remaining metal layer after the chemical mechanical planarization process The following conditions need to be met: the thickness of the remaining metal layer is as thin as possible; the remaining metal layer is a continuous layer covering the upper surface of the interconnect structure; when the target depression value is set, the thickness of the remaining metal layer satisfies the equation: Y = α / 6 ^★ H2-αRa1.

101‧‧‧ substrate

102‧‧‧first dielectric layer

103‧‧‧Second dielectric layer

104‧‧‧hard mask layer

105‧‧‧First barrier

106‧‧‧Second barrier layer

107‧‧‧ metal layer

108‧‧‧ recessed area

In order to make the present invention more comprehensible to those skilled in the art, detailed descriptions of specific embodiments of the present invention are described below with reference to the accompanying drawings, wherein: FIG. 1 is a cross-sectional view of an interconnect structure, in which a metal layer on the interconnect structure Not removed; Figure 2 is a cross-sectional view after removing most metal layers on the upper surface of the interconnect structure using CMP; Figure 3 is a cross-sectional view after removing all remaining metal layers on the upper surface of the interconnect structure using electrochemical polishing ; Figure 4 is a cross-sectional view of the critical state of removing the remaining metal layer on the upper surface of the interconnect structure by electrochemical polishing, and there is still some metal residue on the unpatterned area of the interconnect structure; Cross-sectional view of all the metal residues on the unstructured areas of the interconnect structure; Figure 6 is a graph showing the relationship between the thickness removed by electrochemical polishing and the average roughness after CMP and electrochemical polishing processes; Figure 7 is A graph showing the relationship between the thickness removed by electrochemical polishing and the average roughness caused by the electrochemical polishing process; FIG. 8 shows the thickness removed by electrochemical polishing and the flatness caused by the CMP process. After roughness Ra1, CMP and electrochemical polishing processes average roughness Ra, electrical Graph of the correspondence between the average roughness Ra2 caused by the chemical polishing process, where α is equal to the thickness removed by the electrochemical polishing divided by the average roughness Ra2 caused by the electrochemical polishing process; Cross-section view of most of the metal layers on the upper surface of the interconnect structure with wide and different line densities.

The invention proposes a method for optimizing a metal planarization process. By controlling the thickness of the remaining metal layer on the upper surface of the interconnect structure after the CMP process, the roughness of the metal surface after the remaining metal layer is removed by the electrochemical polishing process is improved.

FIG. 1 shows a specific embodiment of the interconnection structure. Those skilled in the art can understand that the structure of the interconnection structure is not limited to the specific embodiment shown in FIG. 1, and the structure of the interconnection structure may be different according to different process requirements. The interconnect structure shown in FIG. 1 includes a substrate 101, a first dielectric layer 102 formed on the substrate 101, a second dielectric layer 103 formed on the first dielectric layer 102, and a second dielectric layer 103 formed on the second dielectric layer 103. Hard mask layer 104, recessed areas 108 (such as trenches, vias, etc.) formed on hard mask layer 104, second dielectric layer 103, and first dielectric layer 102, formed on hard mask layer 104 and recessed The first barrier layer 105 on the sidewall and the bottom of the advance region 108, the second barrier layer 106 formed on the first barrier layer 105, and the metal layer 107 formed on the second barrier layer 106 and filling the recessed region 108 .

A metal layer is formed on the second barrier layer 106 and fills the recess After the region 108, the next step is to remove the metal layer 107 on the upper surface of the interconnect structure. First, a polishing process with stress, such as CMP, is used to remove most of the metal layer 107 and retain a certain thickness of the metal layer 107; in order to resist the mechanical force of CMP, avoid damage to the underlying structure of the interconnect structure, and improve the electrochemical polishing process After the metal surface roughness, the thickness of the remaining metal layer 107 after the CMP process is preferably as thin as possible, and the remaining metal layer 107 is a continuous layer covering the upper surface of the interconnect structure, as shown in FIG. 2.

Then, a stress-free polishing process, such as electrochemical polishing, is used to remove the remaining metal layer 107 on the upper surface of the interconnect structure, as shown in FIG. 3. After the remaining metal layer 107 on the upper surface of the interconnect structure is removed, the second barrier layer 106 is exposed. Considering the second barrier layer 106 and the first barrier layer 105 and the hard mask layer 104 on the upper surface of the interconnect structure, It is removed in a subsequent process, and the upper surface of the metal layer 107 in the recessed area 108 is flush with or slightly lower than the upper surface of the second dielectric layer 103.

The present invention will also describe how to obtain the thickness of the remaining metal layer 107 after CMP.

In order to simplify the calculation, it is assumed that the metal layers on the upper surface of the interconnect structure have the same thickness, in other words, regardless of whether the line width and line density of the interconnect structure are the same, before using CMP to remove the metal layer on the upper surface of the interconnect structure, The thickness of the metal layer on the upper surface of the connection structure is the same. After the CMP and electrochemical polishing processes are completed, the maximum surface roughness of the metal satisfies the following equation: Rt = Rt1 + Rt2

Among them, Rt is the metal surface after the CMP and electrochemical polishing processes are completed The maximum roughness, Rt1 is the metal surface roughness caused by the CMP process, and Rt2 is the metal surface roughness caused by the electrochemical polishing process.

Based on the normal distribution of the data, under the condition of 3σ, Rt = 6Ra, Ra is the average roughness of the metal surface after the CMP and electrochemical polishing processes are completed, and the relationship is as follows: Rt = Rt1 + Rt2 = 6Ra1 + 6Ra2

Among them, Ra1 is the average roughness of the metal surface caused by the CMP process, and Ra2 is the average roughness of the metal surface caused by the electrochemical polishing process.

As shown in FIG. 5, if the second barrier layer 106 and the first barrier layer 105 and the hard mask layer 104 on the upper surface of the interconnect structure are not considered in a subsequent process, the depression value H2 is equal to that of the second barrier layer 106. The surface height is subtracted from the upper surface height of the metal layer 107 in the recessed area 108.

Rt)，只有滿足H2

Rt，金屬殘留才能被完全去除。CMP後剩餘金屬層107的厚度與最小凹陷值之間的關係滿足以下方程式：Y=α/6(H2-Rt1)=α/6^★H2-αRa1 As shown in FIG. 4, the critical state of the remaining metal layer on the upper surface of the interconnect structure is removed by electrochemical polishing. The upper surface of the metal layer 107 in the recessed area 108 is flush with the upper surface of the second barrier layer 106. There is still some metal 107 remaining on the non-patterned area of the interconnect structure. Generally, the remaining metal height H1 is equal to Rt. It can be seen that after the CMP and electrochemical polishing processes are completed, the metal surface roughness, especially Rt, determines the minimum depression value. The depression value H2 cannot be less than Rt (H2

Rt), only meets H2

Rt, the metal residue can be completely removed. The relationship between the thickness of the remaining metal layer 107 and the minimum depression value after CMP satisfies the following equation: Y = α / 6 (H2-Rt1) = α / 6 ^★ H2-αRa1

Among them, Y is the optimal thickness of the remaining metal layer after CMP; H2 is the minimum depression value, which is a target value set according to the process requirements; In this equation, H2 is a known quantity, α is equal to the thickness of the metal layer removed by electrochemical polishing divided by Ra2; α is an empirical equation obtained through experiments; the ratio α is determined by the type, viscosity, temperature, and substrate of the electrolyte The speed of rotation, the speed of horizontal movement, and the current, voltage, and so on.

It can be known from the above that in order to resist the mechanical force of CMP, avoid damage to the underlying structure of the interconnect structure, and improve the roughness of the metal surface after electrochemical polishing, the thickness of the remaining metal layer after CMP needs to meet the following conditions: As thin as possible; the remaining metal layer is a continuous layer covering the upper surface of the interconnect structure; when a target depression value is set, the thickness of the remaining metal layer satisfies the equation: Y = α / 6 (H2-Rt1) = α / 6 ^★ H2 -αRa1.

If the second barrier layer 106, the first barrier layer 105, and the hard mask layer 104 on the upper surface of the interconnect structure are considered to be removed in subsequent steps, the actual thickness of the remaining metal layer after CMP satisfies the following equation: Y '= YY _b -Y _m

Among them, Y ′ is the actual thickness of the remaining metal layer after CMP, Y _b is the total thickness of the second barrier layer 106 and the first barrier layer 105, and Y _m is the thickness of the hard mask layer 104.

FIG. 9 shows another embodiment of the present invention. The interconnect structure has different line widths and line densities. In the electroplating process, the line width and line density cause step height differences in different line areas, which in turn determines the consistency of the metal layer height. The height of the metal layer overlying the non-patterned area is considered to be 0 angstroms and is used as a reference plane. Generally, the height of the metal layer covering the wide line is lower than the reference plane; otherwise, the metal covering the narrow line is The layer height is higher than the reference plane. In order to completely remove the metal layer on the upper surface of the interconnect structure, the metal layer on the narrow line must be completely removed. On the other hand, since the electrochemical polishing process is a conformal process, when the metal layer on the narrow line is completely removed, the electrochemical polishing process will cause the depression of the wide line. The depth of the depression depends on the step height difference and line density after the CMP process. The depression value satisfies the following equation: Rx = Tmin / Dx-Tx

Among them, Rx is the depression value of the line width x area, Tmin is the step height of the minimum line width relative to the reference plane, Dx is the density of the line width x area, and Tx is the step height of the line width x area relative to the reference plane.

For example, if the narrowest line has a line width of 28 nm, the narrowest line has a step height of 200 Å with respect to the reference plane, the wide line has a line width of 10 μm, and the wide line has a step height of -100 Å with respect to the reference plane. The density is 50%. When the metal layer on the narrowest line is completely removed, the depression value in the 10μm line width area is equal to: R10 = Tmin / D10-T10 = 200/50%-(-100) = 500 Angstrom

Combined with the equation Y '= YY _b -Y _m , if the interconnect structure has different line widths and line densities, the actual thickness of the remaining metal layer after CMP satisfies the following equation: Y "= α' / 6 (H2 + Tmin-Rt1) = α '/ 6 ^★ (H2 + Tmin) -α'Ra1

α ’= (Y’ + Tmin) / Ra2 ’

Among them, Y ”is the actual thickness of the remaining metal layer after the chemical mechanical planarization process, and Tmin is the step height of the minimum line width relative to the reference plane.

Ra2 ’can be obtained according to the following two aspects: 1) The thickness Y ′ + Tmin removed by electrochemical polishing (stressless polishing process); 2) The relationship between the thickness removed by electrochemical polishing and the average roughness of the metal surface caused by the electrochemical polishing process, as shown in FIG. 7.

In summary, in order to completely remove the metal layer on the upper surface of the interconnect structure, while obtaining the target depression value and the minimum metal surface roughness, the thickness of the remaining metal layer after CMP should meet the requirements of the equation, and the step height difference inside the wafer should be as small as possible. The possible small, especially narrow step heights should be optimized and tend to zero.

The above description is intended to illustrate and describe the present invention, and does not disclose or limit the present invention in detail. Although the present invention is described with specific embodiments, examples, and applications, obvious modifications and substitutions in the art will still fall into the present invention. protected range.

101‧‧‧ substrate

102‧‧‧first dielectric layer

103‧‧‧Second dielectric layer

104‧‧‧hard mask layer

105‧‧‧First barrier

106‧‧‧Second barrier layer

107‧‧‧ metal layer

108‧‧‧ recessed area

Claims (7)

A method for optimizing a metal planarization process, comprising: using a chemical mechanical planarization process to remove most metal layers on an upper surface of an interconnect structure until a thickness of a remaining metal layer reaches a predetermined value Y, and the remaining metal layer is a cover A continuous layer on the upper surface of the interconnect structure, wherein the remaining metal layer has a first surface average roughness Ra1, the first surface average roughness Ra1 is caused by chemical mechanical planarization; the stress-free polishing process is used to remove the interconnect structure For the remaining metal layer on the upper surface, after the stress-free polishing process is completed, the upper surface of the metal layer in the recessed area of the interconnect structure is lower than the upper surface of the interconnect structure, and the recess value is H2. The metal layer has a second average surface roughness Ra2. The second average surface roughness Ra2 is caused by stress-free polishing. The thickness of the metal layer removed by the stress-free polishing process is divided by Ra2 to obtain the ratio α. When the depression value H2 is set In order to obtain the minimum metal surface roughness after the stress-free polishing process, the thickness Y of the remaining metal layer after the chemical mechanical planarization process satisfies the following ^{Program: Y = α / 6 ★ H2} -αRa1. The method according to claim 1, wherein before the metal layer on the upper surface of the interconnect structure is removed by a chemical mechanical planarization process, the metal layers on the upper surface of the interconnect structure have the same thickness. The method according to claim 1, wherein after the chemical mechanical planarization process and the stress-free polishing process are completed, the maximum roughness of the metal surface satisfies the following equation: Rt = Rt1 + Rt2 Among them, Rt is the maximum roughness of the metal surface after the chemical mechanical planarization process and the stress-free polishing process are completed, Rt1 is the metal surface roughness caused by the chemical mechanical planarization, and Rt2 is the metal surface roughness caused by the stress-free polishing process. The method according to claim 3, characterized in that, based on the statistical normal distribution, under the condition of 3σ, Rt satisfies the following equation: Rt = Rt1 + Rt2 = 6Ra1 + 6Ra2. The method according to claim 3, characterized in that the depression value H2

Rt. The method according to claim 1, wherein the interconnect structure includes at least one barrier layer and a hard mask layer. Considering that the barrier layer and the hard mask layer on the upper surface of the interconnect structure are removed, chemical mechanical The actual thickness of the remaining metal layer after the planarization process satisfies the following equation: Y '= YY _b -Y _m where Y' is the actual thickness of the remaining metal layer after the chemical mechanical planarization process, Y _b is the thickness of the barrier layer, and Y _m Is the thickness of the hard mask layer. The method according to claim 6, characterized in that the interconnect structure has different line widths, the height of the metal layer covering the area without a pattern is used as a reference plane, and the remaining metal layer after the chemical mechanical planarization process The actual thickness satisfies the following equation: Y "= α '/ 6 ^★ (H2 + Tmin) -α'Ra1 α' = (Y '+ Tmin) / Ra2' where Y" is the remaining metal layer after the chemical mechanical planarization process Actual thickness, Tmin is the height of the minimum line width relative to the reference plane. Ra2 'can be obtained according to the following two aspects: the thickness removed by the stress-free polishing process Y' + Tmin; the thickness removed by the stress-free polishing process and the stress-induced polishing process The relationship between the average roughness of the metal surface.