TW201742226A - Corrected grain for wafer/die stack - Google Patents

Abstract

Representative devices and techniques of the present invention provide corrections for defective grains in a wafer-to-wafer stack or die stack. The grain is coupled to the die in the stack including the defective grains. The modified die electrically replaces the defective die. Alternatively, dummy dies can be coupled to other die stacks in the wafer-to-wafer stack to adjust the height of the stack.

Description

Corrected grain for wafer/die stack

This application relates to modified dies for wafer/die stacking.

There is a continuing demand for greater memory density in limited coverage areas. While advances in technology have reduced the size of memory devices, various applications and consumer markets have reduced the area that memory devices can occupy and limit the amount of power they can consume. One solution to this situation involves vertically stacking the memory device dies. For example, memory grains can be stacked on top of one another such that multiple grains occupy an area of a single die. Stacked dies can result in larger memory bandwidths with smaller form factors and less power usage.

Depending on various techniques including high frequency wide memory (HBM) and hybrid memory cube (HMC) configurations, 2, 4 or up to 8 dynamic random access memory (DRAM) dies can be stacked vertically and can also include memory The body controller is, for example, a base layer. In various methods, stacked memory cells can be interconnected using through-transistor vias (TSVs), microbumps, or other interconnect/communication schemes. The three-dimensional stacking of memory grains can, for example, replace a single memory die on a circuit board.

However, implementing these stacked memory configurations presents various challenges. For example, some shuffling techniques can be complex and/or expensive. In addition, mass production manufacturing processes often do not completely eliminate defects, even with high-volume production techniques. Each batch of memory chips produced has one The determined percentage includes defective grains. The grain (D2D) stack of memory grains containing at least one defective grain constitutes a defective stack. If the defective stack is discarded as waste, many of the discarded grains in the stack are not defective. Therefore, discarding defective stacks increases the number of individual good grains that are discarded as waste.

In accordance with an aspect of the present invention, a microelectronic assembly is disclosed that includes a plurality of semiconductor dies coupled in a die stack, the number of grains in the die stack being preselected to include The predetermined capacity of the die stack is required to be at least one additional die in which at least one of the die is a non-operating die configured to be unused. A die or a die that is only used to electrically couple two other die in the die stack.

In accordance with another aspect of the present invention, a microelectronic configuration is disclosed that includes a plurality of semiconductor wafers coupled in a wafer-to-wafer stack, each wafer including a plurality of dies, the wafer being Aligning to couple the plurality of dies in each wafer to form a plurality of die stacks, each die stack being aligned along an axis substantially transverse to a plane of at least one of the wafers; One or more additional dies coupled to the dies in the one or more die stacks to form one or more modified stacks, one or more of the plurality of dies in each of the modified stacks The grains and the one or more additional grains include at least one inoperative grain.

In accordance with yet another aspect of the present invention, a method is disclosed that includes: coupling a plurality of semiconductor wafers in a wafer-to-wafer stack, each wafer including a plurality of dies; aligning the wafers with Having the plurality of dies in each wafer coupled to form a plurality of die stacks; identifying defective dies within the die stack; and coupling the modified dies to include the defective crystals Grains in the grain stack of the grains.

102‧‧‧ wafer

104‧‧‧ Carrier

106‧‧‧ grain

108‧‧‧ layer

202‧‧‧Wafer to Wafer Stacking/W2W Stacking

204‧‧‧Grade to die stacking/D2D stacking

302‧‧‧ grain

304‧‧‧ grain

306‧‧‧ grain

308‧‧‧Filling materials

310‧‧‧Modify the stack

402‧‧‧ Carrier

502‧‧‧Logical layer

504‧‧‧Surface Mount Technology/SMT

702‧‧‧Revised Wafer

800‧‧‧ exemplary process

802~808‧‧‧Steps in an exemplary process

The detailed description of the present invention is made with reference to the accompanying drawings. In the drawings, the left-most numerical value of the component symbol indicates the first appearance of the component symbol. The same element symbols used in the different figures represent similar or identical items.

For purposes of discussion herein, the devices and systems illustrated in the drawings are shown as having a plurality of components. As described herein, various implementations of devices and/or systems may include fewer components and remain within the scope of the present disclosure. In the alternative, other implementations of the device and/or system may include additional components, or various combinations of the components described, and remain within the scope of the present disclosure.

Figure 1 illustrates an example of joining a wafer to a carrier in accordance with an implementation.

2 illustrates an example of joining multiple wafers into a stack, according to an embodiment.

3 illustrates an example of identifying a non-operating die and adding additional die to a stack including inoperative die, in accordance with an embodiment.

4 illustrates an example of cutting a wafer stack into a plurality of die stacks in accordance with an embodiment.

Figure 5 illustrates some examples of mounting a die stack to a logic layer in accordance with various embodiments.

Figure 6 illustrates some alternative locations of additional dies in the stack, in accordance with various embodiments.

7 illustrates an example of adding additional wafers to a wafer stack to modify one or more defective dies, in accordance with an embodiment.

Figure 8 is a flow diagram of an exemplary process for modifying defective dies in a stack in accordance with an implementation.

Overview

Representative implementations of the apparatus and techniques of the present invention provide additional dies in a wafer-to-wafer (W2W) stack or die (D2D) stack. In various embodiments, the additional die includes additional grains having a die type in the stack. For example, the dies in the stack can include dynamic random access memory (DRAM) dies (or other microelectronic components), and the additional dies can include additional DRAM dies (or similar microelectronic components). .

In various embodiments, defective dies can be identified, for example, during manufacturing testing or during post-manufacturing testing. In practice, the additional grains include modified grains and they are coupled to the grains in the stack including the defective grains. For example, additional dies may be coupled to the dies in the respective stack using surface mount technology (SMT), direct bond interconnect (DBI) technology, or other techniques. In an embodiment, the additional grains replace the defective grains in the respective stack electrically (eg, functionally).

Alternatively, the additional dies may include dummy dies that may be coupled to the die stack in the wafer to wafer stack to adjust the height of the other stacks. For example, if the modified die is coupled to a D2D stack, the dummy die can be coupled to an adjacent D2D stack to keep the overall height of the stack equal. In various embodiments, the dummy die can include an operational die, a non-operational die, a filler (encapsulated material), a portion of the reconstituted wafer, a blank ( Blank) Carrier or similar.

In some implementations, the modified wafer is coupled to the wafer in the W2W stack. In reality In practice, the modified wafer includes one or more additional dies. The modified wafer can be aligned to couple additional dies including the modified dies to the D2D stack, which has defective dies in their respective stacks.

Various implementations and configurations are discussed with reference to electrical and electronic components and different carriers. Although specific components (ie, integrated circuit (IC) wafer dies, wafers, substrates, printed circuit boards (PCBs), memory storage devices, etc.) are mentioned, this is not limiting, but For ease of discussion and ease of explanation. The techniques and devices discussed are suitable for any type or number of packages, package circuits or components, circuits (eg, integrated circuits (ICs), hybrid circuits, ASICS, memory devices, processors, etc.), electrical Components (eg, sensors, transistors, diodes, etc.), combinations of components, carrier structures (eg, wafers, substrates, panels, sheets, PCBs, etc.) or the like. Each of these components, circuits, wafers, structures, and the like may be collectively referred to as "microelectronic components."

The present invention is explained in more detail below using a plurality of examples. Although various implementations and examples are discussed herein and below, further implementations and examples can be accomplished by a combination of features and elements of the various embodiments and examples.

Exemplary wafer-to-wafer and die stacking

FIG. 1 illustrates an example of joining wafer 102 to carrier 104 in accordance with an implementation. In practice, wafer 102 is bonded to carrier 104 as a component for forming a wafer-to-wafer (W2W) stack. In various embodiments, wafer 102 is a semiconductor wafer that has been processed and/or fabricated to include various microelectronic components formed as integrated wafer (IC) die 106, including electronic components, devices, circuits, systems... and many more. For example, in practice, die 106 includes a dynamic random access memory (DRAM) storage device or the like.

As shown in FIG. 1, wafer 102 is comprised of a plurality of dies 106. The illustrations for wafer 102 shown in FIG. 1 are not limiting, and in various embodiments, wafer 102 may include few (less than ten) to very many (eg, hundreds or thousands) The die 106. In practice, each die 106 includes an interconnect layer 108. Layer 108 provides interconnection for each die 106 and may include surface mount technology (SMT) features such as terminals, pads, ball grid arrays (BGAs), microbumps, wire bond connections, via terminations, or the like. .

In another example, layer 108 can include direct bond interconnect (DBI) features such as a hafnium oxide layer and a copper pad. In this embodiment, the yttria layer can be combined with a similar layer at room temperature, and the copper liner, for example, can be heated to expand and fuse to other copper surfaces (or other conductive surfaces). In practice, the nano-smooth connection is derived from the DBI technique.

In a further example, layer 108 may include a redistribution layer (RDL) or similar system to map connections from points on the electronic components of die 106 to terminals, junctions, and the like on mating surfaces of die 106. By.

As shown in FIG. 1, at (A) and (B), wafer 102 is bonded to carrier 104 using SMT, DBI, or other coupling techniques. At (C), the wafers 102 may be planarized, or otherwise thinned (eg, by grinding, blasting, etching, and various combinations thereof, etc.) to, for example, expose connection terminals, such as through 矽Crystal via (TSV) or the like.

Referring to FIG. 2, as shown at (A), a plurality of wafers 102 are bonded to the wafer 102/carrier 104 combination formed with reference to FIG. The resulting W2W stack 202 is shown at (B). For example, the W2W stack 202 includes a plurality of interconnected wafers 102 that are coupled together in a stack, one on top of the other, and via SMT, DBI, Or other coupling technologies are linked together.

In an embodiment, the wafers 102 in the W2W stack 202 are aligned such that the plurality of dies 106 in each wafer 102 are coupled to form a plurality of die (D2D) stacks 204. For example, each D2D stack 204 includes a plurality of interconnected dies 106 that are coupled together in a stack, one on top of the other, and via SMT, DBI, or other The coupling technology is linked together. In practice, each die stack 204 is aligned along an axis that is generally transverse to the plane of the at least one wafer 102. In various implementations, the dies 106 in the D2D stack 204 are interconnected and/or communicated with each other using TSVs, microbumps, or the like and/or are interconnected and/or communicated with each other. In various embodiments, even quantities of wafers are joined to form a W2W stack 202, and a D2D stack 204 comprising the same even number of stacked dies is likewise formed.

Exemplary extra grain

In various implementations, as shown in FIGS. 3 and 4, the microelectronic assembly includes a plurality of semiconductor dies 106 coupled in a die stack 204, wherein the number of dies 106 in the die stack 204 is based on dies The desired capacity of the stack 204 is pre-selected. For example, four DRAM dies of 1 gigabyte capacity can each be pre-selected to be stacked in the D2D stack 204 to produce the desired 4 GB memory storage component.

In various implementations, at least one of the die 106 in the die stack 204 is a non-working die, is configured to be unused, or is used only in the die stack with two other die electrical Grains coupled together. In practice, as shown in FIG. 3(b), additional dies (304 or 306) are coupled to the dies 106 in the die stack 204 to form a plurality of dies and additional dies (304). Or 306) the modification stack 310. In practice, the modification stack 310 includes at least one A grain that does not work. In other words, the modified stack 310 includes a pre-selected number (eg, 4...etc.) of operational dies (106, or 106 and 304) and a non-operating die (106, 302 or 306). In other words, in an embodiment, the number of dies 106 in the die stack 204 is preselected to include at least one additional die 106 that is greater than the desired capacity of the die stack 204. As in the above example, the number of dies 106 in the die stack 310 can include an odd number, and an even number of dies 106 are used for data memory functions. For example, the operating die can include a die 106 or a combination of die 106 and modified die 304. Moreover, the inoperative grains may include additional grains 106, defective grains 302, or dummy grains 306. In various examples, additional dies (304 or 306) may be added to the D2D stack 204 to form a modified stack 310, modify defective dies 302 in the D2D stack 204, decide to modify the overall height of the stack 310, provide excess or The spare die 106 is used for various other purposes.

In various embodiments, the inoperative die includes known operational dies 106, known inoperable dies (302, 306), known defective dies 302, a portion of a reconstituted wafer, or the like. By. In an example, when the inoperative die is set to modify the topmost die in stack 310, the inactive die includes dummy die 306. In another example, when the inoperative grains are disposed between the dies in the modification stack 310 or are configured to modify the bottommost dies of the stack 310, the inoperative dies include inoperative Grains (ie, defective grains) 302.

In various examples, modifying the preselected number of dies in stack 310 includes an even quantity. In an example, the modified stack 310 includes an even number of operational dies (106, or 106 and 304) plus non-working dies (106, 302 or 306). In other examples, the number of wafers in the wafer-to-wafer stack 202 includes an even number, and the wafer-to-wafer stack Each of the modified stacks 310 includes an even number of operational dies (106, or 106 and 304) plus non-working dies (106, 302 or 306).

In practice, the inoperative dies (106, 302 or 306) are passively coupled to modify at least one electrical signal between the dies (106, 304) in the stack 310. The inoperative grains (106, 302 or 306) are interconnected as described above to modify the dies (106, 304) in the stack 310 and serve as passive interconnects.

In an embodiment, the microelectronic assembly 204 can include more than one additional die (304 or 306). For example, one or more additional dies (304 or 306) may be coupled to the die 106 in the D2D stack 204 or to another additional die (304 or 306) to form the modified stack 310. In this case, the modification stack 310 includes two or more inoperative grains (106, 302 or 306).

Additional grains as modified grains or dummy grains

Referring to FIG. 3, die 106, wafer 102, W2W stack 202, and/or D2D stack 204 can be tested during and/or after fabrication. One or more defective grains are revealed or recognized during the test. For example, as shown at (A) in FIG. 3, two defective dies 302 are identified, and in this example they are located in two of the four D2D stacks 204 illustrated.

In practice, as shown at FIG. 3(B), the trim die 304 is coupled to the die 106 in the D2D stack 204 including the defective die 302. For example, in the illustration at (B), the modified die 304 is coupled to the die 106 in the first D2D stack 204 and the other modified die 304 is coupled to the die 106 in the third D2D stack 204, which This is because the first and third D2D stacks 204 contain defective grains 302. In various embodiments, the modified die 304 is used SMT, DBI or other coupling techniques are coupled to the die 106.

In some embodiments, as shown in FIG. 3(B), the trim die 304 is coupled to the topmost die 106 in the D2D stack 204 including the defective die 302. In other embodiments, the trim die 304 can be coupled to another die 106 in the D2D stack 204. For example, the trim die 304 can be coupled to the bottommost die 106 or coupled to another die 106 as desired.

In practice, the modified die 304 electrically replaces (e.g., compensates) the defective die 302 within the respective D2D stack 204. In other words, the trim die 304 operates as a functionally equivalent alternative and performs the entire electronic function of the non-functional defective die 302 in the D2D stack 204. Thus, the modified die 304 includes repeating microelectronic components or microelectronic components that are functionally equivalent to the defective die 302. For example, where the die 106 includes a DRAM device, the trim die 304 also includes the same or equivalent DRAM device.

In various embodiments, again as shown at FIG. 3(B), one or more "dummy dies" 306 are coupled to the dies 106 of other D2D stacks 204 that do not include defective dies 302. For example, the dummy die 306 can adjust the overall height of the other D2D stacks such that they are level with the D2D stack 204 with the modified die 304. In an embodiment, dummy die 306 may comprise a operable die, an inoperable die, a filler (encapsulant) material, a portion of a reconstituted wafer, or the like. Alternatively, the W2W stack 202 may be covered (overmolded) with a filler material 308 (such as cerium oxide) or another high-k dielectric. In some cases, filler material 308 may replace dummy die 306, for example, when those locations are left blank.

In various implementations, as shown in FIG. 4, the W2W stack 202 can include a carrier 402. For example, carrier 402 can be added to the top of W2W stack 202 for W2W Protection, processing, and/or processing of stack 202. In various embodiments, carrier 402 includes a "virtual wafer" like dummy die 306, which can be selected to be thick enough to be used as carrier 402.

In another implementation, the W2W stack 202 can be cut into individual D2D stacks 204, as shown in Figure 4(C). In practice, the cut W2W stack 202 separates the D2D stacks 204 from each other and from the W2W stack 202. Individual D2D stacks 204 can then be prepared for use with a variety of applications. In practice, as shown at Figure 4(C), at the time of dicing, the carrier layer 402 (if included) is also segmented to couple the carrier layer 402 to the grains in the D2D stack 204 (e.g., grain 106, defective crystal grains 302, modified crystal grains 304, dummy crystal grains 306, etc.). In practice, carrier layer 402 can determine the overall height of D2D stack 204. In practice, as shown at Figure 4(C), the lower carrier 104 can be removed before or after the cutting of the W2W stack 202.

In an embodiment, as shown in FIG. 5, D2D stack 204 can be installed to logic or control layer 502 for various applications. In some implementations, logic layer 502 provides control for the microelectronic components of die 106 in D2D stack 204. For example, in one implementation, logic layer 502 provides control logic for memory storage components (eg, DRAM...etc.) of D2D stack 204.

In practice, logic layer 502 is coupled to die 106 in D2D stack 204 using SMT, DBI, or other coupling techniques. For example, Figure 5(B) shows an example of logic layer 502 being coupled to the bottommost die 106 using DBI techniques or the like. Surface mount technology (SMT) 504, such as a ball grid array (BGA), is shown at (C) and (D) to couple logic layer 502 to the bottommost die 106 in D2D stack 204. In an alternate embodiment, the logic layer 502 can be coupled to another die 106 instead of the die 106 at the bottom of the D2D stack 204.

Referring again to FIG. 5, in practice, additional dies (such as, for example, modified dies 304) may also be used in place of carrier layer 402 on D2D stack 204. For example, like (D) As shown, additional dies (eg, trim dies 304) may be preselected to have a thickness that determines the overall height of the D2D stack 204. In an example, the trim die 304 can be coupled to the topmost die 106 in the D2D stack 204. For example, in the example shown at (D), the trim dies 304 are coupled to the topmost dies 106 using SMT techniques 504 (eg, metallic bumps, BGAs...etc.). In other embodiments, the trim die 304 can be coupled to the topmost die 106 using DBI or another type of coupling technique.

FIG. 6 illustrates some alternative locations for placing the trim die 304 in the D2D stack 204 in accordance with various embodiments. For example, the cut D2D stack 204 shown at (A) includes inoperative grains (eg, defective grains 302). At (B), (C), and (D), additional dies, such as modified dies, are coupled to the D2D stack 204 in various configurations. At (B), it is shown that the modified die 304 is coupled between the bottommost die 106 and the logic layer 502 using DBI techniques or the like. This produces a nano-level smooth joint between the modified die 304 and the surface of the die 106 and logic layer 502. At (C), the trim die 304 is shown coupled to the bottommost die 106 using surface mount technology (SMT) (eg, bumping). The modified die 304 is coupled to the logic layer 502 using DBI techniques or the like. At (D), the trim die 304 is shown to be coupled between the bottommost die 106 and the logic layer 502 using SMT techniques (eg, bump formation) or the like.

In an alternative implementation, additional dies (eg, trim dies 304) may be coupled to dies 106 that are different than the bottommost dies 106 in stack 204. Moreover, in some implementations, the modified die 304 can be coupled to the defective die 302.

Referring to FIG. 7, in some implementations, additional dies (such as trim dies 304, dummy dies 306, or the like) can be added to the D2D stack 204 at the wafer level. in other words, One or more trim wafers 702 (eg, any number desired) may be added to the W2W stack 202 prior to cutting. For example, Figure 7 shows two W2W stacks 202 at (A) and (B). In practice, the modified wafer 702 is coupled to the wafer 102 in the W2W stack 202 (as shown at (A)) or to the modified wafer 702 (as shown at (B)).

The correction wafer(s) 702 include one or more additional dies (eg, such as modified dies 304 or dummy dies 306), and the modified wafer 702 is aligned to provide additional The die is coupled to the die (106, 302, 304) in the D2D stack 204. For example, the modified wafer 702 is aligned such that one or more modified dies 304 are coupled to the dies (106, 302, 304) in the D2D stack 204, and the defective dies 302 are included in the D2D stack 204. . Additionally, the modified wafer 702 can be aligned such that one or more dummy dies 306 are coupled to the dies (106, 302, 304) in the D2D stack 204, as described above.

In practice, the modified wafer 702 and additional dies (304, 306) are coupled using SMT, DBI, or other coupling techniques. Moreover, the modified die 304 in the modified wafer 702 electrically (eg, functionally) replaces the defective die 302 in the D2D stack 204 including the defective die 302. In practice, the modified wafer 702 includes additional or additional wafers 102. In other words, the modified wafer 702 includes the same or equivalent wafer as the wafer 102 (which is a wafer-based component).

As shown in FIG. 7, the revision wafer 702 can also include one or more inoperative dies (106, 302 or 306). For example, the modified wafer 702 can include defective grains 302. Thus, in some cases, it may be desirable to include two or more modified wafers 702 to the W2W stack 202. As described above, the modified die 304 of the modified wafer 702 is configured and coupled to the D2D stack 204 based on identifying defective die 302 within the stack 204 (or wafer 102). Correction crystal The excess or inoperable correction die 304 of the circle 702 can be used to determine the stack height of the placeholders, dummy dies 306, or the like unless/until to replace the defective crystals in their respective D2D stack 204 Granule 302.

In various embodiments, carrier layer 402 can be added to the top of W2W stack 202, lower carrier 104 can be removed from the bottom of W2W stack 202, and D2D stack 204 can be coupled after coupling correction wafer 702(s) The W2W stack 202 is cut out. The cut D2D stack 204 can be processed as discussed above for Figures 5 and 6.

The techniques, components, and devices described herein for modifying die 304 and modifying wafer 702 are not limited to the descriptions of FIGS. 1-7, and may be applied to other designs without departing from the scope of the present disclosure. Type, configuration, and structure including other electrical components. Unless otherwise indicated, the specifically described alternative components can be used to implement the techniques described herein. Many variations may have fewer elements than those illustrated in the examples shown in Figures 1-7, or they may have more or alternative elements than those shown.

In addition to describing devices, devices, structures, components, configurations, systems, or the like, Figures 1 through 7 and their respective discussion also illustrate remediation of multilayer microelectronic components (for example, such as W2W stack 202 or An exemplary process for the occurrence of defective dies 106 in the D2D stack 204).

Exemplary process

FIG. 8 is a flow diagram of an exemplary process 800 for modifying defective dies in a multilayer microelectronic stack (eg, such as W2W stack 202 or D2D stack 204) in accordance with various implementations. The modified dies (e.g., modified dies 304) can be coupled to the dies in the stack to electrically and functionally replace the defective dies in the stack.

The order of processes described herein is not intended to be construed as limiting, and any number of described process steps may be combined in any order in order to practice multiple processes or multiple alternative processes. In addition, individual steps may be eliminated from the process without departing from the spirit and scope of the subject matter described herein. In addition, the process may be practiced in any suitable material or combination thereof without departing from the spirit and scope of the subject matter described herein. In alternative implementations, other techniques may be included in the process in various combinations and remain within the scope of the present disclosure.

At step 802, the process includes coupling a plurality of wafers (eg, such as wafer 102) in a wafer-to-wafer (W2W) stack (eg, such as W2W stack 202). In practice, multiple wafers can be coupled in a W2W stack via surface mount technology (SMT) or direct bond interconnect (DBI) technology.

In practice, each wafer includes a plurality of dies (e.g., such as dies 106). In practice, the plurality of dies includes a plurality of memory storage devices, such as dynamic random access memory (DRAM) devices. In other implementations, the plurality of dies include other types of microelectronic components.

At step 804, the process includes aligning the wafers to couple a plurality of dies in each wafer to form a plurality of die (D2D) stacks (eg, such as D2D stack 204). In practice, multiple dies may be coupled in the D2D stack via SMT, DBI, or another technique.

At step 806, the process includes identifying defective dies within the D2D stack. In various implementations, defective grains can be identified during manufacturing testing, quality control testing, or the like.

At step 808, the process includes coupling the modified die to the die in the D2D stack including the defective die. In various embodiments, the modified die can use SMT (for example In other words, such as using microbumps, DBI or other die coupling techniques, the die is coupled into the D2D stack. Furthermore, the modified dies can be coupled to any of the dies in the D2D stack.

In practice, the process includes electrically replacing the defective grains in the D2D stack with modified grains. The trim die can be interconnected and communicated with other die in the D2D stack using through-transistor vias (TSVs), microbumps, or the like. The modified die electrically and functionally replaces the defective die in the D2D stack.

In practice, the process includes coupling one or more dummy dies to dies in one or more other D2D stacks that do not include defective dies. In an embodiment, one or more dummy die adjustments do not include the overall height of one or more other D2D stacks of defective grains. For example, the dummy dies can compensate for the D2D stack with the modified dies to equalize the height of the various D2D stacks.

In practice, the process includes coupling one or more modified wafers to a wafer in a W2W stack. In other words, the trim dies are added to the D2D stack at the wafer level. In practice, the one or more modified wafers include one or more modified dies. For example, the process includes aligning one or more modified wafers to couple one or more modified dies to the dies in one or more D2D stacks including the defective dies.

In practice, the process includes coupling a carrier layer to a wafer in a W2W stack, to a dummy die, and/or to a modified die. In an embodiment, the thickness of the trim or dummy die may be preselected to determine the overall height of the D2D stack. In such embodiments, the modified die or dummy die can act as a carrier layer in the D2D stack and can also be set as the topmost layer in the D2D stack.

In practice, the process includes cutting from the W2W stack including trimming the die D2D stacking. In another implementation, the process includes coupling a D2D stack including modified grains to a logic layer comprised of one or more control members. In practice, the logic layer provides control for microelectronic components (such as memory devices) in the die.

In alternative implementations, other techniques may be included in the process in various combinations and remain within the scope of the present disclosure.

in conclusion

Although the implementation of the present disclosure has been described in terms of structural features and/or methodological acts, it should be understood that the specific features or acts described are not necessarily limited. In contrast, specific features and acts are disclosed as representative forms of implementing the exemplary devices and techniques.

800‧‧‧ exemplary process

802~808‧‧‧Steps in an exemplary process

Claims (20)

A microelectronic assembly comprising: a plurality of semiconductor dies coupled in a die stack, the number of grains in the die stack being preselected to include more than a predetermined amount of the die stack At least one additional die in which at least one of said die is a non-operating die, a die configured to be unused or used only in said crystal A grain in a grain stack that is electrically coupled to two other grains. The microelectronic assembly of claim 1, wherein the number of the grains in the die stack comprises an odd number, and an even number of grains are used for data memory functions. The microelectronic assembly of claim 1, wherein at least one of the dies configured to be unused comprises a dummy die. The microelectronic assembly of claim 3, wherein the dummy die is disposed as the topmost die in the die stack. The microelectronic assembly of claim 1, wherein the non-operating die is disposed between the die in the die stack or is disposed as the bottommost die in the die stack The non-operating die includes an inoperative die. The microelectronic component of claim 1, wherein the non-operating die comprises a known operational die, a non-operational die, a known defect Part of the die or reconstituted wafer. The microelectronic assembly of claim 1 wherein at least one of the die stacks is configured to modify the die to compensate for inoperative grains in the die stack. The microelectronic assembly of claim 7, wherein the modified die performs the non-transportation The full electronic function of the grain. The microelectronic assembly of claim 1, wherein the plurality of semiconductor dies are coupled in the die stack via surface mount technology or direct bond interconnect technology. A microelectronic configuration comprising: a plurality of semiconductor wafers coupled in a wafer-to-wafer stack, each wafer comprising a plurality of dies, the wafers being aligned to make each wafer A plurality of die couplings to form a plurality of die stacks, each die stack being aligned along an axis substantially transverse to a plane of at least one of the wafers; and one or more additional die, coupled Grains in one or more die stacks to form one or more modified stacks, each of the one or more of the plurality of grains in the modified stack and the one or more additional The die includes at least one die that does not operate. The microelectronic configuration of claim 10, further comprising one or more modified wafers coupled to the wafers to wafers in the wafer stack, the one or more modified wafers comprising the One or more additional dies that are aligned to couple the one or more additional dies to the dies in the plurality of dies stacks. The microelectronic configuration of claim 10, wherein the number of wafers in the wafer-to-wafer stack comprises an even quantity, and wherein each of the wafer-to-wafer stacks includes a modified stack The even number of working dies plus the non-working dies. The microelectronic configuration of claim 10, wherein at least one of the one or more additional dies comprises a modified die configured to electrically replace the one or more die stacks Defective grains in the middle. The microelectronic configuration of claim 10, wherein the one or more additional dies are At least one of the dummy dies includes a die coupled to the die in the one or more die stacks, the dummy die adjustments each modifying the overall height of the stack. The microelectronic configuration of claim 14, wherein the one or more dummy dies comprise a operable die, an inoperable die, a filler material, or a portion of a reconstituted wafer. The microelectronic configuration of claim 10, wherein the plurality of die stacks comprising the one or more additional dies are cut from the wafer to wafer stack. A method comprising: coupling a plurality of semiconductor wafers in a wafer-to-wafer stack, each wafer comprising a plurality of dies; aligning the wafers to make the plurality of wafers The grains are coupled to form a plurality of die stacks; the defective grains within the die stack are identified; and the modified grains are coupled to the grains in the die stack including the defective grains. The microelectronic configuration of claim 17, further comprising electrically replacing the defective die in the die stack with the modified die. The microelectronic configuration of claim 17, further comprising coupling the plurality of wafers in the wafer-to-wafer stack via a surface mount technique or a direct bond interconnect technique and coupling the modified die To the grains in the die stack. The microelectronic configuration of claim 17, further comprising cutting the die stack including the modified die from the wafer to wafer stack.