TW201732636A - Configurable interconnection device and method - Google Patents

Abstract

Depicting a device comprising: a first interconnect; a second interconnect; a third interconnect; a first via comprising a metal insulator transition (MIT) material, the first via to couple the first interconnect to the a third interconnect; and a second via comprising a MIT material, the second via being configured to couple the second interconnect to the third interconnect.

Description

Configurable interconnection device and method

The present invention is directed to a configurable interconnection device and method.

Today, a single product design needs to operate at different supply voltages. For example, the same processor is designed to operate at high voltage supply (eg, 1.2V) and low voltage supply (eg, 0.5V). The supply voltage (or voltage range) can be selected and fixed based on the performance and power requirements of the market segment (eg, tablet, laptop, desktop, etc.). For example, processors in the desktop market segment can operate at higher voltages that provide higher frequencies and processing speeds (ie, higher performance), while in the tablet or laptop market segment. The same processor can operate at lower voltages and at lower frequencies and processing speeds. Again, this voltage can be dynamically adjusted during operation (eg, low power mode, turbo mode, etc.).

100, 120‧‧‧

101, 102, 103‧‧‧ curves

200, 700‧‧‧ top view

201a, 305a, 401a, 501a‧‧‧ first interconnection

201b, 305b, 401b, 501b‧‧‧ second interconnection

202a‧‧‧First MIT Perforation

202b‧‧‧Second MIT perforation

202aa‧‧‧ Third MIT Perforation

202bb‧‧‧ Fourth MIT Perforation

203a‧‧‧ third interconnection

203aa‧‧‧fourth interconnection

220‧‧‧ side view

300, 320‧‧‧ circuits

301, 302, 601, 602, 603, 604‧‧ ‧ buffer

303, 323‧‧‧ first reconfigurable perforations or interconnections

304, 324‧‧‧Second reconfigurable perforations or interconnections

400, 500‧‧‧ cross section

402a, 402b, 403a, 403b‧‧‧ metal wire

404a, 404b, 504a‧‧‧ MIT perforation

600, 620‧‧‧ schematic

605a, 605b, 606a, 606b‧‧ MIT or MEMS perforation

607a, 607b, 607c, 607d, 607e‧‧‧ interconnection

701a, 701b‧‧‧ MEMS tape

702, 703, 704, 705, 706a, 706b, 707, 708, 709‧‧‧ metal interconnection

800, 820, 830 ‧ ‧ cross section

900, 1000‧‧‧ flow chart

1600‧‧‧ computing device

1610‧‧‧First processor

1620‧‧‧ audio subsystem

1630‧‧‧Display subsystem

1632‧‧‧Display interface

1640‧‧‧I/O controller

1650‧‧‧Power Management

1660‧‧‧Memory Subsystem

1670‧‧‧Connectivity

1672‧‧‧Hive connection

1674‧‧‧Wireless connectivity

1680‧‧‧ Peripheral connections

1682‧‧‧ to

1684‧‧‧From

1690‧‧‧ processor

HP‧‧‧ pulse signal

In‧‧‧ input

MN1, MP1, MP2‧‧‧ transistor

M5‧‧‧ metal layer 5

M6‧‧‧metal layer 6

M7‧‧‧metal layer 7

Out‧‧‧ output

Vdd‧‧‧Power supply

Vss‧‧‧

The embodiments of the present invention will be more fully understood from the following description of the embodiments of the invention, They are not intended to limit the invention to the particular embodiments, and are intended to be

1A depicts a graph of performance versus frequency and varying supply voltage comparison logic for the case of using an ideal interconnect, an interconnect having a resistive effect, and a configurable interconnect of some embodiments.

FIG. 1B depicts a diagram showing a design that is optimized to achieve high turbine performance and that is not available with the lowest possible energy even when operating at low power supplies.

2A depicts a top view of a configurable interconnect in accordance with some embodiments of the disclosed invention.

2B depicts a side view of the configurable interconnect of FIG. 2A in accordance with some embodiments of the present disclosure.

3A depicts a configurable interconnect configured to have a high resistivity due to a change in stimulus, in accordance with some embodiments.

3B depicts the configurable interconnect of FIG. 3A configured to have low resistivity due to changes in stimulus, in accordance with some embodiments.

4 depicts a cross-sectional view of a configurable interconnect configurable via an application of an electric field in accordance with some embodiments of the present disclosure.

5 depicts a cross-sectional view of a configurable interconnect configurable via current application, in accordance with some embodiments of the present disclosure.

6A depicts a schematic diagram of a configurable interconnect having a configuration configured as a bypass buffer in accordance with some embodiments of the present disclosure.

6B depicts a schematic diagram with a configurable interconnect configured to incorporate the buffer, in accordance with some embodiments of the present disclosure.

7 depicts a top view of an interconnected network having configurable interconnects formed in microelectromechanical switches (MEMS), in accordance with some embodiments of the present disclosure.

8A depicts a cross-section of a network portion of a MEMS-based configurable interconnect, in accordance with some embodiments of the present disclosure.

8B depicts a cross-section of a network portion of a first configured MEMS-based configurable interconnect, in accordance with some embodiments of the present disclosure.

8C depicts a cross-section of a network portion of a second configured MEMS-based configurable interconnect, in accordance with some embodiments of the present disclosure.

9 is a flow chart depicting a method of configuring the resistivity and/or capacitance of a configurable interconnect using an electric field, in accordance with some embodiments of the present disclosure.

10 is a flow chart depicting a method of configuring a resistivity and/or capacitance of a configurable interconnect using changes in temperature, in accordance with some embodiments of the present disclosure.

11 depicts a smart device or computer system or system single chip (SoC) having one or more configurable interconnects in accordance with some embodiments.

SUMMARY OF THE INVENTION AND EMBODIMENT

The power and performance effects of a resistive interconnect are strongly dependent on the supply voltage. Therefore, designs that operate optimally at low voltages operate at higher voltages less efficiently, and vice versa. Applying a design to different market segments and power modes provides design and manufacturing efficiency, but compromises in performance and energy. This compromise may only become more severe as the interconnect resistance increases as scaling increases.

Designing current solutions using logic or processors for resistive interconnects Limited by two non-optimal methods. In the first method, the design of the integrated circuit (IC) is optimized at a specified performance point (eg, high performance or low power). In this case, other performance target products will be significantly affected by suboptimal power performance operations. For example, an IC design optimized to operate at high performance (eg, high frequency) can result in sub-optimal power efficiency for products operating at low voltages and frequencies, as it will consume less than the minimum power consumption actually required for lower performance operation. More power.

1A depicts a graph 100 for operating frequencies and varying the performance of supply voltage comparison logic for the case of using an ideal interconnect, an interconnect having a resistive effect, and a configurable interconnect of some embodiments. Here, the x-axis power supply (Vdd) and the y-axis frequency (in GHz). Figure 100 shows three curves - 101, 102, and 103.

Curve 101 (dotted curve) depicts the performance of an IC with a logically dominant path that is not substantially composed of interconnects (eg, the interconnect resistance is much smaller than the transistor resistance). For example, logic performance is primarily dependent on logic latency and does not depend on interconnect propagation delay. Here, the interconnect has a very low resistivity and the frequency is determined by the transistor current drive (eg, the reciprocal of the transistor resistance), which drives the higher power supply to a higher frequency and leads to higher frequencies and Performance, and when the logic operates at a lower power supply, it is lower and results in lower frequency and performance.

Curve 102 depicts the performance of IC logic using interconnects designed for a particular supply voltage and performance. In this case, as the supply voltage increases, the increase in operating frequency is limited by the interconnect propagation delay. Curve 103 depicts the effectiveness of IC logic using configurable interconnects as described with reference to various embodiments. can. In this case, as the supply level increases (eg, Vdd increases from 0.4V to 1.0V), the interconnect delay is reduced to a lower level than curve 102, which allows for a higher operating frequency than curve 102. For example, various buffers are dynamically introduced into the logical path to overcome the interconnect propagation delay.

Similarly, as the supply level decreases (eg, 1.0V to 0.4V), the interconnect latency is allowed to increase because performance may not be a primary consideration, and the primary consideration is to reduce the energy of the buffers used less frequently. For example, for lower power operations, it is now possible to dynamically bypass the various buffers that were previously dynamically introduced. For example, at high voltages, the buffer can reduce the total delay, but at low voltages, the same buffer can increase the total delay compared to the delay seen during low voltage operation of the circuit with the bypass buffer.

In the second method, the IC product is redesigned with two individual performance points suitable for individual applications (eg, laptop or desktop). This approach improves performance and efficiency when using a single design in products with different power and performance requirements, but when a single product needs to dynamically adjust its power and performance requirements, it cannot be completely resolved.

FIG. 1B depicts a graph 120 showing a design (eg, a turbine design) that is optimized to achieve high turbine (or highest) performance and that is not available with the lowest possible energy even when operating at low power supply. This dual design approach is also very expensive. Various embodiments provide for achieving an optimal design at a lower operating frequency (eg, lower per operational energy than a turbine design) and per computing energy at a turbine frequency level (ie, higher frequency) comparable to a turbine design. Configurable interconnection.

Table 1 shows that it can be better optimized at low voltage (eg, 0.65V) For lower wiring or interconnect capacitance "C", but at high voltage (for example, 1.10V) is optimized for lower wiring or interconnect resistance "R". In some embodiments, the configurable interconnects follow the behavior outlined in Table 1.

Table 1 shows the low and high voltage cases, and the percentage change in capacitor "C" and its equivalent change in resistance "R". In this example, at 0.65V Vdd, the 10% change in capacitance "C" is equivalent to a 41% change in resistance "R" in delay, but is equivalent to 16% at 1.1V Vdd.

In some embodiments, the interconnect resistance and/or capacitance can be dynamically configured (eg, using changes in temperature, by applying an electric field, by introducing a temporary current, by applying external pressure, etc.) to achieve optimal mutuality. Even the design. In some embodiments, the interconnect resistance and/or capacitance can be dynamically reconfigured by a Metal Insulator Transition (MIT) switch. In some embodiments, the interconnect resistance and/or capacitance can be dynamically reconfigured by a microelectromechanical (MEM) switch or a nanomechanical (NEM) switch.

In some embodiments, the dynamic reconfiguration of interconnect properties (eg, resistance, capacitance, buffer spacing, and size) is achieved by a perforated layer that can be a conductor-like metal or insulator depending on different product objectives. Dielectric. In some embodiments, dynamic reconfiguration is achieved by using a scheme that is selected to operate in an alternate secondary circuit in accordance with the supply voltage mode. For example, A buffer is added during high voltage operation to drive the interconnect, while during the low voltage paradigm, the buffer can be bypassed to reduce power. In some embodiments, the manufacturing time configuration of the interconnect (eg, resistors, capacitors, buffers, dimensions, etc.) is achieved by a perforated layer that can be a conductor-like metal or insulator depending on different product objectives. Dielectric.

In some embodiments, one or more interconnects are reconfigured to have a long spacing between buffers at low voltages, for high efficiency per watt and high efficiency at low voltages. For example, at low voltages, it is preferable to adjust the wiring size to minimize (e.g., reduce) the wiring capacitance. In some embodiments, at high voltages, for high performance at high voltages, one or more interconnects are reconfigured to have short spacing between the buffers. For example, at high voltages, it is preferable to adjust the wiring size to minimize the resistance.

In the following description, numerous details are set forth to provide a more thorough explanation of the embodiments of the disclosed invention. However, it is possible that the embodiments of the present invention may be implemented without such specific details as will be apparent to those skilled in the art. In other instances, structures and devices that are well known are shown in the block diagram and not in detail, in order to avoid obscuring the embodiments of the disclosed invention.

It should be noted that in the corresponding figures of the embodiments, the signals are represented by lines. Some lines may be thicker to indicate more of the constituent signal paths, and/or have arrows at one or more ends to indicate the direction of the primary information flow. Such instructions are not considered to be limitations. Rather, the lines are used in conjunction with one or more exemplary embodiments to facilitate a more readily understood circuit or logic unit. Any rendered signal, as specified by design needs or preferences, may actually contain one or more signals that travel in either direction and may be of any suitable signal format Implementation.

Throughout this specification and in the context of the patent application, the term "connected" means a direct connection, such as an electrical, mechanical, or magnetic connection, between any connected things without any intermediate means. The term "coupled" means directly or indirectly connected, such as a direct electrical, mechanical, or magnetic connection between the connected items, or an indirect connection via one or more passive or active intermediate devices.

The term "circuit" or "module" may refer to one or more passive and/or active components that are configured to cooperate with each other to provide a desired function. The term "signal" can refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a" and "the" includes a plurality of references. The meaning of "in" includes "in" and "in".

The term "scaling" generally refers to the conversion of a design (circuit and layout) from one processing technique to another, and subsequently a reduction in layout area. The term "scaling" also generally refers to reducing the size of the arrangement and device within the same technology node. The term "scaling" may also refer to an adjustment of the signal frequency relative to another parameter, such as a power supply level (eg, deceleration or acceleration - that is, corresponding to reduction or amplification, respectively). The term "scaling" can also refer to the magnitude of the power supply voltage (eg, voltage scaling) that is adjusted to the circuit (etc.).

The terms "substantially", "close", "almost", "close", and "about" generally mean within +/- 10% of the target value. Unless otherwise specified, the use of the orderly adjectives "first," "second," and "third", etc., to describe a common item, otherwise merely indicates different instances of the similar items referred to, and is not intended to imply that the items so described must be In time, in space, in The given order is used sequentially, or in any other way.

It is to be understood that the terms so used are interchangeable under the appropriate circumstances, such that the embodiments of the invention described herein, for example, can operate in a different orientation than that described or otherwise described herein.

For the purposes of the present disclosure, the meanings of the phrases "A and/or B" and "A or B" are (A), (B), or (A and B). For the purposes of the present disclosure, the meanings of the phrases "A, B, and/or C" are (A), (B), (C), (A and B), (A and C), (B and C). ) or (A, B, and C). If any of the terms "left", "right", "front", "back", "top", "bottom", "above", "below", etc. are described and claimed, For the purpose of description, it is not necessarily used to describe a permanent relative position.

For the purposes of the embodiments, the transistors in the various circuits, modules, and logic blocks may be tunneling FETs (TFETs), or portions of the transistors of various embodiments may include metal oxide semiconductor (MOS) transistors, including Bungee, source, gate, and block ends. The transistor may also include a three-gate and FinFET transistor, a gate full-circular cylindrical transistor, a square wire, or a rectangular ribbon transistor, or other device that functions as a transistor, such as a carbon nanotube or Spintronics. The symmetrical source and the 汲 extreme of the MOSFET, that is, the equivalent ends, are used interchangeably herein. On the other hand, TFET devices have asymmetric sources and 汲 extremes. Those skilled in the art will appreciate that other transistors, such as bipolar junction transistors - BJT PNP/NPN, BiCMOS, CMOS, etc., can be used with certain transistors without departing from the scope of the disclosed invention.

2A depicts a top view 200 of a configurable interconnect in accordance with some embodiments of the disclosed invention. 2B depicts a side view 220 of a cross-section AA' of the configurable interconnect of FIG. 2A, in accordance with some embodiments of the present disclosure.

In some embodiments, the configurable interconnect of FIGS. 2A-B includes a first interconnect 201a (eg, an interconnect on metal layer 5 (M5)), a second interconnect 201b (eg, parallel to the first Another interconnect in which the interconnect 201a extends), the first MIT via 202a, the second MIT via 202b, the third MIT via 202aa, the fourth MIT via 202bb, and the third interconnect 203a (eg, in the first and second The interconnects on the different metal layers of the interconnect 201a/b), and the fourth interconnect 203aa. Here, the interconnects 201a/b and 203a/aa can be formed of any suitable electrically conductive material (eg, Cu, Al, or any suitable alloy). In some embodiments, the MIT vias 202a/b couple the first and second interconnects 201a/b to the third interconnect 203a. In some embodiments, the MIT vias 202aa/bb couple the first and second interconnects 201a/b to the fourth interconnect 203aa. To avoid obscuring the various embodiments, a cross section AA' is described.

In some embodiments, MIT vias 202a/b (also referred to as metal oxide transistor (MOT or MOTT) vias) couple the first and second interconnects 201a/b with the third interconnect 203a, respectively. In some embodiments, the MIT perforations 202a/b can change their conductive characteristics depending on the application of the stimulus (eg, changes in temperature, electric field, current, pressure, etc.). Thus, the MIT vias 202a/b can transition from metal to insulator or vice versa. In some embodiments, the MIT vias 202a/b are formed by one of: VO ₂ , V _x O _y , Ti-doped V ₂ O ₃ , Fe ₃ O ₄ , FeS, Ti _x O _y , TiS ₂ , LaCoO ₃ , SmNiO ₃ , EuO, doped semiconductors such as Si:P, Si:As, Si:B, and Si:Ga. In some embodiments, the MIT vias 202a/b comprise a group selection consisting of VO ₂ , V _x O _y , Fe ₃ O ₄ , FeS, Ti _x O _y , TiS ₂ , LaCoO ₃ , SmNiO ₃ , and EuO. s material. In some embodiments, the material selected further comprises trace dopants or other impurity species.

In some embodiments, the third interconnect 203a has a lower or the same resistivity than the first and second interconnects 201a/b. For example, the third interconnect 203a is formed on a higher metal layer (eg, metal layer 6 (M6), while the first and second interconnects 201a/b are formed with metal layer 5 (M5)). In some embodiments, the third interconnect 203a has a higher or the same resistivity than the first and second interconnects 201a/b. For example, the third interconnect 203a is formed on the lower metal layer (for example, the metal layer 4 (M4) while the first and second interconnects 201a/b are formed on M5). In some embodiments, the third interconnect 203a extends perpendicular to the first and second interconnects 201a/b. In some embodiments, the interconnects 201a/b are formed on different metal layers. In some embodiments, the interconnects 201a/b have different cross-sectional dimensions. In some embodiments, the interconnects 201a/b have different pitches to adjacent interconnects. In some embodiments, the first, second, and third interconnects comprise materials selected from the group consisting of Cu or Al. In some embodiments, the material further comprises a dopant, an alloy material, or other impurity species.

In some embodiments, the temperature sensitivity of the MIT vias 202a/b can be configured to approximate design requirements to move from high and low capacitance to low resistance and slightly higher capacitance. When the MIT via 202a/b is formed of VO ₂ , the transition from metal to insulator and the reverse transition approach an absolute temperature of 300 (K). In this example, for temperatures above 300K, the MIT vias 202a/b become metal to use two parallel interconnects (eg, interconnects 201a/b).

In some embodiments, the MIT perforations 202a/b are designed to change features at a temperature threshold (eg, 75 degrees Celsius). For example, at temperatures above 75 degrees Celsius, the MIT vias 202a/b transition from an insulator to a metal. Thus, in some embodiments, the MIT vias 202a/b electrically couple the first and second interconnects 201a/b to the third interconnect 203a at temperatures above 75 degrees Celsius. In some embodiments, at temperatures below 75 degrees Celsius, the MIT vias 202a/b transition from metal to insulator, and thus the first and second interconnects 201a/b are electrically decoupled from the third interconnect 203a. In this example, at a higher temperature, the reconfigurable interconnect is configured to have a lower resistance to handle the higher effect of interconnect resistivity on performance at higher temperatures.

FIG. 3A depicts a circuit 300 having a configurable interconnect configured to have a high resistivity due to a change in stimulus, in accordance with some embodiments. It is noted that the elements of Figure 3A having the same reference numerals (or names) as the elements of any other figures may operate or function in any manner similar to the elements described, but are not limited thereto.

In some embodiments, circuit 300 includes a buffer 301, a buffer 302, a first reconfigurable via or interconnect 303, a second configurable via or interconnect 304, a first interconnect 305a (eg, 201a) And a second interconnect 305b (eg, 201b). Buffers 301 and 302 are shown for the purpose of simplifying the circuit. In other embodiments, other types of input and output drivers may be used in place of the buffers 301 and 302 that receive the input "In" and provide the output "Out." Embodiments are not limited to the use cases discussed herein. Reconfigurable interconnects of various embodiments can be used in many use cases.

In some embodiments, the first and second reconfigurable vias or interconnects 303/304 are identical to the MIT vias 202a/b. In some embodiments, the first and second reconfigurable vias or interconnects 303/304 are MEMS or NEMS as described with reference to Figures 7-8. Referring back to FIG. 3A, in some embodiments, the first and second reconfigurable vias or interconnects 303/304 are configured as insulators during low power mode or for designs intended for low power operation. Thus, the first and second interconnects 305a/b are electrically decoupled from each other.

In some such embodiments, buffer 301 drives its output signal to buffer 302 by using first interconnect 305a. Here, the input to the buffer 301 is "In" and the output of the buffer 302 is "Out". In some embodiments where low interconnect resistance is desired (eg, for high power supply or higher performance designs), as shown in FIG. 3B, the first and second reconfigurable vias or interconnects 303/304 groups State into a metal. 3B depicts a circuit 320 having the configurable interconnect of FIG. 3A configured to have a low resistivity due to a change in stimulus, in accordance with some embodiments. Here, the first and second reconfigurable vias or interconnects 303/304 are relabeled as first and second reconfigurable vias or interconnects 323/324, respectively. The perforations or interconnects 303/304 do not pass through the wires that indicate their insulative state (eg, open circuit) while the vias or interconnects 323/324 have lines that pass through them to indicate conductivity (eg, short circuit). The configuration of Figure 3B can result in a lower overall interconnect resistance "R" due to the parallel combination of the first and second interconnects 305a/b. In this configuration, the interconnect capacitance "C" can be increased due to the parallel combination of the capacitances of the first and second interconnects 305a/b.

In some embodiments, the MIT (metal) placed in the back metallization Insulator transitions or MEMS can be used as configurable perforations. In some embodiments, the perforation can: overlap (eg, connect) a plurality of metal lines in parallel, improve net resistance (eg, for high-Vdd performance); cut the lapped metal lines, and improve net capacitance (eg, For low-Vdd performance and energy); route long wiring to the optimal buffer for optimal positioning for each supply voltage; connect additional buffers to drive long wiring (eg, for improved high-Vdd performance); and / Or turn off the extra buffer to drive long wiring (for example, to improve low-Vdd power/performance).

In some embodiments, if the design team needs to use MIT or MEMS reconfigurable interconnects before the MIT or MEMS process options are available, the configuration can be provided to the different markets by processing the mask using the perforation option. The essence of the optimization is the same design. According to some embodiments, this short-term solution using perforations allows for a manufacturing time configuration.

4 depicts a cross-sectional view 400 of a configurable interconnect configurable via an application of an electric field, in accordance with some embodiments of the present disclosure. It is noted that the elements of Figure 4 having the same reference numerals (or names) as the elements of any other figures may operate or function in any manner similar to the elements described, but are not limited thereto.

In some embodiments, the configurable interconnect includes a first interconnect 401a, a second interconnect 401b, metal lines 402a/b and 403a/b, transistors MP1 and MP2, and MIT vias 404a/b. In some embodiments, the MIT vias 404a/b are fabricated from the same materials as described with reference to the MIT vias 202a/b. In some embodiments, metal lines 402a/b and 403a/b are perpendicular to MIT vias 404a/b. In some embodiments, the metal wire 403a/b is coupled to ground (VSS). In some embodiments, metal lines 402a/b are coupled to transistors MP1 and MP2, respectively. In some embodiments, the first interconnect 401a extends parallel to the second interconnect 401b. In some embodiments, metal lines 402a/b and 403a/b are perpendicular to first and second interconnects 401a/b. In this example, the first interconnect 401a is on the metal layer 5 (M5), the second interconnect 401b is on the metal layer 7 (M7), and the metal lines 402a/b and 403a/b are on the metal layer 6. (M6). In other embodiments, other metal layers can be used.

In some embodiments, the transistors MP1 and MP2 can be operated by the pulse signal HP to conduct. In some embodiments, the drain terminals of the transistors MP1 and MP2 are coupled to the wirings 402a/b, respectively. In some embodiments, the source terminals of transistors MP1 and MP2 are coupled to Vdd. In some embodiments, the gate terminals of transistors MP1 and MP2 are coupled to HP. Here, references to signals and nodes are used interchangeably. For example, HP may refer to the contextual signal HP or node HP depending on the context of the sentence.

In some embodiments, when the transistors MP1 and MP2 are turned on, an electric field is formed between the metal lines 402a and 403a and between the metal lines 402b and 403b. In some embodiments, metal lines 402a/b and 403a/b are positioned such that an electric field passes and/or around MIT vias 404a/b. This electric field causes the MIT vias 404a and 404b to transition from an insulator to a metal. In some embodiments, the MIT vias 404a and 404b transition from a metal to an insulator in the absence of an electric field.

In some embodiments, the pulse width of HP can be adjusted or programmable (eg, by firmware, software, and/or hardware). In some embodiments The duration of the HP pulse period is based on the power mode. For example, during a high power mode (eg, turbo mode), the pulse duration is as long as the power mode duration. Thus, during high power mode, interconnects 401a and 401b are electrically coupled to provide lower resistance and faster signal propagation. In some embodiments, during the low power mode, HP remains at the logic high level for as long as the low power mode duration. Thus, interconnects 401a and 401b are electrically decoupled from each other in this mode.

While the embodiment of FIG. 4 is depicted with reference to p-type transistors MP1 and MP2, the p-type transistor can be replaced with an n-type transistor. In some embodiments, instead of coupling the transistor to Vdd (as shown by reference transistors MP1 and MP2), a transistor (eg, an n-type transistor) can be coupled to ground. In one such embodiment, metal lines 403a/b are coupled to ground instead of Vdd. Thus, a complementary version of the embodiment of Figure 4 can be derived.

5 depicts a cross-sectional view 500 of a configurable interconnect configurable via current application in accordance with some embodiments of the present disclosure. It is noted that the elements of Figure 5 having the same reference numbers (or names) as the elements of any other figures may operate or function in any manner similar to the elements described, but are not limited thereto.

In some embodiments, the configurable interconnect includes a first interconnect 501a (eg, similar to 401a), a second interconnect 501b (eg, similar to 401b), and transistors MP1 and MN1, and MIT vias 504a ( For example, 404a). In some embodiments, the drain terminal of transistor MP1 is coupled to second interconnect 501b. In some embodiments, the gate terminal of transistor MP1 is coupled to HP. In some embodiments, the p-type transistor MP1 The source terminal is coupled to Vdd. In some embodiments, the drain terminal of the n-type transistor MN1 is coupled to the first interconnect 501a. In some embodiments, the gate terminal of transistor MN1 is coupled to HP_b (where HP_b is the inverse of HP). In some embodiments, the source terminal of transistor MN1 is coupled to VSS.

In some embodiments, the transistors MP1 and MN1 are turned on when the HP system logic is low (i.e., when HP_b is logic high). Therefore, if the MIT via 504a becomes conductive (ie, transitions from an insulator to a metal), a current path from Vdd to ground can be formed. In some embodiments, the MIT vias 504a are converted from an insulator to a metal by conducting the transistors MP1 and MN1. Therefore, the first and second interconnects 501a/b are electrically coupled. In some embodiments, HP (and HP_b) has a pulse signal that is long enough to cause a pulse duration of MIT via 504a to transition from an insulator to metal. In some embodiments, once the MIT via 504a becomes metal, HP and HP_b cause the transistors MP1 and MN1 to turn off. During this state, the signal routed on the first interconnect 501a is also routed to the second interconnect 501b.

In some cases, over time, the MIT via 504a transitions from metal to insulator. In some embodiments, the transistors MP1 and MN1 are again turned on to maintain the metal features of the MIT via 504a just prior to the transition in the MIT via 504a. This process can be similar to a refresh operation. In some embodiments, depending on the architecture in which the first and second interconnects 501a/b are used, HP and HP_b are again provided as pulse signals to the transistors MP1 and MN1 to refresh the metal features of the MIT via 504a.

In some embodiments, when the two interconnections are for signal transmission (or propagation) The pulse signals HP and HP_b are provided during the high power mode as needed. In some embodiments, during the low power mode, when the signal propagation is via an interconnect, the transistors MP1 and MN1 are kept off.

6A depicts a schematic diagram 600 of a configurable interconnect having a configuration configured as a bypass buffer in accordance with some embodiments of the present disclosure. It is pointed out that the elements of Figure 6A having the same reference numerals (or names) as the elements of any other figures may operate or function in any manner similar to the elements described, but are not limited thereto.

In some embodiments, schematic 600 includes buffers 601, 602, 603, and 604, interconnects 607a, 607b, 607c, and 607d, and 607e, and MIT or MEMS vias 605a, 605b, 606a, and 606b. In some embodiments, 605a, 605b, 606a, and 606b are CMOS multiplexers or transfer gates. While any of the reference bypass buffers 603 and 604 or these buffers are added to the signal propagation path to explain the embodiment, the concept can be used for any circuit topology with different use cases.

In some embodiments, dynamic reconfiguration depends on different product targets by using MIT or MEMS that can make it a class-like conductor metal (or low resistance or short circuit) or an insulator-like dielectric (or high resistance or open circuit). This is achieved by via or CMOS transfer gates 605a, 605b, 606a, and 606b. In some embodiments, dynamic reconfiguration is achieved by using a scheme that is selected to operate in an alternate secondary circuit in accordance with the supply voltage mode.

According to some embodiments, in some embodiments, buffers 603 and 604 can be bypassed during low voltage operation to reduce power. For example, while the MIT vias 606a and 606b are configured as metal, reference is made to various implementations. Any of the approaches discussed in the example (eg, by varying temperature, pressure, providing an electric field, and/or providing a pulsed current) configure MIT vias 605a and 605b as insulators. As such, the signals bypass buffers 603 and 604 during periods of low performance.

In some embodiments, at low voltages, the interconnect is reconfigured to have a long pitch between the buffers 601 and 602 for high performance/watt and low voltage performance. The long pitch or long path is provided by interconnects 607a, 607d, and 607e. For example, at low voltages, it is preferable to adjust the wiring size to minimize the wiring capacitance. In some embodiments, at high voltages, the interconnects are reconfigured for high efficiency at high voltages with short spacing between buffers. The short pitch or short path is provided by interconnects 607a, 607b, 607c, and 607e. For example, at high voltages, it is preferable to adjust the wiring size to minimize the resistance.

Here, FIG. 6A depicts a case where MIT vias 606a and 606b are configured as metal while MIT vias 605a and 605b are configured as insulators. FIG. 6B depicts a schematic 620 with configurable interconnects configured to combine buffers 603 and 604 at higher supply voltages in accordance with some embodiments of the present disclosure.

In some embodiments, buffers 603 and 604 can be added to drive interconnect 607e during high voltage operation. For example, while the MIT vias 606a and 606b are configured as insulators, the MIT vias 605a and 605b are used using any of the approaches discussed with reference to various embodiments (eg, by varying temperature, pressure, providing an electric field, and/or providing a pulsed current). Configured as metal. Therefore, during high performance (eg, turbo mode), the signal passes through the buffer 603 and 604 buffers.

7 depicts a top view 700 of a MEMS or NEMS configurable interconnected network in accordance with some embodiments of the present disclosure. It is to be noted that the elements of Figure 7 having the same reference numerals (or names) as the elements of any other figures may operate or function in any manner similar to the elements described, but are not limited thereto. FIG. 7 is described with reference to FIGS. 6A-B.

In some embodiments, the top view 700 interconnect and MEMS/NEMS configuration includes MEMS strips 701a and 701b, metal interconnects (eg, Cu and Al, etc.) 702, 703, 704, 705, 706a/b, 707, 708, and 709. In some embodiments, interconnect 702 is the same interconnect as 607d. Thus, when MEMS 701a/b are electrically coupled to interconnect 702, buffers 603 and 604 are bypassed.

MEMS strips 701a and 701b are also referred to as micromachine or microsystem technology (MST). The MEMS tape 701a/b can be fabricated using any suitable material. For example, gold, nickel, aluminum, copper, chromium, titanium, tungsten, platinum, silver; nitrides of tantalum, aluminum, and titanium, and tantalum carbide, and other ceramics can be used to form the MEMS tape 701a/b.

In some embodiments, interconnect 703 is used to control the selector of MEM 701a/b. In some embodiments, interconnect 707 is used to control selector_b of MEM 701a/b, where selector_b is the inverse of the selector. For example, when the selector interconnect 703 is biased by a high voltage (eg, Vdd), the selector_b interconnect 707 is biased at a low voltage (eg, ground). In some embodiments, as described with reference to Figures 8A-C, when the selector is biased at a high voltage, the MEM 701a/b is bent in one direction.

Referring back to FIG. 7, in some embodiments, the input is received by interconnect 704. In some embodiments, interconnect 704 is coupled to interconnect 706a that is in turn coupled to MEMS strip 701a. In some embodiments, interconnect 705 is coupled to the output. In some embodiments, interconnect 705 is coupled to interconnect 706b, which in turn is coupled to MEMS strip 701b. In some embodiments, interconnect 708 is coupled to the input of buffer 603. In some embodiments, interconnect 709 is coupled to the output of buffer 604.

8A-C depict a cross section along the dashed line BB of FIG. 7 in accordance with some embodiments. It is to be noted that the elements of Figures 8A-C having the same reference numerals (or names) as the elements of any other figures may operate or function in any manner similar to the elements described, but are not limited thereto.

8A depicts a cross-section 800 of a portion of a MEMS-based configurable interconnected network along a dashed line BB (of FIG. 7) in accordance with some embodiments of the present disclosure. 8B depicts a cross-section 820 of a portion of a first configured MEMS-based configurable interconnected network along a dashed line BB (of FIG. 7) in accordance with some embodiments of the present disclosure. In this configuration, the selector interconnect 703 is biased at a high voltage and the selector_b interconnect 707 is biased at a low voltage (eg, ground). As such, MEMS strip 701a is bent toward and electrically coupled to interconnect 702. The same state occurs for the MEMS tape 701b as well. Thus, bypass buffers 603 and 604 (eg, interconnect 607a is electrically coupled to interconnect 607d and interconnect 607d is electrically coupled to interconnect 607e).

8C depicts a cross-section 830 of a portion of a second configured MEMS-based configurable interconnect network along a dashed line BB (of FIG. 7) in accordance with some embodiments of the present disclosure. In this configuration, selector_b interconnects 707 to The high voltage is biased while the selector interconnect 703 is biased at a low voltage (eg, ground). Thus, MEMS strip 701a is bent toward and electrically coupled to interconnect 708. The same occurs for the MEMS strip 701b. Thus, buffers 603 and 604 are included (eg, interconnect 607a is electrically coupled to interconnect 607b and interconnect 607c is electrically coupled to interconnect 607e).

9 depicts a flow diagram 900 of a method of configuring a resistivity and/or capacitance of a configurable interconnect using an electric field, in accordance with some embodiments of the present disclosure. Flowchart 900 is described with reference to FIG. It is noted that the elements of Figure 9 having the same reference numerals (or names) as the elements of any other figures may operate or function in any manner similar to the elements described, but are not limited thereto.

Although the blocks in the flowchart of FIG. 9 are shown in a particular order, the order of the actions may be modified. Thus, the illustrated embodiments may be implemented in a different order and the various acts/blocks may be implemented in parallel. According to a particular embodiment, the portions of the blocks and/or operations listed in Figure 9 are optional. The block numbers are presented for clarity and are not intended to specify the order in which the various blocks must operate. In addition, operations from a variety of processes can be used in a wide variety of combinations.

At block 901, a first electric field is applied across the first MIT via 404a. For example, an HP pulse of the conductive crystal MP1 is applied, which in turn charges the wiring 402a. The charged line 402a causes an electric field to be generated around the MIT via 404a. As such, the resistance of the MIT via 404a changes from a high resistance to a low resistance or from an open circuit to a short circuit. At block 902, in response to the applied electric field, the first interconnect 401a is electrically coupled to the second interconnect 401b via the first MIT via 404a. At block 903, the second electric field is traversed Two MIT perforations 404b are applied. For example, an HP pulse of the conductive crystal MP2 is applied, which in turn charges the wiring 402b. The charged line 402b causes an electric field to be generated around the MIT via 404b. At block 904, in response to the applied electric field, the first interconnect 401a is electrically coupled to the second interconnect 401b via the second MIT via 404b. In some embodiments, when the transistors MP1 and MP2 are turned off, the electric field is removed and thus the first interconnect 401a and the second interconnect 401b are electrically decoupled.

10 depicts a flowchart 1000 of a method of configuring a resistivity and/or capacitance of a configurable interconnect using a change in temperature, in accordance with some embodiments of the present disclosure. Flowchart 1000 is described with reference to Figures 2A-B. It is noted that the elements of Figure 10 having the same reference numerals (or names) as the elements of any other figures may operate or function in any manner similar to the elements described, but are not limited thereto.

Although the blocks in the flowchart of FIG. 10 are shown in a particular order, the order of the actions may be modified. Thus, the illustrated embodiments may be implemented in a different order and the various acts/blocks may be implemented in parallel. According to a particular embodiment, the partial blocks and/or operations listed in Figure 10 are optional. The block numbers are presented for clarity and are not intended to specify the order in which the various blocks must operate. In addition, operations from a variety of processes can be used in a wide variety of combinations.

At block 1001, the temperature is increased. As such, the temperature of the first and second MIT vias 202a/b rises above a threshold (eg, 75 °C). At block 1002, in response to an increase in temperature, the first interconnect 201a is electrically coupled to the third interconnect 203a via the first MIT via 202a. At block 1003, the response The second interconnect 201b is electrically coupled to the third interconnect 203a via the second MIT via 202b as the temperature increases.

At block 1004, the temperature is reduced below the threshold. Therefore, the temperatures of the first and second MIT perforations fall below the threshold (eg, 75 ° C). At block 1005, in response to a decrease in temperature, the first interconnect 201a is electrically decoupled from the third interconnect 203a via the first MIT via 202a, and in response to a decrease in temperature, the second mutual via the second MIT via 202b The connection 201b is electrically decoupled from the third interconnection 203a.

In some embodiments, the configurable interconnect can be enabled by a single configuration layer. For example, configurable perforations 7 enable the configuration of signals that are primarily routed in metal layer 8 (M8). In some embodiments, a single configuration layer can enable configuration of signals routed in two or more metal layers. For example, configurable perforation 7 can enable configuration of M8 routing or metal layer 7 (M7) routing. This configuration of layers that allow routing in a direction perpendicular to a single configuration layer can be useful. In some embodiments, multiple configuration layers enable configuration of multiple metal layers. For example, the configuration of metal layer 10 (M10) enables RC (time constant) and repeater optimization of the global signal. In another example, the configuration of metal layer 3 (M3) can be optimized for RC/buffers that enable regional and global signals by enabling efficient configurable buffer insertion.

In some embodiments, the configuration of the perforations can occur after most of the manufacturing steps are completed, but before being sold to the consumer to configure the die with a particular application. In some embodiments, the configuration is implemented based on die power and/or performance and a yield metric measured during the test process. For example, higher performance dies can be boxed for high voltage applications and configured to be even at high voltages. Now more efficient. In some embodiments, the MIT material of 504a can be replaced with a fuse.

In some embodiments, high current is passed through the transistors MP1, MN1, and MIT vias 504a to convert the MIT vias 504a into high resistance vias. This enables low power/low voltage products. Otherwise, high resistance perforation transitions enable high voltage/high performance products. In some other embodiments, high current is passed through transistors MP1 and MN1 and MIT vias 504a convert MIT vias 504a to low resistance. This enables high performance/high voltage products. According to various embodiments, the fuse material may be SiO ₂ , a high K oxide material, copper, or a metal wire.

11 depicts a smart device or computer system or system single chip (SoC) 1600 having one or more configurable interconnects in accordance with some embodiments. It is noted that such elements of Figure 11 having the same reference numbers (or names) as the elements of any other figures may operate or function in any manner similar to the elements described, but are not limited thereto.

11 depicts a block diagram of an embodiment of a mobile device in which a planar interface connector can be used. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile or smart phone, a wirelessly enabled e-book reader, or other wireless mobile device. It will be appreciated that a particular component is typically displayed and that all components of such a device are not displayed in computing device 1600.

In accordance with some of the embodiments discussed, in some embodiments, computing device 1600 includes a first processor 1610 having one or more configurable interconnects. According to some embodiments, other blocks of computing device 1600 may also Includes one or more configurable interconnects. Various embodiments of the disclosed invention may also include a network interface within 1670, such as a wireless interface, such that a system embodiment can be incorporated into a wireless device, such as a mobile telephone or a personal digital assistant.

In an embodiment, processor 1610 (and/or processor 1690) can include one or more physical devices, such as a microprocessor, an application processor, a microcontroller, a programmable logic device, or other processing mechanism . The processing operations performed by processor 1610 include executing an operating platform or operating system on which to execute application and/or device functions. Processing operations include operations related to human users or I/O (input/output) with other devices, operations related to power management, and/or operations related to connecting computing device 1600 to another device. Processing operations may also include operations related to audio I/O and/or display I/O.

In one embodiment, computing device 1600 includes an audio subsystem 1620 that represents hardware (eg, audio hardware and audio circuitry) and software (eg, drivers, codecs) associated with providing audio functionality to computing devices. ) components. Audio functions can include speaker and/or headphone output, as well as microphone input. In accordance with some embodiments, in some embodiments, audio subsystem 1620 includes device and/or machine executable instructions to avoid self-listening. Devices for such functionality can be integrated into computing device 1600 or connected to computing device 1600. In one embodiment, the user interacts with computing device 1600 by providing audio commands received and processed by processor 1610.

Display subsystem 1630 represents providing visual and/or tactile display to the user Hardware (eg, display device) and software (eg, driver) components that interact with computing device 1600. Display subsystem 1630 includes a display interface 1632 that includes a particular screen or hardware device for providing display to a user. In an embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least partial processing associated with the display. In one embodiment, display subsystem 1630 includes a touchscreen (or trackpad) device that provides both output and input to the user.

I/O controller 1640 represents hardware devices and software components associated with user interaction. The I/O controller 1640 can be operated to manage the hardware system 1620 and/or the hardware that displays a portion of the subsystem 1630. In addition, I/O controller 1640 depicts a connection point for additional devices connected to computing device 1600 through which a user can interact with the system. For example, a device that can be attached to computing device 1600 can include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, or other I/O device for a particular application, such as a card reader. Machine or other device.

As mentioned above, I/O controller 1640 can interact with audio subsystem 1620 and/or display subsystem 1630. For example, input via a microphone or other audio device can provide input or commands for one or more applications or functions of computing device 1600. In addition, in addition to the display output, an audio output can be provided or the display output can be replaced by an audio output. In another example, if the display subsystem 1630 includes a touch screen, the display device is also used as an input device that can be at least partially managed by the I/O controller 1640. Additional buttons or switches can also be provided on computing device 1600 to provide I/O functionality managed by I/O controller 1640.

In an embodiment, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors, or other environmental sensors, or other hardware that can be included in computing device 1600. Inputs can be part of a direct user interaction and provide environmental input to the system to affect its operation (such as filtering noise, adjusting the display for brightness detection, applying a flash for the camera, or other characteristics).

In one embodiment, computing device 1600 includes power management 1650 that manages battery power usage, battery charging, and characteristics related to power saving operations. Memory subsystem 1660 includes a memory device for storing information in computing device 1600. The memory can include non-volatile (if the power to the memory device is interrupted, the state does not change) and/or volatility (if the power to the memory is interrupted, the state is uncertain) the memory device. The memory subsystem 1660 can store application data, user data, music, photos, files, or other materials, as well as system data (long-term or temporary) related to the execution of applications and functions of the computing device 1600.

The elements of the embodiments are also provided as a machine-readable medium (e.g., memory 1660) for storing computer-executable instructions (e.g., instructions for implementing any other processing discussed herein). The machine readable medium (eg, memory 1660) can include, but is not limited to, flash memory, compact disc, CD-ROM, DVD ROM, RAM, EPROM, EEPROM, magnetic or optical card, phase change memory (PCM), or other type of machine readable medium suitable for storing electronic or computer executable instructions. For example, an embodiment of the present disclosure can be downloaded as a computer program (eg, BIOS) that can be accessed from a remote computer via a communication link (eg, a data modem or a network connection) The server is transferred to the requesting computer (for example, the client).

Connectivity 1670 includes hardware devices (eg, wireless and/or wired connectors and communication hardware) and software components (eg, drivers, protocol stacks) to enable computing device 1600 to communicate with external devices. Computing device 1600 can be a stand-alone device, such as other computing devices, wireless access points or base stations, and peripherals such as earphones, printers, or other devices.

Connectivity 1670 can include a variety of different types of connectivity. For generalization, computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Honeycomb connectivity 1672 generally refers to cellular network connectivity provided by wireless carriers, such as via GSM (Global System for Mobile Communications) or change or derivative, CDMA (code division multiple access) or change or derivative, TDM ( Time-division multiplex) or change or derivative, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular and can include personal area networks (such as Bluetooth, near field, etc.), regional networks (such as Wi-Fi), and / Or a wide area network (such as WiMax), or other wireless communication.

Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (eg, drivers, protocol stacks) to create perimeter connections. It will be appreciated that computing device 1600 can be coupled to peripheral devices of other computing devices ("to" 1682) and has peripheral devices ("from" 1684") connected thereto. Computing device 1600 often has a "dock" connector to connect to other computing devices for purposes such as managing (eg, downloading and/or uploading, changing, synchronizing) content on computing device 1600. In addition, the docking connector can The computing device 1600 is allowed to connect to allow the computing device 1600 to control, for example, to a particular perimeter of the content output of the audiovisual or other system.

In addition to peripheral docking connectors or other peripheral connections, computing device 1600 can generate peripheral connections 1680 via a shared or standard-based connector. Common types can include universal serial bus (USB) connectors (which can include any number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Resolution Multimedia Interface (HDMI), FireWire, or other categories.

References to "an embodiment", "an embodiment", "a portion of an embodiment" or "another embodiment" in this specification are meant to include the particular properties, structures, or characteristics described in connection with the embodiments. Some embodiments, but not necessarily in all embodiments. The various forms of the "embodiment", "an embodiment", or "partial embodiment" are not necessarily all referring to the same embodiment. If the specification states that a component, feature, structure, or feature is "may", "may", or "can" is included, the component, characteristic, structure, or feature does not need to be included. If the specification or the scope of the patent application refers to "a" or "an" element, it does not mean that there is only one element. If the specification or the patent application is referred to the "extra" element, it is not excluded that there is more than one additional element.

In addition, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, the first embodiment can be combined with the second embodiment anywhere where the specific features, structures, functions, or features associated with the two embodiments are not mutually exclusive.

Although described in connection with the specific embodiments of the disclosed invention, Many modifications and variations of the embodiments are apparent to those skilled in the art. For example, other memory architectures, such as dynamic RAM (DRAM), may use the embodiments discussed. All such changes, modifications, and variations are intended to be included within the scope of the appended claims.

In addition, power supply/ground connections to integrated circuit (IC) wafers and other components may or may not be shown in the drawings for simplicity of illustration and discussion, and without obscuring the invention. In addition, the configuration may be shown in the form of a block diagram to avoid obscuring the present invention, and also in view of the fact that the specific details relating to the implementation of such a block diagram configuration are highly dependent on the platform of the disclosed invention (ie, such specific The details should be well within the knowledge of those skilled in the art). It will be apparent to those skilled in the art <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The description is therefore to be considered as illustrative and not restrictive.

The following examples pertain to other embodiments. The specific content in the examples can be used anywhere in one or more embodiments. All of the selective properties of the devices described herein can also be implemented in comparison to methods or processes.

For example, a device is provided comprising: a first interconnect; a second interconnect; a third interconnect; a first via comprising a metal insulator transition (MIT) material, wherein the first via is configured to couple the first Interconnecting to the third interconnect; and a second via comprising MIT material, wherein the second via is configured to couple the second interconnect to the third interconnect. In some embodiments, the MIT material comprises a material selected from the group consisting of VO ₂ , V _x O _y , Fe ₃ O ₄ , FeS, Ti _x O _y , TiS ₂ , LaCoO ₃ , SmNiO ₃ , and EuO.

In some embodiments, the material selected further comprises trace dopants or other impurity species. In some embodiments, the first, second, and third interconnects comprise materials selected from the group consisting of Cu and Al. In some embodiments, the selected material further comprises a dopant, an alloy material, or other impurity species. In some embodiments, the apparatus includes: a fourth interconnect; a fifth interconnect coupled to ground, wherein the fourth and fifth interconnects are disposed on either side of the first via; and coupled To the fourth interconnected transistor.

In some embodiments, the fourth and fifth interconnects are formed on the same metal layer. In some embodiments, the transistor is operable to apply an electric field to the first perforation. In some embodiments, the device includes: a first transistor coupled to the first interconnect and ground; and a second transistor coupled to the third interconnect and supply node. In some embodiments, the apparatus includes a pulse generator to apply: a first pulse to the first transistor; and a second pulse to the second transistor. In some embodiments, the first and second vias are operable to electrically couple the first and second interconnects to the third interconnect when the temperature rises above the threshold.

In another example, a memory is coupled to the memory, the processor has a device according to the device, and a wireless interface is configured to allow the processor to communicate with another device.

In another example, an apparatus is provided that includes first and second nanoelectromechanical systems (NEMS) strips; an input interconnect adjacent to the first NEMS strip; and an output adjacent to the second NEMS strip a first interconnect located adjacent to the first end of the first and second NEMS strips; a second interconnect located at a side of the second end of the first NEMS strip; and a third interconnect located beside the second end of the second NEMS strip. In some embodiments, the apparatus includes circuitry including: an input coupled to the second interconnect; and an output coupled to the third interconnect. In some embodiments, the circuit is a buffer. In some embodiments, the apparatus includes fourth and fifth interconnects positioned alongside the first and second NEMS strips.

In another example, a memory is coupled to the memory, the processor has a device according to the device, and a wireless interface is configured to allow the processor to communicate with another device.

In another example, a method is provided comprising: applying a first electric field across a first perforation comprising a metal insulator transition (MIT) material; and in response to applying the first electric field, first through the first perforation The interconnect is coupled to the third interconnect. In some embodiments, the method includes: applying a second electric field across a second via that includes the MIT material; and in response to applying the second electric field, coupling the second interconnect to the third mutual via the second via even.

In some embodiments, applying the first and second electric fields comprises applying the same electric field across the first and second perforations. In some embodiments, the MIT material comprises a material selected from the group consisting of VO ₂ , V _x O _y , Fe ₃ O ₄ , FeS, Ti _x O _y , TiS ₂ , LaCoO ₃ , SmNiO ₃ , and EuO. In some embodiments, the material selected further comprises trace dopants or other impurity species. In some embodiments, the first, second, and third interconnects comprise materials selected from the group consisting of Cu and Al. In some embodiments, the material further comprises: a dopant, an alloy material, or other impurity species.

In another example, a method is provided that includes: first and first The temperature of the two vias is increased above the threshold, the first and second vias being formed of a metal insulator transition (MIT) material; in response to increasing the temperature, the first interconnect is coupled to the third via via the first via And in response to increasing the temperature, coupling the second interconnect to the third interconnect via the second via.

In some embodiments, the method includes: reducing the temperature of the first and second perforations to below a threshold; in response to decreasing the temperature, the first interconnection and the third mutual via the first perforation Decoupling; and in response to reducing the temperature, the second interconnect is electrically decoupled from the third interconnect via the second via. In some embodiments, the MIT material comprises a material selected from the group consisting of VO ₂ , V _x O _y , Fe ₃ O ₄ , FeS, Ti _x O _y , TiS ₂ , LaCoO ₃ , SmNiO ₃ , and EuO. In some embodiments, the material selected further comprises trace dopants or other impurity species. In some embodiments, the first, second, and third interconnects comprise materials selected from the group consisting of Cu or Al. In some embodiments, the material further comprises a dopant, an alloy material, or other impurity species.

In another example, an apparatus is provided comprising: means for increasing a temperature of the first and second perforations above a threshold, the first and second perforations being formed of a metal insulator transition (MIT) material; a mechanism for coupling the first interconnect to the third interconnect via the first via in response to increasing the temperature; and coupling the second interconnect to the second via via the second via in response to increasing the temperature The third interconnected mechanism. In some embodiments, the apparatus includes: means for reducing the temperature of the first and second perforations below a threshold; in response to reducing the temperature, the first inter And a mechanism for electrically decoupling the third interconnect; and for responding to reducing the Temperature, a mechanism that electrically decouples the second interconnect from the third interconnect via the second via.

In some embodiments, the MIT material comprises a material selected from the group consisting of VO ₂ , V _x O _y , Fe ₃ O ₄ , FeS, Ti _x O _y , TiS ₂ , LaCoO ₃ , SmNiO ₃ , and EuO. In some embodiments, the material selected further comprises trace dopants or other impurity species. In some embodiments, the first, second, and third interconnects comprise materials selected from the group consisting of Cu and Al. In some embodiments, the material further comprises a dopant, an alloy material, or other impurity species.

In another example, a memory is coupled to the memory, the processor has a device according to the device, and a wireless interface is configured to allow the processor to communicate with another device.

The Abstract of the Disclosure will allow the reader to determine the nature and gist of the present disclosure. The Abstract is not to be construed as limiting the scope or the scope of the claims. The scope of the following patent application is hereby incorporated by reference in its entirety in its entirety in its entirety in the the the the the the

400‧‧‧ cross section

401a‧‧‧First Interconnection

401b‧‧‧Second interconnection

402a, 402b, 403a, 403b‧‧‧ metal wire

404a, 404b‧‧‧ MIT perforation

Claims (20)

An apparatus comprising: a first interconnect; a second interconnect; a third interconnect; a first via comprising a metal insulator transition (MIT) material, wherein the first via is configured to couple the first interconnect to the a third interconnect; and a second via comprising an MIT material, wherein the second via is configured to couple the second interconnect to the third interconnect. The device of claim 1, wherein the MIT material comprises VO ₂ , V _x O _y , Fe ₃ O ₄ , FeS, Ti _x O _y , TiS ₂ , LaCoO ₃ , SmNiO ₃ , and EuO. The material selected by the group. The device of claim 2, wherein the selected material further comprises a trace dopant or other impurity species. The device of claim 1, wherein the first, second, and third interconnects comprise a material selected from the group consisting of Cu and Al. The device of claim 4, wherein the selected material further comprises a dopant, an alloying material, or other impurity species. The device of claim 1, comprising: a fourth interconnect; a fifth interconnect coupled to the ground, wherein the fourth and fifth interconnects are disposed on either side of the first via; A transistor coupled to the fourth interconnect. The device of claim 6, wherein the fourth and fifth interconnects are formed on the same metal layer. The device of claim 6, wherein the transistor is operable to apply an electric field to the first perforation. The device of claim 1, comprising: a first transistor coupled to the first interconnect and the ground; and a second transistor coupled to the third interconnect and supply node. The device of claim 9, comprising a pulse generator for applying: a first pulse to the first transistor; and a second pulse to the second transistor. The device of claim 1, wherein the first and second perforations are operable to electrically couple the first and second interconnects to the third interconnect when the temperature rises above the threshold. An apparatus comprising: first and second nanoelectromechanical systems (NEMS) strips; an input interconnect adjacent to the first NEMS strip; an output interconnect adjacent to the second NEMS strip; a first interconnect, Positioned beside the first end of the first and second NEMS strips; a second interconnect located beside the second end of the first NEMS strip; and a third interconnect located in the second NEMS strip Next to the two ends. The device of claim 12, comprising the circuit comprising: An input coupled to the second interconnect; and an output coupled to the third interconnect. The device of claim 13, wherein the circuit is a buffer. The device of claim 12, comprising fourth and fifth interconnections located beside the first and second NEMS bands. A system comprising: a memory; a processor coupled to the memory, the processor having means comprising: a first interconnect; a second interconnect; a third interconnect; a first via comprising a metal insulator transition (MIT) material, wherein the first through hole is configured to couple the first interconnect to the third interconnect; and the second through hole includes MIT material, wherein the second through hole is used to couple the second through hole Connected to the third interconnect; and a wireless interface for allowing the processor to communicate with another device. The system of claim 16, wherein the MIT material comprises VO ₂ , V _x O _y , Fe ₃ O ₄ , FeS, Ti _x O _y , TiS ₂ , LaCoO ₃ , SmNiO ₃ , and EuO. The material selected by the group, and wherein the selected material further comprises trace dopants or other impurity species. The system of claim 16, wherein the first, second, and third interconnects comprise materials selected from the group consisting of Cu and Al. And wherein the selected material further comprises a dopant, an alloying material, or other impurity species. The system of claim 16 wherein the apparatus comprises: a fourth interconnect; a fifth interconnect coupled to ground, wherein the fourth and fifth interconnects are disposed on either side of the first via And a transistor coupled to the fourth interconnect. The system of claim 19, wherein the fourth and fifth interconnects are formed on the same metal layer, and wherein the transistor is operable to apply an electric field to the first via.