TW201735295A - Fan-out type semiconductor package - Google Patents

Abstract

A fan-out type semiconductor package includes: a semiconductor wafer having an active surface on which a connection pad is disposed and an inactive surface disposed to face the active surface; a first capacitor disposed adjacent to the semiconductor wafer; an encapsulation, The at least partially encapsulating the first connecting member and the semiconductor wafer; the first connecting member disposed on the encapsulant, the first capacitor and the semiconductor wafer; and the second capacitor disposed on the semiconductor wafer with the semiconductor wafer disposed thereon a surface of the first connecting member opposite to a surface of a connecting member, wherein the first connecting member includes a connection pad electrically connected to the connection pad of the semiconductor wafer, the first capacitor and the second capacitor, and the first capacitor And the second capacitor is electrically connected to the connection pad via a common power wiring of the redistribution layer.

Description

Fan-out type semiconductor package

The present invention relates to a fan-out type semiconductor package in which a connection terminal can extend beyond a region in which a semiconductor wafer is disposed.

Recently, an important recent trend in the development of technologies related to semiconductor wafers has been to reduce the size of semiconductor wafers. Therefore, in the field of packaging technology, according to the rapid increase in demand for small semiconductor wafers or the like, there has been a need for an implementation of a semiconductor package having a compact size and including a plurality of pins at the same time.

One type of packaging technology suggested to meet the technical requirements as described above is a fan-out type semiconductor package. Such a fan-out type package can be useful in implementing a large number of pins while having a compact size by redrawing the connection terminals beyond the area in which the semiconductor wafer is placed.

Meanwhile, the market for portable electronic devices such as a mini-note PC (tablebook PC), a tablet PC, a smart phone, and a handheld game device includes most of the market for semiconductor devices. Thus, as the demand for high speed portable electronic devices increases, portable electronic devices have a lower degree of power consumption. In the state of high-speed switching, the portable electronic device is required to be able to easily receive power.

Aspects of the present invention provide a fan-out type semiconductor package that improves the level of input impedance in the low frequency domain as well as in the high frequency domain regardless of the limited capacitor space.

According to an aspect of the present invention, a fan-out type semiconductor package may be provided, wherein capacitors may be respectively disposed on one surface and another surface of a connection member including a redistribution layer, and may be commonly connected to the redistribution layer The power wiring is thus electrically connected to the connection pads of the semiconductor wafer.

According to an aspect of the present invention, a fan-out type semiconductor package may include: a semiconductor wafer having an active surface on which a connection pad is disposed; and an inactive surface disposed to face the active surface; a first capacitor Adjacent to the semiconductor wafer; an encapsulant at least partially enclosing the first connecting member and the inactive surface of the semiconductor wafer; a first connecting member disposed in the encapsulant, a first capacitor and the active surface of the semiconductor wafer; and a second capacitor disposed on the first connection opposite a surface of the first connecting member on which the semiconductor wafer is disposed On the other surface of the component, wherein the first connecting component comprises a redistribution layer electrically connected to the connection pad of the semiconductor wafer, the first capacitor, and the second capacitor, and the first capacitor And the second capacitor is electrically connected to the connection pad via a common power wiring of the redistribution layer.

Hereinafter, an exemplary embodiment of the present invention will be described below with reference to the drawings. In the drawings, the shapes, sizes, and the like of the components may be enlarged or reduced for the sake of clarity.

The term "exemplary embodiment" as used herein is not intended to mean the same exemplary embodiment, and the exemplary embodiments are provided to emphasize specific features or characteristics that are different from the specific features or characteristics of the other exemplary embodiments. However, it is contemplated that the exemplary embodiments provided herein can be implemented by combining one exemplary embodiment with another exemplary embodiment in whole or in part. For example, an element described in a particular exemplary embodiment, even if not described in another exemplary embodiment, is understood to be a description of another exemplary embodiment, unless the contrary or contradict description.

The meaning of "connected" from one component to another in the description includes an indirect connection via a third component and a direct connection between the two components. In addition, "electrical connection" means the concept of including physical connections and physical disconnections. It will be understood that when the elements are referred to by "first" and "second", the elements are not limited thereby. "First" and "second" are used for the purpose of distinguishing the elements from other elements, and the order or importance of the elements may not be limited. In some cases, a first element may be referred to as a second element without departing from the scope of the invention as set forth herein. Similarly, the second element may also be referred to as a first element.

Herein, the upper portion, the lower portion, the upper side, the lower side, the upper surface, the lower surface, and the like are determined in the drawings. For example, the first connecting member is disposed above the level of the redistribution layer. However, the scope of the patent application is not limited to this. In addition, the vertical direction refers to the upward direction and the downward direction described above, and the horizontal direction refers to a direction perpendicular to the upward direction and the downward direction. In this case, the vertical cross section refers to a case taken along a plane in the vertical direction, and an example thereof may be a cross-sectional view illustrated in the drawings. In addition, the horizontal cross section refers to a case taken along a plane in the horizontal direction, and an example thereof may be a plan view illustrated in the drawings.

The use of the terminology herein is for the purpose of describing the illustrative embodiments only, In this case, the singular forms include the plural unless the context is otherwise interpreted.

Electronic device

FIG. 1 is a schematic block diagram illustrating an example of an electronic device system.

Referring to FIG. 1, the electronic device 1000 can accommodate the motherboard 1010. The motherboard 1010 can include a wafer related component 1020, a network related component 1030, other components 1040, and the like that are physically or electrically connected to the motherboard 1010. These components can be connected to other components to be described below to form various signal lines 1090.

The wafer related component 1020 can include: a memory chip such as a volatile memory (eg, dynamic random access memory (DRAM)), non-volatile memory (eg, read only memory (read only) Memory; ROM)), flash memory or the like; an application processor chip, such as a central processing unit (eg, a central processing unit (CPU)), a graphics processor (eg, a graphics processing unit (eg, a graphics processing unit) Graphics processing unit; GPU)), digital signal processor, cryptographic processor, microprocessor, microcontroller, or the like; and logic chips, such as analog/digital converters, application-specific circuits Integrated circuit; ASIC) or the like, or other similar components. However, wafer related component 1020 is not limited thereto, but may also include other types of wafer related components. Additionally, wafer related components 1020 can be combined with each other.

Network related component 1030 may include protocols such as: wireless fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series or the like), microwave storage Worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 series or the like), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high speed packet High speed packet access + (HSPA+), high speed downlink packet access + (HSDPA+), high speed uplink packet access + (HSUPA+) , enhanced data GSM environment (EDGE), global system for mobile communications (GSM), global positioning system (GPS), general package radio service (general package radio service; GPRS), code division multiple access (code div Iso multiplex access; CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G, 4G, 5G, and Any other wireless and wired protocols specified later. However, network related component 1030 is not limited thereto, but may also include a variety of other wireless or wired standards or protocols. Additionally, along with the wafer related components 1020 described above, the network related components 1030 can be combined with one another.

The other components 1040 may include a high frequency inductor, a ferrite inductor, a power inductor, a ferrite bead, a low temperature co-fired ceramic (LTCC), and an electromagnetic interference (EMI) filter. , multilayer ceramic capacitor (MLCC) or the like. However, other components 1040 are not limited thereto, but may also include passive components or the like that are used for various other purposes. Additionally, along with the wafer related component 1020 or network related component 1030 described above, other components 1040 can be combined with each other.

Depending on the type of electronic device 1000, electronic device 1000 may include other components that may be physically or electrically connected to or may not be physically or electrically connected to motherboard 1010. Such other components may include, for example, camera module 1050, antenna 1060, display device 1070, battery 1080, audio codec (not shown), video codec (not shown), power amplifier (not shown) ), compass (not shown), accelerometer (not shown), gyroscope (not shown), speaker (not shown), mass storage unit (such as hard disk drive) (not shown), compact disc A (compact disk; CD) machine (not shown), a digital versatile disk (DVD) machine (not shown) or the like. However, such other components are not limited thereto, but may depend on the type of electronic device 1000 or the like, and may include other components used for various purposes.

The electronic device 1000 can be a smart phone, a personal digital assistant (PDA), a digital camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a mini-note PC, a television, Video game consoles, smart watches, automotive components or the like. However, the electronic device 1000 is not limited thereto and may be any other electronic device that processes data.

FIG. 2 is a schematic perspective view illustrating an example of an electronic device.

Referring to FIG. 2, a semiconductor package can be used in various electronic devices 1000 as described above for various purposes. For example, the main board 1110 can be housed in the body 1101 of the smart phone 1100, and the various electronic components 1120 can be physically or electrically connected to the main board 1110. Additionally, other components (such as camera module 1050) that may be physically or electrically connected to or may not be physically or electrically connected to motherboard 1110 may be housed in body 1101. Some of the electronic components 1120 may be wafer related components, and the semiconductor package 100 may be, for example, an application processor between wafer related components, but is not limited thereto. The electronic device is not necessarily limited to the smart phone 1100, but may be other electronic devices as described above.

Semiconductor package

In general, numerous fine circuits are integrated into semiconductor wafers. However, the semiconductor wafer itself cannot act as a finished semiconductor product and may be damaged due to external physical or chemical influences. Therefore, the semiconductor wafer itself is not used, but is packaged and used in an electronic device or the like in a packaged state.

Here, a semiconductor package is required due to the difference in circuit width between the semiconductor wafer and the main board of the electronic device in terms of electrical connection. In detail, the spacing between the connection pads of the semiconductor wafer and the connection pads of the semiconductor wafer is extremely fine, but the size of the component mounting pads of the main board used in the electronic device and the interval between the component mounting pads of the main board are significantly larger than that of the semiconductor wafer. Case. Therefore, it may be difficult to directly mount the semiconductor wafer on the main board, and a packaging technique for buffering a difference in circuit width between the semiconductor wafer and the main board is required.

Semiconductor packages fabricated by packaging techniques may be divided into fan-in type semiconductor packages and fan-out type semiconductor packages depending on the structure and the purpose thereof.

The fan-in type semiconductor package and the fan-out type semiconductor package will be described in more detail below with reference to the drawings.

(Fan-in type semiconductor package)

3A and 3B are schematic cross-sectional views illustrating a state of a fan-in type semiconductor package before and after being packaged.

4 is a schematic cross-sectional view illustrating a packaging process of a fan-in type semiconductor package.

Referring to the drawings, the semiconductor wafer 2220 can be, for example, an integrated circuit (IC) in an uncovered state, comprising: a body 2221 comprising germanium (Si), germanium (Ge), gallium arsenide (GaAs), or Similarly, a connection pad 2222 formed on one surface of the body 2221 and containing a conductive material such as aluminum (Al) or the like; and a passivation layer 2223 such as an oxide film, a nitride film or the like It is formed on one surface of the body 2221 and covers at least a portion of the connection pad 2222. Here, since the connection pad 2222 is extremely small, it is difficult to mount an integrated circuit (IC) on an intermediate-grade printed circuit board (PCB) and a main board of an electronic device or the like.

Therefore, the connection member 2240 can be formed on the semiconductor wafer 2220 depending on the size of the semiconductor wafer 2220 to re-attach the connection pad 2222. The insulating layer 2241 is formed on the semiconductor wafer 2220 by using an insulating material such as a photoimageable dielectric (PID) resin, the via hole 2243h forming the open connection pad 2222, and the wiring pattern 2242 and the via are subsequently formed. The holes 2243 are formed to form the connecting member 2240. Subsequently, a passivation layer 2250 of the protective connection member 2240 may be formed, an opening 2251 may be formed, and the under bump metal layer 2260 or the like may be formed. That is, the fan-in type semiconductor package 2200 including, for example, the semiconductor wafer 2220, the connection member 2240, the passivation layer 2250, and the under bump metal layer 2260 can be fabricated through a series of processes.

As described above, the fan-in type semiconductor package may have a package form in which all connection pads (for example, input/output (I/O) terminals) of the semiconductor wafer are disposed inside the semiconductor wafer, and may have excellent Electrical characteristics and can be produced at low cost. Therefore, many components mounted in smart phones have been manufactured in a fan-in type semiconductor package. In particular, many components installed in smart phones have been developed to implement fast signal transmission while having a compact size.

However, since all of the I/O terminals need to be disposed inside the semiconductor wafer in the fan-in type semiconductor package, the fan-in type semiconductor package has a large space limitation. Therefore, it is difficult to apply this structure to a semiconductor wafer having a large number of I/O terminals or a semiconductor wafer having a compact size. In addition, due to the disadvantages described above, it is not possible to directly mount and use a fan-in type semiconductor package on the main board of the electronic device. The reason is that even if the size of the I/O terminal of the semiconductor wafer and the interval between the I/O terminals of the semiconductor wafer are increased by the redistribution process, the size of the I/O terminal of the semiconductor wafer and the I/O terminal of the semiconductor wafer are increased. The spacing between them is also insufficient to directly mount the fan-in type semiconductor package on the main board of the electronic device.

5 is a schematic cross-sectional view illustrating a state in which a fan-in type semiconductor package is mounted on a plug-in substrate and finally mounted on a main board of an electronic device.

6 is a schematic cross-sectional view illustrating a state in which a fan-in type semiconductor package is embedded in a plug-in substrate and finally mounted on a main board of an electronic device.

Referring to the drawings, in the fan-in type semiconductor package 2200, the connection pads 2222 (ie, I/O terminals) of the semiconductor wafer 2220 can be redistributed again via the interposer substrate 2301, and the fan-in type semiconductor package 2200 can be mounted thereon. Finally, it is mounted on the main board 2500 of the electronic device in a state on the plug-in substrate 2301. Here, the solder balls 2270 and the like may be fixed by the underfill resin 2280 or the like, and the outer side of the semiconductor wafer 2220 may be covered by the molding material 2290 or the like. Alternatively, the fan-in type semiconductor package 2200 may be embedded in a separate interposer substrate 2302, and the connection pads 2222 (ie, I/O terminals) of the semiconductor wafer 2220 may be embedded in the interposer substrate 2302 in the fan-in type semiconductor package 2200. The upper state is again redistributed by the interposer substrate 2302, and the fan-in type semiconductor package 2200 can be finally mounted on the main board 2500 of the electronic device.

As described above, it may be difficult to directly mount and use a fan-in type semiconductor package on a main board of an electronic device. Therefore, the fan-in type semiconductor package can be mounted on a separate interposer substrate via a packaging process and then mounted on a main board of the electronic device, or can be mounted on the main board of the electronic device in a state of being embedded in the interposer substrate. And use.

(Fan-out type semiconductor package)

FIG. 7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package.

Referring to the drawings, in the fan-out type semiconductor package 2100, for example, the outer side of the semiconductor wafer 2120 may be protected by the encapsulation 2130, and the connection pads 2122 of the semiconductor wafer 2120 may be re-distributed by the connection member 2140 up to the outside of the semiconductor wafer 2120. Here, the passivation layer 2150 may be further formed on the connection member 2140, and the under bump metal layer 2160 may be further formed in the opening of the passivation layer 2150. Solder balls 2170 may be further formed on the under bump metal layer 2160. The semiconductor wafer 2120 can be an integrated circuit (IC) including a body 2121, a connection pad 2122, a passivation layer (not shown), and the like. The connecting member 2140 may include an insulating layer 2141, a redistribution layer 2142 formed on the insulating layer 2141, and a via hole 2143 electrically connecting the connection pad 2122 and the redistribution layer 2142 to each other.

As described above, the fan-out type semiconductor package may have a form in which the I/O terminals of the semiconductor wafer are redistributed via a connection member formed on the semiconductor wafer and placed up to the outside of the semiconductor wafer. As described above, in a fan-in type semiconductor package, all I/O terminals of a semiconductor wafer need to be disposed inside the semiconductor wafer. Therefore, when the size of the semiconductor wafer is reduced, it is necessary to reduce the size and pitch of the balls, so that the standardized ball layout is not usable in the fan-in type semiconductor package. On the other hand, the fan-out type semiconductor package has a form in which an I/O terminal of a semiconductor wafer is redistributed via a connection member formed on a semiconductor wafer and placed up to the outside of the semiconductor wafer, as described above. Therefore, even if the size of the semiconductor wafer is reduced, the standardized ball layout can be used as it is in the fan-out type semiconductor package, so that the fan-out type semiconductor package can be mounted on the main board of the electronic device without using a separate interposer substrate, as follows Described.

FIG. 8 is a schematic cross-sectional view illustrating a state in which a fan-out type semiconductor package is mounted on a main board of an electronic device.

Referring to the drawings, the fan-out type semiconductor package 2100 can be mounted on the main board 2500 of the electronic device via the solder balls 2170 or the like. That is, as described above, the fan-out type semiconductor package 2100 includes the connection member 2140 formed on the semiconductor wafer 2120 and capable of re-stacking the connection pad 2122 up to the fan-out area beyond the size of the semiconductor wafer 2120, so that the standardization ball The layout can be used as it is in the fan-out type semiconductor package 2100. Therefore, the fan-out type semiconductor package 2100 can be mounted on the main board 2500 of the electronic device without using a separate interposer substrate or the like.

As described above, since the fan-out type semiconductor package can be mounted on the main board of the electronic device without using a separate interposer substrate, the fan-out type semiconductor package can be thinner than the fan-in type semiconductor package using the interposer substrate. Implemented in the case of thickness. Therefore, the fan-out type semiconductor package can be miniaturized and thinned. In addition, the fan-out type semiconductor package has excellent thermal characteristics as well as electrical characteristics, making it particularly suitable for mobile products. Therefore, a fan-out type semiconductor package can be implemented in a tighter form using a printed circuit board (PCB) than a general package-on-package (POP) form, and the fan-out The type semiconductor package can solve the problem attributed to the occurrence of bending phenomenon.

Meanwhile, the fan-out type semiconductor package refers to a packaging technology for mounting a semiconductor wafer on a main board of an electronic device or the like as described above and protecting the semiconductor wafer from external influence, and is similar to, for example, a plug-in substrate or the like. The concept of a printed circuit board (PCB) having a scale, a purpose, and the like different from the scale, purpose, and the like of the fan-out type semiconductor package and having a fan embedded therein In-type semiconductor package.

A fan-out type semiconductor package which can improve the level of the input impedance in the low frequency domain and the high frequency domain will be described hereinafter with reference to the drawings.

FIG. 9 is a schematic cross-sectional view illustrating an example of a fan-out type semiconductor package.

FIG. 10 is a schematic plan view taken along line I-I' of the fan-out type semiconductor package of FIG. 9.

FIG. 11 is a schematic plan view illustrating the fan-out type semiconductor package of FIG. 9 when viewed in the direction A.

Referring to the drawings, a fan-out type semiconductor package 100A according to an exemplary embodiment of the present invention may include a semiconductor wafer 120 having an active surface on which a connection pad 122 is disposed and a non-active surface disposed to face the active surface. a first capacitor 180 disposed adjacent to the semiconductor wafer 120; an encapsulant 130 encapsulating the first capacitor 180 and at least a portion of the inactive surface of the semiconductor wafer 120; a first connecting member 140 disposed in the bladder a sealing body 130, a first capacitor 180, and an active surface of the semiconductor wafer 120; and a second capacitor 190 disposed on the first connecting member 140 opposite to a surface of the first connecting member 140 on which the semiconductor wafer 120 is disposed On the other surface. The first connection member 140 may include a connection pad 122 electrically connected to the semiconductor wafer 120, a first capacitor 180, and a redistribution layer 142a of the second capacitor 190 and a redistribution layer 142b. The first capacitor 180 and the second capacitor 190 may be electrically connected to the connection pads 122 of the semiconductor wafer 120 via the common power wiring P of the redistribution layer 142a and the redistribution layer 142b. In addition, the fan-out type semiconductor package 100A according to an exemplary embodiment may further include: a second connection member 110 having a via hole 110H; a passivation layer 150 disposed on the first connection member 140; a bump under metal layer 160 It is disposed on the passivation layer 150 and disposed in the opening 151 of the passivation layer 150; and a connection terminal 170 disposed on the under bump metal layer 160.

Generally, a semiconductor package can be mounted on a main board or the like using a connection terminal such as a solder ball. This connection terminal may be disposed on the other surface of the redistribution layer to be electrically connected to the wiring in the redistribution layer. Meanwhile, since a smooth supply of electric power is recently required, it is considered to dispose the decoupling capacitor on a portion of a region where the connection terminal can be disposed on the other surface of the redistribution layer. However, since the space in which the connection terminals can be disposed is limited, when the number of such decoupling capacitors for smooth supply of power (for example, in terms of ensuring capacitance) is increased, the number of connection terminals that can be provided may be reduced. Instead, this can lead to problems with the power supply. As an alternative to the decoupling capacitor, the decoupling capacitor can be considered to be placed around the IC on one surface of the redistribution layer. However, in this case, since the decoupling capacitor and the IC have a significant electrical connection path therebetween, side effects may occur next.

Meanwhile, as in the fan-out type semiconductor package 100A according to the exemplary embodiment, when the first capacitor 180 and the second capacitor 190 are respectively disposed in one of the first connection members 140 including the redistribution layer 142a and the redistribution layer 142b When the surface and the other surface and can be commonly connected to the power wiring P, a sufficient amount of capacitance can be obtained regardless of the limited space, thereby achieving a smooth supply of power. In addition, a low equivalent series inductance (ESL) can be implemented. In more detail, instead of increasing the number of second capacitors 190 disposed on the other surface of the first connection member layer 140, a first capacitor 180 disposed on one surface of the first connection layer 140 may be provided to reduce Space restrictions. In this case, the first capacitor 180 and the second capacitor 190 may be commonly connected to the power wiring P without providing not only the first capacitor 180, thus increasing the total capacitance of the first capacitor 180 and the second capacitor 190 commonly connected to the power wiring P . Thus, the input impedance of the low frequency domain can be improved. In addition, the total equivalent series inductance of the first capacitor 180 and the second capacitor 190 that are commonly connected to the power wiring P can be reduced. Thus, the input impedance in the high frequency domain can be improved.

The respective components included in the fan-out type semiconductor package 100A according to the exemplary embodiment will be described in more detail below.

The semiconductor wafer 120 may be an integrated circuit (IC) provided in an amount of hundreds to millions of elements or more integrated in a single wafer. The integrated circuit can be, for example, an application processor chip such as a central processing unit (eg, a CPU), a graphics processor (eg, a GPU), a digital signal processor, a cryptographic compilation processor, a microprocessor, a microcontroller Or the like, but not limited to this. The semiconductor wafer 120 can be formed based on the active wafer. In this case, the base material of the body 121 may be bismuth (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits may be formed on the body 121. Connection pads 122 can electrically connect semiconductor wafer 120 to other components. The material of the connection pad 122 may be a conductive material such as aluminum (Al) or the like. The passivation layer 123 exposing the connection pad 122 may be formed on the body 121, and may be an oxide film formed of SiO or the like, a nitride film formed of SiN or the like, or an oxide layer and a nitride layer. Double layer. The lower surface of the connection pad 122 may have a stepped portion that passes through the passivation layer 123 from the lower surface of the encapsulation 130. Thus, the phenomenon that the encapsulation body 130 is oozing to the lower surface of the connection pad 122 can be prevented to some extent. The insulating layer (not shown) and the like can be further disposed at other desired locations.

The encapsulant 130 can protect the semiconductor wafer 120, the first capacitor 180, the second connection member 110, and the like. The encapsulated form of the encapsulant 130 is not particularly limited, but may be in the form of at least a portion of the encapsulant 130 surrounding the semiconductor wafer 120, the first capacitor 180, and the second connecting member 110, and the like. For example, the encapsulant 130 may cover the first capacitor 180, the second connecting member 110, and the inactive surface of the semiconductor wafer 120 and fill the space therebetween. In addition, the encapsulant 130 may also fill at least a portion of the space between the passivation layer 123 of the semiconductor wafer 120 and the first connection member 140. At the same time, the encapsulant 130 can fill the via 110H, thus acting as an adhesive and reducing the buckling of the semiconductor wafer 120 depending on certain materials due to the encapsulant 130.

Certain materials of the encapsulant 130 are not specifically limited. For example, an insulating material can be used as the material for the encapsulant 130. In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, or a resin having a reinforcing material such as an inorganic filler impregnated in a thermosetting resin and a thermoplastic resin. Such as ABF, FR-4, BT, PID resin or the like. In addition, known molding materials such as EMC or the like can also be used. Alternatively, a resin in which a thermosetting resin or a thermoplastic resin is impregnated with an inorganic filler in a core material such as glass cloth (or glass cloth) may be used as the insulating material.

The encapsulant 130 may contain conductive particles to block electromagnetic waves, as needed. For example, the conductive particles may be any material that blocks electromagnetic waves, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb). ), titanium (Ti), solder or the like. However, this is merely an example, and the conductive particles are not particularly limited thereto.

The first connection component 140 can be configured to re-attach the connection pads 122 of the semiconductor wafer 120. The tens to hundreds of connection pads 122 having various functions may be redistributed by the first connection member 140, and may be physically or electrically connected to an external source via a connection terminal 170 to be described below depending on a function. The first connecting member 140 may include: an insulating layer 141a and an insulating layer 141b; a redistribution layer 142a and a redistribution layer 142b disposed on the insulating layer 141a and the insulating layer 141b; and a via hole 143a and a via hole 143b, The insulating layer 141a and the insulating layer 141b are penetrated and the redistribution layer 142a and the redistribution layer 142b are connected to each other. In the fan-out type semiconductor package 100A according to the exemplary embodiment, the first connection member 140 may include a plurality of layers, but is not limited thereto, and may also include a single layer.

An insulating material may be used as the material of each of the insulating layers 141a and 141b. In this case, a photosensitive insulating material such as a photoimageable dielectric (PID) resin may also be used as the insulating material. In this case, each of the insulating layer 141a and the insulating layer 141b may be formed to have a small thickness, and the fine pitch of each of the via hole 143a and the via hole 143b may be more easily achieved. When the insulating layer 141a and the insulating layer 141b are a plurality of layers, the materials of the insulating layer 141a and the insulating layer 141b may be the same as each other, and may be different from each other. In the case where the insulating layer 141a and the insulating layer 141b are a plurality of layers, the insulating layer 141a and the insulating layer 141b may be integrated with each other depending on the process, so that the boundary therebetween may not be obvious.

The redistribution layer 142a and the redistribution layer 142b can be used to substantially reattach the connection pads 122. The material of each of the redistribution layer 142a and the redistribution layer 142b may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel ( Ni), lead (Pb), titanium (Ti) or alloys thereof. The redistribution layer 142a and the redistribution layer 142b may perform various functions depending on the design of their corresponding layers. For example, each of the redistribution layer 142a and the redistribution layer 142b may include ground (GND) wiring, power (PWR) wiring, signal (S) wiring, or the like. Here, the signal (S) wiring may include various signals other than the ground wiring, the power wiring, or the like, for example, a data signal or the like. Additionally, each of the redistribution layer 142a and the redistribution layer 142b may comprise a via pad, a connection terminal pad, or the like.

A surface treatment layer (not shown) may be further formed on portions of the wiring exposed from the redistribution layer 142a and the redistribution layer 142b, as needed. The surface treatment layer (not shown) is not particularly limited as long as it is known in the prior art, and can be, for example, electrolytic gold plating, electroless gold plating, organic solderability preservative (OSP) ) or electroless tin plating, electroless silver plating, electroless nickel plating / replaced gold plating, direct immersion gold (DIG) plating, hot air solder leveling (HASL) or the like to form .

The via hole 143a and the via hole 143b can electrically connect the redistribution layer 142a and the redistribution layer 142b formed on the different layers, the connection pad 122, or the like to each other, thereby generating electricity in the fan-out type semiconductor package 100A. path. The material of each of the via hole 143a and the via hole 143b may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel ( Ni), lead (Pb), titanium (Ti) or alloys thereof. Each of the via holes 143a and the via holes 143b may be completely filled with a conductive material, or may be formed along the walls of each of the via holes 143a and the via holes 143b. Additionally, each of via holes 143a and via holes 143b can have all of the shapes known in the prior art, such as tapered shapes, cylindrical shapes, and the like.

The first capacitor 180 can be used to replenish the amount of capacitance that the second capacitor 190 to be described below may not be sufficient when used alone. The first capacitor 180 may be disposed on one surface of the first connection member 140 adjacent to the semiconductor wafer 120. For example, the first capacitor 180 may be disposed on the same level as the semiconductor wafer 120 in the thickness direction T. The first capacitor 180 may be connected to the power wiring P of the first connection member 140 via the power via hole 143 aP of the first connection member 140 . The first capacitor 180 may be a multilayer ceramic capacitor (MLCC), and may be a multilayer ceramic capacitor used as an embedded type element in the prior art. This may allow the first capacitor 180 to be replenished by a sufficient amount of capacitance.

The second capacitor 190 can be used to provide a basic capacitance and implement a low equivalent series inductance. The second capacitor 190 may be surrounded by a connection terminal 170 on the other surface of the first connection member 140 opposed to one surface of the first connection member 140 on which the semiconductor wafer 120 is disposed. For example, the second capacitor 190 may be disposed on the same level as the level of the connection terminal 170 in the thickness direction T. In this case, the second capacitor 190 may be disposed in such a manner that the electrical connection path between the second capacitor 190 and the semiconductor wafer 120 can be significantly reduced. The second capacitor 190 can be directly connected to the power wiring P of the first connection member 140 without a separate via hole. The second capacitor 190 can be a surface-mount technology (SMT) capacitor as described below, and can thus have a structure in which the second capacitor 190 can have electrodes disposed on its lower surface. This structure can allow the second capacitor 190 to have a small thickness and its equivalent series inductance is significantly reduced.

When the levels of the capacitances of the first capacitor 180 and the second capacitor 190 are defined as C ₁ and C ₂ , respectively, C ₁ may be equal to C ₂ . In addition, when the thicknesses of the first capacitor 180 and the second capacitor 190 are defined as t ₁ and t ₂ , respectively, t ₁ may be greater than t ₂ . The second capacitor 190 may be disposed to be surrounded by the connection terminal 170. When the second capacitor 190 is thicker than the connection terminal 170, the fan-out type semiconductor package 100A may be difficult to mount on the main board. For example, the thickness of the second capacitor 190 can be limited and can therefore be less likely to have a high capacitance. At the same time, the first capacitor 180 can be disposed adjacent to the semiconductor wafer 120 and can thus have substantially the same thickness as the thickness of the semiconductor wafer 120. For example, the limit of the thickness of the first capacitor 180 may be less than the limit of the thickness of the second capacitor 190, and the capacitance of the first capacitor 180 may thus be higher than the capacitance of the second capacitor 190.

When the levels of the equivalent series inductances of the first capacitor 180 and the second capacitor 190 are defined as L ₁ and L ₂ , respectively, L ₁ may be equal to L ₂ . In addition, when the levels of the equivalent series resistances (ESR) of the first capacitor 180 and the second capacitor 190 are defined as R ₁ and R ₂ , respectively, R ₁ may be equal to R ₂ . Since the second capacitor 190, which may have a significantly reduced electrical connection path from the semiconductor wafer 120, has a low equivalent series inductance and a low equivalent series resistance, the total equivalent of the first capacitor and the second capacitor that are commonly connected to the power wiring P The series inductance and the total equivalent series resistance can be reduced.

The second connection member 110 may include a redistribution layer 112a and a redistribution layer 112b that redistribute the connection pads 122 of the semiconductor wafer 120 to thereby reduce the number of layers of the first connection member 140. The second connecting member 110 may maintain the hardness of the fan-out type semiconductor package 100A depending on certain materials, as needed, and to ensure the uniformity of the thickness of the encapsulant 130. In some cases, the fan-out type semiconductor package 100A according to the exemplary embodiment may be used as a part of the stacked package due to the second connection member 110. The second connection member 110 may have a through hole 110H. The via 110H may space the semiconductor wafer 120 and the first capacitor 180 disposed in the via 110H from the second connection member 110. For example, the semiconductor wafer 120 and the side surface of the first capacitor 180 may be surrounded by the second connection member 110. The first capacitor 180 may be disposed in a groove formed in the through hole 110H of the second connection member 110. However, this arrangement form is merely an example, and may be modified into other forms in various ways, and the fan-out type semiconductor package 100A may perform another function depending on this form.

The second connecting member 110 may include: an insulating layer 111 contacting the first connecting member 140; a first redistribution layer 112a contacting the first connecting member 120 and embedded in the insulating layer 111; and a second redistribution layer 112b, It is disposed on the other surface of the insulating layer 111 opposed to one surface of the insulating layer 111 in which the first redistribution layer 112a is embedded. The second connection member 110 may include a via hole 113 that penetrates the insulating layer 111 and electrically connects the first redistribution layer 112a and the second redistribution layer 112b to each other. The first redistribution layer 112a and the second redistribution layer 112b may be electrically connected to the connection pads 122. When the first redistribution layer 112a is embedded in the insulating layer 111, the stepped portion due to the thickness of the first redistribution layer 112a can be significantly reduced, and the insulation distance of the first connection member 140 can thus become constant . That is, the distance from the redistribution layer 142a of the first connecting member 140 and the redistribution layer 142b to the lower surface of the insulating layer 111 is from the redistribution layer 142a of the first connection member 140 and the redistribution layer 142b to the connection pad 122. The difference between the distances may be less than the thickness of the first redistribution layer 112a. Therefore, the high-density wiring design of the first connection member 140 can be easily implemented.

The material of the insulating layer 111 is not particularly limited. For example, an insulating material may be used as the material of the insulating layer 111. In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a thermosetting resin or a thermoplastic resin impregnated with an inorganic filler such as glass cloth (or glass fabric). Resins in the core material, for example, prepreg, Ajinomoto Build up Film (ABF), FR-4, Bismaleimide Triazine (BT) or the like. Alternatively, a photoimageable dielectric (PID) resin may be used as the insulating material.

The redistribution layer 112a and the redistribution layer 112b can be used to re-attach the connection pads 122 of the semiconductor wafer 120. The material of each of the redistribution layer 112a and the redistribution layer 112b may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel ( Ni), lead (Pb), titanium (Ti) or alloys thereof. The redistribution layer 112a and the redistribution layer 112b may perform various functions depending on the design of their corresponding layers. For example, each of the redistribution layer 112a and the redistribution layer 112b may include a ground (GND) wiring, a power (PWR) wiring, a signal (S) wiring, or the like. Additionally, each of the redistribution layer 112a and the redistribution layer 112b may comprise a via hole pad, a connection terminal pad, or the like. As a non-limiting example, most of the redistribution layer 112a and the redistribution layer 112b may be formed by ground wiring. In this case, the number of ground wirings formed on the redistribution layer 142a of the first connection member 140 and the redistribution layer 142b can be remarkably reduced, so that the degree of freedom in wiring design can be improved.

A surface treatment layer (not shown) may be further formed on a portion of the wiring exposed through the opening 131 formed in the encapsulant 130 from the redistribution layer 112a and the redistribution layer 112b, as needed. The surface treatment layer (not shown) is not particularly limited as long as it is known in the prior art, and can be, for example, electrolytic gold plating, electroless gold plating, organic solderability preservative (OSP) ) or electroless tin plating, electroless silver plating, electroless nickel plating / replaced gold plating, direct immersion gold (DIG) plating, hot air solder leveling (HASL) or the like to form .

The via hole 113 may electrically connect the redistribution layer 112a and the redistribution layer 112b formed on the different layers to each other, thereby generating an electrical path in the second connection member 110. Each of the via holes 113 may also be formed of a conductive material. Each of the via holes 113 may be completely filled with a conductive material, as illustrated in FIG. 10, or a conductive material may be formed along the walls of each of the via holes 113. Additionally, each of the via holes 113 can have all of the shapes known in the prior art, such as tapered shapes, cylindrical shapes, and the like.

The thickness of the redistribution layer 112a and the redistribution layer 112b of the second connection member 110 may be greater than the thickness of the redistribution layer 142a and the redistribution layer 142b of the first connection member 140. Since the thickness of the second connection member 110 may be equal to or greater than the thickness of the semiconductor wafer 120, the redistribution layer 112a and the redistribution layer 112b formed in the second connection member 110 may be formed large depending on the scale of the second connection member 110. the size of. On the other hand, since the first connecting member 140 is thin, the redistribution layer 142a and the redistribution layer 142b of the first connecting member 140 can be formed to be relatively larger than the size of the redistribution layer 112a and the redistribution layer 112b of the second connecting member 110. Small size.

The inactive surface of the semiconductor wafer 120 may be disposed on a lower level than the upper surface of the second redistribution layer 112b of the second connecting member 110. For example, the inactive surface of the semiconductor wafer 120 can be disposed on a lower level than the upper surface of the insulating layer 111 of the second connection member 110. The height difference between the inactive surface of the semiconductor wafer 120 and the upper surface of the second redistribution layer 112b of the second connection member 110 may be 2 μm or more, for example, may be 5 μm or more. In this case, the occurrence of cracks in the corners of the inactive surface of the semiconductor wafer 120 can be effectively prevented. In addition, the deviation of the insulation distance on the inactive surface of the semiconductor wafer 120 in the case where the encapsulant 130 is used can be significantly reduced.

The passivation layer 150 can be configured to protect the first connection component 140 from external physical or chemical damage. The passivation layer 150 may have an opening 151 that exposes at least a portion of the redistribution layer 142a of the first connection member 140 and the wiring of the redistribution layer 142b. Each of the openings 151 may expose all or only a portion of the surface of each of the redistribution layer 142a and the redistribution layer 142b. In some cases, each of the openings 151 may expose a side surface of each of the redistribution layer 142a and the redistribution layer 142b.

The material of the passivation layer 150 is not particularly limited, and may be, for example, a photosensitive insulating material. Alternatively, a solder resist may be used as the material of the passivation layer 150. Alternatively, an insulating resin (for example, an Ajinomoto accumulation film containing an inorganic filler and an epoxy resin, or the like) containing no core material but containing a filler may be used as the material of the passivation layer 150. The surface roughness of the passivation layer 150 can be lower than in the general case. When the surface roughness is as low as described above, several side effects that may occur next in the circuit formation process can be improved, for example, spots on the surface, difficulty in implementing fine circuits, and the like.

The under bump metal layer 160 can additionally be configured to improve the connection reliability of the connection terminals 170 to improve board level reliability. The under bump metal layer 160 may fill at least a portion of the opening 151 of the passivation layer 150. The under bump metal layer 160 can be formed by a known metallization method. The under bump metal layer 160 may comprise a known metal. The under bump metal layer 160 is formed by forming a seed layer by electroplating copper and forming a plating layer on the seed layer by electroless copper plating.

The connection terminal 170 may be additionally configured to physically connect or electrically connect the fan-out type semiconductor package 100A externally. For example, the fan-out type semiconductor package 100A can be mounted on the main board of the electronic device via the connection terminal 170. Each of the connection terminals 170 may be formed of a conductive material such as solder or the like. However, this is merely an example, and the material of each of the connection terminals 170 is not particularly limited thereto. Each of the connection terminals 170 may be a pad, a ball, a pin, or the like. The connection terminal 170 may be formed in a multilayer structure or a single layer structure. When the connection terminal 170 is formed in a multilayer structure, the connection terminal 170 may include a copper post and solder. When the connection terminal 170 is formed in a single layer structure, the connection terminal 170 may include tin-silver solder or copper. However, this is merely an example, and the connection terminal 170 is not limited thereto. The number, spacing, arrangement, or the like of the connection terminals 170 are not particularly limited and may be sufficiently modified by those skilled in the art depending on the design details. For example, the connection terminal 170 may be provided in an amount of several tens to several thousands depending on the number of the connection pads 122 of the semiconductor wafer 120, but is not limited thereto, and may be provided in an amount of tens of thousands or more.

At least one of the connection terminals 170 may be disposed in the fan-out area. The fan-out area is an area other than the area in which the semiconductor wafer 120 is placed. For example, the fan-out type semiconductor package 100A according to an exemplary embodiment may be a fan-out type package. Compared to fan-in packages, fan-out packages offer excellent reliability, implement multiple input/output (I/O) terminals, and facilitate 3D interconnects. In addition, the fan-out package can be used without a separate board compared to a ball grid array (BGA) package, a land grid array (LGA) package, or the like. Installed on the electronic device. Therefore, the fan-out type package can be manufactured to have a small thickness and can be price competitive.

Although not illustrated in the drawings, the metal layer may be further disposed on the inner wall of the through hole 110 of the second connecting member 110 as needed. That is, the side surface of the semiconductor wafer 120 may also be surrounded by a metal layer. The heat generated by the semiconductor wafer 120 can be efficiently radiated in the upward or downward direction of the fan-out type package 100A via the metal layer, and electromagnetic waves can be effectively prevented from passing through the metal layer. In addition, a plurality of semiconductor wafers may be disposed in the through holes 110H of the second connecting member 110, and the number of the through holes 110H of the second connecting member 110 may be plural, and the semiconductor wafers may be disposed in the respective through holes, as needed. .

12 is a schematic perspective view illustrating an example in which a semiconductor wafer, a first capacitor, a second capacitor, and power wirings of a fan-out type semiconductor package are connected to each other.

FIG. 13 is a schematic cross-sectional view illustrating an example in which a semiconductor wafer, a first capacitor, a second capacitor, and power wirings of a fan-out type semiconductor package are connected to each other.

Referring to the drawings, the first capacitor 180 and the second capacitor 190 may be commonly connected to the power plane of the redistribution layer 142a and the redistribution layer 142b in the first connection member 140. Unlike the examples illustrated in the figures, power planes can be provided in large numbers. For example, various types of power electrode pads may be present in the electrode pads 122 of the semiconductor wafer 120, and there may be various types of power planes connected to the power electrode pads via power via holes. All of the first capacitor 180 and the second capacitor 190 can be connected to any common power plane 142aP1 of the power plane, such as a common power plane of a central processing unit (CPU).

As a non-limiting example, any power connection pads of semiconductor wafer 120 may be connected to power plane 142aP1 described above via power via hole 143aP, and first capacitor 180 may be connected to power line 142aP2 via another power via hole (which Connected to the power plane 142aP1) described above to ultimately connect to the power plane 142aP1 described above. The power plane 142aP1 and the power line 142aP2 may constitute a certain power wiring 142aP of the corresponding layer. The second capacitor 190 may be directly connected to any one of the power wirings 142bP of another layer, and the different layers of the power wiring 142aP and the power wiring 142bP may be connected to each other by the power via hole 143bP to constitute any certain power wiring P.

14A, 14B, 14C, and 14D are schematic perspective views illustrating an example in which a semiconductor wafer, a first capacitor, a second capacitor, and power wiring of a fan-out type semiconductor package are connected to each other in each layer.

Referring to the drawings, the first capacitor 180 can be connected to any of the power wirings 142aP of the corresponding layer via the power via holes 143aP to ultimately electrically connect to certain power connection pads of the semiconductor wafer 120. Additionally, the second capacitor 190 can be directly connected to any of the power wirings 142bP of another layer to ultimately electrically connect to certain power connection pads of the semiconductor wafer 120 (which are electrically coupled to the first capacitor 180). In the drawings, FIGS. 14A to 14C are top perspective views, and FIG. 14D is a bottom perspective view.

15A and 15B are schematic perspective views illustrating an example of a first capacitor.

Referring to the drawings, the first capacitor 180 may be a general embedded type multilayer ceramic capacitor having a length greater than a width. In more detail, the first capacitor 180 may include a body 181, a first external electrode 182a, and a second external electrode 182b. The body 181 may include: a dielectric layer 183; and a first inner electrode 184a and a second inner electrode 184b disposed alternately with a dielectric layer 183 disposed therebetween, the body 181 having a thickness smaller than a width and a length thereof, and a width thereof Can be less than its length. The first outer electrode 182a and the second outer electrode 182b may surround both ends of the body 181 in the longitudinal direction L of the body 181, and may be respectively connected to the first inner electrode 184a and the first alternately outwardly guided to both ends of the body 181 Two internal electrodes 184b. In this case, referring to the drawing, the first external electrode 182a or the second external electrode 182b may be connected to the power wiring 142aP and the power wiring 142bP via the power via hole 143aP in the first connection member 140. The embedded multilayer ceramic capacitor can be complemented by a sufficient amount of capacitance and is competitively priced. In the drawings, FIG. 15A is a perspective view illustrating an appearance of a first capacitor according to an example, and FIG. 15B is an exploded perspective view illustrating an inside of a first capacitor according to an example.

Each of the dielectric layers 183 may comprise a ceramic powder having a high dielectric constant. In this case, the ceramic powder may be, for example, barium titanate (BT)-based powder, barium strontium titanate (BST)-based powder or the like, but is not limited thereto, and may also be Another well known ceramic powder. Each of the first inner electrode 184a and the second inner electrode 184b may be formed by printing a paste having a certain thickness and containing a conductive metal on each of the dielectric layers 183, and may be disposed by A dielectric layer 183 between the inner electrode 184a and the second inner electrode 184b is electrically insulated from each other. The conductive metal may be nickel (Ni), copper (Cu), palladium (Pd) or an alloy thereof, but is not limited thereto. Each of the first outer electrode 182a and the second outer electrode 182b may include an electrode layer and a resin layer. The electrode layer may comprise a conductive material such as gold (Au), silver (Ag), copper (Cu), platinum (Pt), aluminum (Al), nickel (Ni) or the like. The resin layer may contain a conductive resin such as a metal powder and a base resin. The metal powder may include copper (Cu), silver (Ag), or the like, but is not limited thereto. The base resin may be a thermosetting resin such as an epoxy resin, but is not limited thereto.

16A and 16B are schematic perspective views illustrating another example of the first capacitor.

Referring to the drawings, the first capacitor 180 may be an embedded type multilayer ceramic capacitor having a width greater than a length. In more detail, the first capacitor 180 may include a body 181, a first external electrode 182a, and a second external electrode 182b. The body 181 may include: a dielectric layer 183; and a first inner electrode 184a and a second inner electrode 184b disposed alternately with a dielectric layer 183 disposed therebetween, the body 181 having a thickness smaller than a width and a length thereof, and a width thereof Can be greater than its length. The first outer electrode 182a and the second outer electrode 182b may surround both ends of the body 181 in the longitudinal direction L of the body 181, and may be respectively connected to the first inner electrode 184a and the first alternately outwardly guided to both ends of the body 181 Two internal electrodes 184b. In this case, referring to the drawing, the first external electrode 182a or the second external electrode 182b may be connected to the power wiring 142aP and the power wiring 142bP via the power via hole 143aP in the first connection member 140. The embedded multilayer ceramic capacitor can be complemented by a sufficient amount of capacitance and can have a low equivalent series impedance. The detailed materials of each of the components or the like are the same as those described above, and thus are omitted. In the drawings, FIG. 16A is a perspective view illustrating an appearance of a first capacitor according to another example, and FIG. 15B is an exploded perspective view illustrating an inside of a first capacitor according to another example.

17A and 17B are schematic perspective views and cross-sectional views illustrating an example of a second capacitor.

Referring to the drawings, the second capacitor 190 can be a surface mount technology capacitor, and it can thus have the structure of an electrode formed on the lower surface of the second capacitor 190. In more detail, the second capacitor 190 may include a body 197, a first external electrode 198a, and a second external electrode 198b. The body 197 may include: a dielectric layer 193; a first internal electrode 192a and a second internal electrode 192b disposed alternately, with a dielectric layer 193 disposed therebetween; a first via electrode 196a and a second via electrode 196b, It penetrates the dielectric layer 193, is selectively connected to the first inner electrode 192a and the second inner electrode 192b, and the body 197 has a thickness smaller than its width and length. The first outer electrode 198a and the second outer electrode 198b may be spaced apart from each other on the surface of the body 197 in the width direction W of the body 197, and may be respectively connected to the first via hole that is outwardly guided to the surface of the body 197. Electrode 196a and second via electrode 196b. In this case, referring to the drawing, the first external electrode 198a or the second external electrode 198b may be directly connected to the power wiring P. Alternatively, the first external electrode 198a or the second external electrode 198b may be connected to the power wiring P via soldering or the like. The first via hole electrode 196a and the second via hole electrode 196b may be spaced apart from each other in the length direction L of the body 197. Similarly, the first outer electrode 198a and the second outer electrode 198b may be spaced apart from each other in the length direction L of the body 197. The surface mount technology capacitor can be formed by sequentially laminating components on a wafer such as a germanium (Si) board. Thus, a single process can enable the fabrication of multiple capacitors, thus achieving excellent price competitiveness, achieving tight size and significantly reducing equivalent series inductance. In the drawings, FIG. 17A is a perspective view illustrating an appearance of a second capacitor according to an example, and FIG. 17B is an exploded cross-sectional view illustrating an inside of a second capacitor according to an example.

The first inner electrode 192a and the second inner electrode 192b may be metal layers including metals different from each other. For example, the first inner electrode 192a and the second inner electrode 192b may be copper (Cu), gold (Au), aluminum (Al), chromium (Cr), nickel (Ni), titanium (Ti), tungsten (W). Or an alloy thereof, and may contain metals different from each other. This is to selectively connect the first inner electrode 192a and the second inner electrode 192b to the first via hole electrode 196a and the second via hole electrode 196b, respectively, using a selective etching or the like in a manufacturing process. Only when the first inner electrode 192a and the second inner electrode 192b may be formed in a different form from that illustrated in the drawings and may be selectively connected to the first via hole electrode 196a and the second via hole electrode 196b, respectively. The first inner electrode 192a and the second inner electrode 192b may comprise the same material.

The first via electrode 196a and the second via electrode 196b are selectively connectable to the first inner electrode 192a and the second inner electrode 192b, respectively, to selectively selectively the first inner electrode 192a and the second inner electrode, respectively 192b is connected to the first outer electrode 198a and the second outer electrode 198b. The first via hole electrode 196a may be connected to the first inner electrode 192a and may be insulated from the second inner electrode 192b. The insulating method may use the first insulating layer 195a as illustrated in the drawing, but is not limited thereto, and a method of arranging the second internal electrode 192b to avoid connection to the first via hole electrode 196a may be used. The second via hole electrode 196b may be connected to the second inner electrode 192b and may be insulated from the first inner electrode 192a. The insulating method may use the second insulating layer 195b as illustrated in the drawing, but is not limited thereto, and a method of arranging the first internal electrode 192a to avoid connection to the second via hole electrode 196b may be used. Each of the first via electrode 196a and the second via electrode 196b may comprise a common conductive material. A plurality of first via electrodes 196a and a second via electrode 196b may be provided. This allows for control of various features.

Each of the dielectric layers 193 may comprise a ceramic powder having a high dielectric constant. In this case, the ceramic powder may be, for example, barium titanate (BT)-based powder, barium strontium titanate (BST)-based powder or the like, but is not limited thereto, and may also be Another well known ceramic powder. The body 197 may further include an insulating layer 194 formed on one surface of the body 197 to form a first external electrode 198a and a second external electrode 198b. Additionally, the body 197 can further include a plate 191 formed on the other surface of the body 197 to support the remainder of the assembly of the body 197 other than the insulating layer 194. The insulating layer 194 can comprise a common insulating material. The material of the plate 191 is not particularly limited, and may be, for example, a bismuth (Si) wafer.

Each of the first outer electrode 198a and the second outer electrode 198b may include an electrode layer and a resin layer. The electrode layer may comprise a conductive material such as gold (Au), silver (Ag), copper (Cu), platinum (Pt), aluminum (Al), nickel (Ni) or the like. The resin layer may contain a conductive resin such as a metal powder and a base resin. The metal powder may include copper (Cu), silver (Ag), or the like, but is not limited thereto. The base resin may be a thermosetting resin such as an epoxy resin, but is not limited thereto.

18A and 18B are schematic perspective views and cross-sectional views illustrating another example of the second capacitor.

Referring to the drawings, the second capacitor 190 can be a surface mount technology capacitor, and it can thus have the structure of an electrode formed on the lower surface of the second capacitor 190. In more detail, the second capacitor 190 may include a body 197, a first external electrode 198a, and a second external electrode 198b. The body 197 may include: a dielectric layer 193; first and second internal electrodes 192a and 192b alternately disposed with a dielectric layer 193 disposed therebetween; a first via electrode 196a and a second via electrode 196b The penetrating dielectric layer 193 is selectively connected to the first inner electrode 192a and the second inner electrode 192b, and the body 197 may have a thickness smaller than its width and length. The first outer electrode 198a and the second outer electrode 198b may be spaced apart from each other on the surface of the body 197 in the width direction W of the body 197, and may be respectively connected to the first via hole electrode 196a that is guided outward to the surface, and The second via hole electrode 196b. In this case, referring to the drawing, the first external electrode 198a or the second external electrode 198b may be directly connected to the power wiring P. Alternatively, the first external electrode 198a or the second external electrode 198b may be connected to the power wiring P via soldering or the like. The first via hole electrode 196a and the second via hole electrode 196b may be spaced apart from each other in the width direction W of the body 197. Similarly, the first outer electrode 198a and the second outer electrode 198b may be spaced apart from each other in the width direction W of the body 197. For example, the placement of the first via hole electrode 196a and the second via hole electrode 196b and the first external electrode 198a and the second external electrode 198b may be changed. The detailed materials of each of the components or the like are the same as those described above, and thus are omitted. In the drawings, FIG. 18A is a perspective view illustrating an appearance of a second capacitor according to another example, and FIG. 18B is a cross-sectional view illustrating an inside of a second capacitor according to another example.

19 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

Figure 20 is a schematic plan view taken along line II-II' of the fan-out type semiconductor package of Figure 19.

21 is a schematic plan view illustrating the fan-out type semiconductor package of FIG. 20 when viewed in the direction B.

Referring to the drawings, the fan-out type semiconductor package 100B may include a plurality of first capacitors 180. All of the plurality of first capacitors 180 together with the second capacitor 190 can be commonly connected to the power wiring. In this case, the fan-out type semiconductor package 100B can further benefit to ensure capacitance, thereby resulting in more effective impedance improvement. All of the plurality of first capacitors 180 may be disposed to surround the semiconductor wafer 120 on one surface of the first connection member 140. A plurality of first capacitors 180 may be disposed in a plurality of grooves formed in the through holes 110H. In some cases, at least two first capacitors 180 may also be disposed in a single recess. Descriptions of configurations other than the above configurations or the like overlap with those described above, and thus are omitted.

Fig. 22 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package.

23 is a schematic plan view taken along line III-III' of the fan-out type semiconductor package of FIG. 22.

FIG. 24 is a schematic plan view illustrating the fan-out type semiconductor package of FIG. 22 when viewed in the direction C.

Referring to the drawings, the fan-out type semiconductor package 100C may include a plurality of first capacitors 180 and a plurality of second capacitors 190. All of the plurality of first capacitors 180 and the plurality of second capacitors 190 may be commonly connected to the power wiring. In this case, the fan-out type semiconductor package 100C can be particularly beneficial for ensuring capacitance, and can further reduce the total equivalent series impedance, thereby resulting in more effective impedance improvement. All of the plurality of second capacitors 190 may be disposed to surround the connection terminals 170 on the other surface of the first connection member 140 opposite to one surface of the first connection member 140 on which the semiconductor wafer 120 is disposed. For example, a plurality of second capacitors 190 may be disposed on a surface of the passivation layer 150 and may be surrounded by the connection terminals 170. Descriptions of configurations other than the above configurations or the like overlap with those described above, and thus are omitted.

25 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

Referring to the drawings, in the fan-out type semiconductor package 100D according to another exemplary embodiment of the present invention, the second connecting member 110 may include: a first insulating layer 111a contacting the first connecting member 140; a cloth layer 112a that contacts the first connecting member 140 and is embedded in the first insulating layer 111a; and a second redistribution layer 112b that is disposed on a surface of the first insulating layer 111a in which the first redistribution layer 112a is embedded On the other surface of the first insulating layer 111a; a second insulating layer 111b disposed on the first insulating layer 111a and covering the second redistribution layer 112b; and a third redistribution layer 112c disposed in the second On the insulating layer 111b. The first redistribution layer 112a, the second redistribution layer 112b, and the third redistribution layer 112c may be electrically connected to the connection pads 122. Meanwhile, although not illustrated in the drawings, the first redistribution layer 112a, the second redistribution layer 112b, and the second redistribution layer 112b and the third redistribution layer 112c may penetrate the first insulation layer 111a and the second insulation, respectively. The first via holes of the layer 111b and the second via holes are electrically connected to each other.

Since the first redistribution layer 112a is embedded, the insulation distance of the insulating layer 141 of the first connection member 140 can be substantially constant, as described above. Since the second connecting member 110 can include a large number of the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c, the first connection member 140 can be further simplified. Therefore, the reduction in the yield depending on the defects occurring in the process of forming the first connecting member 140 can be improved. The first redistribution layer 112a may be recessed in the first insulating layer 111a such that there is a stepped portion between the lower surface of the first insulating layer 111a and the lower surface of the first redistribution layer 112a. Thus, when the encapsulant 130 is formed, the phenomenon that the material of the encapsulant 130 is oozing to contaminate the first redistribution layer 112a can be prevented.

The lower surface of the first redistribution layer 112a of the second connection member 110 may be disposed on a level higher than the lower surface of the connection pad 122 of the semiconductor wafer 120. In addition, the distance between the redistribution layer 142 of the first connection member 140 and the redistribution layer 112a of the second connection member 110 may be greater than between the redistribution layer 142 of the first connection member 140 and the connection pad 122 of the semiconductor wafer 120. distance. The reason for this is that the first redistribution layer 112a can be recessed in the insulating layer 111. The second redistribution layer 112b of the second connection member 110 can be disposed on a level between the active surface and the inactive surface of the semiconductor wafer 120. The thickness of the second connection member 110 corresponding to the thickness of the semiconductor wafer 120 may be formed. Accordingly, the second redistribution layer 112b formed in the second connection member 110 may be disposed on a level between the active surface and the inactive surface of the semiconductor wafer 120.

The thickness of the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c of the second connection member 110 may be greater than the thickness of the redistribution layer 142 of the first connection member 140. Since the thickness of the second connection member 110 may be equal to or greater than the thickness of the semiconductor wafer 120, the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c may form a large size depending on the scale of the second connection member 110. On the other hand, the redistribution layer 142 of the first connecting member 140 may be formed to be relatively small in size due to being thin.

Descriptions of configurations other than the above configurations or the like overlap with those described above, and thus are omitted. Although not illustrated in the drawings, the characteristics of the fan-out type semiconductor package 100B and the fan-out type semiconductor package 100C described above can also be applied to the fan-out type semiconductor package 100D.

Fig. 26 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package.

Referring to the drawings, in the fan-out type semiconductor package 100E according to another exemplary embodiment of the present invention, the second connection member 110 may include: a first insulating layer 111a; a first redistribution layer 112a and a second redistribution a layer 112b disposed on both surfaces of the first insulating layer 111a; a second insulating layer 111b disposed on the first insulating layer 111a and covering the first redistribution layer 112a; and a third redistribution layer 112c disposed thereon On the second insulating layer 111b, a third insulating layer 111c disposed on the first insulating layer 111a and covering the second redistribution layer 112b, and a fourth redistribution layer 112d disposed on the third insulating layer 111c. The first redistribution layer 112a, the second redistribution layer 112b, the third redistribution layer 112c, and the fourth redistribution layer 112d may be electrically connected to the connection pads 122. Since the second connecting member 110 can include a larger number of redistribution layers 112a, redistribution layers 112b, redistribution layers 112c, and redistribution layers 112d, the first connection members 140 can be further simplified. Therefore, the reduction in the yield depending on the defects occurring in the process of forming the first connecting member 140 can be improved. Meanwhile, although not illustrated in the drawings, the first redistribution layer 112a, the second redistribution layer 112b, the third redistribution layer 112c, and the fourth redistribution layer 112d may penetrate the first insulating layer 111a and the second insulating layer. The first via hole to the third via hole of the 111b and the third insulating layer 111c are electrically connected to each other.

The thickness of the first insulating layer 111a may be greater than the thickness of the second insulating layer 111b and the third insulating layer 111c. The first insulating layer 111a may be substantially thicker to maintain hardness, and the second insulating layer 111b and the third insulating layer 111c may be introduced to form a larger number of redistribution layers 112c and a redistribution layer 112d. The first insulating layer 111a may include an insulating material different from that of the second insulating layer 111b and the third insulating layer 111c. For example, the first insulating layer 111a may be, for example, a prepreg including a core material, an inorganic filler, and an insulating resin, and the second insulating layer 111b and the third insulating layer 111c may be an Ajinomoto accumulation film or include An inorganic filler and a photosensitive insulating film of an insulating resin. However, the materials of the first insulating layer 111a, the second insulating layer 111b, and the third insulating layer 111c are not limited thereto.

The lower surface of the third redistribution layer 112c of the second connection member 110 may be disposed on a lower level than the lower surface of the connection pad 122 of the semiconductor wafer 120. In addition, the distance between the redistribution layer 142 of the first connecting member 140 and the third redistribution layer 112c of the second connecting member 110 may be smaller than the redistribution layer 142 of the first connecting member 140 and the connection pad 122 of the semiconductor wafer 120. The distance between them. The reason for this is that the third redistribution layer 112c may be disposed on the second insulating layer 111b in a convex form, thereby causing contact with the first connecting member 140. The first redistribution layer 112a and the second redistribution layer 112b of the second connection member 110 may be disposed on a level between the active surface and the inactive surface of the semiconductor wafer 120. The thickness of the second connection member 110 corresponding to the thickness of the semiconductor wafer 120 may be formed. Therefore, the first redistribution layer 112a and the second redistribution layer 112b formed in the second connection member 110 may be disposed on a level between the active surface and the inactive surface of the semiconductor wafer 120.

The thickness of the redistribution layer 112a, the redistribution layer 112b, the redistribution layer 112c, and the redistribution layer 112d of the second connection member 110 may be greater than the thickness of the redistribution layer 142 of the first connection member 140. Since the thickness of the second connection member 110 may be equal to or larger than the thickness of the semiconductor wafer 120, the redistribution layer 112a, the redistribution layer 112b, the redistribution layer 112c, and the redistribution layer 112d may be formed to have a large size. On the other hand, the redistribution layer 142 of the first connecting member 140 may be formed to have a relatively small size due to being thin.

Descriptions of configurations other than the above configurations or the like and manufacturing methods overlap with those described above, and thus are omitted. Although not illustrated in the drawings, the characteristics of the fan-out type semiconductor packages 100B and 100C described above can also be applied to the fan-out type semiconductor package 100E.

Fig. 27 is a schematic cross-sectional view showing an example of a case where a fan-out type semiconductor package is mounted on a main board.

Referring to the drawings, the electronic device may include: a main board 400; a fan-out type semiconductor package 100A disposed on the main board 400; and a memory chip package 200 disposed on the fan-out type semiconductor package 100A. A separate passive component 300 or the like can be further disposed on the motherboard 400. The motherboard 400 can be a printed circuit board (PCB) having circuitry 401, and the common printed circuit board can be a rigid or flexible substrate. The fan-out type semiconductor package 100A is the same as the fan-out type semiconductor package described above, and the fan-out type semiconductor package 100B, the fan-out type semiconductor package 100C, and the fan-out type semiconductor package 100D according to another example described above The fan-out type semiconductor package 100E can also be applied as a fan-out type semiconductor package. The memory chip package 200 may include: a wiring substrate 210; at least one memory wafer 220 disposed on the wiring substrate 210; and an encapsulation body 230 encapsulating the memory wafer 220. In this case, at least one memory chip 220 may be connected to the wiring substrate 210 by wire bonding. The passive component 300 can be a capacitor, an inductor, or the like, but is not limited thereto.

The fan-out type semiconductor package 100A and the main board 400 may be electrically connected to each other by the connection terminal 170. Thus, another passive component 300 mounted on the main board 400 or the like can be electrically connected to the fan-out type semiconductor package 100A via the circuit 401 formed in the main board 400. The fan-out type semiconductor package 100A and the memory chip package 200 may also be electrically connected to each other by the connection terminals 240. Thus, the memory chip package 200 can also be electrically connected to the motherboard 400 or other passive components 300. The first capacitor 180 and the second capacitor 190 that are commonly connected to the power wiring of the fan-out type semiconductor package 100A may be electrically connected to at least one memory wafer 220 via a certain power wiring in the wiring substrate 210 of the memory chip package 200. In addition, the first capacitor 180 and the second capacitor 190 may be electrically connected to a certain power wiring of the main board 400. When the passive component 300 is a capacitor or the like, the first capacitor 180 and the second capacitor 190 may be electrically connected to a capacitor or the like via a certain power wiring of the main board 400. Thus, the level of impedance of a certain power supply can be significantly reduced.

FIG. 28 is a view illustrating a change in impedance depending on a combination of a first capacitor and a second capacitor.

In the drawing, line 1 illustrates the case where the second capacitor 190 having a capacitance of 100 nF is connected to the power wiring without the first capacitor 180; the line 2 illustrates the first capacitor 180 having a capacitance of 100 nF and the second having a capacitance of 100 nF The case where the capacitor 190 is commonly connected to the power wiring; the line 3 illustrates the case where the first capacitor 180 having a capacitance of 220 nF and the second capacitor 190 having a capacitance of 100 nF are commonly connected to the power wiring; and the line 4 illustrates the first having a capacitance of 470 nF A capacitor 180 and a second capacitor 190 having a capacitance of 100 nF are commonly connected to the case of power wiring. The method of increasing the capacitance of the first capacitor 180 may be a method of increasing the capacitance of the first capacitor 180 itself or a method of increasing the number of the first capacitors 180. Referring to the drawing, when the total capacitance of the first capacitor 180 is increased by increasing the capacitance of the first capacitor 180, the impedance can be reduced. In this case, since the second capacitor 190 remains fixed, it is understood that the impedance can be improved in a limited space without reducing the area where the connection terminal 170 can be disposed.

As described above, according to an exemplary embodiment of the present invention, it is possible to provide a fan-out type semiconductor package which can improve the level of the input impedance in the low frequency domain and the high frequency domain regardless of the limited space of the capacitor.

While the embodiment has been shown and described, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the invention as defined by the appended claims.

100‧‧‧Semiconductor package
100A, 100B, 100C, 100D, 100E‧‧‧ Fan-out semiconductor packages
110‧‧‧Second connection parts
110H‧‧‧through hole
111‧‧‧Insulation
111a‧‧‧First insulation
111b‧‧‧Second insulation
111c‧‧‧ third insulation
112a‧‧‧First redistribution
112b‧‧‧Second layer
112c‧‧‧ third layer
112d‧‧‧4th layer
113‧‧‧Mesopores
120‧‧‧Semiconductor wafer
121‧‧‧Ontology
122‧‧‧ pads
123‧‧‧ Passivation layer
130‧‧‧Encapsulation
131‧‧‧ openings
140‧‧‧First connecting part
141, 141a, 141b‧‧‧ insulation
142, 142a, 142b‧‧‧ redistribution
142aP, 142bP‧‧‧ power wiring
142aP1‧‧‧Power plane
142aP2‧‧‧Power Line
143a, 143b‧‧ ‧ mesopores
143aP, 143bP‧‧‧Power mesopores
150‧‧‧ Passivation layer
151‧‧‧ openings
160‧‧‧ under bump metal layer
170‧‧‧Connecting terminal
180‧‧‧First capacitor
181‧‧‧ Ontology
182a‧‧‧First external electrode
182b‧‧‧Second external electrode
183‧‧‧ dielectric layer
184a‧‧‧First internal electrode
184b‧‧‧Second internal electrode
190‧‧‧second capacitor
191‧‧‧ board
192a‧‧‧First internal electrode
192b‧‧‧Second internal electrode
193‧‧‧ dielectric layer
194‧‧‧Insulation
195a‧‧‧First insulation
195b‧‧‧Second insulation
196a‧‧‧First via electrode
196b‧‧‧Second interlayer hole electrode
197‧‧‧ Ontology
198a‧‧‧First external electrode
198b‧‧‧Second external electrode
200‧‧‧ memory chip package
210‧‧‧ wiring substrate
220‧‧‧ memory chip
230‧‧‧Encapsulation
240‧‧‧Connecting terminal
300‧‧‧ Passive components
400‧‧‧ motherboard
401‧‧‧ circuit
1000‧‧‧Electronic devices
1010‧‧‧ Motherboard
1020‧‧‧ wafer related components
1030‧‧‧Network related components
1040‧‧‧Other components
1050‧‧‧ camera module
1060‧‧‧Antenna
1070‧‧‧Display device
1080‧‧‧Battery
1090‧‧‧ signal line
1100‧‧‧Smart mobile phone
1101‧‧‧ Ontology
1110‧‧‧ motherboard
1120‧‧‧Electronic components
2100‧‧‧Fan-out semiconductor package
2120‧‧‧Semiconductor wafer
2121‧‧‧ Ontology
2122‧‧‧Connecting mat
2130‧‧‧Encapsulation
2140‧‧‧Connecting parts
2141‧‧‧Insulation
2142‧‧‧Re-layer
2143‧‧‧Interlayer hole
2150‧‧‧ Passivation layer
2160‧‧‧ under bump metal layer
2170‧‧‧ solder balls
2200‧‧‧Fan-in semiconductor package
2220‧‧‧Semiconductor wafer
2221‧‧‧ Ontology
2222‧‧‧Connecting mat
2223‧‧‧ Passivation layer
2240‧‧‧Connecting parts
2241‧‧‧Insulation
2242‧‧‧Wiring pattern
2243‧‧‧Interlayer hole
2243H‧‧‧Interlayer hole
2250‧‧‧ Passivation layer
2251‧‧‧ openings
2260‧‧‧ under bump metal layer
2270‧‧‧ solder balls
2280‧‧‧ bottom filled resin
2290‧‧‧Molded materials
2301‧‧‧Insert substrate
2500‧‧‧ motherboard
A, B, C‧‧‧ directions
I-I', II-II', III-III'‧‧‧ line
P‧‧‧Power Wiring
T‧‧‧ thickness direction
L‧‧‧ Length direction
W‧‧‧Width direction
T1, t2, t3‧‧‧ thickness

The above as well as other aspects, features, and advantages of the present invention will be more clearly understood from the following detailed description. In the drawings: FIG. 1 is a schematic block diagram illustrating an example of an electronic device system. FIG. 2 is a schematic perspective view illustrating an example of an electronic device. 3A and 3B are schematic cross-sectional views illustrating a state of a fan-in type semiconductor package before and after being packaged. 4 is a schematic cross-sectional view illustrating a packaging process of a fan-in type semiconductor package. 5 is a schematic cross-sectional view illustrating a state in which a fan-in type semiconductor package is mounted on a plug-in substrate and finally mounted on a main board of an electronic device. 6 is a schematic cross-sectional view illustrating a state in which a fan-in type semiconductor package is embedded in a plug-in substrate and finally mounted on a main board of an electronic device. FIG. 7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package. FIG. 8 is a schematic cross-sectional view illustrating a state in which a fan-out type semiconductor package is mounted on a main board of an electronic device. FIG. 9 is a schematic cross-sectional view illustrating an example of a fan-out type semiconductor package. FIG. 10 is a schematic plan view taken along line I-I' of the fan-out type semiconductor package of FIG. 9. FIG. 11 is a schematic plan view illustrating the fan-out type semiconductor package of FIG. 9 when viewed in the direction A. 12 is a schematic perspective view illustrating an example in which a semiconductor wafer, a first capacitor, a second capacitor, and power wirings of a fan-out type semiconductor package are connected to each other. FIG. 13 is a schematic cross-sectional view illustrating an example in which a semiconductor wafer, a first capacitor, a second capacitor, and power wirings of a fan-out type semiconductor package are connected to each other. 14A, 14B, 14C, and 14D are schematic perspective views illustrating an example in which a semiconductor wafer, a first capacitor, a second capacitor, and power wiring of a fan-out type semiconductor package are connected to each other in each layer. 15A and 15B are schematic perspective views illustrating an example of a first capacitor. 16A and 16B are schematic perspective views illustrating another example of the first capacitor. 17A and 17B are schematic perspective views and cross-sectional views illustrating an example of a second capacitor. 18A and 18B are schematic perspective views and cross-sectional views illustrating another example of the second capacitor. 19 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package. Figure 20 is a schematic plan view taken along line II-II' of the fan-out type semiconductor package of Figure 19. 21 is a schematic plan view illustrating the fan-out type semiconductor package of FIG. 20 when viewed in the direction B. Fig. 22 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package. 23 is a schematic plan view taken along line III-III' of the fan-out type semiconductor package of FIG. 22. FIG. 24 is a schematic plan view illustrating the fan-out type semiconductor package of FIG. 22 when viewed in the direction C. 25 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package. Fig. 26 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package. Fig. 27 is a schematic cross-sectional view showing an example of a case where a fan-out type semiconductor package is mounted on a main board. FIG. 28 is a view illustrating a change in impedance depending on a combination of a first capacitor and a second capacitor.

100A‧‧‧Fan-out semiconductor package

110‧‧‧Second connection parts

110H‧‧‧through hole

111‧‧‧Insulation

112a‧‧‧First redistribution

112b‧‧‧Second layer

120‧‧‧Semiconductor wafer

121‧‧‧Ontology

122‧‧‧ pads

123‧‧‧ Passivation layer

130‧‧‧Encapsulation

131‧‧‧ openings

140‧‧‧First connecting part

141a, 141b‧‧‧ insulation

142a, 142b‧‧‧ redistribution

143a, 143b‧‧ ‧ mesopores

150‧‧‧ Passivation layer

151‧‧‧ openings

160‧‧‧ under bump metal layer

170‧‧‧Connecting terminal

180‧‧‧First capacitor

190‧‧‧second capacitor

A‧‧‧ direction

I-I'‧‧‧ line

P‧‧‧Power Wiring

T‧‧‧ thickness direction

L‧‧‧ Length direction

T1, t2, t3‧‧‧ thickness

Claims (21)

A fan-out type semiconductor package, comprising: a semiconductor wafer having an active surface and an inactive surface, wherein the active surface is provided with a connection pad and the inactive surface is opposite to the active surface; a first capacitor, The semiconductor wafer is disposed adjacently; an encapsulant at least partially encapsulating the first connecting member and the inactive surface of the semiconductor wafer; a first connecting member disposed on the encapsulant, The first capacitor and the active surface of the semiconductor wafer; and a second capacitor disposed on another surface of the first connecting member, the other surface of the first connecting member The first connecting member is disposed opposite to a surface of the semiconductor wafer, wherein the first connecting member comprises a redistribution layer, and the redistribution layer is electrically connected to the connection pad of the semiconductor wafer a first capacitor and the second capacitor, and the first capacitor and the second capacitor are electrically connected to the half via a common power wiring of the redistribution layer The connection pads of the conductor wafer. The fan-out type semiconductor package of claim 1, wherein C ₁ is equal to C ₂ , wherein C ₁ and C ₂ are capacitances of the first capacitor and the second capacitor, respectively. The fan-out type semiconductor package of claim 1, wherein t _{1 is} greater than t ₂ , wherein t ₁ and t ₂ are thicknesses of the first capacitor and the second capacitor, respectively. The fan-out type semiconductor package of claim 1, wherein L ₁ is equal to L ₂ , wherein L ₁ and L ₂ are equivalent series inductances of the first capacitor and the second capacitor, respectively (equivalent series) Insulators; ESL). The fan-out type semiconductor package of claim 1, wherein R ₁ is equal to R ₂ , wherein R ₁ and R ₂ are equivalent series resistances of the first capacitor and the second capacitor, respectively (equivalent series) Resistances; ESR). The fan-out type semiconductor package of claim 1, wherein the first capacitor and the second capacitor are connected in parallel with each other. The fan-out type semiconductor package of claim 1, further comprising a passivation layer disposed on the other surface of the first connecting member, the first connecting member The other surface is opposite to a surface of the first connecting member on which the semiconductor wafer is disposed, and the passivation layer has an opening exposing at least a portion of the wiring of the redistribution layer, wherein the second capacitor Placed on the surface of the passivation layer. The fan-out type semiconductor package of claim 7, further comprising a connection terminal disposed in the opening of the passivation layer, wherein the connection terminal is disposed to surround the second capacitor. The fan-out type semiconductor package of claim 1, further comprising a second connection member having a through hole, wherein the semiconductor wafer and the first capacitor are disposed in the through hole, and A portion of the encapsulant encapsulates at least a portion of the second attachment component. The fan-out type semiconductor package of claim 9, wherein the second connecting member comprises: a first insulating layer; a first redistribution layer contacting the first connecting member and embedded in the first And a second redistribution layer disposed on the other surface of the first insulating layer, the first surface of the first insulating layer and the first insulating layer being embedded with the first One surface of the redistribution layer is opposed, and the first redistribution layer and the second redistribution layer are electrically connected to the connection pad. The fan-out type semiconductor package of claim 10, wherein the second connecting member further comprises: a second insulating layer disposed on the first insulating layer and covering the second redistribution layer And a third redistribution layer disposed on the second insulating layer, and the third redistribution layer is electrically connected to the connection pad. The fan-out type semiconductor package according to claim 10, wherein a distance between the redistribution layer of the first connecting member and the first redistribution layer is larger than that of the first connecting member The distance between the redistribution layer and the connection pad is described. The fan-out type semiconductor package of claim 10, wherein the first redistribution layer is thicker than the redistribution layer of the first connection member. The fan-out type semiconductor package of claim 10, wherein a lower surface of the first redistribution layer is disposed on a level higher than a lower surface of the connection pad. The fan-out type semiconductor package of claim 11, wherein the second redistribution layer is disposed at a level between the active surface of the semiconductor wafer and the inactive surface of the semiconductor wafer on. The fan-out type semiconductor package of claim 9, wherein the second connecting member comprises: a first insulating layer; a first redistribution layer and a second redistribution layer disposed on the first insulation a second insulating layer disposed on the first insulating layer and covering the first redistribution layer; and a third redistribution layer disposed on the second insulating layer, And the first redistribution layer to the third redistribution layer are electrically connected to the connection pad. The fan-out type semiconductor package of claim 16, wherein the second connecting member further comprises: a third insulating layer disposed on the first insulating layer and covering the second redistribution layer And a fourth redistribution layer disposed on the third insulating layer, and the fourth redistribution layer is electrically connected to the connection pad. The fan-out type semiconductor package of claim 16, wherein the first insulating layer is thicker than the second insulating layer. The fan-out type semiconductor package of claim 16, wherein the third redistribution layer is thicker than the redistribution layer of the first connection member. The fan-out type semiconductor package of claim 16, wherein the first redistribution layer is disposed at a level between the active surface of the semiconductor wafer and the inactive surface of the semiconductor wafer on. The fan-out type semiconductor package of claim 16, wherein a lower surface of the third redistribution layer is disposed on a lower level than a lower surface of the connection pad.