TW201727841A - Electronic package structure and electronic package manufacturing method - Google Patents

Abstract

An electronic package structure includes: a carrier board having a release layer and a metal layer thereon; a first line portion disposed on the metal layer; an electronic component disposed on the first line portion; The coating of the electronic component, in the subsequent process, after removing the metal layer, the release layer and the carrier board, the first line portion may be exposed, so that the first line portion is not required to be exposed by laser Open the hole. The invention further provides a method for manufacturing an electronic package using the electronic package structure.

Description

Electronic package structure and electronic package manufacturing method

The invention relates to a packaging technology, in particular to an electronic packaging structure and a method for manufacturing the electronic package.

With the evolution of semiconductor packaging technology, semiconductor devices have developed different package types, and in order to improve electrical functions and save packaging space, different stereo packaging technologies have been developed, for example, fan-out package stacking. (Fan Out Package on package, referred to as FO PoP), etc., in order to match the increased number of input/outputs on various wafers, and then integrate the integrated circuits of different functions into a single package structure, which can be used as a system package ( SiP) heterogeneous integration features, which can be used to integrate various electronic components, such as memory, central processing unit, graphics processor, image application processor, etc., by stacking design, suitable for various thin and light electronic products. .

Please refer to FIGS. 1A to 1D for a schematic cross-sectional view of a conventional semiconductor package 1 .

As shown in FIG. 1A, a carrier sheet 10 having a release layer 101 is provided, wherein the release layer 101 is required to be released due to poor chemical resistance. A passivation layer 100 is formed on the layer 101 to protect the release layer 101. Next, a first line portion 11 is formed on the passivation layer 100, and a plurality of conductors 12 are formed on the first line portion 11.

As shown in FIG. 1B, a semiconductor element 13 is disposed on the first line portion 11, wherein the semiconductor element 13 has an opposite active surface 13a and an inactive surface 13b, the active surface 13a having a plurality of electrode pads 130, and The semiconductor element 13 is adhered to the first line portion 11 by a bonding layer 131 with its non-active surface 13b.

As shown in FIG. 1C, a cladding layer 14 is formed on the first wiring portion 11 such that the cladding layer 14 covers the semiconductor element 13 and the conductors 12. Then, a second line portion 15 is formed on the cladding layer 14 to electrically connect the second line portion 15 to the semiconductor device 13 to form a plurality of conductive elements 16 such as solder balls on the second line portion 15. .

As shown in FIG. 1D, the carrier 10 and the release layer 101 are removed, and an insulating protective layer 17 is formed on the passivation layer 100, and a plurality of openings 170 are formed in the insulating manner on the insulating protective layer 17 by laser. On the passivation layer 100, a plurality of solder balls (not shown) are formed in the openings 170 for subsequent processing, and the electronic devices are connected (not shown).

However, the conventional semiconductor package 1 is formed by laser forming the openings 170, which is time consuming not only slow (especially when the number of holes is large), but also causes the walls of the openings 170 to be rough. The unevenness causes the subsequent solder balls to be effectively adhered to the openings 170 to cause peeling, resulting in poor electrical connection, poor reliability of the semiconductor package 1, and a decrease in product yield.

Therefore, how to overcome the shortcomings of the prior art is a technical problem that is currently being solved by all walks of life.

In view of the above-mentioned shortcomings of the prior art, the present invention provides an electronic package structure comprising: a carrier plate; a release layer formed on the carrier plate; a metal layer formed on the release layer, such that the release layer is sandwiched Provided between the carrier board and the metal layer; the first line portion formed on the metal layer has opposite first and second sides, and the first line portion is coupled to the second side thereof On the metal layer; the electronic component is disposed on the first side of the first line portion; and the cladding layer is formed on the first side of the first line portion to encapsulate the electronic component.

The invention provides a method for manufacturing an electronic package, comprising: providing a carrier board on which a release layer and a metal layer are sequentially formed; forming a first line portion on the metal layer, wherein the first line portion Having an opposite first side and a second side, and the first line portion is bonded to the metal layer with the second side thereof; the electronic component is disposed on the first side of the first line portion; forming a cladding layer thereon The first side of the first line portion covers the electronic component; and the carrier board, the release layer and the metal layer are removed, and the second side of the first line portion is exposed.

In the above method, the carrier plate and the release layer are removed by laser, and the metal layer is removed by an etching solution. For example, the etching solution is a diluted hydrofluoric acid solution or H3PO4.

In the above method for manufacturing an electronic package structure and an electronic package, the method further includes forming an insulating layer on the metal layer, wherein the insulating layer is bonded to the first The second side of the line portion is such that the insulating layer is interposed between the metal layer and the first line portion. In addition, when the carrier board, the release layer and the metal layer are removed, the insulation layer is removed. For example, the carrier plate and the release layer are removed by laser, and the metal layer and the insulating layer are removed by an etching solution. For example, the etching solution is a diluted hydrofluoric acid solution or H3PO4.

In the above method for manufacturing an electronic package structure and an electronic package, the electronic component has opposite active and non-active surfaces, the active surface has a plurality of electrode pads, and the electronic component is coupled to the first line portion by an inactive surface thereof On the first side.

In the above method for manufacturing an electronic package structure and an electronic package, the electronic component has opposite active and non-active surfaces, the active surface has a plurality of electrode pads, and the electronic component is coupled to the first line portion by an active surface thereof On the first side, the first line portion is electrically connected to the electronic component.

In the above method for manufacturing the electronic package structure and the electronic package, the method further includes forming at least one electrical conductor on the first side of the first line portion when the first line portion is formed, so that the cladding layer covers the Electrical conductor.

In the above method for manufacturing the electronic package structure and the electronic package, the method further comprises: before removing the carrier board, the release layer and the metal layer, forming a second line portion on the cladding layer, and the second line portion is electrically Connect the electronic component.

In the above-described method of manufacturing the electronic package structure and the electronic package, the material forming the metal layer is titanium or aluminum.

As can be seen from the above, the electronic package structure and the electronic package of the present invention are mainly formed by forming a metal layer on the release layer for protecting the release layer, in the subsequent process, after removing the metal layer. , you can reveal the first A line portion does not need to form an opening for exposing the first line portion by laser. Therefore, compared with the prior art, the method of the invention not only improves the processing speed, but also avoids the occurrence of conductive elements due to the roughness of the opening. The phenomenon of shedding. Therefore, the method of the present invention can improve the electrical connection quality, product reliability and yield.

1‧‧‧Semiconductor package

10,20‧‧‧ carrying board

100‧‧‧ Passivation layer

101,201‧‧‧ release layer

11,21,31‧‧‧First Line Department

12,22‧‧‧Electrical conductor

13‧‧‧Semiconductor components

13a, 23a, 33a‧‧‧ action surface

13b, 23b, 33b‧‧‧ non-active surface

130,230,330‧‧‧electrode pads

131,231‧‧‧bonding layer

14,24‧‧ ‧ coating

15,25,35‧‧‧second line department

16,26,28‧‧‧Electrical components

17‧‧‧Insulating protective layer

170‧‧‧ openings

2,3,4‧‧‧Electronic package structure

2', 3', 4'‧‧‧ electronic packages

202,402‧‧‧metal layer

203‧‧‧Insulation

21a, 31a‧‧‧ first side

21b, 31b‧‧‧ second side

210,310‧‧‧First dielectric layer

211,311‧‧‧First line redistribution

22a‧‧‧ end face

23,33‧‧‧Electronic components

250, 250', 350, 350' ‧ ‧ second dielectric layer

251,251’, 351‧‧‧Second line redistribution

260‧‧‧ Metal layer under the bump

331‧‧‧Electrical bumps

5‧‧‧Electronic devices

S‧‧‧ cutting path

1A to 1D are schematic cross-sectional views showing a method of fabricating a conventional semiconductor package; and FIGS. 2A to 2E are cross-sectional views showing a first embodiment of the method for fabricating an electronic package of the present invention; FIGS. 3A to 3E are diagrams A cross-sectional view of a second embodiment of the method of fabricating an electronic package of the present invention; and FIGS. 4A to 4C are cross-sectional views showing a third embodiment of the method of fabricating the electronic package of the present invention.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. Technology disclosed by the invention The content can be covered. In the meantime, the terms "upper", "first", "second" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.

2A to 2E are schematic cross-sectional views showing a first embodiment of the manufacturing method of the electronic package of the present invention.

As shown in FIG. 2A, a carrier 20 is provided, and a release layer 201, a metal layer 202, and an insulating layer 203 are sequentially formed thereon, so that the release layer 201 is sandwiched between the carrier 20 and the metal layer 202. between. Next, a first line portion 21 is formed on the insulating layer 203, wherein the first line portion 21 has a first side 21a and a second side 21b opposite thereto, and the first line portion 21 has a second side 21b thereof The insulating layer 203 is bonded. Thereafter, a plurality of electrical conductors 22 are formed on the first side 21a of the first line portion 21.

In this embodiment, the carrier 20 is a circular plate of a semiconductor material such as glass, and the release layer 201 is formed by coating, and the metal layer 202 is a titanium (Ti) layer and used for The release layer 201 is protected by an oxide layer formed by chemical vapor deposition (CVD).

Furthermore, the first line portion 21 includes at least one first dielectric layer 210 and at least one first line redistribution layer 211 disposed in the first dielectric layer 210. For example, the material forming the first circuit redistribution layer 211 is copper, and the material forming the first dielectric layer 210 is, for example, polybenzoxazole (PBO).

Moreover, the electrical conductors 22 protrude from the first dielectric layer 210 and are electrically connected to the first circuit redistribution layer 211.

Further, the conductor 22 is formed in a spherical shape such as a solder ball, or a columnar shape of a metal material such as a copper post or a solder bump, or a stud formed by a wire bonding machine, but is not limited thereto.

As shown in FIG. 2B, at least one electronic component 23 is disposed on the first side 21a of the first line portion 21, and a cladding layer 24 is formed on the first side 21a of the first line portion 21 to The cladding layer 24 covers the electronic component 23 and the conductors 22.

In this embodiment, the electronic component 23 is an active component, a passive component, or a combination thereof, and the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. Specifically, the electronic component 23 is a semiconductor wafer having an opposite active surface 23a and a non-active surface 23b. The active surface 23a has a plurality of electrode pads 230, and the electronic component 23 is separated by a non-active surface 23b. The bonding layer 231 is adhered to the first side 21a of the first line portion 21.

For example, the bonding layer 231 is formed on the non-active surface 23b of the electronic component 23, and the non-active surface 23b is adhered to the first dielectric layer 210. It should be understood that the bonding layer 231 may be formed on the first dielectric layer 210, and the non-active surface 23b of the electronic component 23 may be adhered to the bonding layer 231.

Furthermore, the cladding layer 24 is an insulating material, such as an epoxy encapsulant, which may be formed on the first dielectric layer 210 by lamination or molding.

Moreover, after the coating layer 24 is subjected to the leveling process, the end surface 22a of the conductor 22 is flush with the active surface 23a of the electronic component 23 and exposed to the cladding layer 24. For example, the leveling process removes part of the material of the cladding layer 24 by grinding (if necessary, removing part of the material of the conductor 22).

As shown in FIG. 2C, a second line portion 25 is formed on the cladding layer 24, and the second line portion 25 is electrically connected to the electronic component 23 and the conductor 22.

In this embodiment, the second line portion 25 includes a plurality of second dielectric layers 250, and a plurality of second line redistribution layers 251 disposed in the second dielectric layer 250, and the second layer of the outermost layer The electrical layer 250' can serve as a solder resist layer to expose a portion of the outermost second line redistribution layer 251' to the solder resist layer. Alternatively, the second line portion 25 may include only a single second dielectric layer 250 and a single second line redistribution layer 251.

Further, the material of the second circuit redistribution layer 251, 251' is made of copper, and the material of the second dielectric layer 250, 250' is made of, for example, poly-p-oxazobenzene (PBO).

Further, a plurality of conductive members 26 such as solder balls are formed on the outermost second line redistribution layer 251'.

Alternatively, an under bump metallurgy (UBM) 260 may be formed on the outermost second line redistribution layer 251' to facilitate bonding of the conductive element 26.

As shown in FIG. 2D, the carrier board 20, the release layer 201, the metal layer 202, and the insulating layer 203 are removed, and the second side 21b of the first line portion 21 and the first line redistribution layer 211 are exposed.

In this embodiment, the carrier plate 20 and the release layer 201 are removed by laser, and the metal layer 202 and the insulating layer 203 are removed by an etching solution diluted with a hydrofluoric acid solution (DHF).

It should be understood that the material of the metal layer 202 is not limited to titanium material, and may be other suitable metal materials, and only needs to be matched with a suitable etching liquid. For example, the material of the metal layer 202 is aluminum (Al) material, so the metal layer 202 is removed by etching with an etching solution of phosphoric acid (H ₃ PO ₄ ), and the insulating layer 203 is removed by DHF.

As shown in Fig. 2E, a singulation process is performed along the cutting path S as shown in Fig. 2D to form an electronic package 2'. Subsequently, the electronic package 2 ′ can form a plurality of conductive elements 28 such as solder balls on the first circuit redistribution layer 211 for subsequent connection with an electronic device such as a package structure or other structure (such as a circuit board or an interposer). 5.

3A to 3E are schematic cross-sectional views showing a second embodiment of the method of manufacturing the electronic package of the present invention. The difference between this embodiment and the first embodiment lies in the manner in which the electronic components are arranged. Therefore, the following description is only for differences, and the same portions will not be described again.

As shown in FIG. 3A, the electronic component 33 is flip-chip provided on the first side 31a of the first line portion 31 with its active surface 33a.

In this embodiment, the first line portion 31 includes at least one first dielectric layer 310 and at least one first line redistribution layer 311.

Furthermore, the electrode pads 330 of the electronic component 33 are bonded to the first circuit redistribution layer 311 by a plurality of conductive bumps 331.

As shown in FIG. 3B, a cladding layer 24 is formed on the first line portion 31. The first side 31a of the conductor 22 is such that the cladding layer 24 covers the electronic component 33 and the conductors 22, and the process of thinning the cladding layer 24 is performed to make the end surface 22a of the conductor 22 The non-active surface 33b of the electronic component 33 is exposed on the surface of the cladding layer 24.

As shown in FIG. 3C, a second line portion 35 is formed on the cladding layer 24, and the second line portion 35 is electrically connected to the conductors 22.

In this embodiment, the second line portion 35 includes a second dielectric layer 350, a second line redistribution layer 351, and a second dielectric layer 350' as a solder resist layer.

As shown in FIG. 3D, the carrier board 20, the release layer 201, the metal layer 202, and the insulating layer 203 are removed, and the second side 31b of the first line portion 31 and the first line redistribution layer 311 are exposed. Thereafter, a plurality of conductive elements 28, such as solder balls, are formed on the exposed first line redistribution layer 311.

As shown in Fig. 3E, a singulation process is performed along the cutting path S as shown in Fig. 3D to form an electronic package 3'. Thereafter, a plurality of conductive elements 26, such as solder balls, are formed on the second line redistribution layer 351 for subsequent attachment of the electronic device 5 such as a package structure or other structure such as a circuit board or interposer.

4A to 4C are cross-sectional views showing a third embodiment of the manufacturing method of the electronic package of the present invention. The difference between this embodiment and the second embodiment is that the insulating layer and the conductor are omitted, so the following description will be made only for differences, and the same portions will not be described again.

As shown in FIG. 4A, a carrier 20 is formed, and a release layer 201 and a metal layer 402 disposed on the release layer 201 are formed thereon. A line portion 31 is bonded to the metal layer 402 with its second side 31b, wherein the metal layer 402 is an aluminum layer.

Next, the electronic component 33 is flip-chip provided on the first side 31a of the first line portion 31 with its active surface 33a.

Then, a cladding layer 24 is formed on the first side 31a of the first line portion 31, so that the cladding layer 24 covers the electronic component 33, and the non-active surface 33b of the electronic component 33 is not exposed. The surface of the cladding layer 24.

As shown in FIG. 4B, the carrier board 20, the release layer 201 and the metal layer 402 are removed, and the second side 31b of the first line portion 31 and the first line redistribution layer 311 are exposed. Thereafter, a plurality of conductive elements 28, such as solder balls, are formed on the exposed first line redistribution layer 311.

In this embodiment, the carrier plate 20 and the release layer 201 are removed by laser, and the metal layer 402 is removed by etching with an etching solution of H ₃ PO ₄ .

As shown in Fig. 4C, a singulation process is performed along the cutting path S as shown in Fig. 4B to form an electronic package 4'.

The method of the present invention forms a metal layer 202, 402 for protecting the release layer 201 on the release layer 201, and in the subsequent process, after removing the metal layer 202, 402 by using an etchant, the first is exposed. The circuit redistribution layer 211, 311, so that the opening of the first circuit redistribution layer 211, 311 is not required to be formed by laser, so the method of the invention not only improves the processing speed but also avoids the roughness of the opening hole compared with the prior art. The phenomenon that the conductive elements 28 are detached is caused.

Therefore, the method of the present invention can improve the electrical connection quality, product reliability and yield.

The invention also provides an electronic package structure 2, 3, 4 comprising: a carrier board 20, a first line portion 21, 31, an electronic component 23, 33 and a cladding layer 24.

The carrier board 20 is provided with a release layer 201 and a metal layer 202, 402.

The first line portion 21, 31 is disposed on the carrier board 20, wherein the first line portion 21, 31 has opposite first sides 21a, 31a and second sides 21b, 31b, and the first The line portions 21, 31 are provided on the metal layers 202, 402 with their second sides 21b, 31b.

The electronic components 23, 33 are disposed on the first sides 21a, 31a of the first line portions 21, 31.

The cladding layer 24 is formed on the first sides 21a, 31a of the first line portions 21, 31 such that the cladding layer 24 covers the electronic components 23, 33.

In one embodiment, the carrier 20 has an insulating layer 203 disposed on the metal layers 202, 402 for bonding the second sides 21b, 31b of the first line portions 21, 31.

In an embodiment, the electronic component 23 has an opposite active surface 23a and a non-active surface 23b. The active surface 23a has a plurality of electrode pads 230, and the electronic component 23 is disposed on the first line portion with its non-active surface 23b. On the first side 21a of 21.

In an embodiment, the electronic component 33 has an opposite active surface 33a and a non-active surface 33b. The active surface 33a has a plurality of electrode pads 330, and the electronic component 33 is disposed on the first line portion 31 with its active surface 33a. The first line portion 31 is electrically connected to the electronic component 33 on the first side 31a.

In one embodiment, the electronic package structure 2, 3 includes at least one electrical conductor 22, which is disposed on the first side 21a, 31a of the first line portion 21, 31, and the cladding layer 24 is overcoated. The conductor 22 is.

In one embodiment, the electronic package structure 2 further includes a second line portion 25 formed on the cladding layer 24, and the second line portion 25 is electrically connected to the electronic component 23.

In one embodiment, the metal layer 202, 402 is formed of titanium or aluminum.

In summary, the electronic package structure and the electronic package of the present invention are manufactured by the metal layer, so that in the subsequent process, only the metal layer is removed, and the first line is exposed. Therefore, it is not necessary to form an opening for exposing the first circuit redistribution layer by laser, so the invention not only improves the processing speed, but also avoids the phenomenon that the conductive element is detached due to the roughness of the opening.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2‧‧‧Electronic package structure

20‧‧‧Loading board

201‧‧‧ release layer

202‧‧‧metal layer

203‧‧‧Insulation

21‧‧‧First Line Department

21a‧‧‧ first side

21b‧‧‧ second side

22‧‧‧Electrical conductor

23‧‧‧Electronic components

230‧‧‧electrode pads

24‧‧‧Cladding

25‧‧‧Second Line Department

250,250’‧‧‧second dielectric layer

251,251’‧‧‧Second line redistribution

26‧‧‧Conductive components

260‧‧‧ Metal layer under the bump

Claims (20)

An electronic package structure comprising: a carrier plate; a release layer formed on the carrier plate; a metal layer formed on the release layer; and a first line portion formed on the metal layer, having a relative One side and a second side, and the first line portion is bonded to the metal layer with the second side thereof; the electronic component is disposed on the first side of the first line portion; and the cladding layer is formed on The first side of the first line portion covers the electronic component. The electronic package structure of claim 1, further comprising an insulating layer formed on the metal layer, wherein the insulating layer is bonded to the second side of the first line portion. The electronic package structure of claim 1, wherein the electronic component has a relative active surface and a non-active surface, the active surface has a plurality of electrode pads, and the electronic component is bonded to the first surface by an inactive surface thereof On the first side of a line. The electronic package structure of claim 1, wherein the electronic component has a relative active surface and a non-active surface, the active surface has a plurality of electrode pads, and the electronic component is disposed on the active surface thereof The first line portion is electrically connected to the electronic component on a first side of the first line portion. The electronic package structure of claim 1, further comprising at least one electrical conductor disposed on the first side of the first circuit portion and covered by the cladding layer. The electronic package structure of claim 1, further comprising a second line portion formed on the cladding layer. The electronic package structure of claim 6, wherein the second line portion is electrically connected to the electronic component. The electronic package structure according to claim 1, wherein the material forming the metal layer is titanium or aluminum. The method for manufacturing an electronic package includes: providing a carrier board on which a release layer and a metal layer are sequentially formed; forming a first line portion on the metal layer, wherein the first line portion has a relative One side and a second side, and the first line portion is bonded to the metal layer with the second side thereof; the electronic component is disposed on the first side of the first line portion; and the cladding layer is formed on the first line portion On the first side, the electronic component is covered; and the carrier, the release layer and the metal layer are removed, and the second side of the first line portion is exposed. The method of manufacturing an electronic package according to claim 9 , further comprising forming an insulating layer on the metal layer, wherein the insulating layer is bonded to the second side of the first line portion, so that the insulating layer is sandwiched Provided between the metal layer and the first line portion. The method for manufacturing an electronic package according to claim 10, further comprising removing the insulating layer when removing the carrier, the release layer and the metal layer. The method for manufacturing an electronic package according to claim 11, wherein the removing of the carrier, the release layer, the metal layer and the insulation layer is performed by laser removing the carrier plate and the release layer. And removing the metal layer and the insulating layer with an etchant. The method for manufacturing an electronic package according to claim 9, wherein the removing of the carrier, the release layer and the metal layer is performed by laser removing the carrier and the release layer, and then The etchant removes the metal layer. The method of manufacturing an electronic package according to claim 12, wherein the etching solution is a diluted hydrofluoric acid solution or phosphoric acid. The method of manufacturing an electronic package according to claim 9, wherein the electronic component has a relative active surface and a non-active surface, the active surface has a plurality of electrode pads, and the electronic component is bonded to the non-active surface thereof On the first side of the first line portion. The method of manufacturing an electronic package according to claim 9, wherein the electronic component has a relative active surface and a non-active surface, the active surface has a plurality of electrode pads, and the electronic component is bonded to the active surface On the first side of the first line portion, the first line portion is electrically connected to the electronic component. The method for manufacturing an electronic package according to claim 9, wherein the forming of the first line portion forms at least one electrical conductor The first side of the first line portion is such that the cladding coats the conductor. The method for manufacturing an electronic package according to claim 9 further comprises forming a second line portion on the cover layer before removing the carrier plate, the release layer and the metal layer. The method of manufacturing an electronic package according to claim 18, wherein the second line portion is electrically connected to the electronic component. The method of manufacturing an electronic package according to claim 9, wherein the material forming the metal layer is titanium or aluminum.