TW201726984A - Method for electrochemical polishing in constant pressure mode - Google Patents

Abstract

The present invention discloses a method of electrochemical polishing in a constant voltage mode, the method comprising: presetting a constant current recipe having a current distribution, including a plurality of locations having different radii on the wafer and presetting each location Current; polishing the first wafer using a constant current recipe; detecting and recording the voltage at each location during the polishing process; generating a constant voltage recipe with a voltage distribution comprising a plurality of locations and voltages recorded for each location; using a constant voltage The formulation polishes the second wafer.

Description

Method for electrochemical polishing in constant pressure mode

This invention relates to electrochemical polishing, and more particularly to a method of electrochemical polishing in a constant pressure mode.

Due to the fast electrochemical polishing effect and good effect, it has been widely used in the semiconductor industry, and the constant current mode is selected in the electrochemical polishing reaction. In constant current mode, the current is constant and stable, indicating that a constant amount of hydrogen ions reacts with the surface of the patterned wafer metal layer. When a large amount of copper layer completely covers the surface of the patterned wafer, the hydrogen ions will react uniformly with the copper layer on the entire wafer until a large amount of copper is removed. Since the copper and barrier materials (钽, tantalum nitride, titanium, titanium nitride, cobalt, ruthenium, etc.) remaining in the patterned trench do not react with the electrolyte, the concentration of hydrogen ions around the copper remaining region is greatly increased. The surface features that cause the depressions and copper lines vary with different line densities and distributions.

In constant current mode, the amount of charged ions is constant regardless of the patterned wafer surface features and structure. At micro-sizes, the removal rate of the entire region is uniform, and therefore, due to the non-uniform distribution of copper lines, the constant current mode will cause a difference in depression between different features.

The present invention provides a method for improving wafer level global recess and wafer scale microscopic recess after a semiconductor metal layer planarization process, which is based on the principle of electrochemical polishing.

In a specific embodiment, a method of electrochemical polishing in a constant voltage mode is provided, comprising: presetting a constant current recipe having a current distribution, including a plurality of locations having different radii on the wafer and presetting each location Current; polishing the first wafer using a constant current recipe; detecting and recording the voltage at each location during the polishing process; generating a constant voltage recipe with a voltage distribution comprising a plurality of locations and voltages recorded for each location; using a constant voltage The formulation polishes the second wafer.

In a specific embodiment, the current preset for the position is proportional to the radius of the position.

In a specific embodiment, the first wafer includes a bare wafer and a metal layer on the bare wafer.

In a specific embodiment, the second wafer includes a wafer having a plurality of patterned trenches or vias and a metal layer on the wafer, the patterned trenches or vias being filled with a metal layer.

The present invention proposes a method of electrochemical polishing in a constant pressure mode that overcomes the bottleneck of the prior art by introducing an automatic stop effect of constant pressure polishing.

101‧‧‧ chuck

102‧‧‧ wafer

103‧‧‧ sprinkler

104‧‧‧Power supply

105‧‧‧ electrolyte

201‧‧‧chip scale

202‧‧‧ unit

203‧‧‧ regional scale

401‧‧‧ line

402‧‧‧ Space

403‧‧‧First copper layer

404‧‧‧Second copper layer

405‧‧‧Block

406‧‧‧ dielectric layer

1 is a typical device diagram of electrochemical polishing; FIG. 2 is a top view of a polishing area and a wafer scale on a wafer; FIG. 3 is a plan view of a wafer scale and a graphic structure area scale on a wafer; and FIG. Figure 5 is a cross-sectional view of the unit of Figure 4 along AA; Figure 6 is another cross-sectional view of the unit of Figure 4 along AA; Figure 7 is a cross-sectional view of the unit of Figure 4 along BB; Figure 8 Is a depression after electrochemical polishing treatment in a constant pressure mode; FIG. 9 is a flow chart of the method of the present invention; FIG. 10 is an ammeter used in the method of the present invention; and FIG. 11 is a voltmeter used in the method of the present invention; .

The invention will be described in detail below with reference to the accompanying drawings.

A typical apparatus for electrochemical polishing, as shown in FIG. 1, includes a chuck 101, a showerhead 103, and a power source 104, both of which are electrically coupled to a power source 104. The chuck 101 supports and rotates the wafer 102 during polishing and is used as an anode. The shower head 103 sprays a charged electrolyte 105 onto the surface of the wafer 102 and is used as a cathode to react and transfer metal ions to the charged electrolyte 105. Go to the nozzle 103. In the prior art, the power source 104 is a constant current source, so electrochemical polishing can be performed in a constant current mode. However, in the present invention, the constant current power source is replaced by a constant voltage power source, and the electrochemical polishing is performed in a constant voltage mode.

In the constant voltage mode of the present invention, the amount of charged ions is variable, depending on the electrical resistance of the entire polishing system. In order to explain the function of the constant voltage mode, the polishing area model is first introduced. The polishing zone is located directly above the showerhead 103, and the charged electrolyte is ejected upward from the showerhead 103.

2 is a top plan view of the polishing area and wafer dimensions on wafer 102. In this model, the polishing area is divided into a plurality of wafer dimensions 201, each wafer dimension 201 comprising a plurality of cells 202, the size of which depends on the model definition and may tend to be nanoscale. Since the charged particles are shared by these units 202, the total amount of charged ions is equal to the sum of the charged ions per unit. Thus, all of these units 202 can be considered to be in parallel, meaning that current is shared by all of the units 202.

Figure 3 shows a top view of the dimensions of the wafer and the dimensions of the patterned structure on the wafer. There are a plurality of graphic structure area scales 203 on each wafer scale 201, the unit 202 is located in the graphic structure area scale 203, and the unit 202 is enlarged as shown in FIG. Further, as shown in FIGS. 4 to 7, a top view and a cross-sectional view of the defining unit 202 are given.

Typically, the electrical resistance of an electrochemical polishing system includes the electrical resistance of the device and the electrical resistance of the charged electrolyte. The electrical resistance of the device can be viewed as a fixed value, and the electrical resistance of the charged electrolyte is related to the size of the polishing zone.

The polishing zone consists of a plurality of cells 202, all of which are connected in parallel. In order to simplify the polishing area model, the boundary effect of the charged electrolyte 105 is ignored, and the current (i.e., ion concentration) and the liquid resistance of the charged electrolyte 105 are the same and uniformly distributed in the charged electrolyte 105. Moreover, for a particular cell 202, the resistance of cell 202 is determined by the structure of cell 202 itself. set.

A typical structure of the unit 202 is shown in FIGS. 4 to 7. The unit 202 is composed of a line 401 and a space 402 buried under the metal before the polishing process, and the line 401 and the space 402 are spaced apart from each other. In a specific embodiment, the metal is copper. Along the cross-sectional view of reference cell 202 along A-A, it can be seen that cell 202 includes a first copper layer 403, a second copper layer 404, a barrier layer 405, and a dielectric layer 406 from top to bottom. The first copper layer 403 is above the barrier layer 405 and the second copper layer 404 is within the line 401. Figure 6 shows another cross-sectional view of cell 202 along A-A where the first copper layer 403 has been removed during the polishing process.

Based on previous estimates, the resistance of unit 202 can be obtained according to the following equation: R = ρ L / A = ρ L / (T * W) (1)

Wherein ρ represents the resistivity of the material; L represents the length, in particular the side length of the cell; A represents the cross-sectional area of the first copper layer 403 and the barrier layer 405, equal to T times W; T represents the first copper layer 403 and The thickness of the barrier layer 405; W represents the side width of the cell.

In some cases, if cell 202 is defined as a square and L is equal to W, then equation (1) can be converted to: R = ρ / T (2)

The resistivity of copper is much smaller than the resistivity of the barrier layer, so the resistance of the copper layer is much smaller than the resistance of the barrier layer 405. Further, according to the equation (1), the electric resistance of the first copper layer 403 and the barrier layer 405 is inversely proportional to the cross-sectional area A, and is also inversely proportional to the thickness T described in the equation (2). Therefore, with the first copper Layer 403 is gradually removed during the polishing process and the resistance of the polishing region will be higher and higher. Thus, if the constant voltage mode is applied to the electrochemical polishing, the current will be automatically reduced. In this way, the removal rate will be well controlled to achieve a good polishing effect. This phenomenon can be defined as the automatic stop effect of the constant voltage mode.

8 to 11 illustrate a specific embodiment of the present invention, and a method for electrochemical polishing in a constant voltage mode, the method comprising: step 901: presetting a constant current recipe having a current distribution, including a wafer a plurality of locations having different radii and currents preset for each location; step 902: polishing the first wafer using a constant current recipe; step 903: detecting and recording the voltage at each location during the polishing process; A constant voltage recipe having a voltage distribution is generated, including a plurality of locations and voltages recorded for each location; step 905: polishing the second wafer using a constant pressure recipe.

Since the method uses a constant pressure mode, a good polishing result is obtained. Figure 8 shows the depression after electrochemical polishing in constant pressure mode, where 35μm and 5μm represent different line widths in the polished area, C (center), M (middle) and E (edge) represent Different locations of the processed wafer. Due to the automatic stop effect of the constant voltage mode, it can be seen that the depressions between the different line widths are very close at the same position; at the same line width, the depressions between the different positions are also very close. Conversely, if constant current mode is used in this method, even in the same position, different lines The depressions between the widths vary greatly; at the same line width, the difference in the depressions between the different positions is also large.

As shown in Figure 10, Table 1 is a constant current formulation for use in the method of the present invention. It can be seen that in this constant current recipe, each position has a corresponding current value. Further, Figure 11 shows the resulting constant pressure formulation. According to Table 1, Table 2 gives the voltage values corresponding to each position.

Table 2 applies only to fixed process conditions, which means that the process conditions must be stable, and the process conditions in the constant pressure formulation are the same as those in the constant flow formulation, including but not limited to electrolyte flow rate, electrolyte temperature And the speed of the wafer. If the change in process conditions exceeds the specified range, Table 2 should be regenerated according to steps 901 through 903.

In order to obtain a uniform removal profile after the electrochemical polishing of the present invention is completed, the current preset for the position is proportional to the radius of the position. Alternatively, the constant current recipe operates in pulse mode and the constant pressure recipe operates in pulse mode. In combination with the pulse mode, the removal rate can be reduced and does not have any adverse effect on the metal surface roughness of the wafer. Since the pulse mode can shorten the polishing time, and the metal surface roughness is inversely proportional to the polishing time, the pulse mode helps to improve the metal surface roughness of the wafer.

In a specific embodiment, the first wafer includes a bare wafer and a metal layer on the bare wafer. The metal layer may be a copper layer, a tin layer, a nickel layer, a silver layer or a gold layer.

In a specific embodiment, the second wafer includes a wafer having a plurality of patterned trenches or vias and a metal layer on the wafer. The patterned trench or via is filled with a metal layer. The metal layer is a copper layer, a tin layer, and a nickel layer. Layer, silver or gold layer.

According to the present invention, relatively uniform copper wires can be produced, and thus the difference in pits can be optimized.

The above description is only a preferred embodiment of the invention and is not intended to limit the invention in any way. A person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them to equivalent variations, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications of the above embodiments may be made without departing from the spirit and scope of the invention.

101‧‧‧ chuck

102‧‧‧ wafer

103‧‧‧ sprinkler

104‧‧‧Power supply

105‧‧‧ electrolyte

Claims (10)

A method of electrochemical polishing in a constant voltage mode, comprising: presetting a constant current recipe having a current distribution, including a plurality of locations having different radii on the wafer and a current preset for each location; Polishing the first wafer using a constant current recipe; detecting and recording the voltage at each location during the polishing process; generating a constant voltage recipe with a voltage distribution, including multiple locations and voltages recorded for each location; and using a constant pressure recipe Polishing the second wafer. The method of claim 1 wherein the current preset for the position is proportional to the radius of the position. The method of claim 1 wherein the first wafer comprises: a bare wafer; and a metal layer on the bare wafer. The method according to claim 3, wherein the metal layer is a copper layer, a tin layer, a nickel layer, a silver layer or a gold layer. The method of claim 1 wherein the second wafer comprises: a wafer having a plurality of patterned trenches or vias; and a metal layer on the wafer, wherein the patterned trench or pass The holes are filled with a metal layer. The method according to claim 5, wherein the metal layer is a copper layer, a tin layer, a nickel layer, a silver layer or a gold layer. The method of claim 1 wherein the constant current recipe operates in a pulse mode. The method of claim 1 wherein the constant pressure recipe operates in a pulse mode. The method of claim 1 wherein the process conditions of the constant pressure formulation are the same as those of the constant current formulation. The method of claim 9 wherein the process conditions comprise: electrolyte flow rate, electrolyte temperature, and wafer rotational speed.